TLE9221SX
FlexRay Transceiver
Automotive Power
Data Sheet
Rev. 1.3, 2015-09-21
TLE9221SX
Data Sheet 2 Rev. 1.3, 2015-09-21
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Behavior of Unconnected Digital Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Overview Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3 Communication Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4 Bus Guardian Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.5 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.6 Wake-up Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.7 Power Supply Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.8 Bus Failure Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.9 Central State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 Host Interface and Status Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2 Status Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2.1 Definition of the Status Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2.2 SIR Readout Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2.3 Clearing Sequence of SIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3 Status Information at the ERRN Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3.1 Reset the ERRN Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7 Wake-up Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1 Local Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1.1 Local Wake-up Falling Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1.2 Local Wake-up Rising Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.2 Remote Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.2.1 Standard Wake-up Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.2.2 Alternative Wake-up Pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.2.3 Wake-up by Payload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.3 Wake-up Flag and Wake-up Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8 Power Supply Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1 INH Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.2 BD_Off and Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table of Contents
Data Sheet 3 Rev. 1.3, 2015-09-21
TLE9221SX
8.3 Undervoltage Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.3.1 Undervoltage Flags and Undervoltage Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.3.2 Undervoltage Event at uVBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.3.3 Undervoltage Event at uVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.3.4 Undervoltage Event at uVIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.4 Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.4.1 BD_Off State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.4.2 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.4.3 Interim BD_Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9 Operating Mode Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.1 Operating Mode Transitions Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.2 Operating Mode Change by Host Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.2.1 Entering BD_Sleep Mode via the BD_GoToSleep Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.2.2 Quitting BD_Sleep by Host Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.3 Operating Mode Changeover by Undervoltage Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.3.1 Priorities of Undervoltage Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.4 Operating Mode Changes by Undervoltage Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.4.1 BD_Sleep Mode Entry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.5 Operation Mode Changes by the Wake-up Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10 Bus Error Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.1 Setting the Bus Error Bit by uVCC Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.2 Setting the Bus Error Bit by RxD and TxD Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.3 Setting the Bus Error Bit by Overcurrent Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11 Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12 Transmitter Time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13 Mode Indication, Power-up and Parity Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.1 Power-up Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.2 Mode Indication Bit EN and Mode Indication Bit STBN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.3 Even Parity Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
14 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
14.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
14.2 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
14.3 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
15 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
15.1 Functional Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
15.2 Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
16 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
16.1 ESD Robustness according to IEC61000-4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
16.2 Bus Interface Simulation Model Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
16.3 Typical RxD Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
16.4 Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
16.5 Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
16.6 Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
17 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
PG-SSOP-16
Type Package Marking
TLE9221SX PG-SSOP-16 9221
Data Sheet 5 Rev. 1.3, 2015-09-21
TLE9221SX
1 Overview
1.1 Features
General Features
• Compliant with the FlexRay Electrical Physical Layer
Specification, version 3.0.1 and ISO 17458
• Optimized for time-triggered in-vehicle networks with
data transmission rates from 1 Mbit/s up to 10 Mbit/s
• Optimized electromagnetic immunity (EMI)
• Very low electromagnetic emission (EME), supporting large
networks and complex bus topologies
• Very high level of ESD robustness, 11 kV according to IEC-61000-4-2
• Supports 60 ns minimum bit time
• Optimized digital inputs to minimize jitter
• Integrated Bus Guardian Interface
• Bus failure protection and error detection
• Automatic voltage adaptation on the digital interface pins
• High current digital outputs, optimized to drive long wires and high capacitive loads
• Green Product (RoHS compliant)
• AEC Qualified
Modes of Operation and Wake-up Features
• Sleep and stand-by operation mode with very low quiescent current
•Receive-only mode
• Separate INH output to control external circuitry
•Local wake-up input
• Remote wake-up via a dedicated wake-up symbol
• Alternative remote wake-up
• Remote wake-up via payload
• Wake-up source recognition and indication
Data Sheet 6 Rev. 1.3, 2015-09-21
TLE9221SX
Overview
Protection and Diagnostics
• Short-circuit protection
• Overtemperature protection
• Undervoltage detection on all power supplies
• Transmitter time-out
• Error and wake-up indication on the ERRN output
• Status Information Register to indicate error bits and wake-up bits
• High Impedance bus input in BD_Off condition
1.2 Description
FlexRay is a serial, deterministic bus system for real-time control applications. It is designed for future
requirements of in-vehicle control applications, providing data transmission rates up to 10 Mbit/s. FlexRay is
designed for collision-free data communication. The nodes do not arbitrate and the FlexRay Communication
Controller (CC) guarantees a collision-free bus access during normal operation.
The TLE9221SX FlexRay transceiver is a FlexRay bus driver (BD) and it accomplishes the physical interface
between the Communication Controller and the bus medium. Fully compliant with the FlexRay Electrical
Physical Layer Specification, version 3.0.1 (acronym EPL) and ISO 17458.
The TLE9221SX supports the following functional classes:
• Functional class “bus driver voltage regulator control”
• Functional class “bus driver bus guardian interface”
• Functional class “bus driver logic level adaption”
• Functional class “bus driver remote wake-up”
The TLE9221SX supports data transmission rates from 1 Mbit/s up to 10 Mbit/s. Besides the transmit and
receive capability of the bus, the TLE9221SX provides arrangements for low power supply management,
supply voltage monitoring and bus failure detection.
In BD_Sleep mode, the TLE9221SX quiescent current decreases to a typical, total current consumption of
47.5 μA, while the device is still able to wake up by a dedicated wake-up pattern on the FlexRay data bus or by
a local wake-up event on the pin WAKE. The INH output pin allows the control of external circuitry depending
on the selected mode of operation.
Fail-safe features, like bus failure detection or the power supply monitoring, combined with an easy accessible
Status Information Register support the requirements of safety-related applications with extended diagnostic
features.
The TLE9221SX is internally protected against transients on all global pins. Global pins are BP, BM, WAKE and
VBAT. It is possible to use the TLE9221SX without any additional external protection circuitry while the
TLE9221SX meets the ESD and ISO pulse requirements of the car manufactures.
The TLE9221SX is designed on the latest Infineon Smart Power Technology SPT, which combines power
devices with a highly integrated logic process. Based on its digital design concept, the TLE9221SX provides
very high immunity against RF disturbances over a wide frequency range.
Based on the high symmetry of the BP and BM signals, the TLE9221SX provides the lowest level of
electromagnetic emission (EME) within a wide frequency range.
Data Sheet 7 Rev. 1.3, 2015-09-21
TLE9221SX
Overview
The TLE9221SX is integrated in a RoHS compliant PG-SSOP-16 package. The TLE9221SX and the Infineon
Smart Power Technology SPT are especially tailored to withstand the harsh conditions of the automotive
environment and qualified according to the AEC-Q100 standard.
Data Sheet 8 Rev. 1.3, 2015-09-21
TLE9221SX
Block Diagram
2 Block Diagram
Figure 1 Block diagram
VBAT
Central State
Machine
Bus Failure
Detector
VBAT
11
VCC VIO
16 3
Power Supply Interface INH
1
Transmitter
Receiver
Wake-up
Detector
BM
BP 15
14
WAKE
GND
12
13
Host
Interface
10
ERRN
STBN
EN
8
2
Communication
Controller
Interface
Bus Guardian
Interface
9
7
6
5
4
RxD
TxEN
TxD
RxEN
BGE
VIO
Voltage
Monitor
Data Sheet 9 Rev. 1.3, 2015-09-21
TLE9221SX
Pin Configuration
3 Pin Configuration
3.1 Pin Assignment
Figure 2 Pin configuration
3.2 Pin Definitions
Table 1 Pin definition and functions
Pin Symbol Function
1INH Inhibit Output;
open drain output to control external circuitry,
“high” impedance in BD_Sleep mode.
2EN Enable Mode Control Input;
digital input for the mode selection,
integrated “pull-down” resistor to GND.
3V
IO Level Shift Input;
reference voltage for the digital input and output pins,
100 nF decoupling capacitor to GND recommended.
1
2
3
4
5
6
7
8
16
15
14
13
12
INH
EN
VIO
TxD
TxEN
RxD
BGE
STBN
VCC
BP
BM
GND
WAKE
VBAT
ERRN
RxEN
11
10
9
Data Sheet 10 Rev. 1.3, 2015-09-21
TLE9221SX
Pin Configuration
4TxD Transmit Data Input;
integrated “pull-down” current source to GND,
logical “low” to drive “Data_0” to the FlexRay bus.
5TxEN Transmitter Enable Not Input;
integrated “pull-up” current source to VIO,
logical “low” to enable the Transmitter.
6RxD Receive Data Output;
logical “low” while “Data_0” is on the FlexRay bus,
output voltage adapted to the voltage on the VIO level shift input.
7BGE Bus Guardian Enable Input;
logical “high” to enable the Transmitter,
integrated “pull-down” current source to GND.
8STBN Stand-by Not Mode Control Input;
digital input for the mode selection,
integrated “pull-down” current source to GND.
9 RxEN Receive Data Enable Not Output;
logical “low” indicates activity on the FlexRay bus,
logical “high” in case the FlexRay Bus is “Idle”,
output voltage adapted to the voltage on the VIO level shift input.
10 ERRN Error Not Diagnosis Output;
logical “low” in failure case,
output voltage adapted to the voltage on the VIO level shift input.
11 VBAT Battery Voltage Supply;
100 nF decoupling capacitor to GND recommended.
12 WAKE Wake-up Input;
local wake-up input, terminated against GND and VBAT,
wake-up input sensitive to signal changes in both directions.
13 GND Ground;
14 BM Bus Line Minus;
negative input/output to the FlexRay bus.
15 BP Bus Line Plus;
positive input/output to the FlexRay bus.
16 VCC Supply Voltage;
Transmitter supply voltage,
100 nF decoupling capacitor to GND recommended.
Table 1 Pin definition and functions
Pin Symbol Function
Data Sheet 11 Rev. 1.3, 2015-09-21
TLE9221SX
Functional Overview
4 Functional Overview
4.1 Functional Description
FlexRay is a differential bus system. The data is exchanged via a dual wire bus medium on the wires BP (Bus
Line Plus) and BM (Bus Line Minus).
Three different bus symbols are supported: “Data_0”, “Data_1” and bus “Idle”. An active Transmitter of the
TLE9221SX drives “Data_0” or “Data_1” to the bus medium, depending on the TxD input signal. To sustain an
“Idle” signal on the FlexRay bus, the Transmitter is turned off, the voltage difference between BP and BM is
below 30 mV, and the absolute voltage level on both bus lines, BP and BM depends on the Bus Biasing (see
Figure 3):
• “Data_1”: uBus = uBP - uBM ≥300 mV →positive voltage between BP and BM
• “Data_0”: uBus = uBP - uBM ≤- 300 mV →negative voltage between BP and BM
•“Idle”: |uBus|=|uBP-uBM|≤30 mV
Figure 3 FlexRay EPL bus signals without Bus Guardian Interface
t
BP
BM
“Idle”2)
“Data_1” “Data_1”
“Idle”1)
TxD
t
1) Some nodes or all nodes inside the FlexRay Network are in BD_Normal mode.
2) All nodes of the FlexRay network are in low power mode.
“Data_0” “Data_0”
VBUS
t
“Data_1” “Data_1”
“Data_0” “Data_0”
“Idle”2)
“Idle”1)
TxEN
t
RxD
t
Data Sheet 12 Rev. 1.3, 2015-09-21
TLE9221SX
Functional Overview
4.2 Modes of Operation
The FlexRay bus driver TLE9221SX supports four different modes of operation:
•BD_Normal mode
•BD_ReceiveOnly mode
• BD_Standby mode
• BD_Sleep mode
Each mode has specific characteristics in terms of quiescent current, data transmission or failure diagnostic.
To enter the BD_Sleep mode, the TLE9221SX provides an intermediate mode, the so-called BD_GoToSleep
command.
Mode changes on the TLE9221SX are either triggered by:
• The Host Interface and a host command on the input pins EN and STBN.
• The Power Supply Interface and an undervoltage event on one of the two power supplies or the reference
supply uVIO.
• The Wake-up Detector and wake-up events either on the FlexRay bus or on the local wake-up pin WAKE.
While all power supplies are turned off, the transceiver TLE9221SX is in BD_Off condition or also called
“without supply”.
In BD_Sleep mode and in BD_Standby mode the quiescent current consumption at all three supplies is
tailored to reach the minimum, and therefore only a limited set of the functions of the TLE9221SX is available.
BD_Sleep mode and BD_Standby mode are also called low power modes. Conversely the modes BD_Normal
and BD_ReceiveOnly are called non-low power modes.
4.3 Behavior of Unconnected Digital Input Pins
The integrated pull-up and pull-down resistors at the digital input pins force the TLE9221SX into a secure, fail
safe behavior if the input pins are not connected and floating (see Table 2 for details).
If the TxEN pin or the BGE pin is not connected in BD_Normal mode, the Transmitter is disabled. If the TxD
input pin is open in BD_Normal mode and the Transmitter is active, the transceiver TLE9221SX drives a
“Data_0” signal to the bus.
If the mode control input pins of the Host Interface are not connected, the pull-down resistors on the EN pin
and on the STBN pin set the TLE9221SX by default to BD_Standby mode.
Table 2 Logical inputs when unconnected
Input Signal Default State Comment
TxD1)
1) In BD_Sleep, BD_Standby, and also in BD_ReceiveOnly mode, the inputs TxD, TxEN and BGE are blocked by the
internal logic. To optimize the total quiescent current consumption, the pull-up and pull-down structures are
disabled in BD_Sleep mode, BD_Standby mode and BD_ReceiveOnly mode.
“low” pull-down to GND
TxEN1) “high” pull-up to uVIO
STBN “low” pull-down to GND
EN “low” pull-down to GND
BGE1) “low” pull-down to GND
Data Sheet 14 Rev. 1.3, 2015-09-21
TLE9221SX
Overview Functional Blocks
5 Overview Functional Blocks
5.1 Transmitter
The Transmitter is the output driver for the FlexRay bus. It is based on a “high” side and “low” side push-pull unit.
The push-pull units are supplied by the power supply uVCC (see Figure 1).
While driving a “Data_1” or “Data_0” signal on to the FlexRay bus, the transceiver is active and enabled. During
an “Idle” signal, the transceiver is turned off.
Figure 1 Block diagram of the Transmitter
The Transmitter is protected by an internal temperature sensor against overheating in terms of a short circuit on
the bus lines BM or BP. The Transmitter is controlled by the Communication Controller Interface (see
Chapter 5.3). The Transmitter is only active in BD_Normal mode.
5.2 Receiver
The Receiver detects communication elements, like “Idle”, “Data_1” and “Data_0”, when it is not in low power
mode. It is connected to the BP and BM I/O pins of the TLE9221SX, together with the Transmitter, the Bus-Failure
Detector, and the Wake-up Detector (see Figure 1). Based on a digital sampling concept, the Receiver is
optimized to withstand the RF immunity requirements of the automotive industry.
The low pass input filter is tailored to support analog bit times down to 60 ns. Data bits below 60 ns may not be
detected as valid communication elements. When the Receiver detects activity on the FlexRay bus behind the
input filter, the differential Receiver distinguishes whether “Data_0” or “Data_1” is signaled by the differential bus
voltage. The bus activity information is provided to the Bus Guardian Interface. The information regarding the
FlexRay data bits is provided to the Communication Controller (see Figure 2).
The thresholds and the timings of the Receiver are available in Figure 38 and Figure 39.
Overtemp.
Sensor
BP
BM
uVCC
Driver
Driver
time-out
Communication
Controller Interface
uVCC
Data Sheet 15 Rev. 1.3, 2015-09-21
TLE9221SX
Overview Functional Blocks
Figure 2 Block diagram of the Receiver
Apart from receiving data, the Receiver is responsible for biasing the FlexRay bus. The biasing of the FlexRay bus
depends on the selected mode of operation.
In BD_Normal mode and BD_ReceiveOnly mode, the voltage uBias is connected to the BP and BM pins across
the common mode resistors RCM1 and RCM2. In BD_Sleep mode, BD_Standby mode and in the BD_GoToSleep
command the I/O pins BP and BM are connected to GND via the common mode resistors RCM1 and RCM2.
When TLE9221SX is not supplied, the bus biasing is open and is neither switched to uBias nor to GND, the BP
and BM pins appear to the FlexRay bus as a high-impedance input (see Table 3 and Figure 2).
5.3 Communication Controller Interface
The Communication Controller Interface is the interface between the FlexRay transceiver TLE9221SX and the
FlexRay Communication Controller (CC). It comprises three digital signals:
• The TxEN (Transmit Data Enable Not) input pin
• The TxD (Transmit Data) input pin
• The RxD (Receive Data) output pin
Table 3 Bus biasing
Mode of Operation Bus Biasing Transmitter
BD Normal uBias active or disabled
BD_ReceiveOnly uBias disabled
BD_Standby GND disabled
BD_GoToSleep command GND disabled
BD_Sleep GND disabled
BD_Off condition Open disabled
Input Filter
BP
Activity
Detection
Clock Source
Communication
Controller
Interface
Bus Guardian
Interface
RCM1 RCM2
GND
uBias
Bus
Biasing
Differential
Receiver
+
-
BM
Data Sheet 16 Rev. 1.3, 2015-09-21
TLE9221SX
Overview Functional Blocks
The logical I/O levels of all three digital pins are adapted to the reference voltage uVIO. In case uVIO is not available
or in an undervoltage condition, the RxD output is set to logical “low” and the input pins TxD and TxEN are set to
their default condition (see Table 2).
The Communication Controller logic block handles the interlock between TxD and TxEN. The Central State
Machine provides the interface to other TLE9221SX function blocks and handles the dependency based on the
selected mode of operation (see Figure 3).
Figure 3 Block diagram of the Communication Controller Interface
The TxD input of the Communication Controller Interface is active only when the Transmitter is activated. To
activate the Transmitter, the transceiver TLE9221SX needs to be in BD_Normal mode, the TxEN input must be at
logical “low” and the BGE input pin must be at logical “high” (see Table 4).
The FlexRay transceiver shall never start data transmission with the communication element “Data_1”. Therefore,
the activation of the Transmitter via the TxEN signal is only possible while the TxD signal is at logical “low” (see
Figure 4).
While the Transmitter is enabled, the Communication Controller Interface drives the serial digital data stream
available at the TxD input pin to the FlexRay bus via the Transmitter. A logical “high” signal at the TxD pin drives
a “Data_1” signal to the FlexRay bus and a logical “low” signal drives a “Data_0” signal (see Table 4).
Communication Controller
Logic Block
Transmitter
Receiver
Central
State
Machine
uVIO
uVIO
uVIO
TxD
TxEN
RxD
Data Sheet 17 Rev. 1.3, 2015-09-21
TLE9221SX
Overview Functional Blocks
Figure 4 FlexRay physical layer bus signals with Bus Guardian Interface
The Receiver of the TLE9221SX is active in all non-low power operating modes. Similar to the TxD input, the RxD
output indicates a “Data_1” signal on the FlexRay bus by a logical “high” signal and the “Data_0” signal by a logical
“low” signal.
In every low power mode, the TxD and TxEN input pins are disabled. The RxD output pin is used to indicate the
wake-up flag, while the transceiver is in low power mode (see Table 5).
5.4 Bus Guardian Interface
The Bus Guardian Interface comprises two digital signals:
• The BGE (Bus Guardian Enable) input pin.
• The RxEN (Receive Enable Not) output pin.
The logical I/O levels of the input and the output pin are adapted to the reference voltage uVIO. In case uVIO is not
available or in undervoltage condition, the RxEN output is set to logical “low” and the input pin BGE is set to its
default condition (see Table 2).
The Bus Guardian logic block handles the connection to the Transmitter and the Receiver. The Central State
Machine provides the interface to other TLE9221SX function blocks and handles the dependency on the selected
mode of operation (see Figure 5).
BGE
TxEN
BP
BM
TxD
t
t
t
Transmitter on Transmitter off Transmitter on Transmitter off
The Transmitter can only be
activated while TxD = “low”
t
RxEN
t
RxD
t
“Idle”
“Data_1” “Data_1”“Data_0” “Data_0” “Data_1” “Data_0” “Data_1” “Idle”
Data Sheet 18 Rev. 1.3, 2015-09-21
TLE9221SX
Overview Functional Blocks
Figure 5 Block diagram of the Bus Guardian Interface
The BGE input is an additional fail safe input, allowing external hardware to block the data stream driven to the
FlexRay bus medium. Switching the BGE input to logical “low” disables the Transmitter of TLE9221SX regardless
of the signals on all the other digital input pins. The BGE input is active only in BD_Normal mode (see Table 4 and
Figure 4).
The RxEN (Receive Enable Not) indicates the activity on the FlexRay bus. In case the FlexRay bus is “Idle”, the
logical signal on the RxEN is “high”. Any active data signal on the FlexRay bus, regardless of whether it is “Data_0”
or “Data_1”, is indicated by a logical “low” signal on the RxEN output pin. Like the RxD output pin, the RxEN output
pin indicates also the wake-up flag while the transceiver is in low power mode (see Table 5 and Figure 4).
Table 4 TxD/TxEN interface, acting as a Transmitter
Mode of Operation TxEN BGE TxD Resulting Signal on the Bus
BD_Normal “high” X1)
1) X = don’t care
X“Idle”
X “low” X “Idle”
“low” “high” “low” “Data_0”
“low” “high” “high” “Data_1”
All other modes X X X “Idle”
Table 5 RxD/RxEN interface, acting as Receiver with Bus Guardian Interface
Mode of Operation Signal on the Bus Wires Wake-up Flag RxD RxEN
BD_Normal,
BD_ReceiveOnly
“Idle” X1) “high” “high”
“Data_0” X “low” “low”
“Data_1” X “high” “low”
Bus Guardian
Logic Block
Transmitter
Receiver
Central
State
Machine
uV
IO
uV
IO
BGE
RxEN
Data Sheet 19 Rev. 1.3, 2015-09-21
TLE9221SX
Overview Functional Blocks
5.5 Host Interface
The Host Interface is the interface between the FlexRay transceiver TLE9221SX and the FlexRay host controller.
It allows the host to control the operating modes and to read status and diagnostics information. It comprises three
digital signals:
• The EN (Enable) input pin
• The STBN (Stand-By Not) input pin
• The ERRN (Error Not) output pin
The logical I/O levels of the pins are adapted to the reference voltage uVIO. In case uVIO is not available or in
undervoltage condition, the ERRN output is set to logical “low” and the input pins EN and STBN are set to their
default condition (see Table 2).
Figure 6 Block diagram of the Host Interface
The EN and STBN pins control the modes of operation. The pins are connected to the Central State Machine via
an input filter. The input filter protects the transceiver TLE9221SX against unintentional mode changes caused by
spikes on the EN and STBN.
BD_Sleep,
BD_StandBy
X “low” (set) “low” “low”
X “high” (not set) “high” “high”
1) X = don’t care
Table 5 RxD/RxEN interface, acting as Receiver with Bus Guardian Interface
Mode of Operation Signal on the Bus Wires Wake-up Flag RxD RxEN
Glitch Filter
Central
State
Machine
uV
IO
uV
IO
uV
IO
STBN
EN
ERRN
SIR
Data Sheet 20 Rev. 1.3, 2015-09-21
TLE9221SX
Overview Functional Blocks
The ERRN output signals failures, diagnostic and status information to the external host controller. The
TLE9221SX also contains a Status Information Register. Access to the Status Information Register is given by the
Host Interface (see details Chapter 6).
5.6 Wake-up Detector
The Wake-up Detector is a separate internal function block to detect wake-up events, be it a local or a remote
wake-up event. The Wake-up Detector also enables the filtering unit to differentiate between real wake-up signals
and floating signals or glitches on the wake-up lines. Active in every operation mode, and also in the BD_Normal
or BD_ReceiveOnly mode, the Wake-up Detector ensures that no wake-up signal gets lost due to a concurrent
change of the operating mode. The Wake-up Detector provides feedback on the wake-up information to the
Central State Machine for further processing (details see Chapter 7).
5.7 Power Supply Interface
The Power Supply Interface is the interface from the bus driver to the external supply voltages. It hosts the inputs
to the power supplies VBAT and VCC and also the level shift input to the reference voltage VIO.
To enable the control of external circuitry, like a voltage regulator for example, the Power Supply Interface of the
TLE9221SX provides an INH output.
All power supplies and the reference voltage are monitored and undervoltage conditions are indicated via the
ERRN output on the Host Interface (details see Chapter 8).
5.8 Bus Failure Detector
The Bus Failure Detector monitors the data stream on the BM and BP I/O pins and compares the bus data with
the digital data stream available at the Communication Controller Interface. Discrepancies between the bus data
and the digital data are interpreted as a bus failure. The Bus Failure Detector is active only in BD_Normal mode.
All detected failures are signaled on the ERRN output by the Host Interface (see Chapter 10).
5.9 Central State Machine
The Central State Machine is the main logic block of the TLE9221SX. It controls all functions of the TLE9221SX,
the failure management as well as the power-up and power-down operations. The Central State Machine also
provides some internal registers to store status, diagnostic and failure information.
• Information about the operating mode handling (see Chapter 9)
• Information about the Status Information Register (see Chapter 6)
• Information about the power management (see Chapter 8)
• Information about the bus failure flag (see Chapter 10)
Table 6 Modes of operation1)
1) No undervoltage flag and no wake-up flag is set.
STBN EN Mode of Operation
“high” “high” BD_Normal
“high” “low” BD_ReceiveOnly
“low” “high” BD_GoToSleep, automatically transferred to BD_Sleep
“low” “low” BD_Standby
Data Sheet 21 Rev. 1.3, 2015-09-21
TLE9221SX
Host Interface and Status Information Register
6 Host Interface and Status Information Register
The Host Interface is the main interface for:
• Selecting and controlling the operation modes of the TLE9221SX by host commands.
• Receiving status information of the TLE9221SX at the ERRN output pin.
• Retrieving diagnostics information of the TLE9221SX by reading the Status Information Register.
The Host Interface is operational when the reference voltage uVIO is in its functional range. In case the supply
uVIO is in undervoltage condition, the Host Interface is blocked and the operating mode of the TLE9221SX
FlexRay transceiver is automatically set to BD_Sleep mode (compare with Chapter 9.3).
6.1 Host Commands
The digital inputs EN and STBN have dual functionality:
• EN and STBN are used to select the operating mode.
• EN and STBN are used to trigger the read-out of the Status Information Register.
The STBN, EN and all other digital inputs of the TLE9221SX are level-triggered and protected with a glitch input
filter. Additionally, a digital input filter is provided at the mode selection pins STBN and EN.
To get a valid host command, which triggers a change of the operating mode, the external signals at the pins
EN and STBN need to be stable at least for time t ≥dBDLogicFilter. Signal changes with a smaller pulse width
than the internal filter time t <dBDLogicFilter are not considered valid host commands and the TLE9221SX
remains in its previous operating mode.
Within the time for mode change t = dBDModeChange the FlexRay transceiver TLE9221SX changes to the selected
mode of operation (see Figure 4). All output signals are valid after the mode transition and when the time for
mode change t = dBDModeChange has expired.
Figure 4 Example of a valid host command
Note: The time for mode change has to be considered for every change of the operation mode. All definitions in
this data sheet are made considering the time for mode change dBDModeChange, even if the time for mode
STBN
host command detection
EN
t
t
BD_Normal BD_Standby
t < dBDLogicFilter
mode transition
t = dBDLogicFilter
t = dBDModeChange
mode change
100% uVIO
50% uVIO
0% uVIO
100% uVIO
50% uVIO
0% uVIO
Data Sheet 22 Rev. 1.3, 2015-09-21
TLE9221SX
Host Interface and Status Information Register
change is not explicitly mentioned, for example in logical status tables, mode diagrams or in elementary
timing diagrams.
6.2 Status Information Register
6.2.1 Definition of the Status Information Register
Failure, wake-up and diagnostic information is stored internally in a 16-bit wide register in the TLE9221SX, the
so-called Status Information Register, or abbreviated to SIR (see Table 7).
6.2.2 SIR Readout Mechanism
The SIR is a “read-only” register and the data can be read out serially by using EN input as a data clock. While
the SIR readout procedure is running, no operation mode change applies to the TLE9221SX. This allows
regular data communication and read-out of the SIR at the same time.
Like all the other functions using the Host Interface, the reference supply uVIO needs to be operational to read
out the SIR.
The SIR readout is possible in all non-low power modes and in BD_Standby mode (see Table 8).
Table 7 Bit definition of the Status Information Register1)
1) The bits are “low” active. For example bit = 0, when set.
Bit Description Summary Flag / Bit
Bit 0 local wake-up bit wake-up flag
Bit 1 remote wake-up bit wake-up flag
Bit 2 reserved, always “high” –
Bit 3 power-up bit –
Bit 4 bus error bit error bit
Bit 5 overtemperature error bit error bit
Bit 6 overtemperature warning bit error bit
Bit 7 Transmitter time-out bit error bit
Bit 8 VBAT undervoltage bit error bit
Bit 9 VCC undervoltage bit error bit
Bit 10 VIO undervoltage bit error bit
Bit 11 error bit –
Bit 12 wake-up source bit –
Bit 13 EN mode indication bit –
Bit 14 STBN mode indication bit –
Bit 15 even parity bit –
Data Sheet 23 Rev. 1.3, 2015-09-21
TLE9221SX
Host Interface and Status Information Register
Note: The SIR readout depends on the current operating mode selected and not on the host command applied.
In case of undervoltage events, the host command could be BD_Normal mode, but the operating mode is
BD_Sleep mode. In BD_Sleep mode, no SIR read-out is possible.
Figure 5 Timing diagram for the SIR readout in BD_Normal mode
During the SIR readout, the EN input acts as the clock and the ERRN output pin acts as the serial “data_out”.
Irrespective of the digital signal at the STBN input, the SIR readout is always initialized by a signal change at
the EN input pin. When the host command BD_Normal is applied to the Host Interface, the SIR read-out starts
with the falling edge at the EN input (see Figure 5). For the host commands BD_Standby and BD_ReceiveOnly
the read-out starts with the rising edge at the EN pin (see Figure 6).
After initialization, the internal timer starts and the TLE9221SX awaits the next signal change within the timing
window dENCLOCK(min) < t < dENCLOCK(max). The next rising edge1) enables the SIR and the bits can be clocked
out.
Table 8 Readout mechanism and modes of operation
Modes of Operation Active / Not Active
BD_Normal active
BD_ReceiveOnly active
BD_GoToSleep Command not active
BD_Standby active
BD_Sleep not active
50% uVIO
STBN
t
initialize Host
Interface
EN
enable
SIR
dENClock
ERRN
clock out
SIR
t
t
dENClock dENClock dENClock dENTimeout
BD_Normal mode BD_ReceiveOnly
exit SIR
select operation mode according to
the host command
0% uVIO
100% uVIO
50% uVIO
0% uVIO
100% uVIO
50% uVIO
0% uVIO
100% uVIO
ERRN Status SIR
Bit 0
SIR
Bit 1
SIR
Bit 15
SIR
Bit 0
ERRN Status
Data Sheet 24 Rev. 1.3, 2015-09-21
TLE9221SX
Host Interface and Status Information Register
If no signal change occurs after the initialization within the time frame t < dENTimeout, the TLE9221SX exits the
SIR readout procedure and changes the operating mode according to the host command applied.
When the SIR is enabled, every falling edge at the EN input serially shifts out the SIR information at the ERRN
output pin. With the first falling edge of the clock at the EN input, the least significant bit, bit 0, is clocked out
to the ERRN output successively followed by bit 1, bit 2, etc, with every successive falling edge of the clock at
the EN input.The SIR bits are “low” active, meaning that the ERRN signal = “low” when the SIR bit is set.
Note: The STBN input pin has no function when the SIR readout is enabled and the readout procedure is
running. Nevertheless, it is recommended to keep the STBN pin stable (“high” or “low”) during the SIR
readout procedure.
Figure 6 SIR readout in BD_ReceiveOnly or BD_Standby mode
The SIR readout procedure can be terminated at any time by stopping the clock at the EN input pin. While the
signal at the EN pin is stable for the time t > dENTimeout, the TLE9221SX exits the SIR and changes to the
operating mode according to the host command applied.
Note: It is recommended to leave the SIR read out procedure with the same EN signal that was present when
the read out procedure was started. When time t = dENTimeout expires, the mode change is triggered
immediately.
1) While the TLE9221SX is in BD_Normal mode, the rising edge is the first signal change after initialization and enables the SIR
readout. For the BD_ReceiveOnly and the BD_Standby mode, there is an additional falling edge between initialization and the SIR
being enabled (compare with Figure 5 and Figure 6).
ERRN status
STBN
t
initialize Host
Interface
EN
enable
SIR
dENClock
ERRN
clock out
SIR
SIR
Bit 0
SIR
Bit 1
SIR
Bit 15
t
t
dENClock dENClock dENClock dENTimeout
ERRN status
BD_ReceiveOnly mode or BD_Standby mode
dENClock
SIR
Bit 0
additional edge
exit SIR
select operation mode according to
the host command
50% uVIO
0% uVIO
100% uVIO
50% uVIO
0% uVIO
100% uVIO
STBN = “high” or “low”
“high” for BD_ReceiveOnly mode
“low” for BD_Standby mode
50% uVIO
0% uVIO
100% uVIO
50% uVIO
0% uVIO
Data Sheet 25 Rev. 1.3, 2015-09-21
TLE9221SX
Host Interface and Status Information Register
6.2.3 Clearing Sequence of SIR
Failure and status information is latched in the SIR and the bits need to be cleared by a host command. In
order to avoid any status bit from being cleared, while the root cause of the bit entry is still present, the
TLE9221SX is equipped with a dedicated sequence to clear the bits of the Status Information Register. Before
clearing any bits, the TLE9221SX checks, if the root cause of the bit entry is resolved. Only if the root cause of
the bit entry has disappeared, the bit will be cleared.
The sequence to clear the bits of the SIR is started by:
• Entering BD_Normal mode via a host command.
• A complete readout of all 16 bits in the SIR.
In case the readout of the SIR is incomplete, for instance, due to a microcontroller interrupt during the readout
procedure, the bits in the SIR remain set.
In case the SIR readout continues after the last bit (bit 15) has been clocked out, the TLE9221SX continues and
clocks out the first bit (bit 0) again. On the second readout the bits in the SIR have been cleared. The bits will
only be cleared if the root cause of setting them has been resolved.
Note: Applying TLE9221SX the host command BD_Normal does not necessarily clear the SIR, since entering
BD_Normal mode can be prevented by an undervoltage event (see Table 13).
6.3 Status Information at the ERRN Output Pin
The ERRN output pin functions as a serial “data-out” during the SIR readout procedure. In any other case, the
ERRN output pin indicates the status information. The ERRN pin indicates failure, wake-up events and the
wake-up source.
The host command applied determines the incident that is signed at the ERRN output pin. The ERRN output
pin is active “low” (details see Table 9).
Table 9 Signaling at ERRN
STBN EN Host Command Error
Bit1)
Wake-up
Flag1)
ERRN Condition
Error Indication
“high” “high” BD_Normal “high” X2) “high” –
“high” “high” BD_Normal “low” X “low” –
“high” “low” BD_ReceiveOnly “high” “high” “high” –
“high” “low” BD_ReceiveOnly “low” “high” “low” –
Wake-up Source Indication
“high” “low” BD_ReceiveOnly X “low” “high” wake-up source bit = “high”
“high” “low” BD_ReceiveOnly X “low” “low” wake-up source bit = “low”
Wake-up Indication
“low” “high” BD_GoToSleep command X “high” “high” automatically transferred to BD_Sleep
“low” “high” BD_GoToSleep command X “low” “low” automatically transferred to BD_Sleep
“low” “low” BD_Standby X “high” “high” –
“low” “low” BD_Standby X “low” “low” –
Data Sheet 26 Rev. 1.3, 2015-09-21
TLE9221SX
Host Interface and Status Information Register
Note: The status signal at the ERRN output depends directly on the host command applied. Since the selection
of the operation mode doesn’t implicitly depend on the host command but also on failure cases and
wake-up events, it is possible that the TLE9221SX is in BD_Sleep mode while the host command
BD_Normal mode is applied to the Host Interface (details see also Table 15, Table 16 and Table 17).
As an example in Figure 7 the TLE9221SX indicates the error flag while the device is in BD_Sleep mode due to
an undervoltage event on uVBAT.
Figure 7 Status at the ERRN while uVBAT undervoltage
6.3.1 Reset the ERRN Output Pin
The ERRN output depends directly on the status bits in the SIR. Resetting the bits in the SIR automatically also
clears the ERRN output and, vice versa, one bit in SIR sets the ERRN output.
As described in Chapter 6.2.3 the SIR can be reset by a dedicated host command or by the readout of the SIR.
Since the SIR and consequently also the ERRN output can only be reset by a dedicated host command,
toggling at the ERRN pin is not possible.
“low” X BD_Sleep X “high” “high” –
“low” X BD_Sleep X “low” “low” –
1) “Low” active, the error bit and the wake-up flag are set while active “low”.
2) “X” = don’t care.
Table 9 Signaling at ERRN
STBN EN Host Command Error
Bit1)
Wake-up
Flag1)
ERRN Condition
STBN
EN
t
dReTimeERRN
t
uVBAT
t
ERRN
t
BD_Sleep (because of uVBAT undervoltage)
50% uVIO
0% uVIO
uBDUVVBAT
100% uVIO
50% uVIO
0% uVIO
100% uVIO
50% uVIO
0% uVIO
dReTimeERRN
100% uVIO
host command = BD_Standby
ERRN = wake-up flag
host command = BD_Normal
ERRN = error bit
Data Sheet 27 Rev. 1.3, 2015-09-21
TLE9221SX
Wake-up Detector
7 Wake-up Detector
The FlexRay transceiver TLE9221SX can detect different wake-up events via the central Wake-up Detector.
These can be either remote wake-up events provided by the FlexRay bus or local wake-up events provided to
the local wake-up pin WAKE.
Wake-up signals are:
• A falling edge at the local wake-up pin WAKE (see Chapter 7.1.1).
• A rising edge at the local wake-up pin WAKE (see Chapter 7.1.2).
• A dedicated wake-up pattern at the FlexRay bus (see Chapter 7.2.1 and Chapter 7.2.2).
• A wake-up pattern implemented in a standard FlexRay frame (see Chapter 7.2.3).
The Wake-up Detector is active in every mode of operation and works over the entire operating range as long
as uVBAT is in its functional range (see Table 20).
Detected wake-up events are analyzed by the Central State Machine and are compared with the overall device
status. They may cause a change of the operation mode (details see Chapter 9.5) and they may set a wake-up
flag or a wake-up bit (details see Chapter 7.3).
7.1 Local Wake-up
The TLE9221SX provides a local wake-up input WAKE, tailored to withstand voltages up to uVBAT(Max). Positive
and negative signal changes on the WAKE pin trigger the Wake-up Detector.
The WAKE input is provided with an internal pull-up and pull-down structure and an internal wake pulse filter
(see Figure 8).
Figure 8 Block diagram of the WAKE input
Depending on the signal at the WAKE input, either the pull-up structure or the pull-down structure is
connected to the WAKE input. While a voltage uVWAKE >uBDWake
Thr is applied to the WAKE input, the internal
pull-up structure is connected to the WAKE input. Conversely, while a voltage uVWAKE <uBDWake
Thr is applied
to the WAKE input, the internal pull-down structure is activated (see Figure 9).
VBAT
WAKE
GND
iBDWakeH
iBDWakeThr
Wake Pulse Filter
Wake-Up
Detector (dBDWakePulseFilter)
iBDWakeL
Data Sheet 28 Rev. 1.3, 2015-09-21
TLE9221SX
Wake-up Detector
Figure 9 Pull-up and pull-down at the WAKE input
7.1.1 Local Wake-up Falling Edge
Figure 10 Local wake-up falling edge
The TLE9221SX detects a falling edge (signal change from uVBAT to GND) at the WAKE pin, followed by a “low”
signal for the time period dBDWakePulseFilter as a local wake-up event (see Figure 10). The implemented
filter time dBDWakePulseFilter avoids that spikes at the WAKE signal are considered as valid wake-up events.
In BD_Sleep mode, BD_Standby mode and during the BD_GoToSleep command the state machine of the
TLE9221SX sets the local wake-up bit (bit 0) in the SIR (active logical “low”), when detecting a local wake-up
event. In non-low power modes, the detection of a local wake-up event is ignored and no status bit is set.
Together with the local wake-up bit, the TLE9221SX also sets the wake-up flag (active logical “low”). The wake-
up source bit (bit 12) remains at logical “high”, when a local wake-up event is detected.
uBDWake
Hys
iBDWake
iBDWakeL
iBDWakeH
pull-down current
pull-up current
uBDWake
uV
BAT
uBDWake
Thr
(min.)
uBDWake
Thr
(max.)
t
dBDWakePulseFilter
WAKE
uBDWakeThr
dBDWakeupReactionlocal
t
100% uVBAT
RxD
RxEN
BD_Sleep BD_Standby
wake-up detection
set local wake-up bit
Data Sheet 29 Rev. 1.3, 2015-09-21
TLE9221SX
Wake-up Detector
In low power modes or in the BD_GoToSleep command an active wake-up flag is indicated at the RxD and
RxEN output within the time period dBDWakeupReactionlocal (see Table 5). In case the transceiver is in
BD_Sleep mode, an active wake-up flag also triggers a mode change to BD_Standby mode (for details see
Table 17).
A local wake-up signal can be detected by the TLE9221SX only if the power supply uVBAT is available. The
detection of a local wake-up is working over the whole operating range of uVBAT (for details see Table 20).
The ERRN output indicates the wake-up event after the time dBDWakeLocal:
dBDWakeLocal = dBDWakePulseFilter + dBDWakeupReactionlocal
7.1.2 Local Wake-up Rising Edge
The WAKE input on the TLE9221SX is a bi-sensitive input and also a rising edge (signal change from GND to
uVBAT) at the pin WAKE is detected as a wake-up event (see Figure 11).
As on a local wake-up, triggered by a falling edge at the input pin WAKE, a rising edge also sets the local wake-
up bit and the wake-up flag respectively.
The internal state machine does not differentiate between a local wake-up triggered by a rising edge and a
falling edge at the pin WAKE. There is no possibility of distinguishing between the rising and falling edge, since
only one SIR entry is available.
Figure 11 Local wake-up rising edge
7.2 Remote Wake-up
For a remote wake-up, also called bus wake-up, a dedicated wake-up pattern is defined in FlexRay systems. A
wake-up pattern consists of at least two wake-up symbols. A wake-up symbol on the FlexRay bus is defined as
a phase of “Data_0” followed by a phase of “Idle” or alternatively a phase of “Data_0” followed by a phase of
“Data_1”. Bus wake-up patterns are detected by the Wake-up Detector and fed to the internal state machine.
The remote wake-up bit (bit 1) in the SIR is set, if the TLE9221SX detects a remote wake-up event in a low
power mode or during the BD_GoToSleep command, regardless of whether the wake-up was triggered by a
standard wake-up pattern or triggered by an alternative wake-up pattern or by a wake-up signal via payload.
t
dBDWakePulseFilter
WAKE
dBDWakeupReactionlocal
t
RxD
RxEN
BD_Sleep BD_Standby
wake-up detection
set local wake-up bit
uBDWakeThr
100% uVBAT
Data Sheet 30 Rev. 1.3, 2015-09-21
TLE9221SX
Wake-up Detector
At the same time that it sets the remote wake-up bit, the TLE9221SX also sets the wake-up flag and the wake-
up source bit. In non-low power modes, the detection of a remote wake-up event is ignored and neither the
remote wake-up bit nor the wake-up flag is set.
In low power modes or in the BD_GoToSleep command, an active wake-up flag is indicated at the RxD and
RxEN outputs within the time period dBDWakeupReactionremote (see Figure 12 and Table 5). In case the
transceiver remains in BD_Sleep mode an active wake-up flag also triggers a mode change to BD_Standby
mode (for details see Table 20).
To detect a remote wake-up event, at least one of the two power supplies needs to be available.
7.2.1 Standard Wake-up Pattern
The standard wake-up pattern is defined by at least two wake-up symbols starting with “Data_0”, followed by
an “Idle” signal. The pulse width for the “Data_0” needs to be at least t = dWU0Detect or longer. The pulse width
for the “Idle” phase shall not be below t = dWUIdleDetect. The maximum time for the standard wake-up pattern
shall not exceed t = dWUTimeout (see Figure 12). The pulse width for “Data_0” may vary between the two wake-
up symbols as long as the pulse width is not below t = dWU0Detect and the standard wake-up pattern does not
exceed t = dWUTimeout. Variation of the pulse width of the “Idle” phase is possible with the same limitations. The
standard wake-up pattern is independent of the data transmission rate.
The Wake-up Detector of the TLE9221SX distinguishes between “Data_0” and “Idle” by the differential bus
voltage. The bus voltage below the threshold uDATA0_LP is identified as a “Data_0” signal and the bus voltage
above the threshold uDATA0_LP is identified as an “Idle” or a “Data_1” signal. The Wake-up Detector does not
differentiate between an “Idle” or a “Data_1” signal.
Figure 12 Standard wake-up pattern
wake-up symbol
“Data_0”
uBus
wake-up symbol
wake-up pattern
t
dWU0Detect
dWUTimeout
dWUIdleDetect dWU0Detect
“Data_0”
uData0_LP
“Idle”
wake-up detection
set remote wake-up bit
RxD
RxEN
BD_Sleep BD_Standby
t
“Idle” “Idle”
dWUIdleDetect
dBDWakeupReactionremote
Data Sheet 31 Rev. 1.3, 2015-09-21
TLE9221SX
Wake-up Detector
7.2.2 Alternative Wake-up Pattern
The definition of the alternative wake-up pattern is similar to that of the standard wake-up pattern, the only
difference is that the wake-up symbols have no “Idle” signal. The “Idle” signal is replaced by a “Data_1” signal
(see Figure 13). The timing requirements for pulse width and time-out are the same as for the standard wake-
up pattern. The alternative wake-up pattern is also independent of the data rate.
Figure 13 Alternative wake-up pattern
7.2.3 Wake-up by Payload
Besides sending a dedicated wake-up pattern on the FlexRay bus, it is also possible to wake up the TLE9221SX
with a wake-up message hidden in the data field of the standard FlexRay frame, called wake-up by payload.
In comparison to the wake-up by standard pattern or to the wake-up with an alternative pattern, the wake-up
by payload is limited to a data transmission rate of 10 Mbit/s.
A dedicated Byte Start Sequence is transmitted before each byte of the payload within the FlexRay data
frame.The Byte Start Sequence (BSS) consists of one “high” bit followed by one “low” bit. To transmit a
“Data_0” byte to the FlexRay bus, the FlexRay controller sends 10 bits. First a “high” bit as part of the Byte Start
Sequence, followed by a “low” bit which also belongs to the Byte Start Sequence and after the Byte Start
Sequence, the controller sends eight “low” bits (HL= BSS; LLLLLLLL= “Data_0”). Sending a “Data_1” byte the
FlexRay controller sends a “high” bit followed by a “low” bit and then sends eight consecutive “high” bits (HL=
BSS; HHHHHHHH= “Data_1”) (see Figure 14).
At a data rate of 10 Mbit/s, one bit in the FlexRay data frame has a bit length of 100 ns. This means that each
data byte in a wake-up pattern has one glitch of 100 ns.
The Wake-up Detector of TLE9221SX has an analog input filter implemented, which filters out the glitches on
the wake-up pattern for glitches shorter than t = dWUInterrupt.
Receiving a complete wake-up by payload, the TLE9221SX sets the remote wake-up bit, the wake-up flag and
also the wake-up source bit. The wake-up flag is set in case the following data pattern is detected in a FlexRay
frame.
wake-up symbol
“Data_0”
uBus
wake-up symbol
wake-up pattern
t
dWU0Detect
dWUTimeout
dWUIdleDetect dWU0Detect
“Data_0”
uData0_LP
“Idle”
wake-up detection
set remote wake-up bit
RxD
RxEN
BD_Sleep BD_Standby
t
“Data_1” “Data_1”
dWUIdleDetect
dBDWakeupReactionremote
Data Sheet 32 Rev. 1.3, 2015-09-21
TLE9221SX
Wake-up Detector
In case any incomplete wake-up pattern is received, no wake-up flag is set and no entry is made to the SIR.
Figure 14 Wake-up by payload
7.3 Wake-up Flag and Wake-up Bits
The wake-up flag and the SIR latch the wake-up event and allow an external microcontroller to read out the
wake-up source. The TLE9221SX provides three bits in the SIR for the wake-up information:
• The local wake-up bit (bit 0)
• The remote wake-up bit (bit 1)
• The wake-up source bit (bit 12)
Even if the Wake-up detector is active in every operation mode, the wake-up bits can only be set in low power
mode or in the BD_GoToSleep command. In every other operation mode no wake-up bit is set (see Table 11).
The local wake-up bit is set in case the TLE9221SX detects a local wake-up event and in case of a remote wake-
up event the remote wake-up bit is set. A remote wake-up can be a wake-up either by a standard pattern, a
wake-up by an alternative pattern or a wake-up by payload.
In case the TLE9221SX detects a local and a remote wake-up event, both entries in the SIR bits are set.
Table 10 Wake-up Payload Content
0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00
0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00
0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00
0xFF 0xFF 0xFF 0xFF 0xFF 0xFF
uBus
wake-up symbol wake-up symbol
wake-up pattern
t
dWU0Detect
dWUTimeout
“Data_1”
“Data_0”“Data_0”
“Data_1”
dWUIdleDetect dWU0Detect
dWUInterrupt
dWUIdleDetect
uData0_LP
Data Sheet 33 Rev. 1.3, 2015-09-21
TLE9221SX
Wake-up Detector
Concurrent with the local wake-up bit or with the remote wake-up bit, the wake-up source bit and the wake-
up flag are set. The wake-up source bit is “high” when detecting a local wake-up event and “low” when a
remote wake-up event is detected. Only the first wake-up event is indicated in the wake-up source bit. In case
the TLE9221SX detects a local and a remote wake-up event simultaneously, the wake-up source bit output
indicates the remote wake-up event.
The SIR is reset either after a complete read-out of the SIR (see Chapter 6.2.3) or when the TLE9221SX enters
into BD_Normal mode. The wake-up flag is reset if both bits, the local wake-up bit and the remote wake-up bit
are reset.
The wake-up flag and the wake-up source bit are indicated at the ERRN output pin of the Host Interface (see
Table 9).
Table 11 Setting the wake-up flag and the wake-up bits
Modes of Operation Wake-up
Event
Local
Wake-up Bit1)
1) Not set = logical “high”, Set = logical “low”
Remote
Wake-up Bit1)
Wake-up
Source Bit1)
Wake-up Flag1)
BD_GoToSleep Remote “high” “low” “low” “low”
Local “low” “high” “high” “low”
BD_Standby Remote “high” “low” “low” “low”
Local “low” “high” “high” “low”
BD_Sleep Remote “high” “low” “low” “low”
Local “low” “high” “high” “low”
Data Sheet 34 Rev. 1.3, 2015-09-21
TLE9221SX
Power Supply Interface
8 Power Supply Interface
The Power Supply Interface distributes the correct voltages to the single function blocks within the
TLE9221SX. It manages the power-up and power-down procedures, monitors the supply voltages uVBAT, uVCC
and also the reference voltage uVIO. To control external circuitry, an INH output is available (see Figure 16).
Figure 15 Block diagram of Power Supply Interface
The Central State Machine is the main logic control unit of the TLE9221SX. All functions, including operation
mode management, the diagnostic function and failure management are controlled and handled by the
Central State Machine. To ensure correct failure management, the Central State Machine is the first function
block which is powered up and the last function block which is powered down. For this reason, the Central
State Machine is supplied by an internal supply uVIN (see Figure 15).
The internal supply uVIN is in its operational range, if at least one of the two power supplies, uVCC or uVBAT, is
above their power-down threshold, uBDBPVBAT or uVBDPDVCC.
Note: The reference voltage uVIO is the level shift supply for all digital inputs and outputs. It is not connected
with the internal supply of the central state machine. Nevertheless, if the reference voltage uVIO is not
available or in undervoltage condition, the internal state machine blocks all host commands and
changes the mode of operation to a low power mode.
Host Interface
Communication Controller
Interface
Bus Guardian Interface
Voltage Monitor
Internal Supply
Central
State
Machine
VBAT
VCC
VIO
VIN
INH
Driver
Data Sheet 35 Rev. 1.3, 2015-09-21
TLE9221SX
Power Supply Interface
8.1 INH Output
The INH output signal is intended to control an external voltage regulator. When the FlexRay transceiver
TLE9221SX is in BD_Sleep mode, the INH output is open and floating. In every other operation mode the INH
output voltage is uINH1Not-Sleep. The voltage uINH1Not-Sleep is derived from the power supply uVBAT by an internal
open drain transistor (see Figure 16).
The transceiver TLE9221SX signals “Sleep” at the INH pin, while the device is in BD_Sleep mode and
“Not_Sleep” in any other mode of operation (BD_Standby, BD_Normal, BD_ReceiveOnly and the
BD_GoToSleep command).
Figure 16 Circuit diagram of the INH output
8.2 BD_Off and Undervoltage
The FlexRay transceiver TLE9221SX monitors the two power supplies uVCC and uVBat and also the reference
voltage uVIO. In case one of the three voltages falls below its dedicated undervoltage detection threshold, the
TLE9221SX changes its mode of operation to low power mode (see Figure 17). For undervoltage condition, the
Central State Machine is still functional.
VBAT (11) INH
State
Machine
(1)
uVBAT
uINH1Not_Sleep
t
U
“Not_Sleep”
(BD_Sleep)
(BD_Normal)
(BD_ReceiveOnly)
(BD_Standby)
(BD_GoToSleep)
“Sleep” 1)
1) The INH output is usually floating.
To achive a “low” signal on the INH output an external load is required.
Data Sheet 36 Rev. 1.3, 2015-09-21
TLE9221SX
Power Supply Interface
Figure 17 Logic diagram of undervoltage detection
The BD_Off state of the FlexRay transceiver TLE9221SX is reached, if both power supplies, uVBAT and uVCC are
below the power-down thresholds uBDPDVBAT and uBDPDVCC. In comparison to undervoltage detection the
reference supply uVIO has no effect on the BD_Off state. Regardless of whether the uVIO voltage is available or
not, the FlexRay transceiver TLE9221SX always changes over to the power-down state BD_Off in case uVBAT
and uVCC are not present (see Figure 18).
≥1
block
host commands
delay line low power
mode
uVBAT
uVCC
uVIO
uBDUVVBAT
uUVIO
uBDUVVCC
+
-
+
-
+
-
Data Sheet 37 Rev. 1.3, 2015-09-21
TLE9221SX
Power Supply Interface
Figure 18 Logic diagram of BD_Off detection
Note: When the transceiver TLE9221SX is in BD_Off state, the Central State Machine is powered down. All
registers in TLE9221SX are built of volatile memory and therefore, all status, diagnostic, and failure
information is reset.
8.3 Undervoltage Events
8.3.1 Undervoltage Flags and Undervoltage Bits
Detected undervoltage events are stored using a dedicated undervoltage bit and they are visible in the SIR.
Along with the undervoltage bit a summary bit, the error bit (bit 11), is set. The error bit is indicated at the
ERRN output, depending on the selected operation mode (see Table 9 and the example in Figure 19).
The TLE9221SX provides three bits in the SIR to signal undervoltage events:
•uV
BAT undervoltage bit (bit 8)
•uV
CC undervoltage bit (bit 9)
•uV
IO undervoltage bit (bit 10)
Undervoltage bits are used to store the information for further use. Therefore undervoltage bits get cleared
only by a power-down or by clearing the SIR (see Chapter 6.2.3).
In comparison to the undervoltage bits, undervoltage flags are not latched and they are only used to trigger
the changes of the operation mode. Undervoltage flags are not visible externally.
An undervoltage event on any supply line directly sets the dedicated undervoltage bit and also the error bit.
The undervoltage flags are set by internal timers. An internal undervoltage detection timer is available for
every supply, uVBAT, uVCC and uVIO. While setting the undervoltage bit, the appropriate undervoltage detection
timer is also triggered. When the undervoltage detection timer expires, while the undervoltage event is still
present, the undervoltage flag is set (see Figure 19).
&BD_Off
uVBAT
uBDPDVBAT
uVCC
uBDPDVCC
+
-
+
-
Data Sheet 38 Rev. 1.3, 2015-09-21
TLE9221SX
Power Supply Interface
In case the undervoltage situation gets cleared while the undervoltage detection timer is running, the
TLE9221SX does not set the undervoltage flag. According to the mode change table, an active undervoltage
flag changes the mode of operation to low power mode (see
and Table 16).
Figure 19 Example of setting the undervoltage flag
Besides the undervoltage detection timer, each supply is also equipped with an undervoltage recovery timer.
The undervoltage recovery timer starts when the external power supply recovers. When the undervoltage
recovery timer expires, the undervoltage flag gets reset (see Figure 19). If the external power supply recovers
only temporarily and the supply line falls back to the undervoltage situation while the undervoltage recovery
timer is still running, the undervoltage flag remains set. Clearing the undervoltage flag allows the transceiver
TLE9221SX to return from low power mode to the previous operational mode selected by the host command
(see Chapter 9.4 and Table 17).
Note: Undervoltage bits are set by an undervoltage event. Undervoltage bits are stored in the SIR and also
indicated at the ERRN output.
Undervoltage flags are set by the undervoltage detection timer. Undervoltage flags are not visible in the
SIR and they are not indicated at the ERRN output. Undervoltage flags are only used to change the mode
of operation after the undervoltage detection timer has expired!
8.3.2 Undervoltage Event at uVBAT
The FlexRay transceiver TLE9221SX considers a voltage fluctuation on the power supply uVBAT, which falls
below the detection threshold uBDUVVBAT and exceeds the blanking time dBDUVBAT_BLK, as an undervoltage
event. Voltage fluctuations on uVBAT shorter than dBDUVBAT_BLK are ignored and not recognized by the Power
uV
BAT
t
BD_Normal
dBDUVVBAT
dBDRVBAT
t
STBN
t
EN
set undervoltage flag
BD_Sleep BD_Normal
clear undervoltage flag
t
ERRN
undervoltage detection timer undervoltage release timer
dReactionTimeERRN
set undervoltage bit
set error bit
dBDUVVBAT_BLK
Data Sheet 39 Rev. 1.3, 2015-09-21
TLE9221SX
Power Supply Interface
Supply Interface. To indicate the undervoltage event on the supply voltage uVBAT, the uVBAT undervoltage bit
(bit 8) and the error bit (bit 11) are set (see Figure 20). After the uVBAT undervoltage detection timer dBDUVVBAT
expires, the uVBAT undervoltage flag is set and the mode of operation changes to BD_Sleep mode.
The Host Interface and the Communication Controller Interface are active while the dBDUVVBAT undervoltage
detection timer is running and the reference supply uVIO is present. When the dBDUVVBAT undervoltage
detection timer expires and the uVBAT undervoltage flag is set, the Host Interface and the Communication
Controller Interface are blocked as long as the uVBAT undervoltage flag remains active (compare also with
Chapter 9.3 and Table 16).
Figure 20 Undervoltage event at uVBAT in non-low power mode
8.3.3 Undervoltage Event at uVCC
Power supply voltage fluctuations on the uVCC power supply, falling below the threshold uBDUVVCC for a time
longer than the blanking time dBDUVVCC_BLK, are considered as undervoltage events. Voltage fluctuations on
uVCC shorter than the time dBDUVCC_BLK are ignored and not recognized by the Power Supply Interface.
Detecting an undervoltage event on uVCC, the FlexRay transceiver TLE9221SX sets the uVCC undervoltage bit
(bit 9) and the error bit (bit 11) (see Figure 21). After the uVCC undervoltage detection timer dBDUVVCC expires,
the uVCC undervoltage flag is set, the mode of operation changes to BD_Standby mode.
The Host Interface remains active while the uVCC undervoltage detection timer is running and the reference
supply uVIO is present. Setting the uVCC undervoltage flag blocks the Host Interface and forces the mode of
operation to BD_Standby mode (compare also with Chapter 9.3 and Table 16).
While the power supply uVCC is in undervoltage condition, the TLE9221SX also disables the Transmitter and
sets the bus error bit (bit 4).
uVBAT
t
non-low power mode
t < dBDUVVBAT_BLK
dBDUVVBAT_BLK
dBDUVVBAT
dBDRVBAT
set uVBAT undervoltage flag,
block host commands
clear uVBAT undervoltage flag,
release host commands
(return to the mode of operation
selected by the host command)
BD_Sleep
uBDUVVBAT (Threshold)
dReactionTimeERRN
t
ERRN
set uVBAT undervoltage bit
set error bit
dBDUVVBAT_Hys
Data Sheet 40 Rev. 1.3, 2015-09-21
TLE9221SX
Power Supply Interface
Figure 21 Undervoltage event at uVCC in non-low power mode
8.3.4 Undervoltage Event at uVIO
The Central State Machine of the TLE9221SX handles an undervoltage event at the reference supply uVIO in a
manner identical to an undervoltage event on the power supply uVBAT.
The supply on the level shift input VIO is the main reference for all digital inputs and outputs of the TLE9221SX.
It is also connected to the pad supply of the external microcontroller (see Figure 44). An undervoltage event
on the level shift input VIO could lead to a misinterpretation of the digital input levels and could generate a
false signal at the digital outputs.
For fail-safe reasons, the TLE9221SX blocks the Host Interface, the Communication Controller Interface and
the Bus Guardian Interface after a small processing time (dReactionTimeERRN) when an undervoltage event has
been detected on the reference supply uVIO (see Figure 22). According to Table 2, all digital inputs are set to
their default level. All digital outputs are set to logical “low”.
The transceiver TLE9221SX detects an undervoltage event, if the supply at the pin VIO drops for the time period
t>dBDUVV
IO_BLK below the undervoltage detection threshold uUVIO (see Figure 22). Voltage fluctuations on
uVIO shorter than dBDUVCC_BLK are ignored and not recognized by the Power Supply Interface.
Although the Host Interface is blocked and the SIR is not accessible while the reference supply uVIO is in
undervoltage condition, the transceiver sets the uVIO undervoltage bit (bit 10) and the error bit (bit 11) (see
Figure 22). After the uVIO undervoltage detection timer dBDUVVIO expires, the uVIO undervoltage flag is set and
the mode of operation changes to BD_Sleep mode (compare also to Chapter 9.3 and Table 16).
uV
CC
t
non-low power mode
t < dBDUVV
CC_BLK
dBDUVV
CC_BLK
dBDUVV
CC
dBDRV
CC
set uV
CC
undervoltage flag,
block host commands
clear uV
CC
undervoltage flag,
release host commands
(return to the mode of operation
selected by the host command)
BD_Standby
uBDUVV
CC
(Threshold)
dReactionTime
ERRN
t
ERRN
set uV
CC
undervoltage bit
set error bit
uBDUVV
CC_Hys
Data Sheet 41 Rev. 1.3, 2015-09-21
TLE9221SX
Power Supply Interface
Figure 22 Undervoltage event at uVIO in non-low power mode
Note: While the TLE9221SX is in undervoltage condition at the reference supply uVIO, all digital outputs are set
to “low”. The outputs do not reflect the status of the transceiver anymore.
For example, wake-up events cannot be indicated at the ERRN, RxD, and RxEN output anymore, since
these outputs are set permanently to “low”.
8.4 Power-up and Power-down
8.4.1 BD_Off State
BD_Off state is reached, when the transceiver does not receive any supply.
The transceiver TLE9221SX is in BD_Off state when the internal supply voltage uVIN is turned off and the
Central State Machine is powered down. When both power supplies, uVCC and uVBAT fall below their power-
down thresholds (uBDPDVBAT and uBDPDVCC), the internal supply is off and the BD_Off state is reached (see
Figure 23).
The status of the reference supply uVIO has no influence on the power-down sequence of the Flexray
transceiver TLE9221SX.
When the FlexRay transceiver TLE9221SX is in BD_Off state, all outputs are logical “low”, the Transmitter and
the Receiver are turned off and the wake-up functions are not operational. If the reference supply uVIO is
available, the inputs are set to their default values (compare with Table 2).
uV
IO
W
QRQORZSRZHUPRGH
t < dBDUVV
IO_BLK
dBDUVV
IO_BLK
G%'59
,2
%'B6OHHS%'B6WDQGE\
uUV
IO
(Threshold)
set uV
IO
undervoltage bit
set error bit
dBDUVV
IO
dBD
ModeChange
set uV
IO
undervoltage flag
clear uV
IO
undervoltage flag,
release host commands
(return to the mode of operation
selected by the host command)
dReactionTime
ERRN
t
ERRN
set all output pins “low”
set all input pins to default
block all host commands
uUV
IO_Hys
Data Sheet 42 Rev. 1.3, 2015-09-21
TLE9221SX
Power Supply Interface
Figure 23 Power-down
8.4.2 Power-up
For the power-up, only the power supplies uVBAT and uVCC are significant. As soon as at least one power supply
is above its reset threshold the internal supply uVIN is available and the Central State Machine gets powered
up. The device TLE9221SX enters into BD_Standby mode within the time period dBDPowerUp as soon as the
voltage values of the power supplies uVBAT and uVCC are above their undervoltage detection threshold limits
uBDUVVBAT and uBDUVVCC (see Figure 24).
dBDPDV
CC
dBDPDV
BAT
uV
BAT
uV
CC
V
t
any operation mode BD_Off
uV
IO
Data Sheet 43 Rev. 1.3, 2015-09-21
TLE9221SX
Power Supply Interface
Figure 24 Power-up
8.4.3 Interim BD_Standby Mode
As a safety measure, the TLE9221SX provides an Interim BD_Standby mode. Changeover to the
Interim_BD_Standby mode takes place during an incomplete power-up procedure (see Figure 25).
In Interim_BD_Standby mode, the TLE9221SX provides the same functions as in BD_Standby mode, except for
the host commands. The host commands are blocked in Interim BD_Standby mode. Therefore, a host
command cannot be used to change the mode of the TLE9221SX, while the power-up has not completed. With
switching over to the interim BD_Standby mode, at least one undervoltage detection timer is started. In case
the power-up is completed before the undervoltage detection timer expires, the TLE9221SX changes the
mode of operation to BD_Standby mode. In case the undervoltage detection timer expires before the power-
up is completed, the undervoltage flag is set depending on which power supply is missing, and the mode of
operation changes to low power mode (compare with Chapter 9.3).
uV
BAT
uV
CC
V
t
uV
IO
dBD
PowerUp
powering up the
Central State Machine
BD_Off Interim_BD_Standby BD_Standby
uBDUV
BAT
uBDPD
BAT
uBDUVV
CC
Host Interface blocked Host Interface released
Data Sheet 44 Rev. 1.3, 2015-09-21
TLE9221SX
Power Supply Interface
Figure 25 Changing over to Interim_BD_Standby mode
power-up
uVBAT > uBDUVVBAT
AND
uVCC > uBDUVVCC
uVBAT < uBDUVVBat
OR
uVCC < uBDUVVCC
BD_Standby
(host commands
released!)
Interim
BD_Standby
set uVCC undervoltage flag
t > dBDUVVCC 1)
t < dBDUVVBAT
AND
uVBAT > uBDUVVBAT
AND
t < dBDUVVCC
AND
uVCC > uBDUVVCC
set uVBat undervoltage flag
BD_Sleep
1) uVBAT undervoltage overrules uVCC undervoltage
t > dBDUVVBAT 1)
host command: EN=“0”, STBN=“0”, BD_Standby mode
BD_Standby
(host commands
blocked!)
uVCC > uBDUVVCC
uVBAT > uBDUVVBAT
Data Sheet 45 Rev. 1.3, 2015-09-21
TLE9221SX
Operating Mode Description
9 Operating Mode Description
The FlexRay transceiver TLE9221SX provides several different operating modes. The four main operating
modes are implemented to handle the requirements of a FlexRay ECU. Two product-specific interim operation
modes are implemented to guarantee secure mode changes even under failure conditions. The BD_Off state
describes the behavior of the TLE9221SX, while it is not supplied (see Table 12).
9.1 Operating Mode Transitions Overview
Depending on the currently selected operating mode, several events can trigger a change of the operating
mode. The options are:
• A valid host command at the Host Interface.
• Setting an undervoltage flag, either for the power supplies uVBAT and uVCC or for the reference voltage uVIO.
• Recovery from an undervoltage event, either for the power supplies uVBAT and uVCC or for the reference
voltage uVIO.
• Wake-up detection either on the FlexRay bus or on the local wake-input WAKE.
• A power-up event at the power supplies uVBAT and uVCC.
It is not possible to change over to every operating mode by a trigger event. There are limitations and
dependencies (see Table 13).
Table 12 Operating modes overview
Modes of Operation Description Clustering
Operating mode
BD_Normal Normal operating mode to transmit data to the bus and receive
data from the bus.
non-low power mode
BD_ReceiveOnly The TLE9221SX can receive data from the bus, but the
Transmitter is blocked.
non-low power mode
BD_Standby Transmitter and Receiver are turned off, the diagnostic
functions and wake-up detection are available.
low power mode
BD_Sleep All functions, except the wake-up detection are turned off. low power mode
Product-specific operating modes
BD_GoToSleep Transition mode to change over to the BD_Sleep mode via a
host command.
interim mode
Interim_BD_Standby Transition mode, to which a changeover is made only after an
incomplete power-up
interim mode
Power-Down
BD_Off State of the TLE9221SX when no supply is fed to it power-down state
Data Sheet 46 Rev. 1.3, 2015-09-21
TLE9221SX
Operating Mode Description
9.2 Operating Mode Change by Host Command
Changeover can be made to every operation mode, except the BD_Sleep mode by a valid host command,
when no undervoltage flag is set. Changeover to BD_Sleep mode can be made only via the BD_GoToSleep
command (see Figure 26 and Table 14).
Table 13 Options for changeover to various operating modes
Target Mode Trigger Event for the Mode Change Limitation
BD_Normal Changeover to BD_Normal mode can be made only
by a valid host command.
Host commands are blocked if
any undervoltage flag is set.
BD_ReceiveOnly Changeover to BD_ReceiveOnly mode can be made
only by a valid host command.
Host commands are blocked if
any undervoltage flag is set.
BD_Standby Changeover to BD_Standby mode can be made by:
• A valid host command
• An undervoltage event at uVCC
• A wake-up event
• A power-up event at uVCC and uVBAT
Changeover to BD_Standby
mode cannot be made from
BD_Sleep mode via host
command (see Figure 26).
Host commands are blocked if
any undervoltage flag is set.
BD_Sleep Changeover to BD_Sleep mode can be made by:
• A valid host command
• An undervoltage event at uVIO or uVBAT
Changeover to BD_Sleep mode
by a host command is possible
only via the BD_GoToSleep
command (see Figure 26).
Host commands are blocked if
any undervoltage flag is set.
BD_GoToSleep Changeover to BD_GoToSleep command can only
be made by a valid host command.
The BD_GoToSleep command
can not be executed while the
wake-up flag is active (see
Table 14).
Host commands are blocked if
any undervoltage flag is set.
Interim_BD_Standby Changeover to Interim_BD_Standby mode takes
place only after an incomplete power-up.
–
BD_Off Changeover to BD_Off condition takes place if the
power supplies uVBAT and uVCC are below their reset
thresholds.
–
Data Sheet 47 Rev. 1.3, 2015-09-21
TLE9221SX
Operating Mode Description
Figure 26 Operating mode change by host command
ENSTBN
LL
INH
Not_Sleep
BD_Standby
ENSTBN
LX
INH
Sleep
BD_Sleep
ENSTBN
LH
INH
Not_Sleep
BD_ReceiveOnly
EN
STBN
HH
INH
BD_Normal
1
BD_GoToSleep
ENSTBN
LH
INH
Not_Sleep
4
2
3
17
5 6 8
7
11
9
10
12
13
14
15 16
18
19
21
20
Not_Sleep
TLE9221SX
Operating Mode Description
Data Sheet 48 Rev. 1.3, 2015-09-21
Table 14 Mode changes by host command1) 2) 3) 4)
No. Primary
Operating Mode
STBN EN Wake-up
Flag
uVBAT
Flag
uVIO
Flag
uVCC
Flag
Secondary
Operating Mode
ERRN5) RxD6) RxEN6) INH Remarks
BD_Normal Mode
1BD_Normal H set “L” HHHH1 => BD_ReceiveOnly H FB FB Not_Sleep 7)
2BD_Normal set “L” HH HHH1 => BD_GoToSleep H1 => H 1 => H Not_Sleep 7)
3BD_Normal set “L” set “L” HHHH1 => BD_Standby H1 => H 1 => H Not_Sleep 7)
BD_ReceiveOnly Mode
4BD_ReceiveOnlyH set “H” 2 => H HHH1 => BD_Normal 2 => H FB FB Not_Sleep 7)
5BD_ReceiveOnlyset “L” LH HHH1 => BD_Standby H1 => H 1 => H Not_Sleep 7)
6BD_ReceiveOnlyset “L” LL HHH1 => BD_Standby 1 => L 1 => L 1 => L Not_Sleep 8)
7BD_ReceiveOnlyset “L” set “H” HHHH1 => BD_GoToSleep H1 => H 1 => H Not_Sleep 9)
8BD_ReceiveOnlyset “L” set “H” LHHH1 => BD_Standby 1 => L 1 => L 1 => L Not_Sleep 8), 10)
BD_GoToSleep Command
9 BD_GoToSleep set “H” H2 => H HHH1 => BD_Normal 2 => H 1=>FB 1=>FB Not_Sleep 9), 11)
10 BD_GoToSleep L set “L” HHHH1 => BD_Standby HHHNot_Sleep
9), 11)
11 BD_GoToSleep set “H” set “L” HHHH1 => BD_ReceiveOnly H1=>FB 1=>FB Not_Sleep 9), 11)
12 BD_GoToSleep L H H H H H 1 => BD_Sleep HHH1 => Sleep 9), 11)
BD_Standby
13 BD_Standby L set “H” HHHH1 => BD_GoToSleep HHHNot_Sleep
9)
14 BD_Standby L set “H” LHHHBD_Standby LLLNot_Sleep
10)
15 BD_Standby set “H” L H H H H 1 => BD_ReceiveOnly H1=>FB 1=>FB Not_Sleep –
16 BD_Standby set “H” L L H H H 1 => BD_ReceiveOnly 1 => H/L 1=>FB 1=>FB Not_Sleep 12)
17 BD_Standby set “H” set “H” 2 => H HHH1 => BD_Normal 2=> H 1=>FB 1=>FB Not_Sleep 7)
BD_Sleep
18 BD_Sleep L set “H” HHHHBD_Sleep HHHSleep 13), 14)
19 BD_Sleep L set “L” HHHHBD_Sleep HHHSleep 13), 14)
TLE9221SX
Operating Mode Description
Data Sheet 49 Rev. 1.3, 2015-09-21
20 BD_Sleep set “H” set “H” 2 => H HHH1 => BD_Normal 2 => H 1=>FB 1=>FB 1 => Not_Sleep 7), 14)
21 BD_Sleep set “H” set “L” HHHH1 => BD_ReceiveOnly H1=>FB 1=>FB 1 => Not_Sleep 14)
1) The table describes the states and signals of flags, operating modes and output pins. This table does not contain any timing information. Time for mode changes or the response
time of the digital outputs are specified in the electrical characteristics (compare with Table 22).
2) All flags are “low” active. “L” means the flag is set. “X” = “don’t care”.
The color red stands for the event which triggered the mode transition.
For example: set “L” or set “H”.
The color blue stands for the consequence of the trigger event.
The numbers, “1 =>”, “2 =>” indicate the order of the consequences.
For example: “1=> BD_Normal” means the transceiver TLE9221SX changes over to BD_Normal mode.
“2=> H” means the flag is cleared after the TLE9221SX has changed over to BD_Normal mode.
“FB” stands for “Follow Bus” and means that depending on the signal on the FlexRay bus, the pins RxD and RxEN can either be “high” or “low”.
3) The wake-up flag stands for a detected wake-up event (compare with Chapter 7.3 and Table 10).
The uVBAT flag is the same as the uVBAT undervoltage flag, which is set after the uVBAT undervoltage detection timer expires (compare with Chapter 8.3.1).
The uVIO flag is the same as the uVIO undervoltage flag, which is set after the uVIO undervoltage detection timer expires (compare with Chapter 8.3.1).
The uVCC flag is the same as the uVCC undervoltage flag, which is set after the uVCC undervoltage detection timer expires (compare with Chapter 8.3.1).
4) The ERRN output indicates the wake-up flag, the wake-up source bit and the error bit (compare with Table 9). The error bit is set only by the undervoltage bits, such as the uVBAT
undervoltage bit (bit 8), the uVCC undervoltage bit (bit 9) and the uVIO undervoltage bit (bit 10). All other possible sources setting the error bit, such as, for example a bus failure or
an overtemperature event, are considered as not set in this table.
5) The signal at the ERRN output pin depends on the host command applied and not on the current operating mode (compare with Chapter 6.3).
6) The signals at the RxD and RxEN outputs depend on the current operation mode, and are independent of the host command applied (compare with Table 5).
7) While TLE9221SX changes over to BD_Normal mode, the wake-up flag is cleared. Moreover, the wake-up flag cannot be set in non-low power mode, and therefore the wake-up flag
is always “high” in BD_Normal mode (see Chapter 7.3).
8) The wake-up flag was set during a previous wake-up event while the TLE9221SX was in low power mode.
9) The interim mode will automatically be left to BD_Sleep when the timer dBDSleep expires. If the host command does not change within the time dBDSleep, the TLE9221SX changes
over by default to BD_Sleep mode (see Chapter 9.2.1).
10) The BD_GoToSleep command cannot be executed while the wake-up flag is active (see Figure 28). The TLE9221SX changes over directly to BD_StandBy mode.
11) Since the BD_GoToSleep command can be executed only when the wake-up flag is cleared, the wake-up flag is always “high” while the TLE9221SX executes the BD_GoToSleep
command.
12) If the host command BD_ReceiveOnly mode is applied, the ERRN output indicates the wake-up source bit (see Table 9).
Table 14 Mode changes by host command1) 2) 3) 4)
No. Primary
Operating Mode
STBN EN Wake-up
Flag
uVBAT
Flag
uVIO
Flag
uVCC
Flag
Secondary
Operating Mode
ERRN5) RxD6) RxEN6) INH Remarks
TLE9221SX
Operating Mode Description
Data Sheet 50 Rev. 1.3, 2015-09-21
13) The EN input pin of the Host Interface is disabled in BD_Sleep mode, as long the STBN input pin remains “low” (see Chapter 9.2.2).
14) A wake-up event would change the operation mode from BD_Sleep to BD_Standby, therefore, the wake-up flag is always “high” while the TLE9221SX remains in BD_Sleep mode.
Data Sheet 51 Rev. 1.3, 2015-09-21
TLE9221SX
Operating Mode Description
9.2.1 Entering BD_Sleep Mode via the BD_GoToSleep Command
The BD_GoToSleep command can be executed from every non-low power mode and from BD_Standby mode
by applying the host command STBN = “L” and EN = “H”. The BD_GoToSleep command cannot be executed
from BD_Sleep mode (see Figure 26).
When the transceiver TLE9221SX recognizes the host command BD_GoToSleep, the TLE9221SX changes over
to the interim mode “BD_GoToSleep command” and starts an internal timer. In case the EN input and the
STBN input remain unchanged during the BD_Sleep mode detection window (t = dBDSleep), the operating
mode automatically changes over to BD_Sleep mode. The time for the mode change, dBDModeChange, is defined
as the time interval between applying the host command and changing over to BD_Sleep mode (see
Figure 27).
Figure 27 Entering BD_Sleep mode
The BD_GoToSleep command can be executed only when the wake-up flag is cleared. When the wake-up flag
is cleared, the output pins RxD and RxEN are set to logical “high” in BD_Sleep mode and also during the
execution of the “BD_GoToSleep command”.
In case the changeover to BD_Sleep mode is made by a host command, the EN input is disabled in BD_Sleep
mode (see Figure 26, Figure 27 and Table 14).
Applying the BD_GoToSleep host command to the TLE9221SX, while the wake-up flag is active, changes the
operating mode directly to BD_Standby mode. The RxD and RxEN outputs are set to “low” and indicate a
previous wake-up event (see Figure 28 and Table 14).
EN
STBN
INH
BD_GoToSleep command
t
t
t = dBDLogicFilter
host command detection
BD_Sleep mode
t = dBDSleep
don’t care
BD_Normal mode
t
RxD
t
RxEN follow Bus
t = dBDModeChange
t
ERRN
All wake-up bits and the error bit are cleared, therefore the ERRN, RxD and RxEN outputs are “high”
Data Sheet 52 Rev. 1.3, 2015-09-21
TLE9221SX
Operating Mode Description
Figure 28 Changing over to BD_Standby, with an active wake-up flag
9.2.2 Quitting BD_Sleep by Host Command
Changeover to BD_Sleep mode can be made by a host command or by an undervoltage event. In case
changeover to BD_Sleep was made by a host command via the BD_GoToSleep command, the EN input pin
gets disabled when the TLE9221SX changes over to BD_Sleep mode.
As long as the STBN input pin remains at logical “low”, any signal change at the EN input is ignored and does
not trigger any mode change. Signal change at the STBN input pin enables the EN input as well and a mode
change is possible.
Via a host command, BD_Sleep mode can only change to BD_Normal mode or to BD_ReceiveOnly mode (see
Figure 26 and Table 14).
9.3 Operating Mode Changeover by Undervoltage Flag
Besides a valid host command, any changeovers in the operating mode may also be triggered by setting the
undervoltage flag after the undervoltage detection timer has expired (compare with Chapter 8.3.1). Setting
the uVIO or the uVBAT undervoltage flag changes the mode of operation to BD_Sleep, and setting the uVCC
undervoltage flag changes the mode of operation to BD_Standby.
If the transceiver TLE9221SX changes over to BD_Sleep mode by setting the uVIO or uVBAT undervoltage flag,
the EN input pin remains active even in BD_Sleep mode.
EN
STBN
INH
mode transition
t
t
t = dBDLogicFilter
host command detection
BD_Standby mode
don’t care
BD_ReceiveOnly mode
t
RxD
t
RxEN follow Bus
t = dBDModechange
Data Sheet 53 Rev. 1.3, 2015-09-21
TLE9221SX
Operating Mode Description
In case any undervoltage flag becomes active, while the FlexRay transceiver TLE9221SX is executing the
BD_GoToSleep command, the mode of operation changes directly to BD_Sleep (see Table 15 and Figure 29).
Setting the undervoltage flag does not cause any change in the operating mode, if the transceiver is already in
BD_Sleep mode.
Figure 29 Operating mode changes by undervoltage flag
ENSTBN
LH
INH
Sleep
BD_Sleep
EN
STBN
HH
INH
BD_Normal
BD_GoToSleep
ENSTBN
LH
INH
Not_Sleep
24
38 39
Not_Sleep
ENSTBN
LL
INH
Not_Sleep
BD_Standby
40
31
32
30
33
34
35
36
ENSTBN
LH
INH
Not_Sleep
BD_ReceiveOnly
25
26
27
28
22
23 37
BD_Off
uVBAT > uBDUVVBAT
and
uVCC > uBDUVVCC
29
TLE9221SX
Operating Mode Description
Data Sheet 54 Rev. 1.3, 2015-09-21
Table 15 Mode changes by setting the undervoltage flags 1) 2) 3) 4)
No. Primary
Operating Mode
STBN EN Wake-up
Flag
uVBAT
Flag
uVIO
Flag
uVCC
Flag
Secondary
Operating Mode
ERRN5) RxD6) RxEN6) INH Remarks
BD_Normal Mode
22BD_NormalHHH set “L” HX 1 => BD_Sleep 1 => L 1 => H 1 => H 1 => Sleep 7), 8)
23BD_NormalXXH Xset “L” X2 => BD_Sleep 1 => L 1 => L 1 => L 2 => Sleep 7), 9), 10)
24BD_NormalHHH HHset “L” 1 => BD_Standby 1 => L 1 => H 1 => H Not_Sleep 7)
BD_ReceiveOnly Mode
25 BD_ReceiveOnly H L H set “L” HX 1 => BD_Sleep 1 => L 1 => H 1 => H 1 => Sleep 8)
26 BD_ReceiveOnly H L L set “L” HX 1 => BD_Sleep H/L 1 => L 1 => L 1 => Sleep 8), 11), 12)
27BD_ReceiveOnlyXXX Xset “L” X2 => BD_Sleep 1 => L 1 => L 1 => L 2 => Sleep 9), 10)
28 BD_ReceiveOnly H L H H H set “L” 1 => BD_Standby 1 => L 1 => H 1 => H Not_Sleep –
29 BD_ReceiveOnly H L L H H set “L” 1 => BD_Standby H/L 1 => L 1 => L Not_Sleep 11), 12)
BD_GoToSleep Command
30 BD_GoToSleep L H H set “L” XX1 => BD_Sleep HHH1 => Sleep 8), 13), 14)
31 BD_GoToSleep X X H X set “L” X1 => BD_Sleep 1 => L 1 => L 1 => L 1 => Sleep 9), 13), 14)
32 BD_GoToSleep L H H X X set “L” 1 => BD_Sleep HHH1 => Sleep 13), 14)
BD_Standby
33BD_StandbyLLH set “L” HX 1 => BD_Sleep HHH1 => Sleep 8),
34BD_StandbyLLL set “L” HX 1 => BD_Sleep LLL1 => Sleep 8), 11)
35BD_StandbyXXX Xset “L” X1 => BD_Sleep 1 => L 1 => L 1 => L 1 => Sleep 9)
36BD_StandbyLLH HHset “L” 1 => BD_Standby HHHNot_Sleep–
37BD_StandbyLLL HHset “L” 1 => BD_Standby LLLNot_Sleep
11)
BD_Sleep
38 BD_Sleep L X H set “L” XX1 => BD_Sleep HHHSleep 8),
39 BD_Sleep X X H X set “L” X1 => BD_Sleep HHHSleep 9)
40 BD_Sleep L X H X X set “L” 1 => BD_Sleep HHHSleep –
TLE9221SX
Operating Mode Description
Data Sheet 55 Rev. 1.3, 2015-09-21
1) The table describes the states and signals of flags, operating modes and output pins. This table does not contain any timing information. Time for mode changes or the response
time of the digital outputs are specified in the electrical characteristics (compare with Table 22).
2) All flags are “low” active. “L” means the flag is set. “X” = “don’t care”.
The color red stands for the event which triggered the mode transition.
For example: set “L” or set “H”.
The color blue stands for the consequence of the trigger event.
The numbers, “1 =>”, “2 =>” indicate the order of the consequences.
For example: “1=> BD_Normal” means the transceiver TLE9221SX changes over to BD_Normal mode.
“2=> H” means the flag is cleared after the TLE9221SX has changed over to BD_Normal mode.
“FB” stands for “Follow Bus” and means that depending on the signal on the FlexRay bus, the pins RxD and RxEN can either be “high” or “low”.
3) The wake-up flag stands for a detected wake-up event (compare with Chapter 7.3 and Table 10).
The uVBAT flag is the same as the uVBAT undervoltage flag, which is set after the uVBAT undervoltage detection timer expires (compare with Chapter 8.3.1).
The uVIO flag is the same as the uVIO undervoltage flag, which is set after the uVIO undervoltage detection timer expires (compare with Chapter 8.3.1).
The uVCC flag is the same as the uVCC undervoltage flag, which is set after the uVCC undervoltage detection timer expires (compare with Chapter 8.3.1).
4) The ERRN output indicates the wake-up flag, the wake-up source bit and the error bit (compare with Table 9). The error bit is set only by the undervoltage bits, such as the uVBAT
undervoltage bit (bit 8), the uVCC undervoltage bit (bit 9) and the uVIO undervoltage bit (bit 10). All other possible sources setting the error bit, such as, for example a bus failure or
an overtemperature event, are considered as not set in this table.
5) The signal at the ERRN output pin depends on the host command applied and not on the current operating mode (compare with Chapter 6.3).
6) The signals at the RxD and RxEN outputs depend on the current operation mode, and are independent of the host command applied (compare with Table 5).
7) While TLE9221SX changes over to BD_Normal mode, the wake-up flag is cleared. Moreover, the wake-up flag cannot be set in non-low power mode, and therefore the wake-up flag
is always “high” in BD_Normal mode (see Chapter 7.3).
8) The uVBAT undervoltage flag overrules the uVCC undervoltage flag (see Chapter 9.3.1).
9) An undervoltage event at uVIO blocks the Host Interface at once and sets all outputs to logical “low” (see Chapter 8.3.4 and Figure 22). The transceiver TLE9221SX can not indicate
the error bit and the wake-up flag.
10) The uVIO undervoltage flag overrules the uVCC undervoltage flag (see Chapter 9.3.1).
11) The wake-up flag was set during a previous wake-up event while the TLE9221SX was in low power mode.
12) If the host command BD_ReceiveOnly mode is applied, the ERRN indicates the wake-up source bit (see Table 9).
13) Since the BD_GoToSleep command can be executed only when the wake-up flag is cleared, the wake-up flag is always “high” while the TLE9221SX executes the BD_GoToSleep
command.
14) The BD_GoToSleep command is considered as low power mode and the ERRN indicates the wake-up flag just as in the BD_Sleep or BD_Standby mode (see Table 9).
Data Sheet 56 Rev. 1.3, 2015-09-21
TLE9221SX
Operating Mode Description
9.3.1 Priorities of Undervoltage Events
Even if there are undervoltage events on both power supplies uVBAT and uVCC, together with an undervoltage
event on the reference supply uVIO, the Central State Machine is operating and handles the undervoltage
events.
An undervoltage event on uVIO blocks the Host Interface at once and interrupts the communication before the
uVIO undervoltage timer expires. When the uVIO undervoltage timer expires, the TLE9221SX changes the mode
of operation to BD_Sleep. In case the uVCC undervoltage flag is set, the uVIO undervoltage flag overrules the
uVCC undervoltage flag.
If the uVCC undervoltage flag was set before the uVIO undervoltage flag, the mode of operation changes from
BD_Standby to BD_Sleep mode.
If the uVIO undervoltage flag was set before the uVCC undervoltage flag, the mode of operation remains in
BD_Sleep mode.
During an uVBAT undervoltage event, the Host Interface and also the Communication Controller Interface
continues to work until the undervoltage detection timer expires. The uVBAT undervoltage flag also overrules
a uVCC undervoltage flag and the transceiver TLE9221SX ends up in BD_Sleep mode. Simultaneous
undervoltage events at uVBAT and uVIO, additionally disable the Host Interface and the Communication
Controller Interface in comparison to a single uVBAT undervoltage event. After the undervoltage detection
timer expires, the TLE9221SX changes over to BD_Sleep mode.
The least significant undervoltage flag is the uVCC undervoltage flag. An active uVCC undervoltage flag changes
the mode of operation from non-low power mode to BD_Standby mode, when no other undervoltage flag is
set. During an uVCC undervoltage event the Transmitter is disabled.
9.4 Operating Mode Changes by Undervoltage Recovery
As stated in Chapter 8.3, any undervoltage flag causes a change in the operating mode and blocks the Host
Interface and the Communication Controller Interface.
After recovering from the undervoltage condition, and after the undervoltage flags are cleared, the FlexRay
transceiver TLE9221SX enables the Host Interface and also the Communication Controller Interface and the
host command applied at the inputs STBN and EN changes the mode of operation (see Figure 30 and
Table 16).
9.4.1 BD_Sleep Mode Entry Flag
A special case is the undervoltage recovery from BD_Sleep mode while the host command BD_Standby is
applied to the Host Interface.
The EN input pin will be disabled while the device is in BD_Sleep mode. A mode changeover via host command
from BD_Sleep mode to BD_Standby mode is not permitted (compare with Table 14). The transceiver
distinguishes the host command BD_Sleep from BD_Standby, after the transceiver recovers from an
undervoltage event.
The BD_Sleep mode entry flag indicates, how the changeover to BD_Sleep mode occurred. If changeover to
BD_Sleep mode took place by setting an undervoltage flag, the BDSME flag (BD_Sleep Mode Entry) is set to
“low” and the EN input pin remains active. If changeover to BD_Sleep mode took place by a host command,
the BDSME flag is set to logical “high” and the EN input pin gets disabled (see Table 16).
The BDSME is an internal flag and it is neither indicated at the ERRN output nor latched in the SIR.
Data Sheet 57 Rev. 1.3, 2015-09-21
TLE9221SX
Operating Mode Description
Figure 30 Change in the mode of operation by undervoltage recovery
ENSTBN
LH
INH
Sleep
BD_Sleep
EN
STBN
HH
INH
BD_Normal
BD_GoToSleep
ENSTBN
LH
INH
Not_Sleep
56
Not_Sleep
ENSTBN
LL
INH
Not_Sleep
BD_Standby
51
53
58
ENSTBN
LH
INH
Not_Sleep
BD_ReceiveOnly
44
45
46
41
42
59
43
57
60
61
474849505254
55
TLE9221SX
Operating Mode Description
Data Sheet 58 Rev. 1.3, 2015-09-21
Table 16 Mode changes via undervoltage recovery1) 2) 3) 4)
No. Primary
Operating
Mode
STBN EN Wake-
up Flag
BDSME
Flag5)
uVBAT
Flag
uVIO
Flag
uVCC
Flag
Secondary
Operating Mode
ERRN6) RxD7) RxEN7) INH Remarks
BD_Sleep -> Host Command BD_Normal
41 BD_Sleep H H 2 => H Xset “H” HH1 => BD_Normal 2 => H 1=>FB 1=>FB 1 => Not_Sleep 8), 9)
42 BD_Sleep H H 2 => H XHset “H” H1 => BD_Normal 2 => H 1=>FB 1=>FB 1 => Not_Sleep 8), 9)
43 BD_Sleep H H 2 => H XHHset “H” 1 => BD_Normal 2 => H 1=>FB 1=>FB 1 => Not_Sleep 8), 9), 10)
BD_Sleep -> Host Command BD_ReceiveOnly
44 BD_Sleep H L X X set “H” HH1 => BD_ReceiveOnly H/L 1=>FB 1=>FB 1 => Not_Sleep 11)
45 BD_Sleep H L X X H set “H” H1 => BD_ReceiveOnly H/L 1=>FB 1=>FB 1 => Not_Sleep 11)
46 BD_Sleep H L X X H H set “H” 1 => BD_ReceiveOnly H/L 1=>FB 1=>FB 1 => Not_Sleep 10), 11)
BD_Sleep -> Host Command BD_Sleep
47 BD_Sleep L H H X set “H” HHBD_Sleep HHHSleep 12)
48 BD_Sleep L H H X H set “H” H BD_Sleep 1 => H 1 => H 1 => H Sleep 12)
49 BD_Sleep L H H X H H set “H” BD_Sleep HHHSleep 10), 12)
BD_Sleep -> Host Command BD_Standby
50 BD_Sleep L L H H set “H” HHBD_Sleep HHHSleep 12), 13)
51 BD_Sleep L L H L set “H” HH1 => BD_Standby HHH1 => Not_Sleep 12), 14)
52 BD_Sleep L L H H H set “H” H BD_Sleep 1 => H 1 => H 1 => H Sleep 12), 13)
53 BD_Sleep L L H L H set “H” H1 => BD_Standby 1 => H 1 => H 1 => H 1 => Not_Sleep 12), 14)
54 BD_Sleep L L H H H H set “H” BD_Sleep HHHSleep 12), 13)
55 BD_Sleep L L H L H H set “H” 1 => BD_Standby HHH1 => Not_Sleep 12), 14)
BD_Standby
56 BD_Standby H H 2 => H XHHset “H” 1 => BD_Normal 2 => H 1=>FB 1=>FB Not_Sleep 8), 9), 15)
57 BD_Standby H L X X H H set “H” 1 => BD_ReceiveOnly H/L 1=>FB 1=>FB Not_Sleep 11), 15), 16)
58 BD_Standby L L H X H H set “H” BD_Standby HHHNot_Sleep
15)
TLE9221SX
Operating Mode Description
Data Sheet 59 Rev. 1.3, 2015-09-21
59 BD_Standby L L L X H H set “H” BD_Standby LLLNot_Sleep
15), 16)
60 BD_Standby L H H X H H set “H” 1 => BD_GoToSleep HHHNot_Sleep
15)
61 BD_Standby L H L X H H set “H” BD_Standby LLLNot_Sleep
15), 16)
1) The table describes the states and signals of flags, operating modes and output pins. This table does not contain any timing information. Time for mode changes or the response
time of the digital outputs are specified in the electrical characteristics (compare with Table 22).
2) All flags are “low” active. “L” means the flag is set. “X” = “don’t care”.
The color red stands for the event which triggered the mode transition.
For example: set “L” or set “H”.
The color blue stands for the consequence of the trigger event.
The numbers, “1 =>”, “2 =>” indicate the order of the consequences.
For example: “1=> BD_Normal” means the transceiver TLE9221SX changes over to BD_Normal mode.
“2=> H” means the flag is cleared after the TLE9221SX has changed over to BD_Normal mode.
“FB” stands for “Follow Bus” and means that depending on the signal on the FlexRay bus, the pins RxD and RxEN can either be “high” or “low”.
3) The wake-up flag stands for a detected wake-up event (compare with Chapter 7.3 and Table 10).
The uVBAT flag is the same as the uVBAT undervoltage flag, which is set after the uVBAT undervoltage detection timer expires (compare with Chapter 8.3.1).
The uVIO flag is the same as the uVIO undervoltage flag, which is set after the uVIO undervoltage detection timer expires (compare with Chapter 8.3.1).
The uVCC flag is the same as the uVCC undervoltage flag, which is set after the uVCC undervoltage detection timer expires (compare with Chapter 8.3.1).
4) The ERRN output indicates the wake-up flag, the wake-up source bit and the error bit (compare with Table 9). The error bit is set only by the undervoltage bits, such as the uVBAT
undervoltage bit (bit 8), the uVCC undervoltage bit (bit 9) and the uVIO undervoltage bit (bit 10). All other possible sources setting the error bit, such as, for example, a bus failure or an
overtemperature event, are considered as not set in this table.
5) BD_Sleep mode entry flag disables the EN input pin when set to logical “low” (see Chapter 9.4.1)
6) The signal at the ERRN output pin depends on the host command applied and not on the current operating mode (compare with Chapter 6.3).
7) The signals at the RxD and RxEN outputs depend on the current operating mode, and are independent of the host command applied (compare with Table 5).
8) While TLE9221SX changes over to BD_Normal mode the wake-up flag is cleared. Moreover, the wake-up flag cannot be set in non-low power mode, and therefore, the wake-up flag
is always “high” in BD_Normal mode (see Chapter 7.3).
9) Changing over to BD_Normal mode clears the SIR, including the undervoltage bits and therefore sets the ERRN output to “high” (compare with Chapter 6.3.1).
10) BD_Sleep mode was either entered by a host command or by setting the uVBAT or uVIO undervoltage flag (see Table 15).
11) If the host command BD_ReceiveOnly mode is applied, the ERRN output indicates the wake-up source bit (see Table 9).
12) This assumes no wake-up event was detected and the wake-up flag is cleared.
Table 16 Mode changes via undervoltage recovery1) 2) 3) 4)
No. Primary
Operating
Mode
STBN EN Wake-
up Flag
BDSME
Flag5)
uVBAT
Flag
uVIO
Flag
uVCC
Flag
Secondary
Operating Mode
ERRN6) RxD7) RxEN7) INH Remarks
TLE9221SX
Operating Mode Description
Data Sheet 60 Rev. 1.3, 2015-09-21
13) The BDSME flag is cleared, changeover to BD_Sleep mode was made by a host command (see Chapter 9.4.1).
14) The BDSME flag is set, changeover to BD_Sleep mode was made by setting one or more undervoltage flags (see Chapter 9.4.1).
15) In BD_Standby mode, only the uVCC undervoltage flag could be active, since any other active undervoltage flag would change the mode of operation to BD_Sleep mode (compare
with Table 15).
16) A wake-up flag could have been set by a wake-up event while the transceiver was in BD_Standby mode.
Data Sheet 61 Rev. 1.3, 2015-09-21
TLE9221SX
Operating Mode Description
9.5 Operation Mode Changes by the Wake-up Flag
Setting the wake-up flag triggers a mode change to BD_Standby mode, regardless of the transceiver being in
BD_Sleep mode or in the BD_GoToSleep command. While the transceiver TLE9221SX remains in BD_Standby
mode, a wake-up event sets the wake-up bit and the wake-up flag. The wake-up flag is indicated at the ERRN,
RxD and RxEN outputs. No mode change by the wake-up event is applied (for details see Figure 31 and
Table 17).
The wake-up flag can be set only in BD_Sleep mode, BD Standby mode or while the BD_GoToSleep command
is being executed (for details see “Wake-up Flag and Wake-up Bits” on Page 32).
While the wake-up flag is active, the FlexRay transceiver TLE9221SX cannot change over to BD_Sleep mode
again (see Figure 28). To reset the wake-up flag, either change the operating mode of the TLE9221SX to
BD_Normal mode or read out the SIR.
Figure 31 Operating mode change by wake-up flag
Setting the wake-up flag triggers not only a change in the operating mode, but also clears all undervoltage
flags. The undervoltage bits available in the SIR remain active.
In case the undervoltage event remains present, setting the wake-up flag clears the undervoltage flag. The
undervoltage detection timer is restarted and the undervoltage flag is set again when the undervoltage
detection timer expires.
Note: Setting the wake-up flag clears only the undervoltage flag, not the undervoltage bit. The undervoltage
bit remains active and is visible in the SIR.
ENSTBN
LH
INH
Sleep
BD_Sleep
BD_GoToSleep
ENSTBN
LH
INH
Not_Sleep
ENSTBN
LL
INH
Not_Sleep
BD_Standby
62
63
64
65
TLE9221SX
Operating Mode Description
Data Sheet 62 Rev. 1.3, 2015-09-21
Table 17 Mode changes by setting the wake-up flag 1) 2) 3) 4)
1) The table describes the states and signals of flags, operating modes and output pins. This table does not contain any timing information. Time for mode changes or the response
time of the digital outputs are specified in the electrical characteristics (compare with Table 22).
2) All flags are “low” active. “L” means the flag is set. “X” = “don’t care”.
The color red stands for the event which triggered the mode transition.
For example: set “L” or set “H”.
The color blue stands for the consequence of the trigger event.
The numbers, “1 =>”, “2 =>” indicate the order of the consequences.
For example: “1=> BD_Normal” means the transceiver TLE9221SX changes over to BD_Normal mode.
“2=> H” means the flag is cleared after the TLE9221SX has changed over to BD_Normal mode.
“FB” stands for “Follow Bus” and means that depending on the signal on the FlexRay bus, the pins RxD and RxEN can either be “high” or “low”.
3) The wake-up flag stands for a detected wake-up event (compare with Chapter 7.3 and Table 10).
The uVBAT flag is the same as the uVBAT undervoltage flag, which is set after the uVBAT undervoltage detection timer expires (compare with Chapter 8.3.1).
The uVIO flag is the same as the uVIO undervoltage flag, which is set after the uVIO undervoltage detection timer expires (compare with Chapter 8.3.1).
The uVCC flag is the same as the uVCC undervoltage flag, which is set after the uVCC undervoltage detection timer expires (compare with Chapter 8.3.1).
4) The ERRN output indicates the wake-up flag, the wake-up source bit and the error bit (compare with Table 9). The error bit is set only by the undervoltage bits, such as the uVBAT
undervoltage bit (bit 8), the uVCC undervoltage bit (bit 9) and the uVIO undervoltage bit (bit 10). All other possible sources setting the error bit, such as, for example, a bus failure or
an overtemperature event, are considered as not set in this table.
No. Primary
Operating Mode
STBN EN Wake-up
Flag
uVBAT
Flag
uVIO
Flag
uVCC
Flag
Secondary
Operating Mode
ERRN5)
5) The signal at the ERRN output pin depends on the host command applied and not on the current operating mode (compare with Chapter 6.3).
RxD6)
6) The signals at the RxD and RxEN outputs depend on the current operation mode, and are independent of the host command applied (compare with Table 5).
RxEN6) INH Remarks
BD_Sleep
62 BD_Sleep L L set “L” 2 => H 2 => H 2 => H 1 => BD_Standby 1 => L 1 => L 1 => L 1 => Not_Sleep 7)
7) Setting the wake-up flag also resets all undervoltage flags.
63 BD_Sleep L H set “L” 2 => H 2 => H 2 => H 1 => BD_Standby 1 => L 1 => L 1 => L 1 => Not_Sleep 7)
BD_Standby
64 BD_Standby L L set “L” HH2 => H BD_Standby 1 => L 1 => L 1 => L Not_Sleep 7), 8)
8) In BD_Standby mode, only the uVCC undervoltage flag can be active (see Table 15).
BD_GoToSleep
65 BD_GoToSleep L H set “L” 2 => H 2 => H 2 => H 1 => BD_Standby 1 => L 1 => L 1 => L 1 => Not_Sleep 7), 8)
Data Sheet 63 Rev. 1.3, 2015-09-21
TLE9221SX
Bus Error Indication
10 Bus Error Indication
In case the TLE9221SX is not able to drive the correct data to the FlexRay bus, the transceiver sets the bus error
bit (bit 4). The bus error bit indicates faulty data by setting the ERRN output to “low” (compare with Table 9).
Therefore, three different detection mechanisms are implemented:
•uV
CC undervoltage detection
• RxD and TxD bit comparison
• Overcurrent detection
Just as any other SIR entry, the bus error bit is reset either by a SIR read-out or by changing over to BD_Normal
mode (compare with Chapter 6.3.1 “Reset the ERRN Output Pin”).
Setting the bus error bit disables the Transmitter of the TLE9221SX in order to avoid corrupt data on the
FlexRay bus. An active bus error bit does not trigger any change in the mode of operation.
10.1 Setting the Bus Error Bit by uVCC Undervoltage
The Transmitter of the TLE9221SX is fed by the power supply uVCC (compare with Figure 2). In case uVCC is in
undervoltage condition, the TLE9221SX cannot drive the correct bus levels to the FlexRay bus. Therefore, the
transceiver sets the uVCC undervoltage bit together with the bus error bit and the error bit.
In BD_Normal mode, the active uVCC undervoltage bit and the active bus error bit disable the Transmitter. The
uVCC undervoltage bit starts the uVCC undervoltage timer and if the timer expires, the undervoltage flag is set
and a mode changeover is initiated (see also Chapter 8.3.3 “Undervoltage Event at uVCC”).
10.2 Setting the Bus Error Bit by RxD and TxD Comparison
The transceiver TLE9221SX compares the digital input signal at TxD with the signal received from the FlexRay
bus at the RxD output. If the data transmit signal at the TxD input is different from the signal received at the
RxD output, the TLE9221SX sets the bus error bit.
The RxD to TxD bit comparison is active only, when the transceiver TLE9221SX is in BD_Normal mode and the
Transmitter is active (TxEN = “low”; BGE = “high”). Both, the rising and the falling edge at the TxD input signal
trigger an internal comparator to compare the TxD signal with the RxD signal. The results are stored in an
internal error counter. When the internal error counter exceeds 10 reported comparison failures, the bus error
bit is set.
The error counter is reset when the Transmitter is reset.
10.3 Setting the Bus Error Bit by Overcurrent Detection
Four different current sensors monitor the output current and the input current at the pins BP and BM. In case
the TLE9221SX detects an overcurrent caused by a bus short-circuit either to GND or to one of the power
supplies, the TLE9221SX sets the bus error bit.
Data Sheet 64 Rev. 1.3, 2015-09-21
TLE9221SX
Overtemperature Protection
11 Overtemperature Protection
The Transmitter of TLE9221SX is protected against overheating with an internal temperature sensor (compare
with Figure 1). The temperature sensor provides two temperature thresholds: TJ(Warning) and TJ(Shut_Down).
On exceeding the lower threshold TJ(Warning), the transceiver sets the overtemperature warning bit (bit 6),
indicating a “high” temperature situation. On exceeding the upper threshold TJ(Shut_Down), the transceiver
TLE9221SX sets the overtemperature shut down bit (bit 5), indicating a critical temperature situation. On
reaching the TJ(Shut_Down) threshold, the transceiver TLE9221SX also disables the Transmitter (see Figure 32).
The overtemperature detection of the Transmitter is active only in BD_Normal mode. An overtemperature
detection event does not trigger any change in the operating mode.
Both bits, the overtemperature shut down bit and the overtemperature warning bit set the error bit (bit 11) in
the SIR. The error bit is indicated at the ERRN output (compare with Chapter 6.3 “Status Information at the
ERRN Output Pin”).
The Transmitter can be enabled again after an overtemperature event by clearing the SIR (see also
Chapter 6.2.3 “Clearing Sequence of SIR”).
Figure 32 Overtemperature protection
t
BP
BM
t
TJ
TJ(Warning)
TJ(Shut_Down)
TxD
t
RxD
t
ERRN
t
BD_Normal
dReTimeERRN
Data Sheet 65 Rev. 1.3, 2015-09-21
TLE9221SX
Transmitter Time-out
12 Transmitter Time-out
To ensure that an active Transmitter blocks the FlexRay bus permanently, a time-out function is implemented
within the TLE9221SX. In case the Transmitter is active for the time period t > dBDTxActiveMax, the
Transmitter will be disabled automatically (see Figure 33). The Transmitter time-out sets the Transmitter
time-out bit (bit 7) in the SIR and also the error bit. In BD_Normal mode, the Transmitter time-out is indicated
at the ERRN output by a logical “low” signal. To reset the TxEN or BGE time-out, either change over again to
BD_Normal mode or read out the SIR (see Chapter 6.3.1 “Reset the ERRN Output Pin”).
Figure 33 Transmitter time-out function
t
BP
BM
TxD
t
RxD
t
ERRN
t
BD_Normal
dReactionTime
ERRN
t
t
TxEN
BGE
dBDTxActiveMax
transmitter time-out
transmitter “active” transmitter “Idle”transmitter “Idle”
Data Sheet 66 Rev. 1.3, 2015-09-21
TLE9221SX
Mode Indication, Power-up and Parity Information
13 Mode Indication, Power-up and Parity Information
13.1 Power-up Bit
After switching on the power supplies uVCC and uVBAT, the FlexRay transceiver TLE9221SX sets the power-up
bit (bit 3) in the SIR. The power-up bit is visible only by reading out the SIR and will be reset by clearing the SIR
(see Chapter 6.2.3 “Clearing Sequence of SIR”).
13.2 Mode Indication Bit EN and Mode Indication Bit STBN
Two bits in the SIR are reserved for the indication of the operating mode. The SIR indicates the current mode
of operation, regardless of whether the mode is selected via host command, undervoltage flag or wake-up
flag. The mode indication bits have the same order as the host commands. Bit 13 of the SIR reflects the related
host command at the EN pin of the actual mode of operation and bit 14 indicates the related host command
at the STBN pin (compare with Table 18).
13.3 Even Parity Bit
The even parity bit (bit 15) can be used to check the transmission of the SIR. The even parity bit is set to logical
“low” if the sum of all status bits is even, and it is logical “high” if the sum of all status bits is odd.
Table 18 Mode indication bits
Mode of Operation Mode Indication Bit EN (bit 13) Mode Indication Bit STBN (bit 14)
BD_Normal “high” “high”
BD_ReceiveOnly “low” “high”
BD_Standby “low” “low”
BD_Sleep no read-out possible no read-out possible
BD_GoToSleep no read-out possible no read-out possible
Data Sheet 67 Rev. 1.3, 2015-09-21
TLE9221SX
General Product Characteristics
14 General Product Characteristics
14.1 Absolute Maximum Ratings
Table 19 Absolute maximum ratings voltages, currents and temperatures1)
All voltages with respect to ground; positive current flowing into the pin;
(unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Voltages
Supply voltage battery uVBAT -0.3 – 40 V – P_14.1.1
Supply voltage VCC uVCC -0.3 – 6.0 V – P_14.1.2
Supply voltage VIO uVIO -0.3 – 6.0 V – P_14.1.3
DC voltage versus GND on
the pin BP
uBP -40 – 40 V – P_14.1.4
DC voltage versus GND on
the pin BM
uBM -40 – 40 V – P_14.1.5
DC voltage versus GND on
the pin INH
uINH -0.3 – uVBAT + 0.3 V – P_14.1.6
DC voltage versus GND on
the pin WAKE
uWAKE -27 – uVBAT + 0.3 V – P_14.1.7
DC voltage versus GND on
the pin STBN
uVSTBN -0.3 – VIO V– P_14.1.8
DC voltage versus GND on
the pin EN
uVEN -0.3 – VIO V– P_14.1.9
DC voltage versus GND on
the pin TxD
uVTxD -0.3 – VIO V– P_14.1.10
DC voltage versus GND on
the pin TxEN
uVTxEN -0.3 – VIO V– P_14.1.11
DC voltage versus GND on
the pin BGE
uVBGE -0.3 – VIO V– P_14.1.12
DC voltage versus GND on
the pin RxD
uVRxD -0.3 – VIO V– P_14.1.13
DC voltage versus GND on
the pin RxEN
uVRxEN -0.3 – VIO V– P_14.1.14
DC voltage versus GND on
the pin ERRN
uVERRN -0.3 – VIO V– P_14.1.15
Currents
Output current on the pin
INH
iINH -1 – – mA – P_14.1.16
Data Sheet 68 Rev. 1.3, 2015-09-21
TLE9221SX
General Product Characteristics
Note: Stresses beyond those listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. Integrated protection
functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault
conditions are considered as “outside” the normal-operating range. Protection functions are not
designed for continuous repetitive operation.
Output current on the pin
RxD
iRxD -40 – 40 mA – P_14.1.17
Output current on the pin
RxEN
iRxEN -40 – 40 mA – P_14.1.18
Output Current on the pin
ERRN
iERRN -40 – 40 mA – P_14.1.19
Temperatures
Junction temperature TJunction -40 – 150 °C– P_14.1.20
Storage temperature TS - 55 – 150 °C– P_14.1.21
ESD Immunity
ESD immunity at BP, BM,
VBAT, WAKE versus GND
uESDEXT -10 – 10 kV HBM,
(100 pF via 1.5 kΩ), 2);
P_14.1.22
ESD immunity at all other
pins
uESDINT -2 – 2 kV HBM,
(100 pF via 1.5 kΩ), 2);
P_14.1.23
ESD immunity to GND
(all pins)
uESDCDM -750 – 750 V CDM, 3);P_14.1.24
1) Not subject to production test, specified by design.
2) ESD susceptibility, Human Body Model “HBM” according to ANSI/ESDA/JEDEC JS-001.
3) ESD susceptibility, Charged Device Model “CDM” according to EIA/JESD22-C101 or ESDA STM5.3.1
Table 19 Absolute maximum ratings voltages, currents and temperatures1) (cont’d)
All voltages with respect to ground; positive current flowing into the pin;
(unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Data Sheet 69 Rev. 1.3, 2015-09-21
TLE9221SX
General Product Characteristics
14.2 Functional Range
Note: Within the functional range, the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
Table 20 Functional range
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Supply Voltages
Transceiver supply voltage VBAT uVBAT 5.5 – 18 V 1);
1) The TLE9221SX is fully functional, including the wake-up functions, in the specified uVBAT range while uVCC and uVIO
are also in their operating range.
P_14.2.1
Transceiver supply voltage VBAT
extended supply range
uVBAT-
EXT
18 – 40 V 60 s, 2), 3);
2) Not subject to production test, specified by design
3) The extended supply range covers the load requirements according to ISO 16750-2 (load dump, jump start). This
range is not qualified for continuous, repetitive operation.
P_14.2.2
Transceiver supply voltage VCC uVCC 4.75 – 5.25 V – P_14.2.3
Transceiver supply voltage VIO uVIO 3.0 – 5.25 V – P_14.2.4
Functional range VBAT including
local and remote wake-up
functions
uVBAT_W
AKE
5.5 – 18 V 1);P_14.2.5
Thermal Parameters
Junction temperature TJunction -40 – 150 °C – P_14.2.6
Data Sheet 70 Rev. 1.3, 2015-09-21
TLE9221SX
General Product Characteristics
14.3 Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information,
please visit www.jedec.org.
Table 21 Thermal resistance1)
1) Not subject to production test, specified by design
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Thermal Resistance
Junction to ambient1) RthJA – 100 – K/W 2)
2) Specified RthJA value is according to Jedec JESD51-2,-7 at natural convection on FR4 2s2p board; The product
(TLE9221SX) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu)
P_14.3.1
Thermal Shutdown Junction Temperature
Thermal warning temperature TJ(Warning) 150 160 170 °C – P_14.3.2
Thermal shut-down temperature TJ(Shut_Down) 170 180 190 °C – P_14.3.3
Temperature difference between warning
temperature and shut-down temperature
ΔT=T
J(Shut_Down) -T
J(Warning)
ΔT10 20 25 °C – P_14.3.4
Data Sheet 71 Rev. 1.3, 2015-09-21
TLE9221SX
Electrical Characteristics
15 Electrical Characteristics
15.1 Functional Device Characteristics
Table 22 Electrical characteristics
5.5 V < uVBAT <18V; 3.0V<uV
IO <5.25V; 4.75V<uV
CC <5.25V; R
DCLOAD =45Ω; CDCLOAD = 100 pF;
-40 °C<T
Junction < 150 °C;
All voltages with respect to ground; positive current flowing into the pin; (unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Current Consumption uVBAT Power Supply
Current consumption
uVBAT,
non-low power mode
iVBAT –5.56.5mABD_Normal,
BD_ReceiveOnly,
open load on INH,
uVBAT = 13.5 V;
P_15.1.1
Current consumption
uVBAT
BD_Sleep
iVBAT_Sleep40 –4565μAuV
BAT =13.5V, uINH1=0V,
EN = “low”, STBN = “low”,
TJunction = 40° C,
uBDWake = 0 V;
P_15.1.4
Current consumption
uVBAT
BD_Standby
iVBAT_Stb – 70 180 μAuV
BAT = 13.5 V,
open load on INH,
uBDWake = 0 V;
P_15.1.5
Current Consumption uVCC Power Supply
Current consumption
uVCC
BD_Normal
iVCC – 25 40 mA Transmitter = “Data_0” or
“Data 1”;
P_15.1.10
Current consumption
uVCC
BD_Normal
iVCC_Tx_Idle – 0.07 1 mA Transmitter = “Idle”,
uVBAT = 13.5 V;
P_15.1.11
Current consumption
uVCC
BD_ReceiveOnly
iVCC_ROM –0.050.5mAuV
BAT = 13.5 V; P_15.1.12
Current consumption
uVCCBD_Sleep
iVCC_Sleep40 –0.52μAuV
CC =5V,
uVBAT = 13.5 V,
TJunction = 40°C;
P_15.1.15
Current consumption
uVCCBD_Standby
iVCC_Stb –28μAuV
CC =5V,
uVBAT = 13.5 V;
P_15.1.16
Data Sheet 72 Rev. 1.3, 2015-09-21
TLE9221SX
Electrical Characteristics
Current Consumption uVIO Power Supply
Current consumption
uVIO, non-low power
mode
iVIO – 0.15 0.5 mA BD_Normal,
BD_ReceiveOnly;
P_15.1.20
Current consumption
uVIO
BD_Sleep
iVIO_Sleep40 –23μAuV
IO =5V, TxEN=uV
IO,
BGE = TxD = “low”,
TJunction =40°C;
P_15.1.23
Current consumption
uVIO
BD_Standby
iVIO_Stb –240μAuV
IO =5V, TxEN=uV
IO,
BGE = TxD = “low”;
P_15.1.24
Table 22 Electrical characteristics (cont’d)
5.5 V < uVBAT <18V; 3.0V<uV
IO <5.25V; 4.75V<uV
CC <5.25V; R
DCLOAD =45Ω; CDCLOAD = 100 pF;
-40 °C<T
Junction < 150 °C;
All voltages with respect to ground; positive current flowing into the pin; (unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Data Sheet 73 Rev. 1.3, 2015-09-21
TLE9221SX
Electrical Characteristics
Undervoltage Detection uVBAT Power Supply
Undervoltage detection
threshold uVBAT
uBDUVVBAT 4.0 4.8 5.5 V falling edge; P_15.1.30
Undervoltage detection
hysteresis uVBAT
uBDUVVBAT
_Hys
– 100 – mV 1); P_15.1.31
Power-down threshold
uVBAT
uBDPDVBAT 2.0 2.8 3.5 V 1); P_15.1.32
VBat undervoltage filter
time
dBDUVVBAT
_Blk
50 – 500 µs 1), uVBAT = 13.5 V to
uBDUVVBAT(min),
(see Figure 20);
P_15.1.33
Response time for uVBAT
undervoltage detection
dBDUVVBAT – 550 650 ms 1), (see Figure 20); P_15.1.35
Response time for uVBAT
undervoltage recovery
dBDRVBAT –610ms
1), (see Figure 20); P_15.1.36
Undervoltage Detection uVCC Power Supply
Undervoltage detection
threshold uVCC
uBDUVVCC 4.0 4.25 4.75 V falling edge; P_15.1.40
Undervoltage detection
hysteresis uVCC
uBDUVVCC
_Hys
– 100 – mV 1); P_15.1.41
Power-down threshold
uVCC
uBDPDVCC 1.5 2.25 3.5 V 1); P_15.1.42
uVCC undervoltage filter
time
dBDUVVCC
_Blk
3–25µsuV
CC =4.75V to
uBDUVVCC(min),
(see Figure 21);
P_15.1.43
Response time for uVCC
undervoltage detection
dBDUVVCC – 550 650 ms 1), (see Figure 21); P_15.1.45
Response time for uVCC
undervoltage recovery
dBDRVCC –610ms
1), (see Figure 21); P_15.1.46
Table 22 Electrical characteristics (cont’d)
5.5 V < uVBAT <18V; 3.0V<uV
IO <5.25V; 4.75V<uV
CC <5.25V; R
DCLOAD =45Ω; CDCLOAD = 100 pF;
-40 °C<T
Junction < 150 °C;
All voltages with respect to ground; positive current flowing into the pin; (unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Data Sheet 74 Rev. 1.3, 2015-09-21
TLE9221SX
Electrical Characteristics
Undervoltage Detection uVIO Power Supply
Undervoltage detection
threshold uVIO
uUVIO 2.0 2.65 3.0 V falling edge; P_15.1.50
Undervoltage detection
hysteresis uVIO
uUVIO_Hys –50–mV
1); P_15.1.51
uVIO undervoltage filter
time
dBDUVVIO
_Blk
3–25µsuV
IO =3V to
uBDUVVIO(min), (see
Figure 22);
P_15.1.52
Response time for uVIO
undervoltage detection
dBDUVVIO – 550 650 ms 1), (see Figure 22); P_15.1.54
Response time for uVIO
undervoltage recovery
dBDRVIO –610ms
1), (see Figure 22); P_15.1.55
Table 22 Electrical characteristics (cont’d)
5.5 V < uVBAT <18V; 3.0V<uV
IO <5.25V; 4.75V<uV
CC <5.25V; R
DCLOAD =45Ω; CDCLOAD = 100 pF;
-40 °C<T
Junction < 150 °C;
All voltages with respect to ground; positive current flowing into the pin; (unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Data Sheet 75 Rev. 1.3, 2015-09-21
TLE9221SX
Electrical Characteristics
Digital Output RxD
“high” level output
voltage
uVDig_Out_High_
RxD
0.8 x
uVIO
–1.0 x
uVIO
ViRxD
H=-2mA,
2);P_15.1.60
“low” level output
voltage
uVDig_Out_Low
_RxD
– – 0.2 x
uVIO
ViRxD
L=2mA,
2);P_15.1.61
Output voltage,
uVIO undervoltage
uVDig_Out_UV
_RxD
– – 250 mV R_BDRxD = 100 kΩ, 3);P_15.1.62
Output voltage,
BD_Off state
uVDig_Out_OFF
_RxD
– – 100 mV R_BDRxD = 100 kΩ, 4);P_15.1.63
Rise time,
15 pF load
dBDRxDR15 –14ns
1), 20% - 80% of uVIO,
C_BDRxD = 15 pF;
P_15.1.64
Fall time,
15 pF load
dBDRxDF15 –14ns
1), 80% - 20% of uVIO,
C_BDRxD = 15 pF;
P_15.1.65
Rise time,
25 pF load
dBDRxDR25 – 2 6 ns 20% - 80% of uVIO,
C_BDRxD = 25 pF;
P_15.1.66
Fall time,
25 pF load
dBDRxDF25 – 2 6 ns 80% - 20% of uVIO,
C_BDRxD = 25 pF;
P_15.1.67
Sum of rise and fall
time,
15 pF load
dBDRxDR15 +
dBDRxDF15
–28ns
1), C_BDRxD = 15 pF; P_15.1.68
Difference of rise and
fall time,
15 pF load
|dBDRxDR15 -
dBDRxDF15|
–0.52.5ns
1), C_BDRxD = 15 pF; P_15.1.69
Sum of rise and fall
time,
25 pF load
dBDRxDR25 +
dBDRxDF25
– 4 12 ns C_BDRxD = 25 pF; P_15.1.70
Difference of rise and
fall time,
25 pF load
|dBDRxDR25 -
dBDRxDF25|
–0.52.5nsC_BDRxD=25pF; P_15.1.71
Digital Output RxEN
“high” level output
voltage
uVDig_Out_High_
RxEN
0.8 x
uVIO
–1.0 x
uVIO
ViRxD
H=-2mA,
2);P_15.1.80
“low” level output
voltage
uVDig_Out_Low
_RxEN
– – 0.2 x
uVIO
ViRxD
L=2mA,
2);P_15.1.81
Output voltage,
uVIO undervoltage
uVDig_Out_UV
_RxEN
– – 250 mV R_BDRxEN = 100 kΩ, 3); P_15.1.82
Table 22 Electrical characteristics (cont’d)
5.5 V < uVBAT <18V; 3.0V<uV
IO <5.25V; 4.75V<uV
CC <5.25V; R
DCLOAD =45Ω; CDCLOAD = 100 pF;
-40 °C<T
Junction < 150 °C;
All voltages with respect to ground; positive current flowing into the pin; (unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Data Sheet 76 Rev. 1.3, 2015-09-21
TLE9221SX
Electrical Characteristics
Output voltage,
BD_Off state
uVDig_Out_OFF
_RxEN
– – 100 mV R_BDRxEN = 100 kΩ, 4); P_15.1.83
Rise time,
25 pF load
dBDRxENR25 –26ns
1), 20% - 80% of uVIO,
C_BDRxEN = 25 pF;
P_15.1.84
Fall time,
25 pF load
dBDRxENF25 –26ns
1), 80% - 20% of uVIO,
C_BDRxEN = 25 pF;
P_15.1.85
Table 22 Electrical characteristics (cont’d)
5.5 V < uVBAT <18V; 3.0V<uV
IO <5.25V; 4.75V<uV
CC <5.25V; R
DCLOAD =45Ω; CDCLOAD = 100 pF;
-40 °C<T
Junction < 150 °C;
All voltages with respect to ground; positive current flowing into the pin; (unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Data Sheet 77 Rev. 1.3, 2015-09-21
TLE9221SX
Electrical Characteristics
Digital Output ERRN
“high” level output
voltage
uVDig_Out_High_
ERRN
0.8 x
uVIO
–1.0 x
uVIO
V iERRNH=-2mA,
2);P_15.1.90
“low” level output
voltage
uVDig_Out_Low
_ERRN
– – 0.2 x
uVIO
V iERRNL=2mA,
2);P_15.1.91
Output voltage,
uVIO undervoltage
uVDig_Out_UV
_ERRN
– – 250 mV R_BDERRN = 100 kΩ, 3); P_15.1.92
Output voltage,
BD_Off state
uVDig_Out_OFF
_ERRN
– – 100 mV R_BDERRN = 100 kΩ, 4); P_15.1.93
Rise time,
25 pF load
dBDERRNR25 –26ns
1), 20% - 80% of uVIO,
C_BDERRN = 25 pF;
P_15.1.94
Fall time,
25 pF load
dBDERRNF25 –26ns
1), 80% - 20% of uVIO,
C_BDERRN = 25 pF;
P_15.1.95
Response time dReaction
TimeERRN
– – 100 μs1), (see Figure 7); P_15.1.96
Digital Input TxD
“high” level input
voltage
uBDLogic_1 0.6 x
uVIO
–uV
IO V 2); P_15.1.100
“low” level input
voltage
uBDLogic_0 -0.3 – 0.4 x
uVIO
V2); P_15.1.101
“high” level input
current
iBDLogic_1 20 200 μA– P_15.1.102
“low” level input
current
iBDLogic_0 – – 1 μA1); P_15.1.103
Input capacitance C_BDTxD – – 5 pF 1); P_15.1.104
Table 22 Electrical characteristics (cont’d)
5.5 V < uVBAT <18V; 3.0V<uV
IO <5.25V; 4.75V<uV
CC <5.25V; R
DCLOAD =45Ω; CDCLOAD = 100 pF;
-40 °C<T
Junction < 150 °C;
All voltages with respect to ground; positive current flowing into the pin; (unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Data Sheet 78 Rev. 1.3, 2015-09-21
TLE9221SX
Electrical Characteristics
Digital Input BGE
“high” level input
voltage
uVDig_In_High
_BGE
0.7 x
uVIO
–uV
IO V 2); P_15.1.110
“low” level input
voltage
uVDig_In_Low
_BGE
-0.3 – 0.3 x
uVIO
V2); P_15.1.111
“high” level input
current
iDig_In_High_BGE 20 200 μA– P_15.1.112
“low” level input
current
iDig_In_Low_BGE -1 – 1 μA–
1) P_15.1.113
Input capacitance C_BDBGE – – 5 pF 1) P_15.1.114
Digital Input STBN
“high” level input
voltage
uVDig_In_High_ST
BN
0.7 x
uVIO
–uV
IO V 2); P_15.1.120
“low” level input
voltage
uVDig_In_Low_ST
BN
-0.3 – 0.3 x
uVIO
V2); P_15.1.121
“high” level input
current
iDig_In_High
_STBN
20 200 μA– P_15.1.122
“low” level input
current
iDig_In_Low
_STBN
-1 – 1 μA1) P_15.1.123
Input capacitance C_BDSTBN – – 5 pF 1) P_15.1.124
Digital Input EN
“high” level input
voltage
uVDig_In_High_E
N
0.7 x
uVIO
–uV
IO V 2); P_15.1.130
“low” level input
voltage
uVDig_In_Low_EN -0.3 – 0.3 x
uVIO
V2); P_15.1.131
“high” level input
current
iDig_In_High_EN 20 200 μA– P_15.1.132
“low” level input
current
iDig_In_Low_EN -1 – 1 μA1) P_15.1.133
Input capacitance C_BDEN – – 5 pF 1) P_15.1.134
Table 22 Electrical characteristics (cont’d)
5.5 V < uVBAT <18V; 3.0V<uV
IO <5.25V; 4.75V<uV
CC <5.25V; R
DCLOAD =45Ω; CDCLOAD = 100 pF;
-40 °C<T
Junction < 150 °C;
All voltages with respect to ground; positive current flowing into the pin; (unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Data Sheet 79 Rev. 1.3, 2015-09-21
TLE9221SX
Electrical Characteristics
Tx Enable Input: TxEN
“high” level input
voltage
uVDig_In_High_Tx
EN
0.7 x
uVIO
–uV
IO V 2); P_15.1.140
“low” level input
voltage
uVDig_In_Low_Tx
EN
-0.3 – 0.3 x
uVIO
V2); P_15.1.141
“high” level input
current
iDig_In_High_TxEN -1 – 1 μA1); P_15.1.142
“low” level input
current
iDig_In_Low_TxEN -200 – -20 μA– P_15.1.143
Input capacitance C_BDTxEN – – 5 pF 1); P_15.1.144
Maximum time of
Transmitter activation
via TxEN
dBDTxActive
Max
1500 – 2600 µs – P_15.1.145
Table 22 Electrical characteristics (cont’d)
5.5 V < uVBAT <18V; 3.0V<uV
IO <5.25V; 4.75V<uV
CC <5.25V; R
DCLOAD =45Ω; CDCLOAD = 100 pF;
-40 °C<T
Junction < 150 °C;
All voltages with respect to ground; positive current flowing into the pin; (unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Data Sheet 80 Rev. 1.3, 2015-09-21
TLE9221SX
Electrical Characteristics
Analog Output INH
Output voltage;
Not_Sleep
uINH1Not-Sleep uVBAT
- 0.8
– – V iINH1=-0.2mA,
uVBAT >5.5V;
P_15.1.150
Absolute leakage
current;
BD_Sleep
|iINH1Leak|– – 5 μAuINH1=0V; P_15.1.151
Local Wake-up Input WAKE
Wake-up detection
threshold
uBDWakeThr 0.35 x
uVBAT
0.5 x
uVBAT
0.65 x
uVBAT
V– P_15.1.160
Hysteresis on pin Wake uBDWakeHys 0.01 x
uVBAT
0.04 x
uVBAT
0.12 x
uVBAT
V– P_15.1.161
High level input current
(pull-up)
iBDWakeH-20 -9 -2 μAuBDWAKE=
uBDWakeThr +50mV,
(see Figure 8), 5);
P_15.1.162
Low level input current
(pull-down)
iBDWakeL2920μAuBDWAKE=
uBDWakeThr -50mV,
(see Figure 8), 5);
P_15.1.163
Wake pulse filter time dBDWake
PulseFilter
10 – 40 μs (see Figure 10); P_15.1.164
Response time to
indicate the wake-up
dBDWakeup
Reactionlocal
– – 100 μs (see Figure 10); P_15.1.165
Table 22 Electrical characteristics (cont’d)
5.5 V < uVBAT <18V; 3.0V<uV
IO <5.25V; 4.75V<uV
CC <5.25V; R
DCLOAD =45Ω; CDCLOAD = 100 pF;
-40 °C<T
Junction < 150 °C;
All voltages with respect to ground; positive current flowing into the pin; (unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Data Sheet 81 Rev. 1.3, 2015-09-21
TLE9221SX
Electrical Characteristics
Bus Transmitter: BP, BM
Differential output
voltage; (“Data_0”,
“Data_1”),
BD_Normal
uBDTxactive 0.6 – 2.0 V 40 Ω<R
DCLOAD <55Ω, 6); P_15.1.170
Differential output
voltage; “Data_0”,
BD_Normal
uBDTxactive_D0 -2.0 – -0.6 V TxD = “low”, TxEN = “low”,
40 Ω<R
DCLOAD <55Ω;
P_15.1.171
Matching between
differential output
voltages at “Data_0”
and “Data_1”
uBDTxactive
_Diff
-200 – 200 mV BD_Normal, TxEN = “low”,
40 Ω<R
DCLOAD <55Ω,
uBDTxactive_Diff =uBDTx
active
-uBDTx
active_D0;
P_15.1.172
BP absolute maximum
output current,
BP shorted to GND,
no time limit
iBPGND
ShortMax
–2260mA– P_15.1.180
BP absolute maximum
output current,
BP shorted to = -5 V,
no time limit
iBP-5VShortMax –4360mA– P_15.1.181
BP absolute maximum
output current,
BP shorted to = 27 V,
no time limit
iBPBAT27
ShortMax
–3760mA– P_15.1.182
BP absolute maximum
output current,
Short to BM
iBPBMShortMax –3060mA– P_15.1.183
BM absolute maximum
output current,
BM shorted to GND,
no time limit
iBMGND
ShortMax
–2260mA– P_15.1.184
BM absolute maximum
output current,
BM shorted to = -5 V,
no time limit
iBM-5VShortMax –4360mA– P_15.1.185
Table 22 Electrical characteristics (cont’d)
5.5 V < uVBAT <18V; 3.0V<uV
IO <5.25V; 4.75V<uV
CC <5.25V; R
DCLOAD =45Ω; CDCLOAD = 100 pF;
-40 °C<T
Junction < 150 °C;
All voltages with respect to ground; positive current flowing into the pin; (unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Data Sheet 82 Rev. 1.3, 2015-09-21
TLE9221SX
Electrical Characteristics
BM absolute maximum
output current,
BM shorted to = 27 V,
no time limit
iBMBAT27ShortM
ax
–3760mA– P_15.1.186
BM absolute maximum
output current,
Short to BP
iBMBPShortMax –3060mA– P_15.1.187
Transmitter delay
negative voltage
dBDTx10 – 31 50 ns RDCLOAD =40Ω, 6), 7),
(see Figure 35);
P_15.1.200
Transmitter delay
positive voltage
dBDTx01 – 31 50 ns RDCLOAD =40Ω, 6), 7),
(see Figure 35);
P_15.1.201
Transmitter delay
mismatch
dBDTxAsym = |dBDTx10
-dBDTx01|
dBDTxAsym – – 4 ns RDCLOAD =40Ω, 6), 7), 8),
(see Figure 35);
P_15.1.203
Fall time differential bus
voltage, (80% -> 20%)
dBusTx10 6 12 18.75 ns RDCLOAD =40Ω, 6),
(see Figure 35);
P_15.1.204
Rise time differential
bus voltage, (20% -
> 80%)
dBusTx01 6 12 18.75 ns RDCLOAD =40Ω, 6),
(see Figure 35);
P_15.1.205
Difference between
differential bus voltage
rise time and fall time
dBusTxDiff= |dBusTx01
- dBusTx10|
dBusTxDiff – – 3 ns RDCLOAD =40Ω,
(see Figure 35);
P_15.1.206
Transmitter delay
Idle -> active
dBDTxia – 55 75 ns RDCLOAD =40Ω,
(see Figure 36);
P_15.1.210
Transmitter delay
Active -> idle
dBDTxai – 55 75 ns RDCLOAD =40Ω,
(see Figure 36);
P_15.1.211
Transmitter delay
mismatch
dBDTxDM = dBDTxai -
dBDTxia
dBDTxDM -30 – 30 ns RDCLOAD =40Ω,
(see Figure 36);
P_15.1.212
Transition time
Idle -> active
dBusTxia – 15 30 ns RDCLOAD =40Ω,
(see Figure 36);
P_15.1.213
Transition time
Active -> idle
dBusTxai – 15 30 ns RDCLOAD =40Ω,
(see Figure 36);
P_15.1.214
Table 22 Electrical characteristics (cont’d)
5.5 V < uVBAT <18V; 3.0V<uV
IO <5.25V; 4.75V<uV
CC <5.25V; R
DCLOAD =45Ω; CDCLOAD = 100 pF;
-40 °C<T
Junction < 150 °C;
All voltages with respect to ground; positive current flowing into the pin; (unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Data Sheet 83 Rev. 1.3, 2015-09-21
TLE9221SX
Electrical Characteristics
Transmitter delay BGE
Idle -> active
dBDBGEia – 55 75 ns RDCLOAD =40Ω,
(see Figure 37);
P_15.1.215
Transmitter delay BGE
Active -> idle
dBDBGEai – 55 75 ns RDCLOAD =40Ω,
(see Figure 37);
P_15.1.216
Table 22 Electrical characteristics (cont’d)
5.5 V < uVBAT <18V; 3.0V<uV
IO <5.25V; 4.75V<uV
CC <5.25V; R
DCLOAD =45Ω; CDCLOAD = 100 pF;
-40 °C<T
Junction < 150 °C;
All voltages with respect to ground; positive current flowing into the pin; (unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Data Sheet 84 Rev. 1.3, 2015-09-21
TLE9221SX
Electrical Characteristics
Bus Receiver: BP, BM
Receiver threshold for
detecting “Data_1”
uData1 150 – 300 mV -10 V < uCM < 15 V, 9); P_15.1.220
Receiver threshold for
detecting “Data_0”
uData0 -300 – -150 mV -10 V < uCM < 15 V, 9); P_15.1.221
Mismatch of Receiver
thresholds
uData1-
|uData0|
-30 – 30 mV uCM = (uBP+uBM)/2 = 2.5 V; P_15.1.222
Common mode voltage
range
uCM -10 – 15 V 10); P_15.1.230
Filter time for bus idle
detection
dBDIdle
Detection
50 – 200 ns uBus = 900 mV -> 30 mV; P_15.1.231
Filter time for bus active
detection
dBDActivity
Detection
100 – 250 ns uBus = 30 mV -> 900 mV; P_15.1.232
Receiver common mode
input resistance
RCM1, RCM2 10 – 40 kΩBus = “Idle”, open load,
uVCC =5V;
P_15.1.233
Receiver differential
input resistance
RCM1 +R
CM2 20 – 80 kΩBus = “Idle”,
open load;
P_15.1.234
Absolute differential
bus “Idle” voltage,
All modes
uBDTxIdle ––30mVTxEN=“high”,
40 Ω<R
DCLOAD <55Ω;
P_15.1.235
“Idle” voltage on BP and
BM,
non-low power mode
uBias
non-low power
1.8 2.4 3.2 V TxEN = “high”, bus = “Idle”,
uVCC =5V,
40 Ω<R
DCLOAD <55Ω;
P_15.1.240
“Idle” voltage on BP and
BM,
BD_Sleep, BD_Standby,
BD_GoToSleep
uBias
low power
-100 – 100 mV TxEN = “high”, bus = “Idle”,
uVCC =5V,
40 Ω<R
DCLOAD <55Ω;
P_15.1.241
Absolute leakage
current on BP, when
Transmitter off
iBPLeak –715μA uBP = uBM = 5 V,
all other pins connected to
GND;
P_15.1.250
Absolute leakage
current on BM, when
Transmitter off
iBMLeak –715μA uBP = uBM = 5 V,
all other pins connected to
GND;
P_15.1.251
Absolute leakage
current loss to GND on
BP
iBPLeakGND – 500 1600 μA uBP = uBM = 0 V,
all other pins connected to
16 V via 0 Ohm;
P_15.1.252
Table 22 Electrical characteristics (cont’d)
5.5 V < uVBAT <18V; 3.0V<uV
IO <5.25V; 4.75V<uV
CC <5.25V; R
DCLOAD =45Ω; CDCLOAD = 100 pF;
-40 °C<T
Junction < 150 °C;
All voltages with respect to ground; positive current flowing into the pin; (unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Data Sheet 85 Rev. 1.3, 2015-09-21
TLE9221SX
Electrical Characteristics
Absolute leakage
current loss to GND on
BM
iBMLeakGND – 500 1600 μA uBP = uBM = 0 V,
all other pins connected to
16 V via 0 Ohm;
P_15.1.253
Receiver delay, falling
edge
dBDRx10 – 65 75 ns C_BDRxD = 25 pF,
dBUSRx0BD =dBUSRx1
BD >
tBit =60ns,
(see Figure 38);
P_15.1.260
Receiver delay, rising
edge
dBDRx01 – 65 75 ns C_BDRxD = 25 pF,
dBUSRx0BD =dBUSRx1
BD >
tBit =60ns,
(see Figure 38);
P_15.1.261
Receiver delay
mismatch
dBDRxAsym = |dBDRx10
-dBDRx01|
dBDRxAsym – – 5 ns C_BDRxD = 25 pF, 8),
dBUSRx0BD =dBUSRx1
BD >
tBit =60ns,
(see Figure 38);
P_15.1.262
Bus driver idle response
time
dBDRxai 50 – 250 ns C_BDRxEN = 25 pF,
(see Figure 39);
P_15.1.263
Bus driver activity
response time
dBDRxia 100 – 300 ns C_BDRxEN = 25 pF,
(see Figure 39);
P_15.1.264
Idle-Loop delay
dBDTxRxai =
dBDRxai+dBDTxai
dBDTxRxai – – 325 ns C_BDRxEN = 25 pF; P_15.1.265
BP output current, bus
“Idle”
iBPIdle – – 5.0 mA -27 V < BP < 27 V; P_15.1.270
BM output current, bus
“Idle”
iBMIdle – – 5.0 mA -27 V < BM < 27 V; P_15.1.271
Input capacitance at pin
BP
C_BDBP – – 30 pF 1); P_15.1.272
Input capacitance at pin
BM
C_BDBM – – 30 pF 1); P_15.1.273
Differential input
capacitance between
BP and BM
C_BDBus – – 20 pF 1); P_15.1.274
Table 22 Electrical characteristics (cont’d)
5.5 V < uVBAT <18V; 3.0V<uV
IO <5.25V; 4.75V<uV
CC <5.25V; R
DCLOAD =45Ω; CDCLOAD = 100 pF;
-40 °C<T
Junction < 150 °C;
All voltages with respect to ground; positive current flowing into the pin; (unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Data Sheet 86 Rev. 1.3, 2015-09-21
TLE9221SX
Electrical Characteristics
Remote Wake-up Detection: BP, BM
Low-power Receiver
threshold for detecting
“Data_0”
uData0_LP -400 – -100 mV (see Figure 12); P_15.1.280
Acceptance time-out of
a “Data_0” phase in the
wake-up pattern
dWU0Detect 1 – 4 µs (see Figure 12); P_15.1.281
Acceptance time-out of
an “Idle” or “Data 1”
phase in the wake-up
pattern
dWUIdleDetect 1 – 4 µs (see Figure 12); P_15.1.282
Acceptance time-out for
wake-up pattern
recognition
dWUTimeout 48 – 140 µs (see Figure 12); P_15.1.283
Acceptance time-out for
interruptions
dWUInterrupt 0.13 – 1 µs (see Figure 14), 1), 11); P_15.1.284
Response time after
wake-up
dBDWakeup
Reactionremot
e
– – 100 μs (see Figure 12); P_15.1.285
Host Commands and SIR
Mode transition time
after applying the host
command
dBDModeChange – – 100 μs (see Figure 4),
iNH1Leak >0.2mA,
all mode changes;
P_15.1.290
Mode transition time to
BD_Standby after
power-up
dBDPowerUp – – 100 μsV
BAT >uBDUVV
BAT,
VCC >uBDUVV
CC,
(see Figure 24);
P_15.1.291
Filter time for detection
of the host commands
at the pins EN and STBN
dBDLogicFilter 10 – 30 μs (see Figure 4); P_15.1.292
Time for mode selection
via the EN pin within the
Go-To-Sleep command
dBDSleep 25 – 50 μs (see Figure 27); P_15.1.293
Timing window for EN
pin to clock out the SIR
dENClock 358μs (see Figure 5); P_15.1.294
Time-out at the EN pin
for the SIR read-out
dENTimeout 10 – 30 μs (see Figure 5); P_15.1.295
1) Not part of production test, specified by design.
Table 22 Electrical characteristics (cont’d)
5.5 V < uVBAT <18V; 3.0V<uV
IO <5.25V; 4.75V<uV
CC <5.25V; R
DCLOAD =45Ω; CDCLOAD = 100 pF;
-40 °C<T
Junction < 150 °C;
All voltages with respect to ground; positive current flowing into the pin; (unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Data Sheet 87 Rev. 1.3, 2015-09-21
TLE9221SX
Electrical Characteristics
15.2 Diagrams
Figure 34 Simplified test circuit
2) No undervoltage at uVIO and either uVCC or uVBAT with supply.
3) Undervoltage at uVIO and either uVCC or uVBAT with supply.
4) BD_Off state uVCC and uVBAT are without supply (see also Chapter 8.4.1).
5) Currents not tested at full uVBAT range in production, they are specified by design.
6) TxD signal is constant from 100 ns up to 4400 ns before the first edge. The parameter is valid for both polarities.
7) Sum of TxD signal rise and fall time (20% - 80% VIO) of up to 9 ns.
8) Guaranteed for +/- 300 mV as well as for +/- 150 mV level of uBus.
9) Activity detected previously for uBus up to +/- 3000 mV
10) Tested on a receiving bus driver. The sending bus driver has a ground offset voltage in the range of -12.5 V to +12.5 V
and sends a 50/50 test pattern.
11) The minimum value is only guaranteed when the phase that is interrupted was continuously present for at least
870 ns.
TLE9221SX
BP
VBAT VIO
GND
C_BDRxD
ERRN
INH
STBN
EN
TxD
BGE
WAKE
RDCLOAD
CDCLOAD
BM
TxEN
RxEN
RxD
uVIO
100 nF
uVcc
uVBAT
100 nF
VCC
100 nF
C_BDRxEN
C_BDERRN
Data Sheet 88 Rev. 1.3, 2015-09-21
TLE9221SX
Electrical Characteristics
Figure 35 Transmitter characteristics
Figure 36 Transmitter characteristics from “Idle” to “active” and vice versa
100% μVIO
50% μVIO
0% μVIO
TxD
uBDTxActive
300 mV
0 mV
-300 mV
- uBDTxActive
uBus
dBDTx10 dBDTx01
100...4400ns
dBusTx10 dBusTx01
100%
80 %
20 %
0 %
t
t
100% uVIO
50% uVIO
0% uVIO
TxEN
0 V
- 30 mV
- 300 mV
- uBDTxactive
uBus
dBDTxia dBDTxai
dBusTxia dBusTxai
t
t
BGE = “high”
TxD = “low”
Data Sheet 89 Rev. 1.3, 2015-09-21
TLE9221SX
Electrical Characteristics
Figure 37 Transmitter characteristics with bus guardian enable
100% uVIO
50% uVIO
0% uVIO
BGE
0 V
- 30 mV
- 300 mV
- uBDTxactive
uBus
dBDBGEia dBDBGEai
dBusTxia dBusTxai
t
t
TxEN = “low”
TxD = “low”
Data Sheet 90 Rev. 1.3, 2015-09-21
TLE9221SX
Electrical Characteristics
Figure 38 Receiver timing characteristics
uBusRx
Data
300 mV
150 mV
0 V
- 150 mV
- 300 mV
- uBusRx
Data
dBusRx10 dBusRx01
dBusRx0
BD
dBusRx1
BD
100% V
IO
50% V
IO
0% V
IO
dBDRx10 dBDRx01
The Receiver timings are valid for bus signals dBusRx0
BD
and dBusRx1
BD
longer as
the minimum bit time = 60 ns and for both polarities:
dBusRx0
BD
= dBusRx1
BD
> t
Bit
= 60 ns
uBus
t
t
Data Sheet 91 Rev. 1.3, 2015-09-21
TLE9221SX
Electrical Characteristics
Figure 39 Receiver transition from “Idle” to “active” and vice versa
0 V
- 30 mV
- 150 mV
- 300 mV
- uBusRx
dBusActive dBusIdle
100% VIO
50% VIO
0% VIO
dBDRxia dBDRxai
100% VIO
50% VIO
0% VIO
RxD
RxEN
The signals on the pins RxD and RxEN switch within a delay < 10 ns
t
dBusRx10 dBusRx01
uBus
t
t
Data Sheet 92 Rev. 1.3, 2015-09-21
TLE9221SX
Application Information
16 Application Information
16.1 ESD Robustness according to IEC61000-4-2
Tests for ESD robustness according to IEC61000-4-2 “Gun test” (150 pF, 330 Ω) have been performed. The
results and test conditions are available in a separate test report.
16.2 Bus Interface Simulation Model Parameter
The simulated value RBDTransmitter describes the equivalent bus driver output impedance.
Figure 40 Bus driver output resistance
16.3 Typical RxD Output Signals
The simulated RxD output behavior describe the rise and fall times of the RxD pin on a 50 Ohm, 10 pF load at
the end of a standard lossless transmission line with 1 ns propagation delay (see Table 25, Figure 41 and
Figure 42).
Table 23 ESD robustness according to IEC61000-4-2
Performed Test Symbol Result Unit Remarks
Electrostatic discharge voltage at pin BM, BP and WAKE versus
GND
uESDIEC ≥ +11 kV 1), 2) Positive pulse
1)ESD susceptibility “ESD GUN IEC61000-4-2”.
Tested by external test facility (IBEE Zwickau, EMC test report no.: 22-02-13).
2) Test result without any external bus filter network, e.g. common mode choke.
Electrostatic discharge voltage at pin BM, BP and WAKE versus
GND
uESDIEC ≤ -11 kV 1), 2) Negative pulse
Table 24 Bus driver simulation resistor
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Bus driver interface simulation resistor RDBDTransmitter 30 100 500 Ω1);
1) Simulated value for reference purposes only.
R
BDTransmitter
= 50Ω x ( uBus
100
– uBus
40
) / ( 2.5 x uBus
40
– uBus
100
)
uBus
100
= differential output voltage on a
100Ω||100pF load,
while driving “Data_1” to the bus. Value based on simulation.
uBus
40
= differential output voltage on a
40Ω||100pF load,
while driving “Data_1” to the bus. Value based on simulation.
Data Sheet 93 Rev. 1.3, 2015-09-21
TLE9221SX
Application Information
Figure 41 RxD output rise time (typical simulation value)
Table 25 RxD output signal (simulated values)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Sum of rise and fall time on the
RxD output
dBDRxDR10+
dBDRxDF10
– – 16.5 ns C_BDRxD = 10 pF, 1)
R_CBDRxD = 50 Ω;
1) Simulated value for reference purposes only.
Difference of rise and fall time on
the RxD output
|dBDRxDR10 -
dBDRxDF10|
––5 nsC_BDRxD=10pF,
1)
R_CBDRxD = 50 Ω;
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
0.0 5.0 10.0 15.0 20.0 25.0
30.0
V
RxD
in V
t in ns
RxD output - rise time (typical) RxD output - rise time (typical)
Data Sheet 94 Rev. 1.3, 2015-09-21
TLE9221SX
Application Information
Figure 42 RxD output fall time (typical simulation value)
16.4 Operating Temperature
The FlexRay transceiver TLE9221SX is qualified for temperature Grade 1 (-40°C to +125°C ambient operating
temperature) according to AEC - Q100. Grade 1 according AEC - Q100 is equivalent to the ambient
temperature for class 1 TAMB_Class1.
Infineon specifies for the electrical characteristics (see Table 22) the junction temperature TJunction. The
ambient temperature can be calculated with the power dissipation and the thermal resistance RthJA (see
Figure 43).
Figure 43 Ambient temperature TA calculation
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
0 5 10 15 20 25 30
V
RxD
in V
t in ns
RxD output - fall time (typical)
TJ = TA + RthJA x Pd
TA = TJ - RthJA x Pd
with:
TA= ambient temperature
TJ= junction temperature
Pd= power dissipation of the FlexRay transceiver
RthJA = thermal resistance junction to ambient
Data Sheet 95 Rev. 1.3, 2015-09-21
TLE9221SX
Application Information
16.5 Application Example
Figure 44 Simplified application example for the TLE9221SX
16.6 Further Application Information
• Please contact us for information regarding the pin FMEA.
• For further information you may visit: http://www.infineon.com
RTA
e.g TLE4473GV53
INH1
INH2
1
Q1
Q2
10μF
10 μF
16
3
7
9
10
5
8
6
2
4
Micro Controller
e.g.
TC17xx-Series
GND
100nF
100nF
11
100nF
15
12
100kΩ
LCMC
RTB
13
FlexRay
Communication
Controller
INH
VBAT
VCC
VIO
BP
BM
WAKE
BGE
RxEN
TxEN
TxD
RxD
ERRN
STBN
EN
BP
BM
GND
14
LDO
100nF
GND
10 μF
WAKE
VBAT
Data Sheet 96 Rev. 1.3, 2015-09-21
TLE9221SX
Package Outlines
17 Package Outlines
Figure 45 PG-SSOP-16
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations, the device is available as a green product. Green products are RoHS compliant
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.Dimensions in mm
Data Sheet 97 Rev. 1.3, 2015-09-21
TLE9221SX
Revision History
18 Revision History
Revision Date Changes
1.3 2015-08-18 Data Sheet updated based on Data Sheet Rev. 1.2:
Package name changed to PG-SSOP-16:
• All Pages
Paragraph on FlexRay Consortium removed:
•Page 6, Description
“ISO 17458” added:
•Page 5, Features
•Page 6, Description
Reference to FlexRay EPL removed:
•Page 5, Features
•Page 6, Description
•Page 11, Functional Description
•Page 19, Host Interface
•Page 20, Power Supply Interface
•Page 26, Reset the ERRN Output Pin
•Page 27, Wake-up Detector
•Page 35, INH Output
•Page 45, Operating Mode Description
•Page 56, BD_Sleep Mode Entry Flag
“CT index ...” removed:
•Table 19, Absolute maximum ratings voltages, currents and
temperatures
•Table 20, Functional range
•Table 22, Electrical characteristics
•Table 23, ESD robustness according to IEC61000-4-2
•Table 24, Bus driver simulation resistor
•Table 25, RxD output signal (simulated values)
•Page 94, Operating Temperature
1.2 2015-03-11 Data Sheet updated based on Data Sheet Rev. 1.1:
• All pages:
Changed package name to PG-SSOP16-1
•Page 12, Table 2
Footnote updated
•Page 69, Table 20
Max. limit of the extended functional range for uVBAT_EXT (P_14.2.2) updated.
Trademarks of Infineon Technologies AG
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EconoDUAL™, EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I2RF™, ISOFACE™, IsoPACK™, LITIX™, MIPAQ™,
ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™, POWERCODE™, PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,
ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SPOC™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited,
UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of
Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay
Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association
Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc.
MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave
Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of
Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc.
TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.
Last Trademarks Update 2011-11-11
Edition 2015-09-21
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG.
All Rights Reserved.
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examples or hints given herein, any typical
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Technologies hereby disclaims any and all
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without limitation, warranties of non-
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