2001-2013 Microchip Technology Inc. DS39582C-page 1
PIC16F87XA
Devices Included in thi s Data Sheet:
High-Performance RISC CPU:
• Only 35 single-word instructions to learn
• All single-cycle instructions except for program
branches, which are two-cycle
• Operating speed: DC – 20 MHz clock input
DC – 200 n s instruct ion cycle
• Up to 8K x 14 words of Flash Program Memory,
Up to 368 x 8 bytes of Data Memory (RAM),
Up to 256 x 8 bytes of EEPROM Data Memory
• Pinout compatible to other 28-pin or 40/44-pin
PIC16CXXX and PIC16FXXX microcontrollers
Peripheral Feat ures:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be increm en ted duri ng Slee p via extern al
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Two Capture, Compare, PWM modules
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• Synchronous Serial Port (SSP) with SPI
(Master mode) and I2C™(Master/Slave)
• Universal Synchronous Asynchronous Receiver
Transmitter (USAR T/SCI) with 9-bi t address
detection
• Parallel Slave Port (PSP) – 8 bits wide with
external RD , WR a nd CS co ntro ls (40/44-pin only)
• Brown-out detection circuitry for
Brown-out Reset (BOR)
Analog Features:
• 10-bit, up to 8-channel Analog-to-Digital
Converter (A/D)
• Brown-out Reset (BOR)
• Analog Comparator mod ule with:
- Two analog compara tors
- Programmable on-chip voltage reference
(VREF) module
- Programmabl e input multi plexing fr om device
inputs and internal voltage reference
- Comparator outputs are externally accessible
S pecial Microc ontroller Features:
• 100,000 eras e/w ri te cy cl e Enhanced Flash
program memory typical
• 1,000,000 erase/write cycle Data EEPROM
memory typical
• Data EEPROM Retention > 40 years
• Self-reprogrammable under software control
• In-Circuit Serial Programming™ (ICSP™)
via two pins
• Single-supply 5V In-Circuit Serial Programming
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
• Power saving Sleep mode
• Selectable oscillator opti ons
• In-Circuit Debug (ICD) via two pins
CMOS Technology:
• Low-power, high-speed Flash/EEPROM
technology
• Fully static design
• Wide operating voltage range (2.0V to 5.5V)
• Commercial and Industrial temperature ranges
• Low-power consumption
• PIC16F873A
• PIC16F874A •PIC16F876A
•PIC16F877A
Device
Program Memory Data
SRAM
(Bytes)
EEPROM
(Bytes) I/O 10-bit
A/D (ch) CCP
(PWM)
MSSP
USART Timers
8/16-bit Comparators
Bytes # Single Word
Instructions SPI Master
I2C
PIC16F873A 7.2K 4096 192 128 22 5 2 Yes Yes Yes 2/1 2
PIC16F874A 7.2K 4096 192 128 33 8 2 Yes Yes Yes 2/1 2
PIC16F876A 14.3K 8192 368 256 22 5 2 Yes Yes Yes 2/1 2
PIC16F877A 14.3K 8192 368 256 33 8 2 Yes Yes Yes 2/1 2
28/40/44-Pin Enhanced Flash Microcontrollers
PIC16F87XA
DS39582C-page 2 2001-2013 Microchip Technology Inc.
Pin Diagrams
PIC16F873A/876A
10
11
2
3
4
5
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
VSS
OSC1/CLKI
OSC2/CLKO
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
28-Pin PDIP, SOIC, SSOP
2
3
4
5
6
1
7
MCLR/VPP
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
VSS
OSC1/CLKI 15
16
17
18
19
20
21 RB3/PGM
VDD
VSS
RB0/INT
RC7/RX/DT
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK 23
24
25
26
27
28
22
RA1/AN1
RA0/AN0
RB7/PGD
RB6/PGC
RB5
RB4
10
11
8
9
12
13
14
28-Pin QFN
PIC16F873A
PIC16F876A
RB2
RB1
RC0/T1OSO/T1CKI
OSC2/CLKO
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC16F874A
37
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
MCLR/VPP
RB3/PGM
RB7/PGD
RB6/PGC
RB5
RB4
NC RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
RC0/T1OSO/T1CKI
OSC2/CLKO
OSC1/CLKI
VSS
VSS
VDD
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS/C2OUT
RA4/T0CKI/C1OUT
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
VDD
RB0/INT
RB1
RB2
44-Pin QFN
PIC16F877A
2001-2013 Microchip Technology Inc. DS39582C-page 3
PIC16F87XA
Pin Diagrams (Continued)
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI
OSC2/CLKO
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC16F874A/877A
40-Pin PDIP
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
44
8
7
6
5
4
3
2
1
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
9
PIC16F874A
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RE0/RD/AN5
OSC1/CLKI
OSC2/CLKO
RC0/T1OSO/T1CK1
NC
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7/PGD
RB6/PGC
RB5
RB4
NC
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC16F874A
37
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7/PGD
RB6/PGC
RB5
RB4
NC RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
NC
NC
RC0/T1OSO/T1CKI
OSC2/CLKO
OSC1/CLKI
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS/C2OUT
RA4/T0CKI/C1OUT
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3/PGM
44-Pin PLCC
44-Pin TQFP
PIC16F877A
PIC16F877A
RC7/RX/DT
PIC16F87XA
DS39582C-page 4 2001-2013 Microchip Technology Inc.
Table of Contents
1.0 Device Overview......................................................................................................................................................................... 5
2.0 Memory Organization................................................................................................................................................................ 15
3.0 Da ta EE PROM and Flash Program Memory............................................................................................. ............................... 3 3
4.0 I/O Ports.................................................................................................................................................................................... 41
5.0 Timer0 Module................................... .... .. .... .. .. ....... .... .. .. .... .. .. ....... .... .. .... .. .. ....... .... .. .. .............................................................. 53
6.0 Timer1 Module................................... .... .. .... .. .. ....... .... .. .. .... .. .. ....... .... .. .... .. .. ....... .... .. .. .............................................................. 57
7.0 Timer2 Module................................... .... .. .... .. .. ....... .... .. .. .... .. .. ....... .... .. .... .. .. ....... .... .. .. .............................................................. 61
8.0 Ca pture/Com pare/P WM Modules....................................................................................................... ..... .. ............................... 6 3
9.0 M aste r Sync hronous Ser ial Port (MS SP ) Module.......................................... ..................... ...................................................... 7 1
10.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USA RT)............................................................ 111
11.0 Analog-to-Digital Converter (A/D) Module ................................................................................. .. ........................................... 127
12.0 Comparator Module............................................................................................................ .. .................................................. 135
13.0 Comparator Voltage Reference Module ............ ......... .... .... .... ......... .... .... .... ......... .... .... .... ......... ..... ........................................ 14 1
14.0 Special Features of the CPU.............................................................................................................................................. .. .. 1 4 3
15.0 Instructio n Se t Summary ......... ..................... ........... .......... ........... .......... ..................... ............................................................ 159
16.0 Development Support....... .... .. .... ......... .. .... .... .. ......... .. .... .... .. ......... .... .. .... .... ....... .... .. .... .... ...................................................... 167
17.0 Elec trical Characteri stics... .......... ..................... ........... ..................... ..................... ........... .................................. .. ................... 1 7 3
18.0 DC and AC Characteristics Graphs and Tables . .................................................................................................................... 197
19.0 Packaging Information.................................................................................................................................................. .. ........ 2 0 9
Appendix A: Revision History................ ........... .... .... .... ........... ...... .... ........... .... .... ........... ...... ............................................................ 21 9
Appendix B: Device Differences............................. .... ........... .... .... .... ......... .... .... .... ........... .... .... .................................................... .. .. 2 1 9
Appendix C:Conversion Considerations................................... .... .... ....... .... .... .. .... ....... .... .... .. .... ...... ................................................ 22 0
Index ................................................................................................................................ .. ........... .. .................................................. 221
On-Line Support...................................... ......... .... .... .... ......... .... .... .... ......... .... .... .... ......... .................................................................. 229
Systems Information and Upgrade Hot Line............................................................................................. .. ...................................... 229
Reader Response............................................................................................................................................................................. 230
PIC16F87XA Product Identification System......................................................... ............... ...... ........................................................ 231
TO OUR VALUED CUSTO MERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to im prove our pu blications to better s uit your needs. Our publications will be refined and
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If you have any questions or c omm ents regardi ng this publication, please contact the M arketing Communications Department via
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We welcome your feedback.
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Errata
An errata sheet, describing minor operational differences from the dat a sheet and recommended workarounds, may exist f or current
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2001-2013 Microchip Technology Inc. DS39582C-page 5
PIC16F87XA
1.0 DEVICE OVERVIEW
This document contains device specific information
about the following devi ces:
• PIC16F873A
• PIC16F874A
• PIC16F876A
• PIC16F877A
PIC16F8 73A/876 A devic es are ava ilabl e only in 28-pi n
pack ages, while PIC16F874A/877A devices are avail-
able in 40-pin and 44-pin packages. All devices in the
PIC16F87XA family share common architecture with
the following diffe rences:
• The PIC16F 873A and PIC16F874 A have one-h alf
of the total on-chip memory of the PIC16F876A
and PIC16F877A
• The 28 -pin device s have three I/O port s, while the
40/44-pin devices have five
• The 28 -pin device s have fourteen interrupt s, while
the 40/44-pin devices have fifteen
• The 28-pin devices have five A/D input channels,
while the 40/44-pin devices have eight
• The Parall el Slave Port is implemented only on
the 40/44-pin devices
The available features are summarized in Table 1-1.
Block diagrams of the PIC16F873A/876A and
PIC16F874A/877A devices are provided in Figure 1-1
and Figure 1-2, respectively. The pinouts for these
device families are listed in Table 1-2 and Table 1-3.
Additional information may be found in the PIC® Mid-
Range Reference Manual (DS33023), which may be
obtained from your local Microchip Sales Representative
or downloaded from the Microchip web si te. The Refer-
ence Manual should be considered a complementary
document to this dat a sheet and is highly recommended
reading for a better understanding of the device architec-
ture and operation of the peripheral mo dules.
TABLE 1-1: PIC16F87XA DEVICE FEATURES
Key Features PIC16F873A PIC16F874A PIC16F876A PIC16F877A
Operating Frequency DC – 20 MHz DC – 20 MHz DC – 20 MHz DC – 20 MHz
Resets (and Delays) POR, BOR
(PWRT, OST) POR, BOR
(PWRT, OST) POR, BOR
(PWRT, OST) POR, BOR
(PWR T, OST)
Flash Program Memory
(14-bit words) 4K 4K 8K 8K
Data Memory (bytes) 192 192 368 368
EEPROM Data Memory (bytes) 128 128 256 256
Interrupts 14 15 14 15
I/O Ports Ports A, B, C Ports A, B, C, D, E Ports A, B, C Ports A, B, C, D, E
Timers 3333
Capt ure/Compare/ PWM modules 2 2 2 2
Serial Communications MSSP, USART MSSP, USART MSSP, USART MSSP, USART
Parallel Communications — PSP — PSP
10-bit Analog-to-Digital Module 5 input channels 8 input channels 5 input channels 8 input channels
Analog Comparators 2 2 2 2
Instruction Set 35 Instructions 35 Instructions 35 Instructions 35 Instructions
Packages 28-pin PDIP
28-pin SOIC
28-pin SS OP
28-pin Q FN
40-pin PDIP
44-pin PLCC
44-pin TQFP
44-pin QF N
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
40-pin PDIP
44-pin PLCC
44-pin TQFP
44-pin QFN
PIC16F87XA
DS39582C-page 6 2001-2013 Microchip Technology Inc.
FIGURE 1-1: PIC16F87 3A/8 76A BLOC K DIAGRAM
Flash
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level S tack
(13-bit)
RAM
File
Registers
Direct Addr 7
RAM Addr(1) 9
Addr MUX
Indirect
Addr
FSR reg
Status re g
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
MCLR VDD, VSS
PORTA
PORTB
PORTC
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RB0/INT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
8
8
Brown-out
Reset
Note 1: Higher order bits are from th e Status register.
USART
CCP1,2 Synchronous
10-bit A/D
Timer0 Timer1 Timer2
Serial Port
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
8
3
Data EEPROM
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
In-Circuit
Debugger
Low-Voltage
Programming
Comparator Voltage
Reference
Device Program Flash Data Memory Data EEPROM
PIC16F 873 A 4K words 192 Bytes 128 Bytes
PIC16F 876 A 8K words 368 Bytes 256 Bytes
Program
Memory
2001-2013 Microchip Technology Inc. DS39582C-page 7
PIC16F87XA
FIGURE 1-2: PIC16F87 4A/8 77A BLOC K DIAGRAM
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
Direct Addr 7
RAM Addr(1) 9
Addr MUX
Indirect
Addr
FSR reg
Status reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
MCLR VDD, VSS
PORTA
PORTB
PORTC
PORTD
PORTE
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
8
8
Brown-out
Reset
Note 1: Higher order bits are from the Status register.
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
Parallel
8
3
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
In-Circuit
Debugger
Low-Voltage
Programming
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
USART
CCP1,2 Synchronous
10-bit A/D
Timer0 Timer1 Timer2
Seri a l Port
Data EEPROM Comparator Voltage
Reference
Device Program Fl ash Data Memory Data EEPROM
PIC16F874A 4K words 192 Bytes 128 Bytes
PIC16F877A 8K words 368 Bytes 256 Bytes
Flash
Program
Memory
Slave Port
PIC16F87XA
DS39582C-page 8 2001-2013 Microchip Technology Inc.
TABLE 1-2: PIC16F873A/876A PINOUT DESCRIPTION
Pin Name PDIP , SOIC,
SSOP Pin# QFN
Pin# I/O/P
Type Buffer
Type Description
OSC1/CLKI
OSC1
CLKI
96I
I
ST/CMOS(3) Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input. ST
buffer when configured in RC mode; otherwise CMOS.
External clock source input. Always associated with pin
function OSC1 (see OSC1/CLKI, OSC2/CLKO pins).
OSC2/CLKO
OSC2
CLKO
10 7 O
O
— Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
MCLR/VPP
MCLR
VPP
126
I
P
ST Master Clear (input) or programming voltage (output).
Master Clear (Reset) input. This pin is an active low Reset
to the device.
Programming voltage input.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
227
I/O
I
TTL Digi tal I/O.
Analog input 0.
RA1/AN1
RA1
AN1
328
I/O
I
TTL Digi tal I/O.
Analog input 1.
RA2/AN2/VREF-/
CVREF
RA2
AN2
VREF-
CVREF
41
I/O
I
I
O
TTL Digi tal I/O.
Analog input 2.
A/D reference voltage (Low) input.
Comparator VREF output.
RA3/AN3/VREF+
RA3
AN3
VREF+
52
I/O
I
I
TTL Digi tal I/O.
Analog input 3.
A/D reference voltage (High) input.
RA4/T0CKI/C1OUT
RA4
T0CKI
C1OUT
63
I/O
I
O
ST Digital I/O – Open-drain when configured as output.
Timer0 external clock input.
Comparator 1 output.
RA5/AN4/SS/C2OUT
RA5
AN4
SS
C2OUT
74
I/O
I
I
O
TTL Digi tal I/O.
Analog input 4.
SPI slave select input.
Comparator 2 output.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a S chmit t Trigger input when used in Serial Programming mode.
3: This buffer is a S chmit t Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
2001-2013 Microchip Technology Inc. DS39582C-page 9
PIC16F87XA
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT
RB0
INT
21 18 I/O
I
TTL/ST(1)
Digit a l I/O.
External interrupt.
RB1 22 19 I/O TTL Digit a l I/O.
RB2 23 20 I/O TTL Digit a l I/O.
RB3/PGM
RB3
PGM
24 21 I/O
I
TTL Digi tal I/O.
Low-voltage (single-supply) ICSP programming enable pin.
RB4 25 22 I/O TTL Digit a l I/O.
RB5 26 23 I/O TTL Digit a l I/O.
RB6/PGC
RB6
PGC
27 24 I/O
I
TTL/ST(2)
Digit a l I/O.
In-circuit debugger and ICSP programming clock.
RB7/PGD
RB7
PGD
28 25 I/O
I/O
TTL/ST(2)
Digit a l I/O.
In-circuit debugger and ICSP programming data.
PORTC is a bidirectional I /O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
11 8 I/O
O
I
ST Digit a l I/O.
Timer1 oscillator output.
Timer1 external clock input.
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
12 9 I/O
I
I/O
ST Digit a l I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
RC2/CCP1
RC2
CCP1
13 10 I/O
I/O
ST Digit a l I/O.
Capture1 input, Compare1 output, PWM1 output.
RC3/SCK/SCL
RC3
SCK
SCL
14 11 I/O
I/O
I/O
ST Digit a l I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
RC4/SDI/SDA
RC4
SDI
SDA
15 12 I/O
I
I/O
ST Digit a l I/O.
SPI data in.
I2C data I/O.
RC5/SDO
RC5
SDO
16 13 I/O
O
ST Digit a l I/O.
SPI data out.
RC6/TX/CK
RC6
TX
CK
17 14 I/O
O
I/O
ST Digit a l I/O.
USART asynchronous transmit.
USART1 synchronous clock.
RC7/RX/DT
RC7
RX
DT
18 15 I/O
I
I/O
ST Digit a l I/O.
USART asynchronous receive.
USART synchronous data.
VSS 8, 19 5, 6 P — Gr ound reference for logic and I/O pins.
VDD 20 17 P — Posit ive supply for logic and I/O pins.
TABLE 1-2: PIC16F873A/876A PINOUT DESCRIPTION (CONTINUED)
Pin Name PDIP , SOIC,
SSOP Pin# QFN
Pin# I/O/P
Type Buffer
Type Description
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a S chmit t Trigger input when used in Serial Programming mode.
3: This buffer is a S chmit t Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
PIC16F87XA
DS39582C-page 10 2001-2013 Microchip Technology Inc.
TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION
Pin Name PDIP
Pin# PLCC
Pin# TQFP
Pin# QFN
Pin# I/O/P
Type Buffer
Type Description
OSC1/CLKI
OSC1
CLKI
13 14 30 32 I
I
ST/CMOS(4) Oscillator crystal or external clock input.
Oscillator crystal input or external clock source
input. ST buffer when configured in RC mode;
otherwise CMOS.
External clock source input. Always associated
with pin function OSC1 (see OSC1/CLKI,
OSC2/CLKO pins).
OSC2/CLKO
OSC2
CLKO
14 15 31 33 O
O
— Oscillator cryst al or clock output.
Oscillator crystal output.
Connects to cryst al or resonator in Crystal
Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which
has 1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
MCLR/VPP
MCLR
VPP
1 2 18 18 I
P
ST Master Clear (input) or programming voltage (output).
Master Clear (Reset) input. This pin is an active
low Reset to the device.
Programming voltage input.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
2 3 19 19 I/O
I
TTL Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
3 4 20 20 I/O
I
TTL Digital I/O.
Analog input 1.
RA2/AN2/VREF-/CVREF
RA2
AN2
VREF-
CVREF
4 5 21 21 I/O
I
I
O
TTL Digital I/O.
Analog input 2.
A/D reference voltage (Low) input.
Comparator VREF output.
RA3/AN3/VREF+
RA3
AN3
VREF+
5 6 22 22 I/O
I
I
TTL Digital I/O.
Analog input 3.
A/D reference voltage (High) input.
RA4/T0CKI/C1OUT
RA4
T0CKI
C1OUT
6 7 23 23 I/O
I
O
ST Digital I/O – Open-drain when configured as
output.
Timer0 external clock input.
Comparator 1 output.
RA5/AN4/SS/C2OUT
RA5
AN4
SS
C2OUT
7 8 24 24 I/O
I
I
O
TTL Digital I/O.
Analog input 4.
SPI slave select input.
Comparator 2 output.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
2001-2013 Microchip Technology Inc. DS39582C-page 11
PIC16F87XA
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-up on all
inputs.
RB0/INT
RB0
INT
33 36 8 9I/O
I
TTL/ST(1)
Digital I/O.
External interrupt.
RB1 34 37 9 10 I/O TTL Digital I/O.
RB2 35 38 10 11 I/O TTL Digital I/O.
RB3/PGM
RB3
PGM
36 39 11 12 I/O
I
TTL Digital I/O.
Low-voltage ICSP programming enable pin.
RB4 37 41 14 14 I/O TTL Digital I/O.
RB5 38 42 15 15 I/O TTL Digital I/O.
RB6/PGC
RB6
PGC
39 43 16 16 I/O
I
TTL/ST(2)
Digital I/O.
In-circuit debugger and ICSP programming clock.
RB7/PGD
RB7
PGD
40 44 17 17 I/O
I/O
TTL/ST(2)
Digital I/O.
In-circuit debugger and ICSP programming data.
TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED)
Pin Name PDIP
Pin# PLCC
Pin# TQFP
Pin# QFN
Pin# I/O/P
Type Buffer
Type Description
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
PIC16F87XA
DS39582C-page 12 2001-2013 Microchip Technology Inc.
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
15 16 32 34 I/O
O
I
ST Digital I/O.
Tim er1 oscillator output.
Timer1 external clock input.
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
16 18 35 35 I/O
I
I/O
ST Digital I/O.
Timer1 oscillator input.
Capture2 input, C ompare2 output, PWM2 output.
RC2/CCP1
RC2
CCP1
17 19 36 36 I/O
I/O
ST Digital I/O.
Capture1 input, C ompare1 output, PWM1 output.
RC3/SCK/SCL
RC3
SCK
SCL
18 20 37 37 I/O
I/O
I/O
ST Digital I/O.
Synchronous serial clock input/output for SPI
mode.
Synchronous serial clock input/output for I2C
mode.
RC4/SDI/SDA
RC4
SDI
SDA
23 25 42 42 I/O
I
I/O
ST Digital I/O.
SPI data in.
I2C data I/O.
RC5/SDO
RC5
SDO
24 26 43 43 I/O
O
ST Digital I/O.
SPI data out.
RC6/TX/CK
RC6
TX
CK
25 27 44 44 I/O
O
I/O
ST Digital I/O.
USART asynchronous transmit.
USART1 synchronous clock.
RC7/RX/DT
RC7
RX
DT
26 29 1 1 I/O
I
I/O
ST Digital I/O.
USART asynchronous receive.
USART synchronous data.
TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED)
Pin Name PDIP
Pin# PLCC
Pin# TQFP
Pin# QFN
Pin# I/O/P
Type Buffer
Type Description
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
2001-2013 Microchip Technology Inc. DS39582C-page 13
PIC16F87XA
PORTD is a bidirectional I/O port or Parallel Slave
Port when interfacing to a microprocessor bus.
RD0/PSP0
RD0
PSP0
19 21 38 38 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD1/PSP1
RD1
PSP1
20 22 39 39 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD2/PSP2
RD2
PSP2
21 23 40 40 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD3/PSP3
RD3
PSP3
22 24 41 41 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD4/PSP4
RD4
PSP4
27 30 2 2 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD5/PSP5
RD5
PSP5
28 31 3 3 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD6/PSP6
RD6
PSP6
29 32 4 4 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD7/PSP7
RD7
PSP7
30 33 5 5 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
PORTE is a bidirectional I/O port.
RE0/RD/AN5
RE0
RD
AN5
8 9 25 25 I/O
I
I
ST/TTL(3)
Digital I/O.
Read control for Parallel Slave Port.
Analog input 5.
RE1/WR/AN6
RE1
WR
AN6
9102626I/O
I
I
ST/TTL(3)
Digital I/O.
Write control for Parallel Slave Port.
Analog input 6.
RE2/CS/AN7
RE2
CS
AN7
10 11 27 27 I/O
I
I
ST/TTL(3)
Digital I/O.
Chip select control for Parallel Slave Port.
Analog input 7.
VSS 12, 31 13, 34 6, 29 6, 30,
31 P — Ground reference for logic and I/O pins.
VDD 11, 32 12, 35 7, 28 7, 8,
28, 29 P — Positive supply for logic and I/O pins.
NC — 1, 17,
28, 40 12,13,
33, 34 13 — — These pins are not internally connected. These pins
should be left unconnected.
TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED)
Pin Name PDIP
Pin# PLCC
Pin# TQFP
Pin# QFN
Pin# I/O/P
Type Buffer
Type Description
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
PIC16F87XA
DS39582C-page 14 2001-2013 Microchip Technology Inc.
NOTES:
2001-2013 Microchip Technology Inc. DS39582C-page 15
PIC16F87XA
2.0 MEMORY ORGANIZATION
There are three memory blocks in each of the
PIC16F87XA devices. The program memory and data
memory have separate buses so that concurrent
access can occur and is detailed in this section. The
EEPROM dat a memory block is detaile d in Section 3.0
“Data EEPROM and Flash Program Memory”.
Addit ional informat ion on devi ce memory may be found
in the PIC® Mid-Range M CU Family R eference Manual
(DS33023).
FIGURE 2-1: PIC16F87 6A/8 77A
PROGRAM MEMORY MAP
AND STACK
2.1 Program Memory Organization
The PIC16F87XA devices have a 13-bit program coun-
ter capable of addressing an 8K word x 14 bit program
memory space. The PIC16F876A/877A devices have
8K words x 14 bits of Flash program memory, while
PIC16F873A/874A devices have 4K words x 14 bits.
Accessing a location above the physically implemented
address will cause a w rap around.
The Rese t vector is at 000 0h and the interru pt vector is
at 0004h.
FIGURE 2-2: PIC16F873A/874A
PROGRAM MEMORY MAP
AND STACK
PC<12:0>
13
0000h
0004h
0005h
Stack Level 1
Stack Level 8
Reset V ector
Interrupt Vector
On-Chip
CALL, RETURN
RETFIE, RETLW
1FFFh
Stack Level 2
Program
Memory
Page 0
Page 1
Page 2
Page 3
07FFh
0800h
0FFFh
1000h
17FFh
1800h
PC<12:0>
13
0000h
0004h
0005h
Stack Level 1
Stack Level 8
Reset Ve ctor
Interrupt Vector
On-Chip
CALL, RETURN
RETFIE, RETLW
1FFFh
Stack Level 2
Program
Memory
Page 0
Page 1
07FFh
0800h
0FFFh
1000h
PIC16F87XA
DS39582C-page 16 2001-2013 Microchip Technology Inc.
2.2 Data Memory Organiz ation
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (Status<6>) and
RP0 (Status<5>) are the bank select bits .
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the S pecial Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
2.2.1 GENERAL PURPOSE REGISTER
FILE
The register file can be accessed either directly, or
indirectly, through the File Select Register (FSR).
RP1:RP0 Bank
00 0
01 1
10 2
11 3
Note: The EEPROM data memory description can
be found in Section 3.0 “Data EEPROM
and Flash Prog ram Memory” of thi s data
sheet.
2001-2013 Microchip Technology Inc. DS39582C-page 17
PIC16F87XA
FIGURE 2-3: PIC16F87 6A/8 77A REG IST ER FILE MAP
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PIE1
PCON
PR2
SSPADD
SSPSTAT
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
7Fh FFh
Bank 0 Bank 1
Unimplemented data memory locations, read as ‘0’.
* Not a physical register.
Note 1: These registers are not implemented on the PIC16F876A.
2: These regi sters are reserved; maintain these registers clear.
File
Address
Indirect addr.(*) Indirect addr.(*)
PCL
STATUS
FSR
PCLATH
INTCON
PCL
STATUS
FSR
PCLATH
INTCON
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
120h 1A0h
17Fh 1FFh
Bank 2 Bank 3
Indirect addr.(*)
PORTD(1)
PORTE(1) TRISD(1)
ADRESL
TRISE(1)
TMR0 OPTION_REG
PIR2 PIE2
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
TXSTA
SPBRG
ADCON1
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
1EFh
1F0h
accesses
70h - 7Fh
EFh
F0h
accesses
70h-7Fh
16Fh
170h
accesses
70h-7Fh
General
Purpose
Register
General
Purpose
Register
TRISB
PORTB
96 Bytes
80 Bytes 80 Bytes 80 Bytes
16 Bytes 16 Bytes
SSPCON2
EEDATA
EEADR EECON1
EECON2
EEDATH
EEADRH Reserved(2)
Reserved(2)
File
Address File
Address File
Address
CMCON
CVRCON
PIC16F87XA
DS39582C-page 18 2001-2013 Microchip Technology Inc.
FIGURE 2-4: PIC16F87 3A/8 74A REG IST ER FILE MAP
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PIE1
PCON
PR2
SSPADD
SSPSTAT
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
7Fh FFh
Bank 0 Bank 1
Indirect addr.(*) Indire ct add r.(*)
PCL
STATUS
FSR
PCLATH
INTCON
PCL
STATUS
FSR
PCLATH
INTCON
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
17Fh 1FFh
Bank 2 Bank 3
Indirect addr.(*)
PORTD(1)
PORTE(1) TRISD(1)
ADRESL
TRISE(1)
TMR0 OPTION_REG
PIR2 PIE2
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
TXSTA
SPBRG
ADCON1
General
Purpose
Register
General
Purpose
Register
1EFh
1F0h
accesses
A0h - FFh
16Fh
170h
accesses
20h-7Fh
TRISB
PORTB
96 Bytes 96 Bytes
SSPCON2
10Ch
10Dh
10Eh
10Fh
110h
18Ch
18Dh
18Eh
18Fh
190h
EEDATA
EEADR EECON1
EECON2
EEDATH
EEADRH Reserved(2)
Reserved(2)
Unimplemented data memory locations, read as ‘0’.
* Not a physical register.
Note 1: These registers are not implemented on the PIC16F873A.
2: These registers are re served; maintain these registers clear.
120h 1A0h
File
Address
File
Address File
Address
File
Address
CMCON
CVRCON
2001-2013 Microchip Technology Inc. DS39582C-page 19
PIC16F87XA
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral features section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR Details
on pag e:
Bank 0
00h(3) INDF Addressi ng this location us es contents of FSR to address dat a memory (not a physic al register) 0000 0000 31, 150
01h TMR0 Timer0 Module Register xxxx xxxx 55, 150
02h(3) PCL Program Counter (PC) Lea st Signif icant Byte 0000 0000 30, 150
03h(3) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 22, 150
04h(3) FSR Indirect Dat a Memory Addre ss Pointer xxxx xxxx 31, 150
05h PORTA —— PORTA Data Latch when writte n: PORT A pins when read --0x 0000 43, 150
06h PORTB PORTB Data Latch when writt en: PORTB pins when read xxxx xxxx 45, 150
07h PORTC POR T C Data Latc h when written : POR TC pins when read xxxx xxxx 47, 150
08h(4) POR TD PORT D Data Latc h when written : POR TD pins when read xxxx xxxx 48, 150
09h(4) PORTE — — — — — RE2 RE1 RE0 ---- -xxx 49, 150
0Ah(1,3) PCLATH — — — Write Buf f er for the uppe r 5 bits of the Program Count er ---0 0000 30, 150
0Bh(3) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 24, 150
0Ch PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 26, 150
0Dh PIR2 —CMIF—EEIFBCLIF——CCP2IF-0-0 0--0 28, 150
0Eh TMR1L Holding Register for th e Least Sign ifican t By te of the 16-bit TMR1 Register xxxx xxxx 60, 150
0Fh TMR1H Holding Register for th e Most Signif icant Byte of the 16-bi t TMR1 Regist er xxxx xxxx 60, 150
10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 57, 150
11h TMR2 Timer2 Module Register 0000 0000 62, 150
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 61, 150
13h SSPBUF Synchronous Seria l Port Receiv e Buf fe r/Transmit Register xxxx xxxx 79, 150
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 82, 82 ,
150
15h CCPR1L Capture/Comp ar e/PWM Regist er 1 (LSB) xxxx xxxx 63, 150
16h CCPR1H Capture/Compar e/P WM Register 1 (MSB) xxxx xxxx 63, 150
17h CCP1CON —— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 64, 150
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 112, 150
19h TXREG USAR T T ran smit Dat a Register 0000 0000 118, 150
1Ah RCREG USART Receive Data Register 0000 0000 118, 150
1Bh CCPR2L Capture/Compar e/P WM Register 2 (LSB ) xxxx xxxx 63, 150
1Ch CCPR2H Capture/Compare/P WM Register 2 (MSB) xxxx xxxx 63, 150
1Dh CCP2CON —— CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 64, 150
1Eh ADRESH A/D Result Register High B yte xxxx xxxx 133, 150
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON0000 00-0 127, 150
Legend: x = unknown, u = unchanged, q = value depend s on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locat i ons are unimplemented, read as ‘0’.
Note 1: The upper byte of th e program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2: Bits PS PIE and PSPIF are reserved on PIC16F873A/ 876A devices; always maintain these bits clear.
3: These regi st ers can be addressed from any bank.
4: PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A /876A devices, read a s ‘0’.
5: Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
PIC16F87XA
DS39582C-page 20 2001-2013 Microchip Technology Inc.
Bank 1
80h(3) INDF Addressi ng this location us es contents of FSR to address dat a memory (not a physic al register) 0000 0000 31, 150
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 23, 150
82h(3) PCL Program Counter (PC) Lea st Signif icant Byte 0000 0000 30, 150
83h(3) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 22, 150
84h(3) FSR Indirect Dat a Memory Addre ss Pointer xxxx xxxx 31, 150
85h TRISA —— PORTA Data Direct i on Register --11 1111 43, 150
86h TRISB PORTB Data Direction Register 1111 1111 45, 150
87h TRISC PORTC Dat a Direction Regist er 1111 1111 47, 150
88h(4) TRISD PO R TD Dat a Direction Register 1111 1111 48, 151
89h(4) TRISE IBF OBF IBOV PSPMODE — PORTE Data Directio n bits 0000 -111 50, 151
8Ah(1,3) PCLATH — — — Write Buffer for t he upper 5 bits of the Program Counter ---0 0000 30, 150
8Bh(3) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 24, 150
8Ch PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 25, 151
8Dh PIE2 —CMIE— EEIE BCLIE —— CCP2IE -0-0 0--0 27, 151
8Eh PCON — — — — — —PORBOR ---- --qq 29, 151
8Fh —Unimplemented — —
90h —Unimplemented — —
91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 83, 151
92h PR2 Timer2 Period Register 1111 1111 62, 151
93h SSPADD Synchronous Seria l Port (I 2C mode) Address Register 0000 0000 79, 151
94h SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 79, 151
95h —Unimplemented — —
96h —Unimplemented — —
97h —Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 111, 151
99h SPBRG Baud Rate Generator Regis ter 0000 0000 113, 151
9Ah —Unimplemented — —
9Bh —Unimplemented — —
9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 135, 151
9Dh CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 141, 151
9Eh ADRESL A/D Result Register Low Byte xxxx xxxx 133, 151
9Fh ADCON1 ADFM ADCS2 —— PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 128, 151
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR Details
on pag e:
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locat i ons are unimplemented, read as ‘0’.
Note 1: The upper byte of th e program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2: Bits PS PIE and PSPIF are reserved on PIC16F873A/ 876A devices; always maintain these bits clear.
3: These regi st ers can be addressed from any bank.
4: PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A /876A devices, read a s ‘0’.
5: Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
2001-2013 Microchip Technology Inc. DS39582C-page 21
PIC16F87XA
Bank 2
100h(3) INDF Addressing th is location uses con tents of FSR to add ress dat a memory (not a physical regi ster) 0000 0000 31, 150
101h TMR0 Timer0 Module Register xxxx xxxx 55, 150
102h(3) PCL Program Counter’s (PC) Least Signif icant Byt e 0000 0000 30, 150
103h(3) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 22, 150
104h(3) FSR Indirect Data Memory Addre ss Pointer xxxx xxxx 31, 150
105h —Unimplemented — —
106h PORTB PORTB Dat a Latch when written: PORTB pins when read xxxx xxxx 45, 150
107h —Unimplemented — —
108h —Unimplemented — —
109h —Unimplemented — —
10Ah(1,3) PCLATH — — — Write Buf fer for t he upper 5 bit s of the Pr ogram Counter ---0 0000 30, 150
10Bh(3) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 24, 150
10Ch EEDA TA EEPROM Data Regist er Low Byte xxxx xxxx 39, 151
10Dh EEADR EEPROM Addr ess Regist er Low Byte xxxx xxxx 39, 151
10Eh EEDATH —— EEPROM Dat a Regi ster High Byte --xx xxxx 39, 151
10Fh EEADRH — — — —(5) EEPROM Addres s Register High Byte ---- xxxx 39, 151
Bank 3
180h(3) INDF Addressing th is location uses con tents of FSR to add ress dat a memory (not a physical regi ster) 0000 0000 31, 150
181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 23, 150
182h(3) PCL Program Counter (PC) Least Signif icant Byte 0000 0000 30, 150
183h(3) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 22, 150
184h(3) FSR Indirect Data Memory Addre ss Pointer xxxx xxxx 31, 150
185h —Unimplemented — —
186h TRISB PORTB Dat a Direction Register 1111 1111 45, 150
187h —Unimplemented — —
188h —Unimplemented — —
189h —Unimplemented — —
18Ah(1,3) PCLATH — — — Write Buff er for the uppe r 5 bit s of the Program Count er ---0 0000 30, 150
18Bh(3) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 24, 150
18Ch EECON1 EEPGD — — — WRERR WREN WR RD x--- x000 34, 151
18Dh EECON2 EEPROM Control Register 2 (not a physi cal register) ---- ---- 39, 151
18Eh —Reserved; maintain cle ar 0000 0000 —
18Fh —Reserved; mainta in clear 0000 0000 —
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR Details
on pag e:
Legend: x = unknown, u = unchanged, q = value depend s on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locat i ons are unimplemented, read as ‘0’.
Note 1: The upper byte of th e program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2: Bits PS PIE and PSPIF are reserved on PIC16F873A/ 876A devices; always maintain these bits clear.
3: These regi st ers can be addressed from any bank.
4: PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A /876A devices, read a s ‘0’.
5: Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
PIC16F87XA
DS39582C-page 22 2001-2013 Microchip Technology Inc.
2.2.2.1 Status Register
The Sta tus regis ter cont ains th e arithme tic st atus of th e
ALU, the Reset status and the bank select bi t s fo r data
memory.
The Status register can be the destination for any
instruc tio n, as with any othe r regi ster . If the Status reg-
ister is the de sti nation for an instruc tion that affe cts the
Z, DC or C bits, the n the write t o t hes e thre e b its is dis-
abled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable, therefore, the result of an instruction with the
Status register as destination may be different than
intended.
For exam pl e, CLRF STATUS, will clea r the upper three
bits and set th e Z bit. Thi s leaves the Statu s register a s
000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
S t atus regis ter becaus e these inst ructions do not affec t
the Z, C or DC bits from the Status register. For other
instructions not affecting any status bits, see
Section 1 5.0 “Instruction Set Summary”.
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
Note: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD ZDCC
bit 7 bit 0
bit 7 IRP: Register Bank Sele ct bit ( used for indi rect addressing)
1 = Bank 2, 3 (100h-1 FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h-1FFh)
10 = Bank 2 (100h-17Fh)
01 = Bank 1 (80h-FFh)
00 = Bank 0 (00h-7Fh)
Each bank is 128 by tes.
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instructi on
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
(for borrow, the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high, or low order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2001-2013 Microchip Technology Inc. DS39582C-page 23
PIC16F87XA
2.2.2.2 OPTION_REG Register
The OPTI ON_ REG Re gister is a re adable and w rit able
register, which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assign-
able register known also as the prescaler), the external
INT inte rrupt, TMR0 and the weak pull-u ps o n POR TB.
REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h)
Note: To achieve a 1:1 prescaler assignment for
the TMR 0 re gis ter, assign the p res ca ler to
the Watchdog Timer.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 RBPU: PORT B Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pi n
0 = Internal instruction cycle clock (CLKO)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increm ent on high-to-low transition on RA4/T0CKI pin
0 = Increm ent on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: When using Low-Voltage ICSP Pro grammin g (LVP) and the pull-up s on PORTB a re
enabled, bit 3 in the TRISB register must be cleared to disable the pull-up on RB3
and ensure the proper operation of the device
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
PIC16F87XA
DS39582C-page 24 2001-2013 Microchip Technology Inc.
2.2.2.3 INTCON Register
The INTCON register is a readable and writable regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB port change and external
RB0/INT pin interrupts.
REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
Note: Interrupt flag bits are set when an interrupt
condition occurs regardles s of the state of it s
corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software
should ensure the appropriate interrupt flag
bits are cle ar prior to enabling an i nterrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIETMR0IEINTE RBIETMR0IFINTF RBIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all in terrupts
bit 6 PEIE: Peripheral Interrupt Enable bi t
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 TMR0IE: TMR0 Ov erfl ow I nterr upt Enab le bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Inte rrupt Enable bit
1 = Enables the RB0/INT external inte rrupt
0 = Disabl es the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/I NT external interrupt occurred (must be cleared in softwa re)
0 = The RB0/INT external in terrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = At le as t on e o f the R B7:R B4 pins chang ed s t a te; a mismatch condition will c on tinu e to set
the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared
(must be cleared in software).
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2001-2013 Microchip Technology Inc. DS39582C-page 25
PIC16F87XA
2.2.2.4 PIE1 Register
The PIE1 regi ster cont ains the indivi dual enable b its for
the peripheral inter rupts.
REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
bit 7 PSPIE: Parall el Slav e Port Read/ Write Interrupt Enable bit(1)
1 = Enables the PSP read/write interrupt
0 = Disabl es the PSP read/write interrupt
Note 1: PSPIE is reserved on PIC16F873A/876A devices; always maintain this bit clear.
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter in terrupt
0 = Disables the A/D converter interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USA RT receiv e interrupt
bit 4 TXIE: USART Tran smit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disabl es the USART transmit interrupt
bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrup t
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bi t
1 = Enables the TMR2 to PR2 match inte rrupt
0 = Disabl es the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Ov erfl ow I nterr upt Enab le bit
1 = Enables the TMR1 overflow interrupt
0 = Disabl es the TMR1 overflow interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582C-page 26 2001-2013 Microchip Technology Inc.
2.2.2.5 PIR1 Register
The PIR1 register contains the individual flag bits for
the peripheral inter rupts.
REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch)
Note: Interrupt flag bits are set when an interrupt
condition occurs regardles s of the state of it s
corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software
should ensure the appropriate interrupt bits
are clear prior to enabling an interrupt.
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
bit 7 PSPIF: Parallel Slave Port Read/Write In terrupt Flag bit(1)
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occu rred
Note 1: PSPIF is reserved on PIC16F873A/876A devices; always maintain this bit clear.
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
bit 5 RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
bit 4 TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
bit 3 SSPIF: Synchron ous Serial Port (SSP) Interrupt Flag bit
1 = The SSP in terrupt condit ion has occurred a nd must be clea red in soft ware before returnin g
from the Interrupt Servic e Routine. The conditions that will set this bit are:
• SPI – A transmission/reception has taken place.
• I
2C Slave – A transmission/reception has taken place.
•I
2C Master
- A transmission/reception has taken place.
- The initiated Start condition was completed by the SSP module.
- The initiated Stop condition was completed by the SSP module.
- The initiated Restart condition was completed by the SSP module.
- The initiated Acknowledge condition was completed by the SSP module.
- A St a rt conditio n occ urred whil e the SSP modul e was Idl e (mult i-master s ystem).
- A Stop condition o cc urre d whil e the SSP m odu le was I dle (m ul ti-m as ter s ystem ).
0 = No SSP interrupt condition has occurred
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR 1 register capture occu rred (must be cleared in software)
0 = No TMR1 register c apture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1 TMR2IF: TMR2 to PR2 Ma tch Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2001-2013 Microchip Technology Inc. DS39582C-page 27
PIC16F87XA
2.2.2.6 PIE2 Register
The PIE2 regi ster cont ains the indivi dual enable b its for
the CCP2 peripheral interrupt, the SSP bus collision
interrupt, EEPROM write operation interrupt and the
comparator i nterrupt.
REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0
—CMIE— EEIE BCLIE —— CCP2IE
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 CMIE: Comparator Interrupt Enable bit
1 = Enables the comparator interrupt
0 = Disable the comparator interrupt
bit 5 Unimplemented: Read as ‘0’
bit 4 EEIE: EEPROM Write Operation Interrupt Enable bit
1 = Enable EEPROM write interrupt
0 = Disable EEPROM write interrupt
bit 3 BCLIE: Bus Collision Interrupt Enable bit
1 = Enable bus collision interrupt
0 = Disable bus collision interrupt
bit 2-1 Unimplemented: Read as ‘0’
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrup t
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582C-page 28 2001-2013 Microchip Technology Inc.
2.2.2.7 PIR2 Register
The PIR2 register contains the flag bits for the CCP2
interrupt, the SSP bus collision interrupt, EEPROM
write operation interrupt and the comparator interrupt.
REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh)
Note: Interru pt flag bi ts are s et when an interrupt
conditi on oc curs regard le ss of the sta te of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0
—CMIF— EEIF BCLIF —— CCP2IF
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 CMIF: Comparator Interrupt Flag bit
1 = The comparator input has changed (must be cleared in software)
0 = The comparator input has not changed
bit 5 Unimplemented: Read as ‘0’
bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3 BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the SSP when configured for I2C Master mode
0 = No bus collision has occurred
bit 2-1 Unimplemented: Read as ‘0’
bit 0 CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR 1 register capture occu rred (must be cleared in software)
0 = No TMR1 register c apture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2001-2013 Microchip Technology Inc. DS39582C-page 29
PIC16F87XA
2.2.2.8 PCON Register
The Power Control (PCON) register contains flag bits
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watchdog Reset
(WDT) and an external MCLR Reset.
REGISTER 2-8: PCON REGISTER (ADDRESS 8Eh)
Note: BOR is unknown on Power-on Reset. It
must be set by the user and checked on
subsequent Resets to see if BOR is clear,
indicating a brown-out has occurred. The
BOR s tatu s bit is a “do n’t car e” and is no t
predictable if the brown-out circuit is dis-
abled (by clearing the BODEN bit in the
configu r ati on word).
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1
— — — — — —PORBOR
bit 7 bit 0
bit 7-2 Unimplemented: Read as ‘0’
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582C-page 30 2001-2013 Microchip Technology Inc.
2.3 PCL and PCLATH
The Program Counter (PC) is 13 bits wide. The low
byte comes from the PCL register which is a readable
and writable register. The upper bits (PC<12:8>) are
not readable, but are indirectly writable through the
PCLATH register. On any Reset, the upper bits of the
PC will b e clea red. Fig ure 2-5 sho ws the tw o sit uation s
for the loading of the PC. The upper example in the
figure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> PCH). The lower example in the
figure shows how the PC is loaded during a CALL or
GOTO instructi on (PCLATH<4:3> PCH).
FIGURE 2-5: LOADING OF PC IN
DIFFERENT SITUATIONS
2.3.1 COMP UT ED GOTO
A comput ed GOTO is a ccom pli shed by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be ex ercise d if th e t able loca tion c rosse s a PCL
memory boundary (each 256-byte block). Refer to the
application note, AN556, “Implementing a Table Read”
(DS00556).
2.3.2 STACK
The PIC16F87XA family has an 8-level deep x 13-bit
wide hardware stack. The stack space is not part of
either progra m or data space a nd the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed, or an interrupt
causes a branch. The stack is POP’ed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
The st ack operates as a circular buf fer . This means that
after the st ack h as be en PU SHed ei ght ti mes, th e nin th
push ov erwrit es the v alue tha t was stor ed fro m the first
push. The tenth push overw ri tes the second push (and
so on).
2.4 Program Memory Paging
All PIC16F87XA devices are capable of addressing a
continuous 8K word block of program memory. The
CALL and GOTO instructions provide only 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALL or GOTO instruction,
the upper 2 bits of the address are provided by
PCLATH<4:3>. When doing a CALL or GOTO instruc-
tion, the us er must ensure that the p a ge s ele ct bit s are
programmed so that the desired program memory
page is addressed. If a return from a CALL instru ction
(or interrup t) is executed, the e ntire 13-bit PC is popped
off the stack. Therefore, manipulation of the
PCLATH<4:3> bits is not required for the RETURN
instructions (which POPs the address from the stack).
Example 2-1 shows the calling of a subroutine in
page 1 of the program memory. This e xample assu mes
that PCLATH is saved and restored by the Interrupt
Service Routi ne (if interrupts are used).
EXAMPLE 2-1: CALL OF A SUBROUTINE
IN PAGE 1 FROM PAGE 0
PC
12 8 7 0
5PCLATH<4:0>
PCLATH
Instruction with
ALU
GOTO,CALL
Opcode < 10:0 >
8
PC
12 11 10 0
11
PCLATH<4:3>
PCH PCL
87
2
PCLATH
PCH PCL
PCL as
Destination
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLW a nd RETFIE in struction s
or the vectoring to an inter rupt address.
Note: The contents of the PCLATH register are
unchanged after a RETURN or RETFIE
instruction is executed. The user must
rewrite the contents of the PCLATH regis-
ter for any subsequent subroutine calls or
GOTO instructions.
ORG 0x500
BCF PCLATH,4
BSF PCLATH,3 ;Select page 1
;(800h-FFFh)
CALL SUB1_P1 ;Call subroutine in
: ;page 1 (800h-FFFh)
:
ORG 0x900 ;page 1 (800h-FFFh)
SUB1_P1
: ;called subroutine
;page 1 (800h-FFFh)
:
RETURN ;return to
;Call subroutine
;in page 0
;(000h-7FFh)
2001-2013 Microchip Technology Inc. DS39582C-page 31
PIC16F87XA
2.5 Indirect Addressing, INDF and
FSR Registers
The INDF register is no t a physica l register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
acces ses the register pointed to by the File Sele ct Reg-
ister, FSR. Reading the INDF register itself, indirectly
(FSR = 0) will read 00h. Writing to the INDF register
indirec tly resu lts in a no operation (alth oug h status bit s
may be affec ted). An ef fectiv e 9-bit add ress is o btaine d
by conc atenat ing the 8 -bit F SR regi ster and the IRP bit
(Status<7>) as shown in Figure 2-6.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
EXAMPLE 2-2: INDIRECT ADDRESS ING
FIGURE 2-6: DIRECT/INDI RECT ADDRESS ING
MOVLW 0x20 ;initialize pointer
MOVWF FSR ;to RAM
NEXT CLRF INDF ;clear INDF register
INCF FSR,F ;inc pointer
BTFSS FSR,4 ;all done?
GOTO NEXT ;no clear next
CONTINUE
: ;yes continue
Note 1: For register file map detail, see Figure 2- 3.
Data
Memory(1)
Indirect AddressingDirect Addressing
Bank Select Location Select
RP1:RP0 6 0
From Opcode IRP FSR Register
70
Bank Select Location Select
00 01 10 11
Bank 0 Bank 1 Bank 2 Bank 3
FFh
80h
7Fh
00h
17Fh
100h
1FFh
180h
PIC16F87XA
DS39582C-page 32 2001-2013 Microchip Technology Inc.
NOTES:
2001-2013 Microchip Technology Inc. DS39582C-page 33
PIC16F87XA
3.0 DAT A EEPROM AND FLASH
PROGRAM MEMORY
The data EEPROM and Flash program memory is read-
able and writable during normal operation (over the full
VDD range). This memory is not directly mapped in the
register file space. Instead, it is indirectly addressed
through the Special Function Registers. There are six
SFRs used to read and write this m emory:
• EECON1
• EECON2
• EEDATA
• EEDATH
• EEADR
• EEADRH
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed.
These devices have 128 or 256 bytes of data EEPROM
(dependi ng on t he d evice), w ith an addres s range fro m
00h to FF h. On devic es with 128 bytes , addresses from
80h to FFh are unimplemented and will wraparound to
the begin nin g of d at a EEPROM memory. When writin g
to unimplemented locations, the on-chip charge pump
will be turned off.
When interfacing the program memory block, the
EEDATA and EEDATH registers form a two-byte word
that holds the 14 -bit data for read/ write and the EEADR
and EEA DRH re gisters form a two-byte wor d that holds
the 13-bit address of the program memory location
being accessed. These devices have 4 or 8K words of
program Flash, with an address range from 0000h to
0FFFh for the PIC16F873A/874A and 0000h to 1FFFh
for the PIC1 6F876A/877 A. Addresses above th e range
of the respective device will wraparound to the
beginning of program memory.
The EEPROM data memory allows single-byte read and
write. The Flash program memory allows single-word
reads and four-word block writes. Program memory
write operations automatically perform an erase-before-
write on blocks of four words. A byte write in data
EEPROM memory automatically erases the location
and writes the new data (erase-before-write).
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device for byte or word operations.
When the device is code-protected, the CPU may
continu e to rea d an d write the da t a EEPROM memory.
Depending on the settings of the write-protect bits, the
device may or may not be able to write certain blocks
of the program memory; however , reads of the program
memory are allowed. Whe n code-pr otected, the dev ice
programmer can no longer access data or program
memory; this does NOT inhib it in tern al r ead s o r wr ites .
3.1 EEADR and EEADRH
The EEADRH:EEADR register pair can address up to
a maximum of 256 bytes of data EEPROM or up to a
maximum of 8K words of program EEPROM. When
selecting a data address value, only the LSByte of the
address is writte n to the EEADR regi st er. When se lect-
ing a program address value, the MSByte of the
address is written to the EEADRH register and the
LSByte is written to the EEADR register.
If the device contains less memory than the full add ress
reach of the address register pair, the Most Significant
bits of the reg isters are not im plem ented. F or exam ple,
if the de vi ce has 128 bytes of dat a EEPROM, th e M os t
Signific ant bit of EEADR i s not impl ement ed on a cces s
to data EEPROM.
3.2 EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses.
Control bit, EEPGD, determines if the access will be a
program or data memory access. When clear, as it is
when reset, any sub seque nt operati ons will operate on
the data memory. When set, any subsequent
operations will operate on the program memory.
Control bits, RD and WR, initiate read and write or
erase, respectively. These bits cannot be cleared, only
set, in software. They are cleared in hardware at com-
pletion of the read or write operation. The inability to
clear the WR bit in software prevents the accidental,
premature termination of a write operation.
The WREN bit, when set, will allow a write or erase
operation. On power-up, the WREN bit is clear. The
WRERR bit is set when a write (or erase) operation is
interrupted by a MCLR or a WDT Time-out Rese t dur -
ing normal operation. In these situations, following
Reset, the user can check the WRERR bit and rewrite
the location. The data and address will be unchanged
in the EEDATA and EEADR registers.
Interrupt flag bit, EEIF in the PIR2 register, is set when
the write is complete. It must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the EEPROM write sequence.
Note: The self-programming mechanism for Flash
program memory has been changed. On
previous PIC16F87X devices, Flash pro-
gramming was done in single-word erase/
write cycles. The newer PIC18F87XA
devices use a four-word erase/write
cycle. See Section 3.6 “Writing to Flash
Program Memory” for more information.
PIC16F87XA
DS39582C-page 34 2001-2013 Microchip Technology Inc.
REGISTER 3-1: EECON1 REGISTER (ADDRESS 18Ch)
R/W-x U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD — — — WRERR WREN WR RD
bit 7 bit 0
bit 7 EEPGD: Program/Data EEPROM Select bit
1 = Accesses program memory
0 = Accesses data memory
Reads ‘0’ after a POR; this bit cannot be changed while a write operation is in progress.
bit 6-4 Unimplemented: Read as ‘0’
bit 3 WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during normal
operation)
0 = The write operation completed
bit 2 WREN: EEPROM Write Enable bi t
1 = Allows write cycles
0 = Inhibits write to the EEPROM
bit 1 WR: Write Control bit
1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.
0 = Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read; RD is cleared in hardware. The RD bit can only be set (not
cleared) in soft ware.
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2001-2013 Microchip Technology Inc. DS39582C-page 35
PIC16F87XA
3.3 Reading Data EEPROM Memory
To read a data memory location, the user must write th e
address to the EEADR register, clear the EEPGD con-
trol bit (EECON1<7>) and then set control bit RD
(EECON1<0>). The data is available in the very next
cycle in the EEDATA register; therefore, it can be read
in the next instruction (see Example 3-1). EEDATA will
hold this value until another read or until it is written to
by the user (during a write operation).
The steps to reading the EEPROM data memory are:
1. Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the device.
2. Clear the EEPGD bit to point to EEPROM data
memory.
3. Set the RD bit to start the read operation.
4. Read the data from the EEDATA register.
EXAMPLE 3-1: DATA EEPROM READ
3.4 Writing to Data EEPROM Memory
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data to
the EEDATA register. Then the user must follow a
specific write sequen ce to initiate the write for each byte.
The write will not initiate if the write sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment (see Example 3-2).
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware
After a write sequence has been initiated, clearing the
WREN bit wil l not af fect this wri te cycle. T he WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
clea red by software.
The steps to write to EEPROM data memory are:
1. If step 10 is not implemented, chec k the WR bit
to see if a write is in progress.
2. Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the device.
3. Write the 8-bit data value to be programmed in
the EEDATA register.
4. Clear the EEPGD bit to point to EEPROM data
memory.
5. Set the WREN bit to enable program operations.
6. Disable interrupts (if enabled).
7. Execute the special five instruction sequence:
• Write 55h to EECON2 in two steps (first
to W, then to EECON2)
• Write AAh to EECON2 in two steps (first
to W, then to EECON2)
• Set the WR bit
8. Enable interrupts (if using interrupts).
9. Clear the WREN bit to disable program
operations.
10. At the completion of the write cycle, the WR bit
is cleared and the EEIF interrupt flag bit is set.
(EEIF must be cleared by firmware.) If step 1 is
not implemented, then firmware should check
for EEIF to be set, or WR to clear, to i ndicate th e
end of the program cycle.
EXAMPLE 3-2: DATA EEPROM WRITE
BSF STATUS,RP1 ;
BCF STATUS,RP0 ; Bank 2
MOVF DATA_EE_ADDR,W ; Data Memory
MOVWF EEADR ; Address to read
BSF STATUS,RP0 ; Bank 3
BCF EECON1,EEPGD ; Point to Data
; memory
BSF EECON1,RD ; EE Read
BCF STATUS,RP0 ; Bank 2
MOVF EEDATA,W ; W = EEDATA
BSF STATUS,RP1 ;
BSF STATUS,RP0
BTFSC EECON1,WR ;Wait for write
GOTO $-1 ;to complete
BCF STATUS, RP0 ;Bank 2
MOVF DATA_EE_ADDR,W ;Data Memory
MOVWF EEADR ;Address to write
MOVF DATA_EE_DATA,W ;Data Memory Value
MOVWF EEDATA ;to write
BSF STATUS,RP0 ;Bank 3
BCF EECON1,EEPGD ;Point to DATA
;memory
BSF EECON1,WREN ;Enable writes
BCF INTCON,GIE ;Disable INTs.
MOVLW 55h ;
MOVWF EECON2 ;Write 55h
MOVLW AAh ;
MOVWF EECON2 ;Write AAh
BSF EECON1,WR ;Set WR bit to
;begin write
BSF INTCON,GIE ;Enable INTs.
BCF EECON1,WREN ;Disable writes
Required
Sequence
PIC16F87XA
DS39582C-page 36 2001-2013 Microchip Technology Inc.
3.5 Reading Flash Program Memory
To read a program memory location, the user must write
two bytes of the address to t he EEADR and EEADRH
registers, set the EEPGD control bit (EECON1<7>) and
then set control bit RD (EECON1<0>). Once the read
control bi t is set, the program memory Fl ash controller
will use the next two instruction cycles to read the data.
This cau ses these two in structions immedi ately follo w-
ing the “BSF EECON1,RD” instruction to be ignored.
The data is available in the very next cycle in the
EEDATA and EEDATH registers; therefore, it can be
read as two bytes in the following instructions. EEDA TA
and EEDATH regi ste rs will hold t his value un til anot her
read or until it is written to by the user (during a write
operation).
EXAMPLE 3-3: FLASH PROGRAM READ
BSF STATUS, RP1 ;
BCF STATUS, RP0 ; Bank 2
MOVLW MS_PROG_EE_ADDR ;
MOVWF EEADRH ; MS Byte of Program Address to read
MOVLW LS_PROG_EE_ADDR ;
MOVWF EEADR ; LS Byte of Program Address to read
BSF STATUS, RP0 ; Bank 3
BSF EECON1, EEPGD ; Point to PROGRAM memory
BSF EECON1, RD ; EE Read
;
NOP
NOP ; Any instructions here are ignored as program
; memory is read in second cycle after BSF EECON1,RD
;
BCF STATUS, RP0 ; Bank 2
MOVF EEDATA, W ; W = LS Byte of Program EEDATA
MOVWF DATAL ;
MOVF EEDATH, W ; W = MS Byte of Program EEDATA
MOVWF DATAH ;
Required
Sequence
2001-2013 Microchip Technology Inc. DS39582C-page 37
PIC16F87XA
3.6 Writing to Flash Program Memory
Flash program memory may only be written to if the
destination address is in a segment of memory that is
not write-protected, as defined in bits WRT1:WRT0 of
the device configuration word (Register 14-1). Flash
program memory must be written in four-word blocks. A
block consists of four words with sequential addresses,
with a lower boundary defined by an address, where
EEAD R<1:0> = 00. At the same time, all block writes to
program memory are done as erase and write opera-
tions. The write operation is edge-aligned and cannot
occur across boundaries.
To write program data, it must first be loaded into the
buffer registers (see Figure 3 -1). This is accomplished
by first writing the destination addres s to EEADR and
EEADRH and then writing the data to EEDATA and
EEDATH. After the address and data hav e been set up,
then the following sequence of events must be
executed:
1. Set the EEPGD control bit (EECON1<7>).
2. Write 55h, then AAh, to EECON2 (Flash
programming sequence).
3. Set the WR control bit (EECON1<1>).
All four buffer register locations MUST be written to with
corr ect data. If only one, two o r three words ar e bei ng
written to in the block of four words, then a read from
the program memory location(s) not being written to
must be performed. This takes the data from the pro-
gram location(s) not being written and loads it into the
EEDAT A and EED A TH reg isters. Then the s equence of
events to transfer data to the buffer registers must be
executed.
To transfer data from the buffer registers to the program
memory , the EEADR and EEADRH must point to the last
location in the four-word block (EEADR<1:0> = 11).
Then the following sequence of events must be
executed:
1. Set the EEPGD control bit (EECON1<7>).
2. Write 55h, then AAh, to EECON2 (Flash
programming sequence).
3. Set control bit WR (EECON1<1>) to begin the
write operation.
The user mu st follow the same specific sequence to ini-
tiate the wri te for eac h word in the pr ogra m blo ck, wri t-
ing each program word in sequence (00,01,10,11).
When the write is performed on the last word
(EEADR<1:0> = 11), the block of four words are
automatically erased and the contents of the buffer
registers are written into the program memory.
After th e “BSF EECON1,WR” instruction, the processor
requires tw o c ycles to se t up the erase/w rite op eration.
The user must place tw o NOP i ns truc tio ns after the WR
bit is set. Sinc e dat a is being written to buf fe r registers,
the writing of the first three words of the block appears
to occur immediately. The processor will halt internal
operat io ns for the typi ca l 4 ms, onl y du ring the cy cl e in
which the erase takes place (i.e., the last word of the
four-word block). This is not Sleep mode as the clocks
and peripherals will continue to run. After the write
cycle, the processor will resume operation with the third
instruction after the EECON1 write instruction. If the
sequenc e is perfo rmed to an y other loc ation, the action
is ignored.
FIGURE 3-1: BLOCK WRITES TO FLASH PROGRAM MEMORY
14 14 14 14
Program Memory
Buffer Register
EEADR<1 :0 > = 00
Buffer Register
EEADR<1:0> = 01
Buffer Register
EEADR<1:0> = 10
Buffer Register
EEADR<1:0> = 11
EEDATAEEDATH
75 07 0
6 8
First word of block
to be written
Four words of
to Flash
automatically
after this word
is wr itten
are transferred
Flash are eras ed,
then all buffers
PIC16F87XA
DS39582C-page 38 2001-2013 Microchip Technology Inc.
An example of the complete four-word write sequence
is shown in Example 3-4. The initial address is loaded
into the EEADRH:EEADR register pair; the four words
of data are loaded using indirect addressing.
EXAMPLE 3-4: WRITING TO FLASH PROGRAM MEMORY
; This write routine assumes the following:
;
; 1. A valid starting address (the least significant bits = ‘00’)is loaded in ADDRH:ADDRL
; 2. The 8 bytes of data are loaded, starting at the address in DATADDR
; 3. ADDRH, ADDRL and DATADDR are all located in shared data memory 0x70 - 0x7f
;
BSF STATUS,RP1 ;
BCF STATUS,RP0 ; Bank 2
MOVF ADDRH,W ; Load initial address
MOVWF EEADRH ;
MOVF ADDRL,W ;
MOVWF EEADR ;
MOVF DATAADDR,W ; Load initial data address
MOVWF FSR ;
LOOP MOVF INDF,W ; Load first data byte into lower
MOVWF EEDATA ;
INCF FSR,F ; Next byte
MOVF INDF,W ; Load second data byte into upper
MOVWF EEDATH ;
INCF FSR,F ;
BSF STATUS,RP0 ; Bank 3
BSF EECON1,EEPGD ; Point to program memory
BSF EECON1,WREN ; Enable writes
BCF INTCON,GIE ; Disable interrupts (if using)
MOVLW 55h ; Start of required write sequence:
MOVWF EECON2 ; Write 55h
MOVLW AAh ;
MOVWF EECON2 ; Write AAh
BSF EECON1,WR ; Set WR bit to begin write
NOP ; Any instructions here are ignored as processor
; halts to begin write sequence
NOP ; processor will stop here and wait for write complete
; after write processor continues with 3rd instruction
BCF EECON1,WREN ; Disable writes
BSF INTCON,GIE ; Enable interrupts (if using)
BCF STATUS,RP0 ; Bank 2
INCF EEADR,F ; Increment address
MOVF EEADR,W ; Check if lower two bits of address are ‘00’
ANDLW 0x03 ; Indicates when four words have been programmed
XORLW 0x03 ;
BTFSC STATUS,Z ; Exit if more than four words,
GOTO LOOP ; Continue if less than four words
Required
Sequence
2001-2013 Microchip Technology Inc. DS39582C-page 39
PIC16F87XA
3.7 Protection Against S purious Write
There are conditions when the device should not write
to the data EEPROM or Flash program memory. To
protect against spurious writes, various mechanisms
have been built-in. On power-up, WREN is cleared.
Also, the Power-up T imer (72 ms durat ion) prevent s an
EEPROM write.
The wri te in iti ate sequence and the WR EN bi t tog ether
help prevent an accidental write during brown-out,
power glitch or software malfunction.
3.8 Operation During Code-Protect
When the dat a EEPROM is code-prote ct ed, the micro-
controll er can read and writ e to th e EEPROM n ormally.
However, all external access to the EEPROM is
disabl ed. External write access to the progra m memory
is also disabled.
When program memory is code-protected, the microcon-
troller can read and write to program memory normally,
as well as execute instructions. Writes by the device may
be selectively inhibited to region s of the mem ory depend-
ing on the setting of bits WR1:WR0 of the configuration
word (see Section 14.1 “Configuration Bits” for addi-
tional information). External access to the memory is also
disabled.
TABLE 3-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM AND
FLASH PROGRAM MEMORIES
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B it 0 Value on
Power-on
Reset
Value on
all other
Resets
10Ch EEDATA EEPROM/Flash Data Register Low Byte xxxx xxxx uuuu uuuu
10Dh EEADR EEPROM/Flash Address Register Low Byte xxxx xxxx uuuu uuuu
10Eh EEDATH —— EEPROM/Flash Data Register High Byte xxxx xxxx ---0 q000
10Fh EEADRH — — — EEPR OM /Flash Addr ess Regist er High Byte xxxx xxxx ---- ----
18Ch EECON1 EEPGD ——— WRERR WREN WR RD x--- x000 ---0 q000
18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ----
0Dh PIR2 —CMIF —EEIFBCLIF — — CCP2IF -0-0 0--0 -0-0 0--0
8Dh PIE2 —CMIE —EEIEBCLIE — — CCP2IE -0-0 0--0 -0-0 0--0
Legend: x = unk nown, u = unchanged, - = unimplemented, read as ‘0’, q = value depends upon condition.
Shaded cells are not used by data EEPROM or Flash program memory.
PIC16F87XA
DS39582C-page 40 2001-2013 Microchip Technology Inc.
NOTES:
2001-2013 Microchip Technology Inc. DS39582C-page 41
PIC16F87XA
4.0 I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Addit ion al inf orm atio n o n I/O ports ma y b e f ound in the
PIC® Mid-Range Reference Manual (DS33023).
4.1 PORTA and the TRIS A Register
PORTA is a 6-bit wide, bidirectional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make th e corresponding PORT A pin
an input (i.e., put the corresponding output driver in a
High-Impe dance mode). Cle aring a TRISA bi t (= 0) will
make the correspon ding POR TA pin a n output (i.e., put
the contents of the output la tch on the selected pin).
Reading the PORTA register reads the status of the
pins, where as wri tin g to i t wi ll write to th e port latch. All
write operations are read-modify-write operations.
Therefore , a write to a port implies that the port pins are
read, the value is modified and then written to the port
data l atch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Sc hmitt T rigg er input and an open-dra in output.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
Other PORTA pins are multiplexed with analog inputs
and the analog VREF input for both the A/D converters
and the comparators. The operation of each pin is
select ed by cl ear ing/se tting the appropr iate control bit s
in the ADCON1 and/or CMCON registers.
The TRISA register controls the direction of the port
pins even when they are being used as analog inputs.
The user mu st ensure the bit s in the TRISA regi ster are
maintained set when using them as analog inputs.
EXAMPLE 4-1: INITIALIZI NG PORTA
FIGURE 4-1: BLOCK DIAGRAM OF
RA3:RA0 PINS
Note: On a Power-on Rese t, thes e pins are co n-
figured as analog inputs and read as ‘0’.
The comparators are in the off (digital)
state.
BCF STATUS, RP0 ;
BCF STATUS, RP1 ; Bank0
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0x06 ; Configure all pins
MOVWF ADCON1 ; as digital inputs
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6>are always
; read as '0'.
Data
Bus
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD
RD PORTA
VSS
VDD
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
Analog
Input
Mode
TTL
Input
Buffer
To A/D Converter or Comparator
TRISA
PIC16F87XA
DS39582C-page 42 2001-2013 Microchip Technology Inc.
FIGURE 4-2: BLOCK DIAGRAM OF RA4/T0CKI PIN
FIGURE 4-3: BLOCK DIAGRAM OF RA5 PIN
Data Bus
WR PORTA
WR TRISA
RD PORTA
Data Latch
TRIS Latch
RD TRISA
Schmitt
Trigger
Input
Buffer
N
VSS
I/O pin(1)
TMR0 Clock Input
Q
D
QCK
QD
Q
CK
EN
QD
EN
C1OUT
Note 1: I/O pin has protection diodes to VSS only.
CMCON<2:0> = x01 or 011
1
0
Data Bus
WR PORTA
WR TRISA
RD PORTA
Data Latch
TRIS Latch
RD TRISA
TTL
Input
Buffer
I/O pin(1)
A/D Converter or SS Input
Q
D
QCK
QD
Q
CK
EN
QD
EN
C2OUT
CMCON<2:0> = 011 or 101
1
0P
N
VSS
VDD
Note 1: I/O pin has protection diodes to VDD and VSS.
Analog
IIP Mode
2001-2013 Microchip Technology Inc. DS39582C-page 43
PIC16F87XA
TABLE 4-1: PORTA FUNCTIONS
TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit# Buffer Function
RA0/AN0 bit 0 TTL Input/output or analog input.
RA1/AN1 bit 1 TTL Input/output or analog input.
RA2/AN2/VREF-/CVREF bit 2 TTL Input/output or analog input or VREF- or CVREF.
RA3/AN3/VREF+ bit 3 TTL Input/output or analog input or VREF+.
RA4/T0CKI/C1OUT bit 4 ST Input/output or external clock input for Timer0 or comparator output.
Output is open-drain type.
RA5/AN4/SS/C2OUT bit 5 TTL Input/output or analog input or slave select input for synchronous serial
port or comparator output.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B it 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
05h PORTA —— RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
85h TRISA —— PORTA Data Direction Register --11 1111 --11 1111
9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 0000 0111
9Dh CVRCON CVREN CVROE CVRR —CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000
9Fh ADCON1 ADFM ADCS2 —— PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000
Legend: x = unk nown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Note: When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of
the following modes, where PCFG3:PCFG0 = 0100, 0101, 011x, 1101, 1110, 1111.
PIC16F87XA
DS39582C-page 44 2001-2013 Microchip Technology Inc.
4.2 PORTB and the TRISB Register
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISB bit (= 0)
will make th e corresp onding POR TB pi n an out put (i.e .,
put the contents of the outpu t latch on the selected pin).
Three pins of POR TB are mu ltiplexed with the In-Circuit
Debugger and Low-Voltage Programming function:
RB3/PGM, RB6/PGC and RB7/PGD. The alternate
functions of these pins are described in Section 14.0
“Special Features of the CPU”.
Each of th e POR TB pins has a we ak inte rnal pul l-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
FIGURE 4-4: BLOCK DIAGRAM OF
RB3:RB0 PINS
Four of the PORTB pins, RB7:RB4, have an interrupt-
on-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB port change
interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mism at c h c ond it i on wi ll cont i n ue to s et f lag bi t RB IF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
This interrupt-on-mismatch feature, together with soft-
ware configurable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the application
note, AN552, “Implementing Wake-up on Key Stroke”
(DS00552).
RB0/INT is an external interrupt input pin and is
configured using the INTEDG bit (OPTION_REG<6>).
RB0/IN T is disc usse d in det ail in Section 14.11.1 “I NT
Interrupt”.
FIGURE 4-5: BLOCK DIAGRAM OF
RB7:RB4 PINS
Data Latch
RBPU(2)
P
VDD
QD
CK
QD
CK
QD
EN
Data Bus
WR Port
WR TRIS
RD TRIS
RD Port
Weak
Pull-up
RD Port
RB0/INT
I/O pin(1)
TTL
Input
Buffer
Schmitt Trigger
Buffer
TRIS Latch
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
RB3/PGM
Data Latch
From other
RBPU(2) P
VDD
I/O pin(1)
QD
CK
QD
CK
QD
EN
QD
EN
Data Bus
WR Port
WR TRIS
Set RBIF
TRIS Latch
RD TRIS
RD Port
RB7:RB4 pins
Weak
Pull-up
RD Port
Latch
TTL
Input
Buffer ST
Buffer
RB7:RB6 Q3
Q1
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
In Serial Programming Mode
2001-2013 Microchip Technology Inc. DS39582C-page 45
PIC16F87XA
TABLE 4-3: PORTB FUNCTIONS
TABLE 4-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit# Buffer Function
RB0/INT bit 0 TTL/ST(1) Input/output pin or external interrupt input. Internal software programmable
weak pull-up.
RB1 bit 1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit 2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3/PGM(3) bit 3 TTL Input/output pin or programming pin in LVP mode. Internal software
programmable weak pull-up.
RB4 bit 4 TTL Input/output pin (with interrupt-o n-change). Internal soft ware progra mmable
weak pull-up.
RB5 bit 5 TTL Input/output pin (with interrupt-o n-change). Internal soft ware progra mmable
weak pull-up.
RB6/PGC bit 6 TTL/ST(2) Input/output pin (with interrupt-on-change) or in-circuit debugger pin.
Internal software programmable weak pull-up. Serial programming clock.
RB7/PGD bit 7 TTL/ST(2) Input/output pin (with interrupt-on-change) or in-circuit debugger pin.
Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schm itt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode or in-circuit debugger.
3: Low-Vo ltage ICSP Programming (LVP) is enabled by default which disables the RB3 I/O function. LVP
must be disabled to enable RB3 as an I/O pin and allow maximum compatibility to the other 28-pin and
40-pin mid-range devices.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchange d. Shade d cel ls are not used by PORTB.
PIC16F87XA
DS39582C-page 46 2001-2013 Microchip Technology Inc.
4.3 PORTC and the TRISC Register
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISC bit (= 0)
will mak e the correspo nding PORT C pin a n output (i.e.,
put the contents of the outpu t latch on the selected pin).
PORT C is multip lexed with s everal periphe ral function s
(Table 4-5). PORTC pins have Schmitt Trigger input
buffers.
When the I2C module is enabled, the PORTC<4:3>
pins can be configured with normal I2C levels, or with
SMBus levels, by using the CKE bit (SSPSTAT<6>).
When enabling peripheral functions, care should be
taken in defining TRIS bit s fo r each POR T C pi n. Some
peripherals override the TRIS bit to make a pin an
outp ut , whi le ot her pe ri ph e r al s ov err i d e the TR IS bi t to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write in str uction s (BSF, BCF, XORWF) with TRISC as the
destination, should be avoided. The user should refer
to the corresponding peripheral section for the correct
TRIS bit settings.
FIGURE 4-6: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<2:0>,
RC<7:5>
FIGURE 4-7: PORTC BLOCK DIAGRAM
(PERIPHERA L OUTPUT
OVERRIDE) RC<4:3>
Port/Peripheral Select(2)
Data Bus
WR Port
WR TRIS
Data Latch
TRIS Latch
Schmitt
Trigger
QD
Q
CK
QD
EN
Peripheral Data Out 0
1
QD
Q
CK
P
N
VDD
VSS
RD Port
Peripheral
OE(3)
Peripheral Input
I/O
pin(1)
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral Select signal selects between port
data and peripheral output.
3: Peripheral OE (Output Enable) is only activated if
Peripheral Select is active.
RD TRIS
Port/Peripheral Select(2)
Data Bus
WR Port
WR TRIS
Data Latch
TRIS Latch
Schmitt
Trigger
QD
Q
CK
QD
EN
Peripheral Data Out 0
1
QD
Q
CK
P
N
VDD
VSS
RD Port
Peripheral
OE(3)
SSP Input
I/O
pin(1)
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral Select signal selects between port data
and peripheral output.
3: Peripheral OE (Output Enable) is only activated if
Peripheral Select is active.
0
1
CKE
SSPSTAT<6>
Schmitt
Trigger
with
SMBus
Levels
RD TRIS
2001-2013 Microchip Technology Inc. DS39582C-page 47
PIC16F87XA
TABLE 4-5: PORTC FUNCTIONS
TABLE 4-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit# Buffer Type Function
RC0/T1OSO/T1CKI bit 0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input.
RC1/T1OSI/CCP2 bit 1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/
Compare2 output/PWM2 output.
RC 2/CCP1 bit 2 ST Input/output port pin or Capture1 in put/Compare1 outp ut/
PWM1 output.
RC3/SCK/SCL bit 3 ST RC3 can also be the synchronous serial clock for both SPI and
I2C modes.
RC4/SDI/SDA bit 4 ST RC4 can also be the SPI data in (SPI mode) or data I/O (I2C mode).
RC5/SDO bit 5 ST Input/output port pin or Synchronous Serial Port data output.
RC6/TX/CK b it 6 ST Input/output port pin or USART asynchronous transmit or
synchronous clock.
RC7/RX/DT bit 7 ST Input/output port pin or USART asynchronous receive or
synchronous data.
Legend: ST = Schmitt Trigger input
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged
PIC16F87XA
DS39582C-page 48 2001-2013 Microchip Technology Inc.
4.4 PORTD and TRISD Registers
PORTD is an 8-bit port with Schmitt Trigger input
buffers. Each pin is individua lly configurable as an input
or output.
PORTD can be configured as an 8-bit wide
microprocessor port (Parallel Slave Port) by setting
control bit, PSPMODE (TRISE<4>). In this mode, the
input buffers are TTL.
FIGURE 4-8: PORTD BLOCK DIAGRAM
(IN I/O PORT MODE)
TABLE 4-7: PORTD FUNCTIONS
TABLE 4-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Note: PORTD and TRISD are not implemented
on the 28-pin devices .
Data
Bus
WR
Port
WR
TRIS
RD Port
Data Latch
TRIS Latch
RD
Schmitt
Trigger
Input
Buffer
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
QD
CK
QD
CK
EN
QD
EN
TRIS
Name Bit# Buffer Type Function
RD0/PSP0 bit 0 ST/TTL(1) Input/output port pin o r Para llel Slave Port bit 0.
RD1/PSP1 bit 1 ST/TTL(1) Input/output port pin o r Para llel Slave Port bit 1.
RD2/PSP2 bit2 ST/TTL(1) In put/output port pin or Parall el Slave Port bit 2.
RD3/PSP3 bit 3 ST/TTL(1) Input/output port pin o r Para llel Slave Port bit 3.
RD4/PSP4 bit 4 ST/TTL(1) Input/output port pin o r Para llel Slave Port bit 4.
RD5/PSP5 bit 5 ST/TTL(1) Input/output port pin o r Para llel Slave Port bit 5.
RD6/PSP6 bit 6 ST/TTL(1) Input/output port pin o r Para llel Slave Port bit 6.
RD7/PSP7 bit 7 ST/TTL(1) Input/output port pin o r Para llel Slave Port bit 7.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu
88h TRISD PORTD Data Direction Register 1111 1111 1111 1111
89h TRISE IBF OBF IBOV PSPMODE —PORTE Data Direction Bits 0000 -111 0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PORTD .
2001-2013 Microchip Technology Inc. DS39582C-page 49
PIC16F87XA
4.5 PORTE and TRISE Register
PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7) which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
The PORTE pins become the I/O control inputs for the
microprocessor port when bit PSPMODE (TRISE<4>) i s
set. In this mode, the user must make certain that the
TRISE<2:0> bit s are set and that the pins are configured
as digital inputs. Also, ensure that ADCON1 is config-
ured for digital I/O. In this mode, the input buffers are
TTL.
Register 4-1 shows the TRISE register which also
controls the Parallel Slave Port operation.
PORTE pins are multiplexed with analog inputs. When
selected for analog input, these pins will read as ‘0’s.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
FIGURE 4-9: PORTE BLOCK DIAGRAM
(IN I/O PORT MODE)
TABLE 4-9: PORTE FUNCTIONS
Note: PORTE and TRISE are not implemented
on the 28-pin devices .
Note: On a Power-on Reset, these pins are
configured as analog inputs and read as ‘0’.
Data
Bus
WR
Port
WR
TRIS
RD Port
Data Latch
TRIS Latch
RD
Schmitt
Trigger
Input
Buffer
QD
CK
QD
CK
EN
QD
EN
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
TRIS
Name Bit# Buffer Type Function
RE0/RD/AN5 bit 0 ST/TTL(1)
I/O port pin or read control input in Parallel Slave Port mode or analog input:
RD
1 =Idle
0 = Read operation. Contents of PORTD register are output to PORTD
I/O pins (if chip selected).
RE1/WR/AN6 bit 1 ST/TTL(1)
I/O port pin or write control input in Parallel Slave Port mode or analog input:
WR
1 =Idle
0 = Write operation. Value of PORTD I/O pins is latched into PORTD
register (if chip selected).
RE2/CS/AN7 bit 2 ST/TTL(1)
I/O por t pin or chip sele ct con trol i nput in Pa ralle l Slav e Port m ode or analo g input:
CS
1 = Device is not selected
0 = Device is selected
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parall el Slave Port mode.
PIC16F87XA
DS39582C-page 50 2001-2013 Microchip Technology Inc.
TABLE 4-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
REGISTER 4-1: TRISE REGISTER (ADDRESS 89h)
Add r e s s Name B it 7 Bit 6 Bit 5 Bit 4 B i t 3 B it 2 B it 1 B it 0 Val ue on:
POR, BOR
Value on
all other
Resets
09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111
9Fh ADCON1 ADFM ADCS2 —— PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000
Legend: x = unk nown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1
IBF OBF IBOV PSPMODE — Bit 2Bit 1Bit 0
bit 7 bit 0
Parallel Slave Port Status/Control Bits:
bit 7 IBF: Input Buffer Full Status bit
1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received
bit 6 OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1 = A write occurred when a previously input word has not been read (must be cleared in
software)
0 = No overflow occurred
bit 4 PSPMODE: Parallel Slave Port Mode Select bit
1 = PORTD functions in Parallel Slave Port mode
0= PORTD functions in general purpose I/O mode
bit 3 Unimplemented: R ead as ‘0’
PORTE Data Direction Bits:
bit 2 Bit 2: Direction Control bit for pin RE2/CS/AN7
1 = Input
0 = Output
bit 1 Bit 1: Direction Control bit for pin RE1/WR/AN6
1 = Input
0 = Output
bit 0 Bit 0: Direction Control bit for pin RE0/RD/AN5
1 = Input
0 = Output
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2001-2013 Microchip Technology Inc. DS39582C-page 51
PIC16F87XA
4.6 Parallel Slave Port
The Parallel Slave Port (PSP) is not implemented on
the PIC16F873A or PIC16F876A.
PORTD operates as an 8-bit wide Parallel Slave Port,
or microprocessor port, when control bit PSPMODE
(TRISE<4> ) i s set . In Slave mode, it is asynchronously
readable and writa ble by the extern al world throu gh RD
control input pin, RE0/RD/AN5, and WR control input
pin, RE1/WR/AN6.
The PSP can directly interface to an 8-bit
microp rocess or dat a bu s. T he exte rnal mic roproce ssor
can read or write the PORTD latch as an 8-bit latch.
Setting b it PSPMODE enables port pin RE0/RD/AN5 to
be the RD inpu t, R E1/W R/AN6 to b e the WR inp ut an d
RE2/CS/AN7 to be the CS (Chip Select) input. For this
functionality, the corresponding data direction bits of
the TRISE register (TRISE<2:0>) must be configured
as inputs (set). The A/D port configuration bits,
PCFG3:PCFG0 (ADCON1<3:0>), must be set to
configure pins RE2:RE0 as digital I/O.
There a re act ually two 8-bit l atches: one for d ata o utput
and one for dat a inp ut. The user w rites 8-bit d ata to the
PORTD data latch and reads data from the port pin
latch (note that they have the same address). In this
mode, the TRISD regi st er is ig nore d sin ce the ext erna l
device is controlling the direction of data flow.
A write to the PSP occurs when both the CS and WR
lines are first detected low. When either the CS or W R
lines b ecome high (level trigg ered), th e Input Buffer Full
(IBF) status flag bit (TRISE<7>) is set on the Q4 clock
cycle, following the next Q2 cycle, to signal the write is
complete (Figure 4-11). The interrupt flag bit, PSPIF
(PIR1<7>), is also set on the same Q4 clock cycle. IBF
can onl y be cleared by readi ng the PO RTD input latc h.
The Input Buffer Overflow (IBOV) status flag bit
(TRISE<5>) is set if a second write to the PSP is
attempted when the previous byte has not been read
out of the buffer.
A read from t he PSP occurs when both the CS and RD
lines are first detected low. The Output Buffer Full
(OBF) status flag bit (TRISE<6>) is cleared
immediately (Figure 4-12), indicating that the PORTD
latch is waiting to be read by the external bus. When
either the CS or RD pin becomes hig h (level trigg ered),
the interru pt flag bit PSPIF is set on the Q4 clock cycle,
following the next Q2 cycle, indicating that the read is
complete. OBF remains low until data is written to
PORTD by the user firmware.
When not in PSP mode, t he IBF and OBF bits are hel d
clear. However, if flag bit IBOV was previously set, it
must be cleared in firmware.
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF must be cleared by the us er in fi rmware and th e
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1<7>).
FIGURE 4-10: PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
Data Bus
WR
Port
RD Port
RDx pin
QD
CK
EN
QD
EN
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1<7>)
Read
Chip Select
Write
RD
CS
WR
TTL
TTL
TTL
TTL
Note 1: I/O pins have protection diodes to VDD and VSS.
PIC16F87XA
DS39582C-page 52 2001-2013 Microchip Technology Inc.
FIGURE 4-11: PARALLEL SLAVE PORT WRITE WAVEFORMS
FIGURE 4-12: PAR ALLEL SLAVE PORT READ WAV EFORM S
TABLE 4-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
RD
IBF
OBF
PSPIF
PORTD<7:0>
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
IBF
PSPIF
RD
OBF
PORTD<7:0>
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
08h PORTD Port Data Latch when written; Port pins when read xxxx xxxx uuuu uuuu
09h PORTE — — — — —RE2RE1RE0---- -xxx ---- -uuu
89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
9Fh ADCON1 ADFM ADCS2 —— PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000
Legend: x = unk nown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873A/876A ; always maintain these bits clear.
2001-2013 Microchip Technology Inc. DS39582C-page 53
PIC16F87XA
5.0 TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 5-1 is a bloc k diagram o f the T imer0 mod ule and
the prescaler shared with the WDT.
Additional information on the Timer0 module is
available in the PIC® Mid-Range MCU Family Refer-
ence Manual (DS33023).
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0
module will increment every instruction cycle (without
prescaler). If the TMR0 register is written, the incre-
ment is inhibited for the following two instru ction cycles.
The user can work around this by writing an adjusted
value to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit, T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discus se d in detail in Sec tion 5.2 “Using T i mer0 w ith
an External Clock”.
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The
prescaler is not readable or writable. Section 5.3
“Prescaler” details the operation of the prescaler.
5.1 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0
register ov erflows from FFh to 00h. This overflow sets
bit TMR0IF (INTCON<2>). The interrupt can be
masked by clearing bit TMR0IE (INTCON<5>). Bit
TMR0IF must be cleared in software by the Timer0
module Interrupt Service Routine before re-enabling
this interrupt. The TMR0 interrupt cannot awaken the
processor from Sleep since the timer is shut-off during
Sleep.
FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
RA4/T0CKI
T0SE
pin
M
U
X
CLKO (= FOSC/4)
Sync
2
Cycles TMR0 Reg
8-bit Prescaler
8-to-1 MUX
M
U
X
MUX
Watchdog
Timer
PSA
01
0
1
WDT
Time-out
PS2:PS0
8
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPT ION_RE G <5:0>).
PSA
WDT Enable bit
M
U
X
0
10
1
Data Bus
Set Fl a g b i t TMR0I F
on Overflow
8
PSA
T0CS
PRESCALER
PIC16F87XA
DS39582C-page 54 2001-2013 Microchip Technology Inc.
5.2 Using Timer0 with an External
Clock
When no pr escal er is used, t he ex ternal clo ck inp ut is
the same as the pre sc al er outp ut. Th e sy nch ron iz atio n
of T0CKI with the internal phase clocks is accom-
plishe d by sampling the prescale r output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necess ary fo r T0CK I to b e high for at leas t 2 TOSC (and
a small RC delay of 20 ns) and low for at least 2 TOSC
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
5.3 Prescaler
There is only one prescal er av ai lable which is mutu ally
exclus ively shar ed between th e T imer0 mod ule and the
Watchdog Timer. A prescaler assignment for the
T imer0 module means that there is no prescaler for the
Watchdog Timer and vice versa. This prescaler is not
readable or writable (see Figure 5-1).
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment an d prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler . When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writable.
REGISTER 5-1: OPTION_REG REGISTER
Note: Writing to TMR0 when the prescaler is
assign ed to Timer0 will clear th e prescal er
count, but will not change the prescaler
assignment.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 RBPU
bit 6 INTEDG
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increm ent on high-to-low transition on T0CKI pin
0 = Increm ent on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: To avoid an unintended device Reset, the instruction sequence shown in the PIC®
Mid-Range MCU Family Reference Manual (DS33023) must be executed when
changing the prescaler assignment from Timer0 to the WDT. This sequence must
be followed even if the WDT is disabled.
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TM R0 Rate WDT Rat e
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PIC16F87XA
TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0
Add r e s s Nam e Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
01h,101h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unk nown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
PIC16F87XA
DS39582C-page 56 2001-2013 Microchip Technology Inc.
NOTES:
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PIC16F87XA
6.0 TIMER1 MODULE
The Timer1 module is a 16 -bi t tim er/c ou nter cons is tin g
of two 8-bit registers (TMR1H and TMR1L) which are
readable and writable. The TMR1 register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rol ls over to 0000h. Th e TMR1 inter rupt, if e nabled,
is generated on overflow which is latched in interrupt
flag bit, TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit, TMR1IE (PIE1<0>).
Timer1 can operate in one of two modes:
•As a Timer
• As a Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
Timer1 can be enabled/disabled by setting/clearing
control bit, TMR1ON (T1CON<0>).
Timer1 also has an internal “Reset input”. This Reset
can be generated by either of the two CCP modules
(Section 8.0 “Capture/Compare/PWM Modules”).
Register 6-1 shows the Timer1 Control register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. That is, the TRISC<1:0> value is
ignored and these pins read as ‘0’.
Additional information on timer modules is available in
the PIC® Mid-Range MCU Family Reference Manual
(DS33023).
REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 T1CKPS1:T1CKPS0: Ti mer1 In put Clock Pres cale Se lect bits
11 = 1:8 prescale value
10 = 1:4 prescale value
01 = 1:2 prescale value
00 = 1:1 prescale value
bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Osci llator is shut-off (the oscillator inverter is turned off t o elim inate power drain)
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
When TMR1CS = 1:
1 = Do not synchronize ex ternal clock input
0 = Synchroni ze external clock in put
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582C-page 58 2001-2013 Microchip Technology Inc.
6.1 Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit, T1SYNC
(T1CON<2>), has no effect since the internal clock is
always in sync.
6.2 Timer1 Counter O peration
Timer1 may operate in either a Synchronous, or an
Asynchronous mode, depending on the setting of the
TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur o n a rising edge. Af ter Ti mer1
is enab led in Coun ter mode, the module must fi rst have
a falling edge before the counter begins to increment.
FIGURE 6-1: TIMER1 INCREMENTING EDGE
6.3 Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mod e, the timer incr ement s on every risin g edge of
clock input on pin RC1/T1OSI/CCP2 when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI when
bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple counter.
In this configuration, during Sleep mode, Timer1 will not
increment even if the external clock is presen t since the
synchronization circuit is shut-off. The prescaler,
however, will continue to increment.
FIGURE 6-2: TIMER1 BLOCK DIAGRAM
T1CKI
(Default High)
T1CKI
(Default Low)
Note: Arrows indicate counter increments.
TMR1H TMR1L
T1OSC T1SYNC
TMR1CS
T1CKPS1:T1CKPS0 Q Clock
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
TMR1ON
On/Off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
Clock Input
2
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(2)
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
Set Flag bit
TMR1IF on
Overflow TMR1
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PIC16F87XA
6.4 Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYN C (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during Sleep and can
generate an interrupt-on-overflow which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer.
In Asynchronous Counter mode, Timer1 cannot be
used as a time base for capture or compare operations.
6.4.1 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L while the timer is running
from an e xternal asy nchronous cl ock will ens ure a valid
read (taken care of in hardware). However, the user
should keep i n min d that re ading t he 16-b it time r in tw o
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For write s, it is re comm ended that the us er simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers while the
register is incrementing. This may produce an
unpredictable value in the timer r egister.
Reading the 16-bit value requires some care.
Examples 12-2 and 12-3 in the PIC® Mid-Range MCU
Family Reference Manual (DS33023) show how to
read and write Timer1 when it is running in
Asynchronous mode.
6.5 Timer1 Oscillator
A crystal oscillator circu it is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit, T1OSCEN (T1CON<3>). The oscil-
lator is a low-power oscillator, rated up to 200 kHz. It
will co ntinue to run durin g Sleep. It is primarily inte nded
for use with a 32 kHz crystal. Table 6-1 shows the
capacitor selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user m us t prov id e a so ftware time delay to en su re
proper oscillator start-up.
T ABLE 6-1: CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
6.6 Resetting Timer1 Using a CCP
Trigger Output
If the CCP 1 or CCP2 mo dule is config ured in C omp are
mode to generate a “special event trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1.
T imer 1 must be co nfigured fo r either T i mer or Synch ro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this Rese t operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of ope ration, the CCPRxH: CCPRx L regis -
ter pair effectively becomes the period register for
Timer1.
Osc Type Freq. C1 C2
LP 32 kHz 33 pF 33 pF
100 k Hz 15 pF 15 pF
200 k Hz 15 pF 15 pF
These values are for design guidance only.
Crystals Tested:
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
100 kHz Epson C-2 100.00 KC-P ± 20 PPM
200 kHz STD XTL 200.000 kHz ± 20 PPM
Note 1: Higher ca pacitance increases th e s t a bil ity
of oscillator but also increas es the start-up
time.
2: Since each resonator/crystal ha s its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
Note: The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit, TMR1IF (PIR1<0 >).
PIC16F87XA
DS39582C-page 60 2001-2013 Microchip Technology Inc.
6.7 Resetting of Timer1 Regist er Pair
(TMR1H, TMR1L)
TMR1H an d TMR1L reg isters are not rese t to 00h on a
POR, or any other Reset, except by the CCP1 and
CCP2 special event triggers.
T1CON register is reset to 00h on a Power-on Reset,
or a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other Resets, the register
is unaffected.
6.8 Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
TABLE 6-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Address Nam e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 B it 1 Bit 0 V a lue on:
POR, BOR
Value on
all other
Resets
0Bh,8Bh,
10Bh, 18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unk nown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
2001-2013 Microchip Technology Inc. DS39582C-page 61
PIC16F87XA
7.0 TIMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a
post scaler . It can be used a s the PWM time base for the
PWM mode of the CCP module(s). The TMR2 register
is readable and writable and is cleared on any device
Reset.
The input clock (FOSC/4) has a prescale option of
1:1, 1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1: 0>).
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit,
TMR2IF (PIR1<1>)).
T imer2 can b e shut-of f by clearing control bit, T MR2ON
(T2CON<2>), to minimize power consum ption.
Register 7-1 shows the Timer2 Control register.
Additional information on timer modules is available in
the PIC® Mid-Range MCU Family Reference Manual
(DS33023).
FIGURE 7-1: TIMER2 BLOCK DIAGRAM
REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
Comparator
TMR2
Sets Fla g
TMR2 Reg
Output(1)
Reset
Postscaler
Prescaler
PR2 Reg
2
FOSC/4
1:1 to 1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
Note 1: TMR2 register output can be software selected by the
SSP module as a baud clock.
T2OUTPS3:
T2OUTPS0
T2CKPS1:
T2CKPS0
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 postscale
0001 = 1:2 postscale
0010 = 1:3 postscale
•
•
•
1111 = 1:16 postscale
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582C-page 62 2001-2013 Microchip Technology Inc.
7.1 Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (POR, MCLR Reset, WDT
Reset or BOR)
TMR2 is not cleared when T2CON is written.
7.2 Output of TMR2
The output of TMR2 (before the post scaler) is fed to the
SSP module, which optionally uses it to generate the
shift clock.
TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Address Name Bit 7 Bit 6 Bit 5 B it 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh, 18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
11h T MR2 Timer2 Module’s Register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
2001-2013 Microchip Technology Inc. DS39582C-page 63
PIC16F87XA
8.0 CAPTURE/COMPARE/PWM
MODULES
Each Capture/Compare/PWM (CCP) module contains
a 16-bit register which can operate as a:
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle register
Both the CCP1 and CCP2 modules are identical in
operatio n, with th e except ion being the operati on of the
specia l event trigger. Table 8-1 and Table 8-2 sho w the
resources and interactions of the CCP module(s). In
the following sections, the operation of a CCP module
is describe d with respec t to CCP1. CCP2 opera tes the
same as CCP1 except where noted.
CCP1 Mo dul e:
Capture/Compare/PWM Register 1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. The special event trigger is
generated by a compare match and will reset Timer1.
CCP2 Mo dul e:
Capture/Compare/PWM Register 2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. The special event trigger is
generated by a compare match and will reset Timer1
and start an A/D conversion (if the A/D module is
enabled).
Additional information on CCP modules is availabl e in
the PIC® Mid-Range MCU Family Reference Manual
(DS33023) and in application note AN594, “Using the
CCP Module(s)” (DS005 94).
TABLE 8-1: CCP MODE – TIMER
RESOURCES REQUIR ED
TABLE 8-2: INTERACTION OF TWO CCP MODULES
CCP Mode Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
CCPx Mode CCPy Mode Interaction
Capture Capture Same TMR1 time base
Capture Compare The compare should be configured for the special event trigger which clears TMR1
Compare Compare The compare(s) should be configured for the special event trigger which clears TMR1
PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt)
PWM Capture None
PWM Compare None
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DS39582C-page 64 2001-2013 Microchip Technology Inc.
REGISTER 8-1: CCP1CON REGISTER/CCP2CON REGISTER (ADDRESS 17h/1Dh)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 CCPxX:CCPxY: PWM Least Significant bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits
0000 =Capture/Compare/PWM disabled (resets CCPx module)
0100 =Capture mode, every falling edge
0101 =Capture mode, every rising edge
0110 =Capture mode, eve r y 4th rising edge
0111 =Capture mode, eve r y 16t h risin g edge
1000 =Compare mode, set output on match (CCPxIF bit is set)
1001 =Compare mode, clear output on match (CCPxIF bit is set)
1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is
unaffected)
1011 = Compare mode, trigger sp ecial event (CCPxIF bit is set, CCPx pin is unaffected); CCP1
resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is
enabled)
11xx =PWM mode
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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8.1 Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 r egister wh en an eve nt occurs
on pin RC2/CCP1. An event is defined as one of the
following:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
The type of event is configured by control bits,
CCP1M3:CCP1M0 (CCPxCON<3:0>). When a cap-
ture is made, the interrupt request flag bit, CCP1IF
(PIR1<2>), is set. The interrupt flag must be cleared in
softw are. If another capture occurs before the value in
register CCPR1 is read, the old captured value is
overwritten by the new value.
8.1.1 CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be
configured as an input by setting the TRISC<2> bit.
FIGURE 8-1: CAPTURE MODE
OPERATION BLOCK
DIAGRAM
8.1.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode, or Synchro-
nized Counter mode, for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
8.1.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit, CCP1IF, following any such
change in ope rati ng mod e.
8.1.4 CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. Any Reset will clear
the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleare d, therefore , the first cap ture may be from
a non-zero prescaler. Example 8-1 shows the recom-
mended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 8-1: CHANGING BETWEE N
CAPTURE PRESCALERS
Note: If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a
Capture condition.
CCPR1H CCPR1L
TMR1H TMR1L
Set Flag bit CCP1IF
(PIR1<2>)
Capture
Enable
Qs CCP1CON<3:0>
RC2/CCP1
Prescaler
1, 4, 16
and
Edge Detect
pin
CLRF CCP1CON ; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load the W reg with
; the new prescaler
; move value and CCP ON
MOVWF CCP1CON ; Load CCP1CON with this
; value
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DS39582C-page 66 2001-2013 Microchip Technology Inc.
8.2 Compare Mode
In C ompare mo de, t he 16 -bit CC PR1 r egist er va lue is
constantly compared against the TMR1 register pair
value. Whe n a match occurs, the RC2/CC P1 pin is:
• Driven high
•Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 8-2: COMPARE MODE
OPERATION BLOCK
DIAGRAM
8.2.1 CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an
output by clearing the TRIS C<2> bit.
8.2.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode, or Synchro-
nized Counter mode, if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.2.3 SOFTWARE INTERRUPT MODE
When Ge nerate Software Interrupt mode is chosen, the
CCP1 pin is n ot af fecte d. The CCPIF b it is set, c ausing
a CCP interrupt (if enabled).
8.2.4 SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 regi ste r pai r. This allo ws the CCPR 1 re gis ter t o
ef fectively b e a 16-bit progra mmable pe riod registe r for
Timer1.
The special event trigger output of CCP2 resets the
TMR1 re gist e r p ai r and starts an A/D co nv ersi on (if the
A/D module is enabled).
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to
the default low level. This is not the
PORTC I/O data latch.
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
QS
ROutput
Logic
Special Event Trigger
Set Flag bit CCP1IF
(PIR1<2>)
Match
RC2/CCP1
TRISC<2> CCP1CON<3:0>
Mode Selec t
Output Enable
pin
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>)
and set bit GO/DONE (ADCON0<2>).
Note: The special event trigger from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR 1<0 >).
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8.3 PWM Mode (PWM)
In Pulse Width Modulation mode, the CCPx pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the POR TC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Figure 8-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a ste p-by-step proc edure on how t o set up the CC P
module for PWM operation, see Section 8.3.3 “Setup
for PWM Operatio n”.
FIGURE 8-3: SIMPLIFIED PWM BLOCK
DIAGRAM
A PWM output (Figure 8-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 8-4: PWM OUTPUT
8.3.1 PWM PERIO D
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period].
When TM R2 is equal to PR2, t he following three event s
occur on the next increment cycle:
•TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from C CPR1L into
CCPR1H
8.3.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10- b i t re so l uti on is av ai l ab le. T he CC PR 1L c on tai ns
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM Duty Cycle =(CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 Prescale Value)
CCPR1L and CCP1CON<5:4> can be written to a t any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitch-free PWM
operation.
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
The ma ximum P WM res olut ion (b its) for a given PWM
frequency is given by the following formula.
EQUATION 8-1:
Note: Clearing the CCP1CON register will force
the CCP1 PWM o utpu t la tch to th e de fau lt
low level. This is not the PORTC I/O data
latch.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
RQ
S
Duty Cycle Registers CCP1CON<5:4>
Clear Time r,
CCP1 pin and
latch D.C.
TRISC<2>
RC2/CCP1
Note 1: The 8-bit timer is concatenated with 2-bit internal Q
clock, or 2 bits of the prescaler, to create 10-bit time
base.
Period
Duty Cycle
TMR2 = P R 2
TMR2 = Duty Cycle
TMR2 = PR2
Note: The Timer2 postscaler (see Section 7.1
“Timer2 Prescaler and Postscaler”) is
not used in the determination of the PWM
frequency. The postscaler could be used
to have a servo update rate at a different
frequency than the PWM output.
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
log(FPWM
log(2)
FOSC )bitsResolution =
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DS39582C-page 68 2001-2013 Microchip Technology Inc.
8.3.3 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2 register.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC <2> bit.
4. Set the TMR2 prescale value and enab le Time r2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
TABLE 8-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
TABLE 8-4: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0xFFh 0xFFh 0xFFh 0x3Fh 0x1Fh 0x17h
Maximum Resolution (bi ts) 10 10 10 8 7 5.5
Addr e s s Na m e Bi t 7 Bit 6 Bi t 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
0Bh,8Bh,
10Bh, 18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 — — — — — — —CCP2IF---- ---0 ---- ---0
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unk nown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
Note 1: The PSP is not implemented on 28-pin devices; always maintain these bits clear.
2001-2013 Microchip Technology Inc. DS39582C-page 69
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TABLE 8-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Add r e s s Name B it 7 Bi t 6 B i t 5 Bit 4 B it 3 B it 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
0Bh,8Bh,
10Bh, 18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 — — — — — — —CCP2IF---- ---0 ---- ---0
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
87h TRI S C PORT C D ata Dire cti o n Regi s ter 1111 1111 1111 1111
11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000
92h PR2 Timer2 Module’s Period Register 1111 1111 1111 1111
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h CCPR 1L Capt ur e/ Compare/PWM Regi s ter 1 (L SB) xxxx xxxx uuuu uuuu
16h CCPR 1H Capt ure/ Co mpare/PWM Re gi s ter 1 (MS B) xxxx xxxx uuuu uuuu
17h CCP1CON —— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh CCPR2L Captur e/ Co mp ar e/P WM Regi s ter 2 (L SB) xxxx xxxx uuuu uuuu
1Ch CCPR 2H Capt ure/Compar e/P WM Regi s ter 2 (MS B) xxxx xxxx uuuu uuuu
1Dh CCP2CON —— CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unk nown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PWM and T imer2.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
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NOTES:
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9.0 MASTER SYNCHRONOUS
SERIAL PORT (MS SP)
MODULE
9.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
periphera l or m icroc ontroll er dev ices. Th ese p eriphera l
devices may be serial EEPROMs, shift registers,
displa y drivers, A/D converte rs, etc. The MSSP modul e
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
- Full Master mo de
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
•Master mode
• Multi-Master mode
• Slave mode
9.2 Control Registers
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON and SSPCON2). The use
of the se registers and thei r ind iv idu al c on figuration bit s
differ significantly, depending on whether the MSSP
module is operated in SPI or I2C mode.
Additional details are provided under the individual
sections.
9.3 SPI Mode
The SPI m ode allow s 8 bits o f data to be sync hronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pi ns are used:
• Serial Data Out (SDO) – RC5/SDO
• Serial Data In (SDI) – RC4/SDI/SDA
• Serial Clock (SCK) – RC3/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) – RA5/AN4/SS/C2OUT
Figure 9-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 9-1: MSSP BLOCK DIAGRAM
(SPI MODE)
Note: When the SPI is in Slave mode with SS pin
control enabled (SSPCON<3:0> = 0100),
the state of the SS pin can affect the state
read back from the TRISC<5> bit. The
Peripheral OE signal from the SSP mod-
ule in PORTC controls the state that is
read back from the TRISC<5> bit (see
Section 4.3 “PORTC and the TRISC
Register” for information on PORTC). If
Read-Modify-Write instructions, such as
BSF, are perf ormed on the TRIS C register
while the SS pin is h igh, th is will ca use th e
TRISC<5> bit to be set, thus disabling the
SDO output.
Read Write
Internal
Data Bus
SSPSR reg
SSPM3:SSPM0
bit0 Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 Output
TOSC
Prescaler
4, 16, 64
2
Edge
Select
2
4
Data to TX/RX in SSPSR
TRIS bit
2
SMP:CKE
RC5/SDO
SSPBUF reg
RC4/SDI/SDA
RA5/AN4/
RC3/SCK/SCL
Peripheral OE
SS/C2OUT
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DS39582C-page 72 2001-2013 Microchip Technology Inc.
9.3.1 REGISTERS
The MSSP module has four registers for SPI mode
operation. These are:
• MSSP Control Register (SSPCON)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
SSPCON and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON regis-
ter is readable and writable. The lower six bits of the
SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double-
buff ered. A write to SSPBUF will write to bo th SSPBUF
and SSPSR.
REGISTER 9-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE) (ADDRESS 94h)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF
bit 7 bit 0
bit 7 SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6 CKE: SPI Clock Select bi t
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
Note: Polarity of clock state is set by the CKP bit (SSPCON1<4>).
bit 5 D/A: Data/Address bit
Used in I2C mode only.
bit 4 P: Stop bit
Used in I2C mode onl y . This bit is cl eared when the MSSP module is disabled, SSPEN is cleared.
bit 3 S: Start bit
Used in I2C mode only.
bit 2 R/W: Read/W ri te bit information
Used in I2C mode only.
bit 1 UA: Update Address bit
Used in I2C mode only.
bit 0 BF: Buffer Full Status bit (Receive mode only)
1 = Receiv e complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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REGISTER 9-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) (ADDRESS 14h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
bit 7 WCOL: Write Collision Detect bit (Transmit mode only )
1 = The SSPBUF register is written while it is still transmitting the previous word. (Must be
cleared in software.)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1 = A new byte is received while the SSPBUF registe r is still holding the previ ous dat a. In cas e
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPBUF, even if only transmitting data, to avoid setting overflow. (Must be
cleared in software.)
0 = No overflow
Note: In Master mode, the overflow bit is not set, since each new reception (and
transmission) is initiated by writing to the SSPBUF register.
bit 5 SSPEN: Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCK, SDO, SDI, and SS as se rial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note: When enabled, these pins must be properly configured as input or output.
bit 4 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for cloc k is a low level
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0101 = SPI S lave mod e, clock = SCK pin. SS pin control disabled. SS can b e used as I/O pi n.
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note: Bit combinations not specifically listed here are either reserved or implemented in
I2C mo de onl y.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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DS39582C-page 74 2001-2013 Microchip Technology Inc.
9.3.2 OPERATION
When initializing the SPI, several options need to be
specif ied. This is done by progra mming the ap propriate
control bits (SSPCON<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on risi ng/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MS SP consi sts of a trans mit/rec eive shift r egiste r
(SSPSR) and a buf fer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
unti l the rece ived da ta is ready. Once th e eight bits of
data have been received, that byte is moved to the
SSPBUF register. Then, the Buffer Full detect bit, BF
(SSPSTAT<0>), and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception b efore
reading the data that was just r eceived. Any write to the
SSPBUF register durin g transmission/rec eption of dat a
will be ign ore d an d the wr ite c ol lis io n de tec t bi t, WC OL
(SSPCON<7>), will be set. User software must clear
the WCOL bit so that it can be determin ed if the foll ow-
ing write(s) to the SSPBUF register completed
successfully.
When the application software is expecting to receive
valid da ta, the SSPBUF shoul d be read before th e next
byte of dat a to transfer is writ ten to the SSPBUF. Buffer
Full bit, BF (SSPSTAT<0>), indicates when SSPBUF
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, the BF bit is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally, the MSSP interrupt is used to
determine when the transmission/reception has com-
pleted. T he SSPBUF must be rea d and/or written. If the
interrupt method is not goi ng to b e used, then sof tw a re
polling can be d one to ensure that a write collision d oes
not occur. Example 9-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
The SSPSR is n ot directly re adable or wri table and can
only be accessed by addressing the SSPBUF regis ter.
Additionally, the MSSP Status register (SSPSTAT)
indicates the various status conditions.
EXAMPLE 9-1: LOADING THE SSPBUF (SSPSR) REGISTER
LOOP BTFSS SSPSTAT, BF ;Has data been received(transmit complete)?
BRA LOOP ;No
MOVF SSPBUF, W ;WREG reg = contents of SSPBUF
MOVWF RXDATA ;Save in user RAM, if data is meaningful
MOVF TXDATA, W ;W reg = contents of TXDATA
MOVWF SSPBUF ;New data to xmit
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9.3.3 ENABLING SPI I/O
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pin s. For the pins t o beha ve as t he serial port fun c-
tion, some must have their data direction bits (in the
TRIS regi ster) appropriately programmed. That is:
• SDI is a uto matically control led by the SPI modul e
• SDO must have TRISC<5> bit cleared
• SCK (Master mode) must have TRISC<3> bit
cleared
• SCK (Slave mode) must have TRISC<3> bit set
•SS
must have TRISC<4> bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
9.3.4 TYPICAL CONNEC TI ON
Figure 9-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their
programmed clock edge and latched on the opposite
edge of the clock. Both processors should be
programmed to the same Clock Polarity (CKP), then
both controllers would send and receive data at the
same tim e. Whet her the dat a is meaningful (or dummy
data) depends on the application software. This leads
to three scenarios for data transmission:
• Master sends data–Slave sends dummy data
• Master sends data–Slave sends data
• Master sends dummy data–Slave sends data
FIGURE 9-2: SPI MASTE R/S LAVE CONNECTION
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDO
SDI
PROC ES SOR 1
SCK
SPI Master SSPM3:SSPM0 = 00xxb
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
LSb
MSb
SDI
SDO
PROCESSOR 2
SCK
SPI Slave SSPM3:S SPM0 = 010xb
Serial Clock
PIC16F87XA
DS39582C-page 76 2001-2013 Microchip Technology Inc.
9.3.5 MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 9-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF registe r is written to. If the SPI is
only going to receive, the SDO output could be
disabled (programmed as an input). The SSPSR
register will conti nue to shif t in the signa l present on th e
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
The clock polarity is selected b y appropriately program-
ming the CKP bi t (SSPCON<4>). This then, would give
waveforms for SPI communication as shown in
Figure 9-3, Figure 9-5 and Figure 9-6, where the MSB
is transmitted first. In Master mode, the SPI clock rate
(bit rate) is user programmable to be one of the
following:
•F
OSC/4 (or TCY)
•FOSC/16 (or 4 • TCY)
•F
OSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 40 MHz) of
10.00 Mbps.
Figure 9-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
dat a is shown.
FIGURE 9-3: SPI MODE WAVEFORM (MASTER MODE)
SCK
(CKP = 0
SCK
(CKP = 1
SCK
(CKP = 0
SCK
(CKP = 1
4 Clock
Modes
Input
Sample
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 7 bit 0
SDI
SSPIF
(SMP = 1)
(SMP = 0)
(SMP = 1)
CKE = 1)
CKE = 0)
CKE = 1)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(CKE = 0)
(CKE = 1)
Next Q4 Cycle
after Q2
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9.3.6 SLAVE MODE
In Slave m ode , the data is transmitted and r ece iv ed a s
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
9.3.7 SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode wit h SS pin control ena bled
(SSPCON<3:0> = 04h). The pin must n ot be dri ven low
for the SS pin to function as an input. The data latch
must be high. When the SS pin is low , transmission and
receptio n are enab led and the SDO pin is driv en. When
the SS pin goes high, the SDO pin is no longer driven
even if in the middle of a tran smitted byte an d becomes
a floating output. External pull-up/pull-down resistors
may be desirable , depending on the application.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high le vel or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an in put. This d isables transmissi ons from th e SDO.
The SDI can always be left as an input (SDI function)
since it cann ot cre ate a bus con flict.
FIGURE 9-4: SLAVE SYNCHRONIZATION WAVEFORM
Note 1: When the SPI is in Sla ve mode with SS pin
control enabled ( SSPCON<3:0> = 0100),
the SPI module will reset if the SS pin is set
to VDD.
2: If the SPI is us ed in Slave Mo de with CK E
set, then the SS pin control must be
enabled.
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7
SDO bit 7 bit 6 bit 7
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
bit 0
bit 7 bit 0
Next Q4 Cycle
after Q2
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DS39582C-page 78 2001-2013 Microchip Technology Inc.
FIGURE 9-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
FIGURE 9-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Optional
Next Q4 Cycle
after Q2
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 1)
CKE = 1)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Not Optional
Next Q4 Cycle
after Q2
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9.3.8 SLEEP OPERATION
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI Transmit/Receive Shift register
operat es asy nchron ously to the devi ce. Th is al lows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bit s have been received , the MSSP interrupt
flag bit will be set and if enabled, w ill w ake the device
from Sleep.
9.3.9 EFFECTS OF A RESET
A Reset disable s the MSSP module and termina tes the
current transfer.
9.3.10 BUS MODE COMPATIBILITY
Table 9-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 9-1: SPI BUS MODES
There is also a SMP bit w hich co ntrols whe n the dat a is
sampled.
TABLE 9-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Stan dard SPI Mode
Terminology
Control Bits State
CKP CKE
0, 0 0 1
0, 1 0 0
1, 0 1 1
1, 1 1 0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TRISC PORTC Data Direction Register 1111 1111 1111 1111
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
TRISA — PORTA Data Direction Register --11 1111 --11 1111
SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’.
Shaded cells are not used by the MSSP in SPI mode.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on 28-pin devices; always maintain these bits clear.
PIC16F87XA
DS39582C-page 80 2001-2013 Microchip Technology Inc.
9.4 I2C Mode
The MSSP module in I2C mode fully implements all
master an d sla ve func tion s (in cl udi ng general call sup-
port) and provides interrupts on Start and Stop bits in
hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCL) – RC3/SCK/SCL
• Serial data (SDA) – RC4/SDI/SDA
The user must confi gure these pins as inputs or output s
through the TRISC<4:3> bits.
FIGURE 9-7: MSSP BLOCK DIAGRAM
(I2C MODE)
9.4.1 REGISTERS
The MSSP module has six registers for I2C operat ion.
These are:
• MSSP Control Register (SSPCON)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
• MSSP Address Register (SSPADD)
SSPCON, SSPCON2 and SSPSTAT are the control
and status registers in I2C mode operation. The
SSPCON and SSPCON2 registers are readable and
writable. The lower six bits of the SSPSTAT are
read-only. The upper two bits of the SSPSTAT are
read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
SSPADD register holds the slave device address
when the SSP is configured in I2C Sl ave m ode . Wh en
the SSP is configured in Master mode, the lower
seven bits of SSPADD act as the baud rate generator
reload value.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double-
buff ered. A write to SSPBUF will write to bo th SSPBUF
and SSPSR.
Read Write
SSPSR reg
Match Detect
SSPADD reg
Start and
Stop bit Detect
SSPBUF reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT reg)
RC3/SCK/SCL
RC4/SDI/
Shift
Clock
MSb LSb
SDA
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REGISTER 9-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE) (ADDRESS 94h)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF
bit 7 bit 0
bit 7 SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high-speed mode (400 kHz)
bit 6 CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit
1 = Indicates that a Stop bit has been detec ted last
0 = Stop bit was not detected last
Note: This bit is cleared on Reset and when SSPEN is cleared.
bit 3 S: Start bit
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
Note: This bit is cleared on Reset and when SSPEN is cleared.
bit 2 R/W: Read/W ri te bit information (I2C mode only)
In Slave mode:
1 = Read
0 = Write
Note: This bit holds the R/W bit information following the last address match. This bit is
only valid from the address match to the next Start bit, Stop bit or not ACK bit.
In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
Note: ORing this b it with SEN, RSEN, PEN, RCEN o r ACKEN will i ndicate i f the MSSP i s
in Idle mode.
bit 1 UA: Update Address (10-bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
In Transmit mode:
1 = Receiv e complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
In Receive mode:
1 = Data Transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0 = Data Transmit complete (does not include the ACK and Stop bits), SSPBUF is empty
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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DS39582C-page 82 2001-2013 Microchip Technology Inc.
REGISTER 9-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE) (ADDRESS 14h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
bit 7 WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for
a transmission to be started. (Must be cleared in so ftware.)
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word. (Must be
cleared in software.)
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6 SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte. (Must be
cleared in software.)
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5 SSPEN: Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins
0 = Disables the serial port and configures these pins as I/O port pins
Note: When enabled, the SDA an d SCL pins must be properly co nfigured a s input o r output.
bit 4 CKP: SCK Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In Master mode:
Unused in this mode.
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011 = I2C Firmware Controlled Master mode (Slave Idle)
1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
Note: Bit combinations not specifically listed here are either reserved or implemented in
SPI mode only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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REGISTER 9-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE) (ADDRESS 91h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
bit 7 GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledge
0 = Acknowledge
Note: Valu e that will be t ransmitte d when the user initi ates an Acknow ledge s equence at
the end of a receive.
bit 4 ACKEN: Acknowled ge Sequ enc e Enab le bit (Ma ste r Recei ve mo de onl y)
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence Idle
bit 3 RCEN: Receive Enable bit (Master mode only )
1 = Enables Receive mode for I2C
0 = Receive Idle
bit 2 PEN: Stop Condition Enable bit (Master mode only)
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Id le
bit 1 RSEN: Repeated Start Condition Enabled bit (Master mode only)
1 = Initiate Repeated Start condition on SD A and SCL pins. Au tomatical ly c leared b y hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enabled/Stretch Enabled bit
In Maste r mode :
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by ha rdware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both sl ave transmit and slave receive (stretch enabled)
0 = Clock stretching is enabled for slave transmit only (PIC16F87X compatibility)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: For bit s ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mo de,
this bit may not be se t (no s poo lin g) an d the SSPBUF may no t be w ritt en (or writes
to the SSPBUF are disabled).
PIC16F87XA
DS39582C-page 84 2001-2013 Microchip Technology Inc.
9.4.2 OPERATION
The MSSP module functions are enabled by setting
MSSP Enable bit, SSPEN (SSPCON<5>).
The SSPCON register allows control of the I2C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
•I
2C Master mode, clock = OSC/4 (SSPADD + 1)
•I
2C Slave mode (7-bit address)
•I
2C Slave mode (10-bit address)
•I
2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
•I
2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
•I
2C Firmware Controlled Master mode, slave is
Idle
Selection of any I2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain, pro-
vided these pins are programmed to inputs by setting
the appro priate TRISC b its. To ensure proper o peration
of the module, pull-up resistors must be provided
externally to the SCL and SDA pins.
9.4.3 SLAVE MODE
In Slave mod e, the SCL and SDA pins mu st be co nfi g-
ured as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
The I2C Slave mod e h ardwa re w i ll alw a ys ge nera te a n
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits
When an add ress is matched, or the data transfer af ter
an add res s mat ch i s rece ived , th e ha rdw are au tom ati-
cally will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value
currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
• The buffer full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
• The overflow bi t, SSPOV (SSPCON<6>), was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The
BF bit is cleared by readi ng the SSPBUF register , whil e
bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low fo r pro per op eration. The high and low times o f th e
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter #100
and parameter #101.
9.4.3.1 Addressing
Once the MSSP module has been enabled, it waits for
a S t art conditio n to occur. Foll owing the S t art condi tion,
the 8 bits are shifted into the SSPSR register . All incom-
ing bits are sampled with the rising edge of the clock
(SCL) line. The value of register SSPSR<7:1> is com-
pared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK pulse is generated.
4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is
set (interrupt is generated if enabled) on the
falling edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) o f the firs t address b yte specify if this i s a 10-b it
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address, the first byte would equal
‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two
MSbs of the address. The sequence of events for
10-bit address is as follows, with steps 7 through 9 for
the slave-transmitter:
1. Receive first (high) byte of address (bits SSPIF,
BF and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of address (bits
SSPIF, BF and UA are set).
5. Update the SSPADD registe r with the f irst (high)
byte of a ddre ss . If m at ch rel ea ses SCL line, this
will clear bit UA.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive Repeated Start condition.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
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9.4.3.2 Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleare d. The re ceived ad dre ss is loa ded in to
the SSPBUF register and the SDA line is held low
(ACK).
When the address byte overflow condition exists, then
the No Acknow ledge (ACK) puls e is given. An overfl ow
condition is defined as either bit BF (SSPSTAT<0>) is
set or bit SSPOV (SSPCON<6>) is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1< 3>) must be cleared in soft-
ware. The SSPSTAT register is used to de termine the
status of the byte.
If SEN is enabled (SSPCON<0> = 1), RC3/SCK/SCL
will be held low (cloc k stretch) following each dat a trans-
fer. The clock must be released by setting bit CKP
(SSPCON<4>). See Section 9.4.4 “Clock Stretching”
for more detail.
9.4.3.3 Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPST A T register is set. The received address is loaded
into the SSPBUF register . The ACK puls e will be sent on
the ninth bit and pin RC3/SCK/S CL is held low regard-
less of SEN (see Section 9.4.4 “Clock Stretching” for
more detail). By stretching the clock, the master will be
unable to assert another clock pulse until the slave is
done preparing the transmit data. The transmit data
must be loaded into the SSPBUF register, which also
loads the SSPSR register. Then pin RC3/SCK/SCL
should be enabled by setting bit CKP (SSPCON<4>).
The eight data bits are shifted out on the falling edge of
the SCL input. This ensures that the SDA signal is valid
during the SCL high time (Figure 9-9).
The ACK pulse from the master-receiver is latched on
the rising edge of the nin th SCL input pu lse. If the SDA
line is high (not ACK), then the data transfer is com-
plete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets SSPSTAT regis-
ter) and the slave monitors for another occurrence of
the Start bit. If the SDA line was low (ACK), the next
transmit da ta must be loaded into the SSPBUF register .
Again, pin RC3/SCK/SCL must be enabled by setting
bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determ in e the s tatus
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
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FIGURE 9-8: I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
S1 234 56 7891 2345 67 8912345 789 P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
ACK
Receiving Data
ACK
Receiving Data
R/W = 0
ACK
Receiving Address
Cleared in software
SSPBUF is read
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D2
6
(PIR1<3>)
CKP (CKP does not reset to ‘0’ wh e n SE N = 0)
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FIGURE 9-9: I2C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
A6 A5 A4 A3 A2 A1 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9
SSPBUF is written in s oftware
Cleared in software
SCL held low
while CPU
responds to SSPIF
From SSPIF ISR
Data in
sampled
S
ACK
Transmitting Data
R/W =
1
ACK
Receiving Address
A7 D7
9 1
D6 D5 D4 D3 D2 D1 D0
2 3 4 5 6 7 8 9
SSP BUF is writte n in s o f tw are
Cleared in software From SSPIF ISR
Transmitting Data
D7
1
CKP
P
ACK
CK P is s e t in so ftware CK P is s e t in so ftware
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FIGURE 9-10: I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S123456789 123456789 12345 789 P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7 D6D5D4D3 D1D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
D2
6
(PIR1<3>) Cleared in software
Receive Second Byte of Address
Cleared by hardware
when SSPADD is updated
with low byte of addr ess
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
ACK
CKP
12345 789
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Cleared in software Cleared in software
SSPOV (SSPCON<6>)
SSPOV is set
because SSPB UF is
still full. ACK is not sent.
(CKP does not reset to ‘0’ when SEN = 0)
Clock is held low until
update of SSPADD has
taken place
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FIGURE 9-11: I2C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S123456789 1 23456789 12345 789 P
11110A9A8 A7 A6A5A4A3A2A1A0 11110 A8
R/W=1
ACK
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
Bus master
terminates
transfer
A9
6
(PIR1<3>)
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
Receive First Byte of Address
12345 789
D7 D6 D5 D4 D3 D1
ACK
D2
6
Tran smitting Data Byte
D0
Dummy read of SSPBUF
to clear BF flag
Sr
Cleared in software
Write of SSPBUF
initiates transmit
Cleared in software
Completion of
clears BF flag
CKP (SSPCON<4>)
CKP is set in software
CKP is automatically cleared in hardware holding SCL low
Clock is held low until
update of SSPADD has
taken place
data transmission
Clock is held low until
CKP is set to ‘1’
BF flag is clear
third address sequence
at the end of the
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9.4.4 CLOCK STRETCHING
Both 7 and 10-bit Slave modes implement automatic
clock stretching during a transmit sequence.
The SEN bit (SSPCON2<0>) al lows clock stretch ing to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.
9.4.4.1 Clock Stretching for 7-bit Slave
Receive Mode (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence, if the BF
bit is set, the CKP bit in the SSPCON register is
automatically cleared, forcing the SCL output to be
held low. The CKP bit being cleared to ‘0’ will assert
the SCL lin e low. The CKP bit must be set in the user’s
ISR befo re recep tion i s allo wed to co ntinue . By hol ding
the SCL line low, the user has time to service the ISR
and read the contents of the SSPBUF before the
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring (see
Figure 9-13).
9.4.4.2 Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)
In 10-bit Slave Receive mode, during the address
sequence, clock stretching automatically takes place
but CKP is not c lea red . Duri ng t his time, if th e UA b it i s
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address, with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
9.4.4.3 Clock Stretching for 7-bit Slave
Transmit Mode
7-bit Slave Transmit mode implements clock stretching
by clearing the C KP bit af ter the falli ng edge of the ninth
clock, if the BF bit is clear. This occurs regardless of the
state of the SEN bit.
The user’s ISR must set the C KP bit before tran smis-
sion is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 9-9).
9.4.4.4 Clock Stretching for 10-bit Slave
Transmit Mode
In 10-bit Slave Transmit mode, clock stretching is con-
trolled during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence, which contains the high order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode and clock stretching is controlled by the BF flag
as in 7-bit Slave Transmit mode (see Figure 9-11).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
Note: If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling ed ge of the ni nth c lock oc curs and if
the user hasn’t cleared the BF bit by read-
ing the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching, on the basis of the
state of the BF bit, only occurs during a
data sequence, not an address sequence.
Note 1: If the u ser lo ads t he co nten t s of SSPBUF,
setting the BF bit before the f alling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching wil l not occur .
2: The CKP bit can be set in software
regardless of the state of the BF bit.
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9.4.4.5 Clock Synchronization and the
CKP Bit
When the CKP bit is cleared, the SCL output is forced
to ‘0’; however, setting the CKP bit will not assert the
SCL output low until the SCL output is already sampled
low. Therefore, the CKP bit will not assert the SCL line
until an external I2C master device has already
asserted the SCL line. The SCL output will remain low
until the CKP bit is set and all other devices on the I2C
bus have deasserted SCL. This ensures that a write to
the CKP bit will not violate the minimum high time
requirement for SCL (see Figure 9-12).
FIGURE 9-12: CLOCK SYNCHRONIZATION TIMING
SDA
SCL
DX-1DX
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON
CKP
Master device
deasserts clock
Master device
asserts clock
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FIGURE 9-13: I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
S1 234 56 789 1 2345 67 89 12345 789 P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
ACK
Receiving Data
ACK
Receiving Data
R/W = 0
ACK
Receiving Address
Cleared in software
SSPBUF is read
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D2
6
(PIR1<3>)
CKP
CKP
written
to ‘1’ in
If BF is cleared
prior to the falling
edge of the 9th clock,
CKP will not be reset
to ‘0’ and no clock
stretching will occur
software
Clock is held low until
CKP is set to ‘1’
Clock is not held low
because buffer full bit is
clear prior to falling edge
of 9th clock Clock is not held low
because ACK = 1
BF is set after falling
edge of the 9th clock,
CKP is reset to ‘0’ and
clock stretching occurs
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FIGURE 9-14: I2C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT <0>)
S123456789 123456789 12345 789 P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7D6D5D4D3 D1D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
D2
6
(PIR1<3>) Cleared in software
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address after falling edge
UA (S SP ST AT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address after falling edge
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
ACK
CKP
12345 789
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Cleared in software Cleared in software
SSPOV (SSPCON<6>)
CKP written to ‘1’
Note:An update of the SSPADD register
before the fall ing edge of the ninth cl ock
will have no effect on UA, and UA will
remain set.
Note:An update of the SSPADD register
before the falling edge of the ninth clock
will have no effect on UA and UA will
remain set. in software
Clock is held low until
update of SSPADD has
taken place
of ninth clock
of ninth clock
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
Dummy read of SSPBUF
to clear BF flag
Clock is held low until
CKP is set to ‘1’Clock is not held low
because ACK = 1
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9.4.5 GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually determines
which device will be the slav e addressed by the master.
The exception is the general call address which can
address all devices. When this address is used, all
devices should, in theory , respond with an Acknowledge.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the Gen-
eral Call Ena ble bit (GCEN) is enabled (SSPCON2< 7>
set). Following a Start bit detect, 8 bits are shifted into
the SSPSR and the address is compared against the
SSPADD. It is also compared to the general call
address and fixed in hardware.
If the general call address matches, the SSPSR is
transferre d to the S SPBUF, the BF f lag bit is set (eighth
bit) and on the falling edg e of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
When the i nterrupt is serviced, the s ou rce f or the inter-
rupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the seco nd half of the addre ss to match an d the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-bit Address mode, then the second
half of the address is not necessary, the UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 9-15).
FIGURE 9-15: SLAV E MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
SDA
SCL S
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
Cleared in software
SSPBUF is read
R/W = 0
ACK
General Call Address
Address is compared to general call address.
GCEN (SSPCON2<7>)
Receiving Data ACK
123456789123456789
D7 D6 D5 D4 D3 D2 D1 D0
After ACK, set interrupt.
‘0’
‘1’
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9.4.6 MASTER MODE
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop con-
ditions . The S t op (P) and S t art (S) bit s are clea red fro m
a Reset o r when the MSSP m odule is di sabled. Control
of the I2C bus may be t aken when th e P bit is set or th e
bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.
Once Master mode is enabled, the user has six
options.
1. Assert a Start condition on SDA and SCL.
2. Assert a Repeated Start condition on SDA and
SCL.
3. Write to the SSPBUF register, initiating
transmission of data/address.
4. Configure the I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDA and SCL.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP interrupt if enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeat ed Sta rt
FIGURE 9-16: MSSP BLOCK DIAGRAM (I2C MASTER MODE)
Note: The MSSP module, when configured in
I2C Mast er mode, does n ot allow que ueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the S tart condi-
tion is complet e. In th is ca se, the SSPBUF
will not be wri tten to an d the WCO L bi t will
be set, indicating that a write to the
SSPBUF did not occur.
Read Write
SSPSR
Start bit, Stop bit,
Sta rt bit Detect
SSPBUF
Internal
Data Bus
Set/Re set, S, P, WC O L ( SSP STAT)
Shift
Clock
MSb LSb
SDA
Acknowledge
Generate
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
SCL
SCL In
Bus Collision
SDA In
Receive Enable
Clock Cntl
Clock Arbitrate/WCOL Detect
(hold off clock source)
SSPADD<6:0>
Baud
Set SS PIF, BC LIF
Reset ACKSTAT, PEN (SSPCON2)
Rate
Generator
SSPM3:SSPM0
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9.4.6.1 I2C Master Mode Operation
The master device generates all of the serial clock
pulses and the S t a rt and Stop conditions. A tra nsfer i s
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer , the I2C bus will
not be released.
In Master Transmitter mode, serial data is output
through SDA while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
recei vin g dev ice ( 7 bits) and the Rea d/Writ e (R/W) bit.
In this case, the R/W bit will be logi c ‘0’. Ser ial da ta is
transmitted 8 bits at a time. After each byte is t rans m it-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master Rec eive mode , the first byte transm itted con-
tains the slave address of the transmitting device
(7 bits) and th e R/W bit. In this case, the R/W bit w ill b e
logic ‘ 1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA while SCL outputs the
serial clock. Serial d ata is received 8 bit s at a time. After
each byte is received, an Acknowledge bit is transmit-
ted. Start and Stop conditions indicate the beginning
and end of transmission.
The baud rate gen erator use d for the SPI mode ope ra-
tion is used to set the SCL clock frequency for either
100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 9.4.7 “B aud Rate Generator” for more det ail.
A typical transmit sequence would go as follows:
1. The user generates a Start condition by setting
the Start Enable bit, SEN (SSPC ON2<0>).
2. SSPIF is set. The MSSP module will wait the
required Start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
4. Addres s is shi fted out the SDA p in un til all 8 bit s
are transmitted.
5. The MSSP modu le shift s in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
6. The MSSP modul e gene rates an int errupt a t the
end of th e ninth c lock cyc le by settin g the SSPIF
bit.
7. The user loads the SSPBUF with eight bits of
data.
8. Dat a is shif ted out the SDA pin un til al l 8 b its ar e
transmitted.
9. The MSSP modu le shift s in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
10. The MSSP mo dule g enerate s an int errupt at th e
end of th e ninth c lock cyc le by settin g the SSPIF
bit.
11. The user generates a Stop condition by setting
the Stop Enable bit, PEN (SSPCON2<2>).
12. Interrupt is genera ted once the Stop cond ition i s
complete.
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9.4.7 BAUD RATE GENERATOR
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSP ADD register (Figure 9-17). When a write occurs to
SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to 0 and stops
until an other re load h as t aken pl ace. Th e BRG c ount i s
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of th e last dat a bit is followed by ACK), the int ernal
clock wi ll aut omatica lly st op count ing and t he SCL pin
will rema in in it s last state.
Table 9-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
FIGURE 9-17: BAUD RATE GENER ATOR BLOCK DIAGRAM
TABLE 9-3: I2C CLOCK RATE W/BRG
SSPM3:SSPM0
BRG Down Counter
CLKO FOSC/4
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control Reload
FCY FCY*2BRG Value FSCL
(2 Rollovers of BRG)
10 MHz 20 MHz 19h 400 kHz(1)
10 MHz 20 MHz 20h 312.5 kHz
10 MHz 20 MHz 3Fh 100 kHz
4 MHz 8 MHz 0Ah 400 kHz(1)
4 MHz 8 MHz 0Dh 308 kHz
4 MHz 8 MHz 28h 100 kHz
1 MHz 2 MHz 03h 333 kHz(1)
1 MHz 2 MHz 0Ah 100 kHz
1 MHz 2 MHz 00h 1 MHz(1)
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
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9.4.7.1 Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count, in the
event that the clock is held low by an external device
(Figure 9-17).
FIGURE 9-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
SCL
SCL deasserted but slave holds
DX-1DX
BRG
SCL is sampled high, reload takes
place and BRG start s it s count
03h 02h 01h 00h (hold off) 03h 02h
Reload
BRG
Value
SCL low (clock arbitration) SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
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9.4.8 I2C MASTER MODE START
CONDITION TIMING
To initiate a Start condi tion, the user se t s t he Start con-
dition e nab le b it, SEN (SSPCON2<0> ). If th e SDA and
SCL pins are samp led high, the Baud Rate Generator
is reloaded with the contents of SSPADD<6:0> and
starts its c oun t. I f SC L an d SDA are both sampl ed hig h
when the Baud Rate Generator times out (TBRG), the
SDA pin is driven low. The action of the SDA being
driven low , w hil e SC L is hi gh, is the Start condi tio n an d
causes the S bit (SSPSTAT<3>) to be set. Following
this, the Baud Rate Ge nerator is reloaded w ith the con-
tents of SSPADD<6:0> and resumes its count. When
the Baud Rate Gene rator time s out (TBRG), the SEN bit
(SSPCON2<0>) will be automatically cleared by hard-
ware, the Baud Rate Generator is suspended, leaving
the SDA line held low and the Start condition is
complete.
9.4.8.1 WCOL Status Flag
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
FIGURE 9-19: FIRST START BIT TIMING
Note: If at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low , or if during the Start condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag (BCLIF) is
set, the Start condition is aborted and the
I2C module is reset into its Idle state.
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
conditi on is complete.
SDA
SCL
S
TBRG
1st Bit 2nd Bit
TBRG
SDA = 1, At completion of Start bit,
SCL = 1
Write to SSPBUF occurs here
TBRG
hardware clears SEN bit
TBRG
Write to SEN bit occurs here Set S bit (SSPSTAT<3>)
and sets SSPIF bit
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9.4.9 I2C MASTER MODE REP EAT ED
START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I2C logic
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted lo w. When the SC L pin is sam-
pled low, the Baud Rate Generator is loaded with the
contents of SSPADD<5:0> and begins counting. The
SDA pin is released (brought high) for one Baud Rate
Generator c ount (TBRG). When th e Baud Rate G enera-
tor times out, if SDA is sampled high, the SCL pin will
be deasserted (brought high). When SCL is sampled
high, the Baud Rate Generator is reloaded with the
contents of SSPADD<6:0> and begins counting. SDA
and SCL must be sampled high for one TBRG. This
action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG while SCL is high. Following
this, the RSEN bit (SSPCON2<1>) will be automatically
cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be s et. The SSPIF bit will
not be set until the Baud Rate Generator has timed out.
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode or the default first address in 10-bit mode. After
the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10 -bit mode ) or eight bits of data (7-bit
mode).
9.4.9.1 WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequenc e is in pro gress , the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 9-20: REPEAT START CONDITION WAVEFORM
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus col lis ion dur ing th e Rep eat ed Start
conditi on oc curs if:
• SDA is sampled low when SCL goes
from low to high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
Note: Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
SDA
SCL
Sr = Repeated Start
Write to SSPCON2
Writ e to SSPBUF occurs here
Falling edge of ninth clock,
end of Xmit
At completion of Start bit,
hardw are clea rs R SEN bi t
1st Bit
Set S (SSPSTAT<3>)
TBRG
TBRG
SDA = 1,
SDA = 1,
SCL (no change) SCL = 1
occurs here,
TBRG TBRG TBRG
and sets SSPIF
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9.4.10 I2C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simpl y
writing a value to the SSPBUF register. This action will
set the Buffer Full fla g b it, BF, and allow the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification, parameter
#106). SCL is held low for one Baud Rate Generator
rollove r count (TBRG). Data should be valid before SCL
is released high (see data setup time specification,
parameter #1 07). When t he SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond w ith an ACK bit during the ninth bit time, if an
address match occurred or if data was received prop-
erly . The status of ACK is written i nto th e ACKDT bi t on
the falli ng edge of the ninth clock. If the ma ster receives
an Acknowledge, the Acknowledge Status bit,
ACKSTA T, is cleare d. If not, the bit is set. Af ter the nin th
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 9-21).
After the write to the SSPBUF, each bit of address will
be shif ted out on the falling ed ge of SCL, until all s even
address bits and the R/W bit are completed. On the fal l-
ing edge of the eighth clock, the master will deassert
the SDA pin, allowing the slave to respond with an
Acknowledge. On the fall ing edge of the ni nth clock, the
master will sample the SDA pin to see if the address
was rec ognized by a sla ve. The st atus of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth c lock transmis-
sion of the address, the SSPIF is set, the BF flag is
cleared and th e Baud Ra te Genera tor is t urned o ff until
another write to the SSPBUF takes place, ho ldi ng SCL
low and allowing SDA to float.
9.4.10.1 BF Status Flag
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all eight bits are shifted out.
9.4.10.2 WCOL Status Fl ag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
9.4.10.3 ACKSTAT Status Flag
In T ran smit mod e, the ACKSTAT bit (SSPCON2<6 >) is
cleared when the slave has sent an Acknowledge
(ACK =0) and is set when the slave does Not Acknowl-
edge (ACK =1). A slave sends an Acknowledge when
it has recognized its address (including a general call)
or when the slave has properly received its data.
9.4.11 I2C MASTER MODE RECEPTION
Master mode recepti on is enabl ed by pro grammin g th e
Receive Enable bit, RCEN (SSPCON2<3>).
The Baud Rate Generator begins counting and on each
rollov er, th e state of the SCL pin chan ges (high t o low/
low to high) and data is shifted into the SSPSR. After the
falling edge of the eighth clock, the recei ve enable fla g
is automatically cleared, the contents of the SSPSR are
loaded into the SSPBUF, the BF flag bit is set, the
SSPIF flag bit is set and the Baud Rate Generator is
suspended from counting, holding SCL low. The MSSP
is now in Id le stat e, a waitin g th e ne xt comm and. Whe n
the buffer is read by the CPU, the BF flag bit is automat-
ically cleared. The user can then send an Acknowledge
bit at th e end of recept ion by setting the Acknowledge
Seque nce Enable bit, ACKEN (SSPCON 2 <4>).
9.4.11.1 BF Status Flag
In receiv e op eration, the BF bit is s et whe n an add res s
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
9.4.11.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set w hen 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous recepti on.
9.4.11.3 WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a dat a
byte), th e WCOL bi t is set an d the conte nts of th e buffer
are unchanged (the write doesn’ t occur).
Note: The MSSP module must be in an Idle state
before the RCEN bit is set or t he RCEN bit
will be disregarded.
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FIGURE 9-21: I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SEN
A7 A6 A5 A4 A3 A2 A1 ACK = 0D7 D6 D5 D4 D3 D2 D1 D0
ACK
Transmitting Data or Second Half
R/W = 0Transmit Address to Slave
123456789 123456789 P
Cleared in software service routine
SSPBUF is written in software
from SSP interrup t
After Start con ditio n, SEN clea red by hardware
S
SSPBUF written with 7-bit address and R/W.
Start transmit.
SCL held low
while CPU
responds to SSPIF
SEN = 0
of 10-bit Address
Write SSPCON2<0> SEN = 1
Start condition begins From Slave, clear ACKSTAT bit SSPCON2<6>
ACKSTAT in
SSPCON2 = 1
Cleared in software
SSPBUF written
PEN
Cleared in software
R/W
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FIGURE 9-22: I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
P
9
87
6
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4 A3 A2 A1
SDA
SCL 12345678912345678 9 1234
Bus master
terminates
transfer
ACK Receiving Data from Slave
Receiving Data from Slave D0
D1
D2
D3D4
D5
D6D7
ACK
R/W = 1
Transmit Address to Slave
SSPIF
BF
ACK is not sent
Write to SSPCON2<0> (SEN = 1),
Write to SSPBUF occurs here,
ACK from Sla ve
Master configured as a receiver
by programming SSPCON2<3> (RCEN = 1)PEN b i t = 1
written here
Data shifted in on falling edge of CLK
Cleared in software
start XMIT
SEN = 0
SSPOV
SDA = 0, SCL = 1
while CPU
(SSPSTAT<0>)
ACK
Last bit is shifte d into SSPSR and
content s are unloaded into SSPBUF
Cleared in software
Cleared in software
Set SSPIF interrupt
at end of receive
Set P bit
(SSPSTAT<4>)
and SSPIF
Cleared in
software
ACK from master
Set SSPIF at end
Set SSPIF interrupt
at end of Acknowledge
sequence
Set SSPIF interrupt
at end of Acknow-
ledge sequ en ce
of receive
Set ACKEN, start Acknowledge sequence,
SSPOV is set because
SSPBUF is still full
SDA = ACKDT = 1
RCEN cleared
automatically
RCEN = 1, start
next receive
Write to SSPCON2<4>
to start Acknowledge sequence,
SDA = ACKDT (SSPCON2<5>) = 0
RCEN cleared
automatically
responds to SSPIF
ACKEN
begin Start condit ion
Cleared in software
SDA = ACKDT = 0
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9.4. 12 ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the use r wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low . Following this, the ACKEN bit is automatically
cleared, the baud rate generator is turned off and the
MSSP module then goes into Idle mode (Figure 9-23).
9.4.12.1 WCOL Status Fl ag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buf fer are un ch anged (th e write doesn ’t
occur).
9.4.13 STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert th e SDA line low. When the SDA line is sam-
pled low, the Baud Rate Generator is reloaded and
counts down to 0. When the Baud Rate Generator
times out, the SCL pin will be brought high and one
TBRG (Baud Rate Generator rollover count) later, the
SDA pin will be deass erted. Wh en the SDA pin is sam-
pled hi gh whil e SCL is high, the P bi t (SSPSTAT<4>) is
set. A TBRG la ter, the PEN bit i s cleared and the SSPIF
bit is set (Figure 9-24).
9.4.13.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 9-23: ACKNOW LEDGE SEQUEN CE WAVEFORM
FIGURE 9-24: STOP CONDITION RECEIVE OR TRANSMIT MODE
Note: TBRG = one Baud Rate Generator period.
SDA
SCL
Set SSPIF at the end
Acknowledge sequence starts here,
write to SSPCON2 ACKEN automatically cleared
Cleared in
TBRG TBRG
of receive
8
ACKEN = 1, ACKDT = 0
D0
9
SSPIF
software Set SSP IF at the end
of Acknowledge sequence
Cleared in
software
ACK
SCL
SDA
SDA asserted low before rising edge of clock
Write to SSPCON2,
set PEN
Falling edge of
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
9th clock
SCL b rought high after TBRG
Note: TBRG = one Baud Rate Generator period.
TBRG TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
TBRG
to setup Stop condition
ACK
P
TBRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
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9.4.14 SLEEP OPERATION
While in Sleep mode, the I2C module can receive
address es or data and when an addr ess match or com-
plete byte transfer occurs, wake the processor from
Sleep (if the MSSP interrupt is enabled).
9.4.15 EFFECT OF A RESET
A Reset disable s the MSSP module and termina tes the
current transfer.
9.4.16 MULT I-MAST ER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
deter mination of when the b us is free. The S top (P) an d
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit (SSPSTAT<4>) is set, or the
bus is Idle, with both the S and P bits clear. When the
bus is busy, enabling the SSP interrupt will generate
the interrupt when the Stop condition occurs.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is at
the expected output level. This check is performed in
hardware with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
• A Repeated Start Condition
• An Acknowledge Condition
9.4.17 MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the da ta sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF, and reset the
I2C port to its Idle state (Figure 9-25).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can b e written to. When the us er servic es th e
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated S tart, S top or Acknowledge condition
was in progress when the bus collision occurred, the con-
dition is aborted, the SDA and SCL lines are deasserted
and the respe ct iv e co ntr ol bits in the SS PC ON2 regi st er
are cleared. When the user services the bus collision
Interrupt Service Routine and if the I2C bus is free, the
user can resume communication by asserting a Start
condition.
The Master will continue to monitor the SDA and SCL
pins . I f a Stop cond itio n oc c urs , th e SSPI F bi t will be se t.
A write to the SSPBUF will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detec tion of S t art and S to p conditio ns allows the determi -
nation of when the bus is fr ee. Contro l of the I2C bus can
be tak en when the P bit is set in th e SSPSTAT register or
the bu s is Idle and th e S and P bits are c le are d.
FIGURE 9-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
SDA
SCL
BCLIF
SDA released
SDA line pulled low
by another source Sample SDA. While SCL is high,
data doesn’t match what is driven
Set bus collision
interrupt (BCLIF)
by the master. Bus collision has occurred.
by master
Data changes
while SCL = 0
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9.4.17.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDA or SC L are sampled low at the begi nning of
the Start condition (Figure 9-26).
b) SCL is s am pl ed l ow be fore SD A is asserted low
(Figure 9-27).
During a Start condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCLIF flag is set and
• the MSSP module is reset to its Idle state
(Figure 9-26).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs because it is
assumed that another master is attempting to drive a
data ‘ 1’ during the Start condition.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 9-28). If, howe ve r, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
count s dow n to 0 an d dur ing this tim e, if the SCL pin i s
sampled as ‘0’, a bus collision does not occur. At the
end of t he BRG co unt , the SCL pin is a ss erte d lo w.
FIGURE 9-26: BUS COLLISION DURING START CONDITION (SDA ONLY)
Note: The reason that bus col lision is not a factor
duri ng a Start cond iti on is that no t wo bus
masters can assert a S t art condition at the
exact same time. Therefore, one master
will always assert SDA before the other.
This condition does not cause a bus colli-
sion because the two masters must be
allowed to arbitrate the first address fol-
lowin g the S t art conditi on. If the addres s is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
SDA
SCL
SEN
SDA sampled low before
SDA goes low before the SEN bit is set.
S bit and SSPIF set because
SSP module reset into Idle state.
SEN cleared automatically because of bus collision.
S bit and SSPIF set because
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SDA = 0, SCL = 1.
BCLIF
SSPIF
SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software
SSPIF and BCLIF are
cleared in software
Set BCLIF,
Start condition. Set BCLIF.
S
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FIGURE 9-27: BUS COLLISION DURING START CONDITION (SCL = 0)
FIGURE 9-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA
SCL
SEN bus collision occurs. Set BCLIF.
SCL = 0 before SDA = 0,
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
Interrupt cleared
in software
bus collision occurs. Set BCLIF.
SCL = 0 b efore BR G ti me-out,
‘0’‘0’
‘0’‘0’
SDA
SCL
SEN
Set S
Less t han TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
S
Interrupts cleared
in software
set SS PIF
SDA = 0, SCL = 1,
SCL pulled low after BRG
time-out
Set SS PIF
‘0’
SDA pulled low by other master .
Reset BRG and assert SDA.
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
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9.4.17.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occu rs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
When the user dea sserts SDA and the pin is a llowed to
float high, the BRG is loaded with SSPADD<6:0> and
counts down to 0. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
If SDA is l ow , a bus collision h as occurre d (i.e., anoth er
master is attempting to transmit a data ‘0’, see
Figure 9-29). If SDA is sampled high, the BRG is
reloaded and begin s counting. If SDA goes from high to
low before the BRG times out, no bus collision occurs
becaus e no tw o maste rs can a ssert SDA at exactl y the
same time.
If SCL goes from hig h to low bef ore th e BR G time s o ut
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
tran smit a data ‘1’ during the Repeated Start condition
(Figure 9-30).
If at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
FIGURE 9-29: BUS COLLISION DURING A REPEATED ST ART CONDITION (CASE 1)
FIGURE 9-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SDA
SCL
RSEN
BCLIF
S
SSPIF
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
Cleared in software
‘0’
‘0’
SDA
SCL
BCLIF
RSEN
S
SSPIF
Interrupt cleared
in software
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
TBRG TBRG
‘0’
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9.4.17.3 Bus Collision During a Stop
Condition
Bus collision oc curs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) Aft er the SCL pin is deasserted, SC L is sampled
low before SDA goes high.
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
floa t. Wh en t he p in i s sa mpled hig h (c loc k arbi tr atio n),
the Baud R ate Generator is load ed with SSPADD<6:0>
and cou nt s d own to 0. After the BRG times o ut, SDA i s
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a dat a ‘0’ (Figure 9-31). If the SCL pin i s sample d
low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 9-32).
FIGURE 9-31: BUS COLLISION DURING A STOP CONDITION (CASE 1)
FIGURE 9-32: BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
SDA asserted low
SDA sampled
low after TBRG,
set BCLIF
‘0’
‘0’
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
Assert SDA SCL goes low before SDA goes high,
set BCLIF
‘0’
‘0’
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NOTES:
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10.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial
Communications Interface or SCI.) The USART can be
configured as a full-duplex asynchronous system that
can communicate with peripheral devices, such as
CRT terminals and personal computers, or it can be
configured as a half-duplex synchronous system that
can co mmun icate with periph eral de vi ces, such as A/D
or D/A integrated circuits, serial EEPROMs, etc.
The USART can be configured in the following modes:
• Asynchronous (full-duplex)
• Synchronous – M aster (half-duplex)
• Synchronous – Slave (half-duplex)
Bit SPE N (R CSTA<7>) a nd bi ts TRISC< 7:6> have to be
set in order to configure pins RC6/TX/CK and RC7/RX/DT
as the Universal Synchronous Asynchronous Receiver
Transmitter.
The USART module also has a multi-processor
communic ation capability using 9-bit address detection.
REGISTER 10-1: TXST A: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN SYNC — BRGH TRMT TX9D
bit 7 bit 0
bit 7 CSRC: Clock Sourc e S ele ct bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable b it
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in Sync mode.
bit 4 SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 Unimplemented: Re ad as ‘0’
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode.
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: 9th bit of Transmit Data, can be Pa rity bit
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582C-page 112 2001-2013 Microchip Technology Inc.
REGISTER 10-2: RCSTA: RECEIVE ST ATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
bit 7 SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CR EN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bi t (RX9 = 1):
1 = Enables addres s detectio n, enables interrupt and load of the receiv e buff er when RSR<8 >
is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of Received Data (can be parity bit but must be calculated by user firmware)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2001-2013 Microchip Technology Inc. DS39582C-page 113
PIC16F87XA
10.1 USART Baud Rate Generator
(BRG)
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 10-1 shows the formula for computation of the
baud rate for dif f eren t US ART modes which on ly a ppl y
in Master mode (internal clock).
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculate d
using the formula in Table 10-1. From this, the error in
baud rate can be determined.
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
becaus e the FOSC/(16 (X + 1)) equation can reduce the
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
10.1.1 SAMPLING
The dat a on the RC7/RX/D T pin is sa mpled three time s
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
TABLE 10-1: BAUD RATE FORMULA
TABLE 10-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed)
0
1
(Asy nchronous) Baud Rate = FOSC/(64 (X + 1))
(Synchronous) Baud Rate = FOSC/(4 (X + 1)) Baud Rate = FOSC/(16 (X + 1))
N/A
Legend: X = v alue in SPBRG (0 to 255)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
PIC16F87XA
DS39582C-page 114 2001-2013 Microchip Technology Inc.
TABLE 10-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
BAUD
RATE
(K)
FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz
KBAUD %
ERROR
SPBRG
value
(decimal) KBAUD %
ERROR
SPBRG
value
(decimal) KBAUD %
ERROR
SPBRG
value
(decimal)
0.3------- --
1.2 1.221 1.75 255 1.202 0.17 207 1.202 0.17 129
2.4 2.404 0.17 129 2.404 0.17 103 2.404 0.17 64
9.6 9.766 1.73 31 9.615 0.16 25 9.766 1.73 15
19.2 19.531 1.72 15 19.231 0.16 12 19.531 1.72 7
28.8 31.250 8.51 9 27.778 3.55 8 31.250 8.51 4
33.6 34.722 3.34 8 35.714 6.29 6 31.250 6.99 4
57.6 62.500 8.51 4 62.500 8.51 3 52.083 9.58 2
HIGH 1.221 - 255 0.977 - 255 0.610 - 255
LOW 312.500 - 0 250.000 - 0 156.250 - 0
BAUD
RATE
(K)
FOSC = 4 MHz FOSC = 3.6864 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal) KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3 0.300 0 207 0.3 0 191
1.2 1.202 0.17 51 1.2 0 47
2.4 2.404 0.17 25 2.4 0 23
9.6 8.929 6.99 6 9.6 0 5
19.2 20.833 8.51 2 19.2 0 2
28.8 31.250 8.51 1 28.8 0 1
33.6 - - - - - -
57.6 62.500 8.51 0 57.6 0 0
HIGH 0.244 - 255 0.225 - 255
LOW 62.500 - 0 57.6 - 0
TABLE 10-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
BAUD
RATE
(K)
FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz
KBAUD %
ERROR
SPBRG
value
(decimal) KBAUD %
ERROR
SPBRG
value
(decimal) KBAUD %
ERROR
SPBRG
value
(decimal)
0.3---------
1.2---------
2.4 - - - - - - 2.441 1.71 255
9.6 9.615 0.16 129 9.615 0.16 103 9.615 0.16 64
19.2 19.231 0.16 64 19.231 0.16 51 19.531 1.72 31
28.8 29.070 0.94 42 29.412 2.13 33 28.409 1.36 21
33.6 33.784 0.55 36 33.333 0.79 29 32.895 2.10 18
57.6 59.524 3.34 20 58.824 2.13 16 56.818 1.36 10
HIGH 4.883 - 255 3.906 - 255 2.441 - 255
LOW 1250.000 - 0 1000.000 0 625.000 - 0
BAUD
RATE
(K)
FOSC = 4 MHz FOSC = 3.6864 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal) KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3------
1.2 1.202 0.17 207 1.2 0 191
2.4 2.404 0.17 103 2.4 0 95
9.6 9.615 0.16 25 9.6 0 23
19.2 19.231 0.16 12 19.2 0 11
28.8 27.798 3.55 8 28.8 0 7
33.6 35.714 6.29 6 32.9 2.04 6
57.6 62.500 8.51 3 57.6 0 3
HIGH 0.977 - 255 0.9 - 255
LOW 250.000 - 0 230.4 - 0
2001-2013 Microchip Technology Inc. DS39582C-page 115
PIC16F87XA
10.2 USART Asynchronous Mode
In this mode, the USART uses standard Non-Return-
to-Zero (NRZ) format (one Start bit, eight or nine data
bits and one Stop bit). The most comm on data format
is 8 bits. An on-chip, dedicated, 8-bit Baud Rate
Generator can be used to derive standard baud rate
frequencies from the oscillator. The USART transmits
and rece ives the LSb first. Th e transmitter a nd rece iver
are functionally independent but use the same data
format and baud rate. The baud rate generator
produces a clock, either x16 or x64 of the bit shift rate,
depending on bit BRGH (TXSTA<2>). Parity is not
supported by the hardware but can be implemented in
software (and stored as the ninth data bit).
Asynchronous mode is stopped during Sleep.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the
following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
10.2.1 USART ASYNCHRONOUS
TRANSMITTER
The USART transmitter block diagram is shown in
Figure 10-1. The heart of the tra nsmitter is the T ransmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer, TXREG.
The TXREG register is loaded with data in software.
The TSR register is not loaded until the Stop bit has
been transmitted from the previous load. As soon as
the Stop bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXR EG re giste r i s em pty and
flag bit, TXIF (PIR1<4>), is set. This interrupt can be
enabled/disabled by setting/clearing enable bit, TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enab le bi t TXI E and ca nno t be cl eare d in soft -
ware. It will re set only wh en ne w dat a is loa ded i nto th e
TXREG register . While flag bit TXIF indicates the st atus
of the TXREG register , another bit, TRMT (TXST A<1>),
shows the status of the TSR register. Status bit TRMT
is a read-only bit which is set when the TSR register is
empty. No interrupt logic is tied to this bit so the user
has to poll this bit in order to determine if the TSR
register is empty.
Transmission is enabled by setting enable bit, TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the Baud Rate Generator (BRG) has produced a
shift clock (Figure 10-2). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally, when transmission
is first started, the TSR register is empty. At that point,
transfer to the TXREG register will result in an immedi-
ate transfer to TSR, resulting in an empty TXREG. A
back-to-back transfer is thus possible (Figure 10-3).
Clearing enable bit TXEN during a transmission will
cause the tra nsm is s ion to be ab orte d and will rese t th e
transmitter. As a result, the RC6/TX/CK pin will revert
to high-impedance.
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG reg-
ister. This is because a data write to the TXREG regis-
ter can resu lt in an immediate tra nsfer of the dat a to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit may be loaded in the TSR
register.
FIGURE 10-1: USART TRANSMIT BLOCK DIAGRAM
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
2: Flag bit T XIF is set whe n enable bit TXEN
is set. TXIF is cle ared by loadi ng TXRE G.
TXIF
TXIE
Interrupt
TXEN Baud Rate CLK
SPBRG
Baud Rate Generator TX9D
MSb LSb
Data Bus
TXREG Register
TSR Register
(8) 0
TX9
TRMT SPEN
RC6/TX/CK pin
Pin Buffer
and Control
8
PIC16F87XA
DS39582C-page 116 2001-2013 Microchip Technology Inc.
When setting up an Asynchronous Transmission,
follow these steps:
1. Initiali ze th e SPBRG re giste r for the ap prop ria te
baud rate. If a high-speed baud rate is desired,
set bit BRGH (Section 10.1 “USART Baud
Rate Generator (BRG)”).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, then set enable bit TXIE.
4. If 9-bit transmission is desired, then set transmit
bit TX9.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts
transmission).
8. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
FIGURE 10-2: ASYNCHRONOUS MASTER TRANSMISSION
FIGURE 10-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
TABLE 10-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 B it 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unk nown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
Word 1 Stop Bit
Word 1
Transmit Shift Reg
Start Bit Bit 0 Bit 1 Bit 7/8
Write to TXREG Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
TXIF bit
(Transmit Buf fer
Reg. Empty Flag)
TRMT bit
(Transmit Shif t
Reg. Empty Flag)
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1 Word 2
Word 1 Word 2
Start Bit Stop Bit Start Bit
Transmit Shift Reg.
Word 1 Word 2
Bit 0 Bit 1 Bit 7/8 Bit 0
Note: This timing diagram shows two conse cutive transmissions.
2001-2013 Microchip Technology Inc. DS39582C-page 117
PIC16F87XA
10.2.2 USART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure 10-4.
The data is received on th e RC 7/RX/D T p in an d dri ve s
the data recovery block. The data recovery block is
actuall y a high-spee d shifter , operating at x16 times th e
baud rate; whereas the main receive serial shifter
operates at the bit rate or at F OSC.
Once Asynchronous mode is selected, reception is
enabled by setti ng bit CRE N (RCSTA<4>).
The heart of the receiver is the Receive (Serial) Shift
Register (RSR). After sampling the Stop bit, the
received data in the RSR is transferred to the RCREG
register (if it is empty). If the transfer is complete, flag
bit, R CIF (PIR1<5>), is se t. T he ac tual i nterr upt can be
enabled/disabled by setting/clearing enable bit, RCIE
(PIE1<5>). Flag bit RCIF is a read-only bit which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double-buffered register (i.e., it is a two-deep FIFO ). It
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to
begin shifting to the RSR register. On the detection of
the Stop bit of the third byte, if the RCREG register is
still full, the Overrun Error bit, OERR (RCSTA<1>), will
be set. The word in the RSR will be lost. The RCREG
register can be read twice to retrieve the two bytes in
the FIFO. Overrun bit OERR has to be cleared in soft-
ware. Th is is done by re setting the re ceive logi c (CREN
is cleared and then set). If bit OERR is set, transfers
from the RSR register to the RCREG register are inhib-
ited and no further dat a will be received. It is, therefor e,
essential to clear error bit OERR if it is set. Framing
error bit, FERR (RCSTA<2>), is set if a Stop bit is
detected as cle ar. Bit FER R and the 9th re cei ve bit a re
buffered the same way as the receive data. Reading
the RCREG will load bits RX9D and FERR with new
values , the refo r e, it is ess ent ial for the us er to re ad th e
RCSTA r egis ter bef ore reading the RCREG register in
order not to lose the old FERR and RX9D inform ation .
FIGURE 10-4: USA R T RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
RSR Register
MSb LSb
RX9D RCREG Register FIFO
Interrupt RCIF
RCIE Data Bus
8
64
16
or Stop Start
(8) 710
RX9
FOSC
PIC16F87XA
DS39582C-page 118 2001-2013 Microchip Technology Inc.
FIGURE 10-5: ASY NCHR ON OUS RECEPTION
When setting up an Asynchronous Reception, follow
these steps:
1. Initiali ze th e SPBRG re giste r for the ap prop ria te
baud rate. If a high-speed baud rate is desired,
set bit BRGH (Section 10.1 “USART Baud
Rate Generator (BRG)”).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, then set enable bit
RCIE.
4. If 9-bit reception is desired, then set bit RX9.
5. Enable the reception by setting bit CREN.
6. Flag b it RC IF will be set when rec ept ion is com -
plete an d an interru pt will be generate d if enabl e
bit RCIE is set.
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bi t CREN.
10. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TABLE 10-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Start
bit bit 7/8
bit 1bit 0 bit 7/ 8 bit 0Stop
bit
Start
bit Start
bit
bit 7/8 Stop
bit
RX (pin)
Reg
Rcv Buffer Reg
Rcv Shift
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG Word 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word,
causing the OERR (Overrun Error) bit to be set.
Add r e s s Nam e B it 7 Bit 6 Bit 5 Bit 4 Bi t 3 Bit 2 Bit 1 B i t 0 Valu e on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
1Ah R CREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
99h S PB RG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unk nown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
2001-2013 Microchip Technology Inc. DS39582C-page 119
PIC16F87XA
10.2.3 SETTING UP 9-BIT MODE WITH
ADDRES S DETE CT
When setting up an Asynchronous Reception with
address detect enabled:
• Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH.
• Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
• If interrupts are desired, then set enable bit RCIE.
• Set bit RX9 to enable 9-bit reception.
• Set ADDEN to enable address detect.
• Enable the reception by setting enable bit CREN.
• Flag bit RCIF will be set when reception is
complete, and an interrupt will be generated if
enable bit RCIE was set.
• Read the RCSTA register to get the ninth bit and
determine if any error occurred during reception.
• Read the 8-bit rece ived data by reading the
RCREG register to determine if the device is
being addressed.
• If any error occurred, clear the error by clearing
enable bi t CREN.
• If the device has been addressed, clear the
ADDEN bi t to al low da t a b yte s and address bytes
to be read into th e receiv e buf fer and interrup t the
CPU.
FIGURE 10-6: USA R T RECEIVE BLOCK DIAGRAM
x64 B aud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
RSR Register
MSb LSb
RX9D RCREG Register FIFO
Interrupt RCIF
RCIE Data Bus
8
64
16
or Stop Start(8) 7 1 0
RX9
RX9
ADDEN
RX9
ADDEN
RSR<8>
Enable
Load of
Receive
Buffer
8
8
FOSC
PIC16F87XA
DS39582C-page 120 2001-2013 Microchip Technology Inc.
FIGURE 10-7: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
FIGURE 10-8: ASY NCHR ON OUS RECEPT ION WITH ADDRESS BYTE FIRST
TABLE 10-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Start
bit bit 1bit 0 bit 8 bit 0Stop
bit
Start
bit bit 8 Stop
bit
RC7/RX/DT
Load RSR
Read
RCIF
Word 1
RCREG
Bit 8 = 0, Data Byte Bit 8 = 1, Address Byte
Note: This timing diagram shows a data byte followed by an address b yte. The data byte is not read into the RCREG (Receive Buffer)
because ADDEN = 1.
(pin)
Start
bit bit 1bit 0 bit 8 bit 0Stop
bit
Start
bit bit 8 Stop
bit
RC7/RX/DT
Load RSR
Read
RCIF
Word 1
RCREG
Bit 8 = 1, Address Byte Bit 8 = 0, Data Byte
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)
because ADDEN was not updated and still = 0.
(pin)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Valu e on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
99h SPB RG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unk nown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
2001-2013 Microchip Technology Inc. DS39582C-page 121
PIC16F87XA
10.3 USART Synchronous
Master Mode
In Sync hronous Ma ster mode, the data is trans mitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same tim e). When transmitting dat a,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit, SYNC (TXSTA<4>). In
additio n, enabl e bit, SPEN (RCSTA<7>), is set in ord er
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines, respectively. The
Master mode ind icates t hat the process or transmit s th e
master clock on the CK line. The Master mode is
entered by setting bit, CSRC (TXSTA<7>).
10.3.1 USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 10-6. The heart of the tra nsmitter is the T ransmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
softw are. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCYCLE), the TXREG is em pty an d int er-
rupt bit, TXIF (PIR1<4>), is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will re set o nly when ne w dat a i s loa ded i nto th e
TXREG register . While flag bit TXIF indicates the st atus
of the TXREG register , ano ther bit, TRMT (TXSTA<1>),
shows the status of the TSR register. TRMT is a read-
only bit which is set when the TSR is empty. No inter-
rupt log ic is tied to th is bi t so the us er has t o p oll t his bit
in order to determ ine if the TSR register is empty. The
TSR is not mapped in data memory so it is not available
to the user.
Transmission is enabled by setting enable bit, TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first dat a bit will be shif ted out on the next av ailable
rising edge of the clock on the CK line. Data out is
stab le around the fal ling edge of the sync hronous cloc k
(Figure 10-9). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Fi gure 10-10). This is a dvant age ous wh en slow
baud rates are selected since the BRG is kept in Reset
when bits TXEN, CREN and SREN are clear. Setting
enable bit TXEN will start the BRG, creating a shift
clock immediately. Normally, when transmission is first
started, the TSR register is empty so a transfer to the
TXREG register will result in an immediate transfer to
TSR, resulting in an empty TXREG. Back-to-back
transfers are possible.
Clearing enable bit TXEN during a transmission will
cause the tra nsm is s ion to be ab orte d and will rese t th e
transmitter. The DT and CK pins will revert to high-
impeda nce. If ei ther bit C REN or bi t SREN is set durin g
a transmis sion , the transm issi on is abor ted and the DT
pin reverts to a high-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic, however, is not
reset, although it is disconnected from the pins. In order
to reset the tran sm itte r, the user has to cle ar bi t TXEN.
If bit SR EN is set (t o interrupt an on-goin g trans mission
and rece ive a si ngle wo rd), then af ter the single w ord is
received, bit SREN will be cleared and the serial port
will re vert back to transmitting since bit TXEN is still set.
The DT line will immediately switch from High-
Impedan ce R eceiv e mod e to tran smit and st art d rivin g.
To avoid this, bit TXEN should be cleared.
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a da ta write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was writt en befo re writ ing the “new” T X9D,
the “present” value of bit TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initiali ze the SPBRG re gis ter for the ap prop ria te
baud rate (Section 10.1 “USART Baud Rate
Generator (BRG)”).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. S tart transmission by loading da ta to the TXREG
register.
8. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
PIC16F87XA
DS39582C-page 122 2001-2013 Microchip Technology Inc.
TABLE 10-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
FIGURE 10-9: SY NCHRO NOUS TRANSMISSION
FIGURE 10-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unk nown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission .
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
bit 0 bit 1 bit 7
Word 1
Q1Q2 Q3Q4 Q1Q2 Q3Q4Q1Q2Q3 Q4Q1Q2Q3 Q4Q1 Q2 Q3 Q4 Q3 Q4 Q1Q2 Q3Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3 Q4
bit 2 bit 0 bit 1 bit 7
RC7/RX/DT
RC6/TX/CK
Write to
TXREG reg
TXIF bit
(Interrupt Flag)
TXEN bit ‘1’ ‘1’
Word 2
TRMT bi t
Write Word 1 Write Word 2
Note: Sync Master mode; SPBRG = 0. Continuous transmission of two 8-bit words.
pin
pin
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXREG Reg
TXIF bit
TRMT bit
bit 0 bit 1 bit 2 bit 6 bit 7
TXEN b it
2001-2013 Microchip Technology Inc. DS39582C-page 123
PIC16F87XA
10.3.2 USART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either enable bit, SREN
(RCSTA<5>), or enable bit, CREN (RCSTA<4>). Data
is sam pled on the RC 7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the recep-
tion is c ontinuous until CREN is cleared. If bo th bits are
set, CREN takes precedence. Af ter clocking the last bit,
the r eceived data in the Receiv e Shift Regi ster (R SR)
is transferred to the RCREG register (if it is empty).
When the transfer is complete, in terrupt flag bit, RCIF
(PIR1<5>), is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit, RCIE
(PIE1<5>). Flag bit RCIF is a read-only bit which is
reset by the ha rdware . In thi s c as e, it i s r ese t whe n th e
RCREG register has been read and is empty. The
RCREG is a double-buffered register (i.e., it is a two-
deep FIFO). It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third by te to begi n shiftin g into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full, then Overrun Error bit, OERR
(RCSTA<1>), is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited so
it is essential to clear bit OERR if it is set. The ninth
receive bit is buffered the same way as the receive
data. Reading the RCREG register will load bit RX9D
with a new value, therefore, it is essential for the user
to read the RCSTA register before reading RCREG in
order not to lose the old RX9D information.
When setting up a Synchronou s Master Reception:
1. Initiali ze the SPBRG re gis ter for the ap prop ria te
baud rate (Section 10.1 “USART Baud Rate
Generator (BRG)”).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interru pt flag bit RCIF wil l be set when recep tion
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TABLE 10-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPB RG B aud Rate Generator Register 0000 0000 0000 0000
Legend: x = unk nown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
PIC16F87XA
DS39582C-page 124 2001-2013 Microchip Technology Inc.
FIGURE 10-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
10.4 USART Synchronous Slave Mode
Synchronous Slave mo de differs from the Master mod e
in the fact that the shift clock is supplied externally at
the RC6/TX/ CK pin (instead of bei ng supplied internally
in Master mode). This allows the device to transfer or
receive data while in Sleep mode. Slave mode is
entered by clearing bit, CSRC (TXS TA<7>).
10.4.1 USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes is identica l, except in the cas e of the Slee p mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
d) When the first word has been sh ifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from Sleep and if the global interrupt is
enabled , the p rog ram wil l bran ch to the in terrupt
vector (0004h).
When setting up a Synchronous Slave Transmission,
follow thes e steps:
1. Enabl e the synchro nous slav e serial p ort by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit tran sm ission is desired, then set bi t TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. S tart transmission by loading da ta to the TXREG
register.
8. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
CREN bit
RC7/RX/DT
RC6/TX/CK
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
Q3 Q4Q1Q2Q3 Q4Q1Q2 Q3Q4Q2 Q1 Q2Q3Q4Q1Q2 Q3Q4 Q1 Q2Q3Q4Q1 Q2Q3Q4 Q1 Q2Q3 Q4Q1Q2Q3 Q4 Q1Q2 Q3Q4
‘0’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘0’
Q1Q2Q3Q4
pin
pin
2001-2013 Microchip Technology Inc. DS39582C-page 125
PIC16F87XA
TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
10.4.2 USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep
mode. Bit SREN is a “don't care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP inst ruction , then a w ord m ay be rec eived durin g
Sleep. On completely receiv ing the word, the R SR reg-
ister will trans fer th e data to the RCREG reg ist er an d if
enable bit RCIE bit is set, the interrupt generated will
wake the chip from Sleep. If the global interrupt is
enabled , the pro gram w ill branc h to the interru pt vec tor
(0004h).
When setting up a Synchronous Slave Reception,
follow thes e steps:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
5. Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TABLE 10-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h T XRE G USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices, always maintain these bits clear.
PIC16F87XA
DS39582C-page 126 2001-2013 Microchip Technology Inc.
NOTES:
2001-2013 Microchip Technology Inc. DS39582C-page 127
PIC16F87XA
11.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog -to-Digital (A/D) Converter module has five
input s for the 28-pin devi ces and eight for the 40/4 4-pin
devices.
The conversion of an analog input signal results in a
corresponding 10-bit digital number. The A/D module
has high and low-voltage reference input that is soft-
ware se lectable to some com bination of V DD, VSS, RA2
or RA3.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D clock must be derived from
the A/D’s internal RC oscillator.
The A/D module has four registers. These registers are:
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
The ADCON0 register, shown in Register 11-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 11-2, configures the func-
tions of the port pins. The port pins can be configured
as analog inputs (RA3 can also be the voltage
reference) or as digital I/O.
Addition al information on usi ng the A/D module can b e
found in the PIC® Mid-Range MCU Family Reference
Manual (DS33023).
REGISTER 11-1: ADCON0 REGISTER (ADDRES S 1Fh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON
bit 7 bit 0
bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits (ADCON0 bits in bold)
bit 5-3 CHS2:CHS0: Analog Channel Select bits
000 = Channel 0 (AN0)
001 = Channel 1 (AN1)
010 = Channel 2 (AN2)
011 = Channel 3 (AN3)
100 = Channel 4 (AN4)
101 = Channel 5 (AN5)
110 = Channel 6 (AN6)
111 = Channel 7 (AN7)
Note: The PIC16F873A/876A devices only implement A/D channels 0 through 4; the
unimplemented selections are reserved. Do not select any unimplemented
channels with these devices.
bit 2 GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress (setting this bit starts the A/D conversion which is automatically
cleared by hardware when the A/D conv ersion is complete)
0 = A/D conversion not in progress
bit 1 Unimplemented: Read as ‘0’
bit 0 ADON: A/D On bit
1 = A/D converter module is powered up
0 = A/D converter module is shut-off and consumes no operating current
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
ADCON1
<ADCS2> ADCON0
<ADCS1:ADCS0> Clock Conversion
000 FOSC/2
001 FOSC/8
010 FOSC/32
011 FRC (clock derived from the internal A/D RC oscillator)
100 FOSC/4
101 FOSC/16
110 FOSC/64
111 FRC (clock derived from the internal A/D RC oscillator)
PIC16F87XA
DS39582C-page 128 2001-2013 Microchip Technology Inc.
REGISTER 11-2: ADCON1 REGISTER (ADDRES S 9Fh)
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM ADCS2 —— PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ‘0’.
0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ‘0’.
bit 6 ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in shaded area and in bold)
bit 5-4 Unimplemented: Read as ‘0’
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: On any device Reset, the port pins that are multiplexed with analog functions (ANx)
are forced to be an analog input.
ADCON1
<ADCS2> ADCON0
<ADCS1:ADCS0> Clock Co nve rsion
000 FOSC/2
001 FOSC/8
010 FOSC/32
011 FRC (clock derived from the internal A/D RC oscillator)
100 FOSC/4
101 FOSC/16
110 FOSC/64
111 FRC (clock derived from the internal A/D RC oscillator)
A = Analog input D = Digital I/O
C/R = # of analog input channels/# of A/D voltage references
PCFG
<3:0> AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VREF+VREF-C/R
0000 AAAA A A AAV
DD VSS 8/0
0001 AAAAVREF+A A AAN3VSS 7/1
0010 DDDA A A AAVDD VSS 5/0
0011 DDDAV
REF+A A AAN3VSS 4/1
0100 DDDD A D AAVDD VSS 3/0
0101 DDDDVREF+D A AAN3VSS 2/1
011x DDDD D D DD — —0/0
1000 AAAAV
REF+VREF-A A AN3AN26/2
1001 DDAA A A AAV
DD VSS 6/0
1010 DDAAV
REF+A A AAN3VSS 5/1
1011 DDAAVREF+VREF-A A AN3AN24/2
1100 DDDAV
REF+VREF-A A AN3AN23/2
1101 DDDDV
REF+VREF-A A AN3AN22/2
1110 DDDD D D DAV
DD VSS 1/0
1111 DDDDV
REF+VREF-D A AN3AN21/2
2001-2013 Microchip Technology Inc. DS39582C-page 129
PIC16F87XA
The ADRESH:ADRESL registers contain the 10-bit
result of the A/D conversion. When the A/D conversion
is complete, the result is loaded into this A/D Result
register pair, the GO/DONE bit (ADCON0<2>) is cleared
and the A/D interrupt flag bit ADIF is set. The block
diagram of the A/D module is sh own in Figure 11-1.
After the A/D module has been configured as desired,
the sele cted channel m ust be a cq uired before the co n-
version is started. The analog input channels must
have the ir corres pondin g TRIS bi ts selected a s inputs.
To determine sample time, see Section 11.1 “A/D
Acquisition Requirements”. After this acquisition
time has elapsed, the A/D conversion can be started.
To do an A/D Conversi on, follow these s teps:
1. Configure the A/D module:
• Configure analog pins/voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D con ve rsi on clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set PEIE bit
• Set GIE bit
3. Wait the required acquisition time.
4. Start conversion:
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete by either:
• Polling for the GO/DONE bit to be cleared
(interrupts disabled); OR
• Waiting for the A/D interrupt
6. Read A/D Result register pair
(ADRESH:ADRESL), clear bit ADIF if required.
7. For the next conversion, go to step 1 or step 2
as required. The A/D conversion time per bit is
defined as TAD.
FIGURE 11-1: A/D BLOCK DIAGRAM
(Input Voltage)
VAIN
VREF+
(Reference
Voltage)
VDD
PCFG3:PCFG0
CHS2:CHS0
RE2/AN7(1)
RE1/AN6(1)
RE0/AN5(1)
RA5/AN4
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
111
110
101
100
011
010
001
000
A/D
Converter
Note 1: Not available on 28-pin devices.
VREF-
(Reference
Voltage) VSS
PCFG3:PCFG0
PIC16F87XA
DS39582C-page 130 2001-2013 Microchip Technology Inc.
11.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog i nput model is shown in Figure 1 1-2. The source
impedance (RS) and the internal sampling switch
impedance (RSS) directly affect the time required to
charge the capacitor CHOLD. The sampling switch
(RSS) impedan ce vari es over the device vol tag e (VDD);
see Figure 11-2. The maximum recommended
impedance for analog sources is 2.5 k. As the
impedance is decreased, the acquisition time may be
decreased. After the analog input channel is selected
(changed), this acquisition must be done before the
convers io n can be st a rted.
To calculate the minimum acquisition time,
Equation 11-1 may be used. This equation assumes
that 1/2 LS b error is used (1024 st eps for the A/D). The
1/2 LSb er ror is the ma ximu m error allow ed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the PIC® Mid-Range MCU Family Reference Manual
(DS33023).
EQUATION 11-1: ACQUISITION TIME
FIGURE 11-2: ANALOG INPUT MODEL
TACQ
TC
TACQ
=
=
=
=
=
=
=
=
Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
TAMP + TC + TCOFF
2 s + TC + [(Temperature – 25°C)(0.05 s/°C)]
CHOLD (RIC + RSS + RS) In(1/2047)
- 120 pF (1 k + 7 k + 10 k) In(0.0004885)
16.47 s
2 s + 16.47 s + [(50°C – 25C)(0.05 s/C)
19.72 s
Note 1: The reference voltage (VREF) has no effect on the equation since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after eac h conv ersion.
3: The maximum recommended impedance for analog sources is 2.5 k. This is required to meet the pin
leakage specification.
CPIN
VA
RSANx
5 pF
VDD
VT = 0.6V
VT = 0.6V ILEAKAGE
RIC 1K
Sampling
Switch
SS RSS
CHOLD
= DAC Capacitance
VSS
6V
Sampling Switch
5V
4V
3V
2V
567891011
(k)
VDD
= 120 pF
± 500 nA
Legend: CPIN
VT
ILEAKAGE
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
2001-2013 Microchip Technology Inc. DS39582C-page 131
PIC16F87XA
11.2 Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D con versio n requires a mi nimum 12 TAD per 10-bit
conversion. The source of the A/D conversion clock is
software selected. The seven possible options for TAD
are:
•2 T
OSC
•4 TOSC
•8 TOSC
•16 TOSC
•32 TOSC
•64 TOSC
• Internal A/D module RC osc il lat or (2-6 s)
For correct A/D conversions, the A/D conversion clock
(TAD) m us t be se lect ed to ens ure a minim um TAD time
of 1.6 s.
Table 11-1 shows the resultant TAD time s deri ved fr om
the device operating frequencies and the A/D clock
sour ce se lec ted .
11.3 Configuring Analog Port Pins
The ADCON1 and TRI S register s contro l the opera tio n
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding TRIS bits
set (input) . If the TRIS bit is cleare d (output), the digit al
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
TABLE 1 1-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (ST ANDARD DEVICES (F))
Note 1: When reading the port register, any pin
configured as an analog input channel w ill
read as cleared (a low level). Pins config-
ured as digital inputs will convert an analog
input. Analog levels on a digitally config-
ured input will not affect the conversion
accuracy.
2: Analog le vels on any pin that is defined a s
a digital input (including the AN7:AN0
pins) may cause the input buffer to con-
sume current that is out of the device
specifications.
AD Clock Source (TAD)Maximum Device Frequency
Operation ADCS2:ADCS1:ADCS0
2 TOSC 000 1.25 MHz
4 TOSC 100 2.5 MHz
8 TOSC 001 5 MHz
16 TOSC 101 10 MHz
32 TOSC 010 20 MHz
64 TOSC 110 20 MHz
RC(1, 2, 3) x11 (Note 1)
Note 1: The R C sourc e has a typical TAD time of 4 s but can vary between 2-6 s.
2: When the device frequencies are greater than 1 MHz, the RC A/D conv ersion clock source is only
recommended for Sleep operation.
3: For extended voltage devices (LF), please refer to Section 17.0 “Electrical Characteristics”.
PIC16F87XA
DS39582C-page 132 2001-2013 Microchip Technology Inc.
11.4 A/D Conversions
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL regi sters). After the A/D con version
is aborte d, the nex t acquis ition on th e select ed channe l
is automa tically st arted. The GO/DONE bit can the n be
set to start the conversion.
In Figure 11-3, after the GO bit is set, the first time
segment has a minimum of T CY and a maximum of T AD.
FIGURE 11-3: A/D CONVERSION TAD CYCLES
11.4.1 A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D resu lt is loaded at the completion
of the A/D co nversion. Thi s register p air is 16 bit s wide.
The A/D mo dule gives the flexi bility to lef t or right justif y
the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification.
Figure 11-4 shows the operation of the A/D result
justification. The extra bits are loaded with ‘0’s. W he n
an A/D result will not overwrite these locations (A/D dis-
able), these registers may be used as two general
purpose 8-bit registers.
FIGURE 11-4: A/D RESULT JUSTIFICATION
Note: The GO/DONE bit should NOT be set in
the sam e inst ruction th at turns on the A/D.
TAD1TAD2TAD3TAD4 TAD5TAD6
T
AD
7T
AD
8
TAD9
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
b9 b8 b7 b6 b5 b4 b3 b2
TAD10 TAD11
b1 b0
TCY to TAD
Conversion starts
ADRES is loaded
GO bit is cleare d
ADIF bit is set
Holding capacitor is connected to analog input
10-bit Result
ADRESH ADRESL
0000 00
ADFM = 0
0
2 1 0 77
10-bit Result
ADRESH ADRESL
10-bit Result
0000 00
70 7 6 5 0
ADFM = 1
Right Justified Left Justified
2001-2013 Microchip Technology Inc. DS39582C-page 133
PIC16F87XA
11.5 A/D Operation During Sleep
The A/D module can operate during Sleep mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed which eliminates all digital
switchi ng noise fro m the conv ersion. Whe n the conver-
sion i s comple ted, the GO /DONE bit will be cleared and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
Sleep. If the A/D interrupt is no t e nab led , th e A/ D mo d-
ule will then be turned off, although the ADON bit will
remain set.
When the A/D clock sour ce is anoth er clock optio n (not
RC), a SLEEP instructi on will cause the present conver-
sion t o be aborte d and the A/D mod ule to be turned of f,
though the ADON bit will remain set.
Turning of f the A/D plac es the A/D m odu le in it s lowes t
current consumption state.
11.6 Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
convers ion is aborte d. All A/D inp ut pins are configure d
as analog inputs.
The value that is in the ADRESH:ADRESL registers is
not modified for a Power-on Reset. The
ADRESH:ADRESL registers w ill cont ain unkno wn data
after a Power-on Reset.
TABLE 11-2: REGISTERS/BITS ASSOCIATED WITH A/D
Note: For the A/D module to operate in Sleep,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To allow the con-
version to occur during Sleep, ensure the
SLEEP instruction immediately follows the
instruction that se ts the GO/DONE bit.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Value on
MCLR, WDT
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON0000 00-0 0000 00-0
9Fh ADCON1 ADFM ADCS2 —— PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000
85h TRISA —— PORT A Data Direction Register --11 1111 --11 1111
05h PORTA —— PORTA Data Latch when written: POR TA pins when read --0x 0000 --0u 0000
89h(1) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111
09h(1) PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
Legend: x = unk nown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These registers are not available on 28-pin devices.
PIC16F87XA
DS39582C-page 134 2001-2013 Microchip Technology Inc.
NOTES:
2001-2013 Microchip Technology Inc. DS39582C-page 135
PIC16F87XA
12.0 COMPARATOR MODULE
The com pa rato r modul e con tain s tw o anal og comp a ra-
tors. The inputs to the comparators are multiplexed
with I/O port pins RA0 through RA3, while the outputs
are mul tiplexed to pin s RA4 and R A5. The on -chip vo lt-
age reference (Section 13.0 “Comparator Voltage
Reference Module”) can also be an input to the
comparators.
The CMC ON regist er (Registe r 12-1) controls the com -
parator input and output multiplexers. A block diagram
of the various comparator configurations is shown in
Figure 12-1.
REGISTER 12-1: CMCON REGISTER
R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1
C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0
bit 7 bit 0
bit 7 C2OUT: Com parator 2 Output bit
When C2INV = 0:
1 = C2 VIN+ > C2 VIN-
0 = C2 VIN+ < C2 VIN-
When C2INV = 1:
1 = C2 VIN+ < C2 VIN-
0 = C2 VIN+ > C2 VIN-
bit 6 C1OUT: Com parator 1 Output bit
When C1INV = 0:
1 = C1 VIN+ > C1 VIN-
0 = C1 VIN+ < C1 VIN-
When C1INV = 1:
1 = C1 VIN+ < C1 VIN-
0 = C1 VIN+ > C1 VIN-
bit 5 C2INV: Comparator 2 O utput Invers ion bit
1 = C2 output inverted
0 = C2 output not inverted
bit 4 C1INV: Comparator 1 O utput Invers ion bit
1 = C1 output inverted
0 = C1 output not inverted
bit 3 CIS: Compar ator Input Sw itch bit
When CM2:CM0 = 110:
1 =C1 VIN- connects to RA3/AN 3
C2 VIN- connects to RA2/AN2
0 =C1 V
IN- connects to RA0/AN0
C2 VIN- connects to RA1/AN1
bit 2 CM2:CM0: Comparator Mode bits
Figure 12-1 shows the Comparator modes and CM2:CM0 bit settings.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582C-page 136 2001-2013 Microchip Technology Inc.
12.1 Comparator Configuration
There are eight modes of operation for the compara-
tors. The CMCON register is used to select these
modes. Figure 12-1 shows the eight possible modes.
The TRISA register controls the data direction of the
comparator pins for each mode. If the Comparator
mode is cha nged, the comparator output leve l may not
be valid for the specified mode change delay shown in
Section 17.0 “Electrical Characteristics”.
FIGURE 12-1: COMPARATOR I/O OPERATING MODES
Note: Compara tor in terr upts sh ould be disab led
during a Comparator mode change.
Otherwise, a false interrupt may occur.
C1
RA0/AN0 VIN-
VIN+
RA3/AN3 Off (Read as ‘0’)
Comparators Reset
A
A
CM2:CM0 = 000
C2
RA1/AN1 VIN-
VIN+
RA2/AN2 Off (Read as ‘0’)
A
A
C1
RA0/AN0 VIN-
VIN+
RA3/AN3 C1OUT
Two Independent Comparators
A
A
CM2:CM0 = 010
C2
RA1/AN1 VIN-
VIN+
RA2/AN2 C2OUT
A
A
C1
RA0/AN0 VIN-
VIN+
RA3/AN3 C1OUT
Two Common Reference Comparators
A
A
CM2:CM0 = 100
C2
RA1/AN1 VIN-
VIN+
RA2/AN2 C2OUT
A
D
C2
RA1/AN1 VIN-
VIN+
RA2/AN2 Off (Read as ‘0’)
One Independent Comparator with Output
D
D
CM2:CM0 = 001
C1
RA0/AN0 VIN-
VIN+
RA3/AN3 C1OUT
A
A
C1
RA0/AN0 VIN-
VIN+
RA3/AN3 Off (Read as ‘0’)
Comparators Off (POR Default Value)
D
D
CM2:CM0 = 111
C2
RA1/AN1 VIN-
VIN+
RA2/AN2 Off (Read as ‘0’)
D
D
C1
RA0/AN0 VIN-
VIN+
RA3/AN3 C1OUT
Four Inputs Multiplexed to Two Comparators
A
A
CM2:CM0 = 110
C2
RA1/AN1 VIN-
VIN+
RA2/AN2 C2OUT
A
A
From Comparator
CIS = 0
CIS = 1
CIS = 0
CIS = 1
C1
RA0/AN0 VIN-
VIN+
RA3/AN3 C1OUT
Two Common Reference Comparators with Outputs
A
A
CM2:CM0 = 101
C2
RA1/AN1 VIN-
VIN+
RA2/AN2 C2OUT
A
D
A = Analog Input, port reads zeros always. D = Digital Input. CIS (CMCON<3>) is the Comparator Input Switch.
CVREF
C1
RA0/AN0 VIN-
VIN+
RA3/AN3 C1OUT
Two Independent Comparators with Outputs
A
A
CM2:CM0 = 011
C2
RA1/AN1 VIN-
VIN+
RA2/AN2 C2OUT
A
A
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RA4/T0CKI/C1OUT
VREF Module
2001-2013 Microchip Technology Inc. DS39582C-page 137
PIC16F87XA
12.2 Comparator Operation
A singl e com pa rator i s sho wn i n Fig ure 12-2 al ong wi th
the relationship between the analog input levels and
the digit al ou tput. When the an alog input a t VIN+ is less
than the analog input VIN-, the o utput of the co mparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 12-2 represent
the uncertainty due to input offsets and response time.
12.3 Comparator Reference
An external or internal reference signal may be used
depending on the comparator operating mode. The
analog signal present at VIN- is compar ed to the si gna l
at VIN+ and the digital output of the comparator is
adjusted accordingly ( Figure 12-2).
FIGURE 12-2: SINGLE COMP ARATOR
12.3.1 EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be c onfigured to have the com-
parators operate from the same or different reference
sour ces. How ever , th resho ld detecto r applica tions ma y
require th e s am e re fere nc e. Th e re fere nc e s ignal m us t
be between VSS and VDD and can be applied to either
pin of the comparator(s).
12.3.2 INTERNAL REFERENCE SIGNAL
The compar ator module also allows the selection of an
internally generated voltage reference for the compara-
tors. Section 13.0 “Comparator Voltage Reference
Module” contains a det ailed description of the Comp ar-
ator V olt age Reference module that provides this s ignal.
The internal reference sign al is used whe n com p arators
are in mode, CM<2:0> = 110 (Figure 12-1). In this
mode, the internal voltage reference is applied to the
VIN+ pin of both comparators.
12.4 Comparator Response Time
Response time is the minimum time, after selecting a
new re ference volt ag e or i nput s ource, before the c om-
parato r output has a valid lev el. If the internal referenc e
is changed, the maximum delay of the internal voltage
reference must be co nside red when using the comp ar-
ator outputs. Otherwise, the maximum delay of the
comp arators shoul d be used (Section 17.0 “Electrical
Characteristics”).
12.5 Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
output s may al so be dire ctly output to the RA4 and RA5
I/O pins . When enab led, multipl exors in th e output p ath
of the RA4 and RA5 pins will switch and the output of
each pin will be the unsy nc hro niz ed output of the com-
parator. The uncertainty of each of the comparators is
related t o the input of fset voltage and the resp onse time
given in the specifications. Figure 12-3 shows the
comp ara tor outp ut blo ck diagra m.
The TRISA bits will still function as an output enable/
disable for the RA4 and RA5 pins while in this mode.
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON<4:5 >).
–
+
VIN+
VIN-Output
VIN–
VIN+
Output
Output
VIN+
VIN-
Note 1: When reading the Port register, all pins
configu red a s anal og inp uts will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
2: Analog l evels o n any p in defin ed as a dig-
ital input may cause the input buffer to
consume more current than is specified.
3: RA4 is an open collector I/O pin. When
used as an output, a pull-up resistor is
required.
PIC16F87XA
DS39582C-page 138 2001-2013 Microchip Technology Inc.
FIGURE 12-3: COMPARATOR OUTPUT BLOCK DIAGRAM
12.6 Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
stat us of the output b its, as rea d from CMCON<7:6> , to
determine the actual change that occurred. The CMIF
bit (PIR re gisters) is the Compara tor Interrupt Fl ag. The
CMIF bit must be reset by clearing it (‘0’). Since it is
also possible to write a ‘ 1’ to this register, a simulated
interrupt may be initiated.
The CMIE bit (PIE reg isters) and the PEIE bit (INTC ON
register ) must be set to enable the in terrupt. In addition,
the GIE bit must also be set. If any of these bits are
clear, the interrupt is not enabled, though the CMIF bit
will still be set if an interrupt condition occurs.
The user , in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON will end the
mismatch condition.
b) Clear flag bit CMIF.
A mismatc h co ndi tio n will co nti nue to set fla g bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
DQ
EN
To RA4 or
RA5 Pin
Bus
Data
Read CMCON
Set
MULTIPLEX
CMIF
bit
-+
DQ
EN
CL
Port Pins
Read CMCON
Reset
From
Other
Comparator
CxINV
Note: If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR
registers) interrupt flag may not get set.
2001-2013 Microchip Technology Inc. DS39582C-page 139
PIC16F87XA
12.7 Comparator Operation During
Sleep
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional if enabled. This interrupt will
wake-up the device from Sleep mode when enabled.
While the comparator is powered up, higher Sleep
currents than shown in the power-down current
specification will occur. Each operational comparator
will consume additional current as shown in the com-
parat or specifi cations. To minimize powe r consum ption
while in Sleep mode, turn off the comparators,
CM<2:0> = 111, before entering Sleep. If the device
wakes up from Sleep, the contents of the CMCON
register are not affected.
12.8 Effects of a Reset
A device Reset forces the CMCON register to its Reset
state, causing the comparator module to be in the
Comparator Off mode, CM<2:0> = 111. This ensures
compatibility to the PIC16F87X devices.
12.9 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 12-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. Th e analog input, th erefore, must be betw een
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 k is rec-
ommended for the analog sources. Any external com-
ponent connected to an analog input pin, such as a
capacitor or a Zener diode, should have very little
leakage current.
FIGURE 12-4: ANALOG INPUT MODEL
VA
RS < 10K
AIN CPIN
5 pF
VDD
VT = 0.6 V
VT = 0.6 V
RIC
ILEAKAGE
±500 nA
VSS
Legend: CPIN = Input Capacitance
VT= Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS= Source Impedance
VA = Analog Voltage
PIC16F87XA
DS39582C-page 140 2001-2013 Microchip Technology Inc.
TABLE 12-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR
Value on
all other
Resets
9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 0000 0111
9Dh CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000
0Bh, 8Bh,
10Bh,18Bh INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INTIE RBIE TMR0IF INTIF RBIF 0000 000x 0000 000u
0Dh PIR2 —CMIF— — BCLIF LVDIF TMR3IF CCP2IF -0-- 0000 -0-- 0000
8Dh PIE2 —CMIE— — BCLIE LVDIE TMR3IE CCP2IE -0-- 0000 -0-- 0000
05h PORTA —— RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
85h TRISA —— PORTA Data Direction Register --11 1111 --11 1111
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
2001-2013 Microchip Technology Inc. DS39582C-page 141
PIC16F87XA
13.0 COMPARATOR VO LTAGE
REFERENC E MODULE
The Comparator Voltage Reference Generator is a
16-tap resistor ladder network that provides a fixed
voltage reference when the comparators are in mode
‘110’. A programmable register controls the function of
the reference generator. Register 13-1 lists the bit
functions of the CVRCON register.
As shown in Figure 13-1, the resistor ladder is seg-
mented to provide tw o ranges of C VREF values and has
a power-down function to conserve power when the
reference is not bein g used. The comp arat or refer ence
supply voltage (also referred to as CVRSRC) comes
directly from VDD. It should be noted, h owever, that th e
voltage at the top of the ladder is CVRSRC – VSAT,
where VSAT is the saturation voltage of the power
switch transistor. This reference will only be as
accurate as the values of CVRSRC and VSAT.
The output of the reference generator may be con-
nected to the RA2/AN2/VREF-/CVREF pi n. This can be
used as a simple D/A function by the user if a very high-
impedance load is used. The primary purpose of this
function is to provide a test path for testing the
reference generator function.
REGISTER 13-1: CVRCON CONTROL REGISTER (ADDRESS 9Dh)
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0
bit 7 bit 0
bit 7 CVREN: Comparator Voltage Reference Enable bit
1 =CV
REF c i rcuit powered on
0 =CV
REF c i rcuit powered do wn
bit 6 CVROE: Comparator VREF Output Enable bit
1 =CVREF voltage level is output on RA2/AN2/VREF-/CVREF pin
0 =CV
REF voltage level is disconnected from RA2/AN2/VREF-/CVREF pin
bit 5 CVRR: Comparator VREF Range Selection bit
1 = 0 to 0.75 CVRSRC, with CVRSRC/24 step size
0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size
bit 4 Unimplemented: Read as ‘0’
bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits 0 VR3:VR0 15
When CVRR = 1:
CVREF = (VR<3:0>/ 24) (CVRSRC)
When CVRR = 0:
CVREF = 1/4 (CVRSRC) + (VR3:VR0/ 32) (CVRSRC)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F87XA
DS39582C-page 142 2001-2013 Microchip Technology Inc.
FIGURE 13-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
TABLE 13-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
CVRR
8R
CVR3
CVR0
16:1 Analog MUX
8R RRRR
CVREN
CVREF
16 Stages
Input to
Comparator
CVROE
RA2/AN2/VREF-/CVREF
VDD
CVR2
CVR1
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR
Value on
all other
Resets
9Dh CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000
9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 0000 0111
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’.
Shaded cells are not used with the comparator voltage reference.
2001-2013 Microchip Technology Inc. DS39582C-page 143
PIC16F87XA
14.0 SPECIAL FEATURES OF THE
CPU
All PIC16F87XA devices have a host of features
intended to maxim ize system reliability, minimize cost
through elimination of external components, provide
power saving operating modes and offer code
protection. These are:
• Oscillator Selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Sleep
• Code Protection
• ID Locations
• In-Circuit Serial Programming
• Low-Voltage In-Circuit Serial Programming
• In-Circuit Debugger
PIC16F87XA devices have a Watchdog Timer which
can be shut-off only through configuration bits. It runs
off its own RC oscillator for added reliability.
There are two timers that offer necessary delays on
power-up. One is the Oscillator Start-up Timer (OST),
intende d to keep the chip in Reset until the crystal oscil-
lator is stable. The other is the Power-up Timer
(PWRT), which provides a fixed delay of 72 ms (nomi-
nal) on pow er-up on ly. It is designed to keep th e par t in
Reset while the power su pply stabili zes. With these two
timers on-chip, most applications need no external
Reset circuitry.
Sleep mode is designed to offer a very low current
power-down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer wake-up or
through an interrupt.
Several oscillator options are also made available to
allow the part to fit the application. The RC oscillator
option saves system cost while the LP crystal option
saves power. A set of configuration bits is used to
select various options.
Additional information on special features is available
in the PIC® Mid-Range MCU Family Reference Manual
(DS33023).
14.1 Configurati on Bits
The configura tion b it s c an be program med (read as ‘0’),
or left unprogrammed (read as ‘1’) to select various
device configurations. The erased or unprogrammed
value of the Configuration Word register is 3FFFh.
These bits are mapped in program memory location
2007h.
It is impo rtant to n ote that addre ss 2007h is be yond the
user program memory space which can be accessed
only during programming.
PIC16F87XA
DS39582C-page 144 2001-2013 Microchip Technology Inc.
REGISTER 14-1: CONFIGURATION WORD (ADDRESS 2007h)(1)
R/P-1 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1
CP — DEBUG WRT1 WRT0 CPD LVP BOREN ——PWRTENWDTEN FOSC1FOSC0
bit 13 bit0
bit 13 CP: Flash Program Memory Code Protection bit
1 = Code protection off
0 = All program memory code-protected
bit 12 Unimplemented: Read as ‘1’
bit 11 DEBUG: In-Circuit Debugger Mode bit
1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins
0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger
bit 10-9 WRT1:WRT0 Flash Program Memory Write Enable bits
For PIC16F876A/877A:
11 = Write protection off; all program memory may be written to by EECON control
10 = 0000h to 00FFh write-protected; 0100h to 1FFFh may be written to by EECON control
01 = 0000h to 07FFh write-protected; 0800h to 1FFFh may be written to by EECON control
00 = 0000h to 0FFFh write-protected; 1000h to 1FFFh may be written to by EECON control
For PIC16F873A/874A:
11 = Write protection off; all program memory may be written to by EECON control
10 = 0000h to 00FFh write-protected; 0100h to 0FFFh may be written to by EECON control
01 = 0000h to 03FFh write-protected; 0400h to 0FFFh may be written to by EECON control
00 = 0000h to 07FFh write-protected; 0800h to 0FFFh may be written to by EECON control
bit 8 CPD: Data EEPROM Memory Code Protection bit
1 = Data EEPROM code protection off
0 = Data EEPROM code-protected
bit 7 LVP: Low-Voltage (Single-Supply) In-Circuit Serial Programming Enable bit
1 = RB3/PGM pin has PGM function; low-voltage programming enabled
0 = RB3 is digital I/O, HV on MCLR must be used for programming
bit 6 BOREN: Brown-out Reset Enable bit
1 = BOR enabled
0 = BOR disabled
bit 5-4 Unimplemented: Read as ‘1’
bit 3 PWRTEN: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 2 WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0 FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS os cillator
01 = XT oscillator
00 = LP oscillator
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Note 1: The erased (unprogrammed) value of the Configuration Word is 3FFFh.
2001-2013 Microchip Technology Inc. DS39582C-page 145
PIC16F87XA
14.2 Oscillator Configurations
14.2.1 OSCILLATOR TYPES
The PIC16F87XA can be operated in four different
oscill ator mod es. The u ser can p rogram two c onf igura-
tion bit s (FOSC1 and FOSC0) to s ele ct one of these four
modes:
• LP Low-Power Crystal
• XT Crystal/Resonator
• HS High-Speed Crys t al / Res ona tor
• RC Resistor/Capacitor
14.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKI and OSC2/CLKO pins
to est ablis h oscil lation (Figure 14-1). The PIC1 6F87XA
oscill ato r design requires the use of a p a ral lel cut cry s-
ta l. Use of a series c ut crys tal ma y give a frequency out
of the crystal manufacturer’s specifications. When in
XT, LP or HS modes, the device can have an external
clock so urce t o dr ive th e OSC1/ CLKI pin (Figure 14-2).
FIGURE 14-1: CRY STAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
FIGURE 14-2: EXTERNAL CLOCK INPUT
OPERATION ( HS, XT OR
LP OSC CONF IGURA TION )
TABLE 14-1: CERAMIC RESONATORS
Note 1: See Table 14-1 and Table 14-2 for recommended
values of C1 and C2.
2: A series resistor (Rs) may be required for AT
strip cut crystals.
3: RF varies with the crystal chosen.
C1(1)
C2(1)
XTAL
OSC2
OSC1
RF(3)
Sleep
To
Logic
PIC16F87XA
Rs(2)
Internal
Ranges Tested:
Mode Freq. OSC1 OSC2
XT 455 kHz
2.0 MHz
4.0 MHz
68-100 pF
15-68 pF
15-68 pF
68-100 pF
15-68 pF
15-68 pF
HS 8.0 MHz
16.0 MHz 10-68 pF
10-22 pF 10-68 pF
10-22 pF
These v alues are for design gu idance o nly.
See notes following Table 14-2.
Reson ators U sed :
2.0 MHz Murata Erie CSA2.00MG 0.5%
4.0 MHz Murata Erie CSA4.00MG 0.5%
8.0 MHz Murata Erie CSA 8.00 MT 0.5%
16.0 MHz Murata Erie CSA16.00MX 0.5%
All resonators used di d not have built-in capacitors.
OSC1
OSC2
Open
Clock from
Ext. Sy stem PIC16F87XA
PIC16F87XA
DS39582C-page 146 2001-2013 Microchip Technology Inc.
TABLE 14-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR 14.2.3 RC OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additiona l cos t sav in gs . The RC osc il lat or
frequency is a function of the supply voltage, the
resistor (REXT) and capacitor (CEXT) values and the
operating temperature. In a ddi tio n to thi s, the oscillator
frequency will vary from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C
components used. Figure 14-3 shows how the R/C
combination is connected to the PIC16F87XA.
FIGURE 14-3: RC OSCILLATOR MODE
Osc Type Crystal
Freq. Cap. Range
C1 Cap. Range
C2
LP 32 kHz 33 pF 33 pF
200 kHz 15 pF 15 pF
XT 200 kHz 47-68 pF 47-68 pF
1 MHz 15 pF 15 pF
4 MHz 15 pF 15 pF
HS 4 MHz 15 pF 15 pF
8 MHz 15-33 pF 15-33 pF
20 M Hz 15-33 pF 15-33 pF
These value s are for desi gn guidance only.
See notes following this table.
Crystals Used
32 kHz Epson C-001R32.768K-A ± 20 PPM
200 kHz STD XTL 200.000KHz ± 20 PPM
1 MHz ECS ECS-10-13-1 ± 50 PPM
4 MHz ECS ECS-40-20-1 ± 50 PPM
8 MHz EPSON CA-301 8.000M-C ± 30 PPM
20 MHz EPSON CA-301 20.000M-C ± 30 PPM
Note 1: Higher capac itance increases the stability
of oscillator but als o increases the st art-up
time.
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
3: Rs may be required in HS mode, as well
as XT mode, to av oid ov erdrivi ng crys tal s
with low drive level specification.
4: When migr ating from other PIC® devi ces ,
oscillator performance should be verified.
OSC2/CLKO
CEXT
REXT
PIC16F87XA
OSC1
FOSC/4
Internal
Clock
VDD
VSS
Recommended values: 3 k REXT 100 k
CEXT > 20 pF
2001-2013 Microchip Technology Inc. DS39582C-page 147
PIC16F87XA
14.3 Reset
The PIC16F87XA differentiates between various kinds
of Reset:
• Pow er-on Rese t (POR)
•MCLR
Reset during normal operation
•MCLR
Reset duri ng Sleep
• WDT Reset (during normal operation)
• WDT Wake-up (during Sleep)
• Brown-out Reset (BOR)
Some regi sters a re not af fected in any Rese t condi tion.
Their st atus is unknow n on POR and uncha nged in any
other Reset. Most other registers are reset to a “Reset
state” on Power-on Reset (POR), on the MCLR and
WDT Rese t, on MCL R Rese t du ring Sleep and Brown-
out Reset (BOR). They are not affected by a WDT
wake-up which is viewed as the resumption of normal
operatio n. The T O and PD bits are set or cleared differ-
ently in different Reset situations as indicated in
Table 14-4. These bits are used in software to deter-
mine t he n at ure of th e Res et. Se e Tabl e 1 4-6 for a fu ll
description of Reset states of all registers.
A simp lified block di agram o f the on- chip Re set cir cuit
is sh own in Figure 14-4.
FIGURE 14-4: SI MPLI FI ED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
RQ
External
Reset
MCLR
VDD
OSC1
WDT
Module
VDD Rise
Detect
OST/PWRT
On-chip
RC OSC
WDT
Time-out
Power- on Rese t
OST
10-bit Ripple Counter
PWRT
Chip_Reset
10-bit Ripple Counter
Reset
Enable OST
Enable PWRT
Sleep
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
Brown-out
Reset BODEN
(1)
PIC16F87XA
DS39582C-page 148 2001-2013 Microchip Technology Inc.
14.4 MCLR
PIC16F87XA devices have a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
differs from previous devices of this family. Voltages
applied to the pin that exceed its specification can
result in both Resets and current consumption outside
of device specification during the Reset event. For this
reason, Microchip recommends that the MCLR pin no
longer be tied directly to VDD. The use of an RCR
network, as shown in Fig ure 14-5, is sugg ested.
FIGURE 14-5: REC OM MENDE D MCLR
CIRCUIT
14.5 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the rang e of 1.2V -1.7V). To take
advantage of the POR, tie the MCLR pin to VDD
through an RC network, as described in Section 14.4
“MCLR”. A maximum rise time for VDD is specified.
See Section 17.0 “Electrical Characteristics” for
details.
When the device starts normal operation (exits the
Reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating condi-
tions are met. Brown-out Reset may be used to meet
the st art-up conditio ns. For add itional i nformation , refer
to application note, AN607, “Power-up Trouble
Shooting” (DS00607).
14.6 Power-up Ti me r (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only from the POR. The Power-
up Timer operates on an internal RC oscillator. The
chip is kept in Reset as long as the PWRT is active. The
PWR T’ s time dela y allo ws VDD to rise to an a ccept abl e
level. A configuration bit is provided to enable or
disable the PWRT.
The pow er-up time de lay will v ary from chi p to chip due
to VDD, temperature and process variation. See
Section 17.0 “Electrical Characteristics” for details
(TPWRT, parameter #33).
14.7 Oscillator Start-up Timer (OST)
The Oscill ator S tart-up Time r (OST) provides a de lay of
1024 oscillator cycles (from OSC1 input) after the
PWR T delay is over (if PWR T is enabled) . This helps to
ensure that the crystal oscillator or resonator has
started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
Sleep.
14.8 Brown-out Reset (BOR)
The configuration bit, BODEN, can enable or disable
the Brown-out Reset circuit. If VDD falls below VBOR
(parameter D005, about 4V) for longer than TBOR
(param eter #35, abo ut 100 S), the brown-ou t situation
will reset the device. If VDD falls below VBOR for less
than TBOR, a Reset may not occur.
Once the brown-out occurs, the device will remain in
Brown-out Reset until VDD rises above VBOR. The
Power-up Timer then keeps the device in Reset for
TPWRT (parameter #33, about 72 mS). If VDD should
fall below VBOR during TPWRT, the Brown-out Reset
process will restart when VDD rises above VBOR with
the Power-up Timer Reset. The Power-up Timer is
always enabled when the Brown-out Reset circuit is
enabled, regardless of the state of the PWRT
configu r ati on bit.
14.9 Time- out Sequence
On power-up, the time-out sequence is as follows: the
PWRT delay starts (if enabled) when a POR Reset
occurs. Then, OST starts counting 1024 oscillator
cycles when PWRT ends (LP, XT, HS). When the OST
ends, the device comes out of Reset.
If MCLR is kept low long enough, the time-outs will
expire. Bringing MCLR high will begin execution
immediately. This is useful for testing purposes or to
synchronize more than one PIC16F87XA device
operating in parallel.
Table 14-5 shows the Reset conditions for the Status,
PCON and PC registers, while Table 14-6 shows the
Reset conditions for all the registers.
C1
R1(1)
VDD
MCLR
PIC16F87XA
R2(2)
Note 1: R1 < 40 k is recommended to make
sure that the voltage drop across R does
not violate the device’s electrical
specification.
2: R2 > than 1K will limit any current
flowing into MCLR from the external
capacitor C, in the event of MCLR/VPP
breakdown due to Electrostatic
Discharge (ESD) or Elect rical
Overstress (EOS).
2001-2013 Microchip Technology Inc. DS39582C-page 149
PIC16F87XA
14.10 Power Control/Status Register
(PCON)
The Power Control/Status Register, PCON, has up to
two bit s dep end ing upon the dev ic e.
Bit 0 is the Brown-out Reset Status bit, BOR. The BOR
bit is unknow n on a Power-on R eset. It must then be set
by the user and checked on subse quent Resets to see if
it has been cleared, indicating that a BOR has occurred.
When the Brown-out R eset is disabled, the state of the
BOR bit is unpredictable and is, therefore, not valid at
any time.
Bit 1 is the Power-on Reset Status bit, POR. It is
cleared on a Power-on Reset and unaffected other-
wise. The user must set this bit following a Power-on
Reset.
TABLE 14-3: TIME-OUT IN VARIOUS SITUATIONS
TABLE 14-4: STATUS BITS AND THEIR SIGNIFICANCE
TABLE 14-5: RESET CONDITIONS FOR SPECIAL REGISTERS
Oscillator Co nfigu ration Power-up Brown-out Wake-up from
Sleep
PWRTE = 0PWRTE = 1
XT, HS, LP 72 ms + 1024 TOSC 1024 TOSC 72 ms + 1024 TOSC 1024 TOSC
RC 72 ms — 72 ms —
POR BOR TO PD Condition
0x11Power-on Reset
0x0xIllegal, TO is set on POR
0xx0Illegal, PD is set on POR
1011Brown-out Rese t
1101WDT Reset
1100WDT Wake-up
11uuMCLR Reset during normal operation
1110MCLR Reset during Sleep or Interrupt Wake-up from Sleep
Legend: x = don’t care, u = unchanged
Condition Program
Counter Status
Register PCON
Register
Power-on Reset 000h 0001 1xxx ---- --0x
MCLR Reset during normal operation 000h 000u uuuu ---- --uu
MCLR Reset during Sleep 000h 0001 0uuu ---- --uu
WDT Reset 000h 0000 1uuu ---- --uu
WDT Wake- up PC + 1 uuu0 0uuu ---- --uu
Brown-out Reset 000h 0001 1uuu ---- --u0
Interrupt Wa ke-up from Sleep PC + 1(1) uuu1 0uuu ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
PIC16F87XA
DS39582C-page 150 2001-2013 Microchip Technology Inc.
TABLE 14-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Devices Power-on Rese t,
Brown-out Reset MCLR Resets,
WDT Reset Wake-up via WDT or
Interrupt
W 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
INDF 73A 74A 76A 77A N/A N/A N/A
TMR0 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
PCL 73A 74A 76A 77A 0000 0000 0000 0000 PC + 1(2)
STATUS 73A 74A 76A 77A 0001 1xxx 000q quuu(3) uuuq quuu(3)
FSR 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 73A 74A 76A 77A --0x 0000 --0u 0000 --uu uuuu
PORTB 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
PORTD 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
PORTE 73A 74A 76A 77A ---- -xxx ---- -uuu ---- -uuu
PCLATH 73A 74A 76A 77A ---0 0000 ---0 0000 ---u uuuu
INTCON 73A 74A 76A 77A 0000 000x 0000 000u uuuu uuuu(1)
PIR1 73A 74A 76A 77A r000 0000 r000 0000 ruuu uuuu(1)
73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu(1)
PIR2 73A 74A 76A 77A -0-0 0--0 -0-0 0--0 -u-u u--u(1)
TMR1L 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 73A 74A 76A 77A --00 0000 --uu uuuu --uu uuuu
TMR2 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu
T2CON 73A 74A 76A 77A -000 0000 -000 0000 -uuu uuuu
SSPBUF 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
SSPCON 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu
CCPR1L 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1H 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 73A 74A 76A 77A --00 0000 --00 0000 --uu uuuu
RCSTA 73A 74A 76A 77A 0000 000x 0000 000x uuuu uuuu
TXREG 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu
RCREG 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu
CCPR2L 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2H 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu
ADRESH 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 73A 74A 76A 77A 0000 00-0 0000 00-0 uuuu uu-u
OPTION_REG 73A 74A 76A 77A 1111 1111 1111 1111 uuuu uuuu
TRISA 73A 74A 76A 77A --11 1111 --11 1111 --uu uuuu
TRISB 73A 74A 76A 77A 1111 1111 1111 1111 uuuu uuuu
TRISC 73A 74A 76A 77A 1111 1111 1111 1111 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition,
r = reserved, maintain clear. Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 14-5 for Reset value for specific condition.
2001-2013 Microchip Technology Inc. DS39582C-page 151
PIC16F87XA
FIGURE 14-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA RC NETWORK)
TRISD 73A 74A 76A 77A 1111 1111 1111 1111 uuuu uuuu
TRISE 73A 74A 76A 77A 0000 -111 0000 -111 uuuu -uuu
PIE1 73A 74A 76A 77A r000 0000 r000 0000 ruuu uuuu
73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu
PIE2 73A 74A 76A 77A -0-0 0--0 -0-0 0--0 -u-u u--u
PCON 73A 74A 76A 77A ---- --qq ---- --uu ---- --uu
SSPCON2 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu
PR2 73A 74A 76A 77A 1111 1111 1111 1111 1111 1111
SSPADD 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 73A 74A 76A 77A --00 0000 --00 0000 --uu uuuu
TXSTA 73A 74A 76A 77A 0000 -010 0000 -010 uuuu -uuu
SPBRG 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu
CMCON 73A 974 76A 77A 0000 0111 0000 0111 uuuu uuuu
CVRCON 73A 74A 76A 77A 000- 0000 000- 0000 uuu- uuuu
ADRESL 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
ADCON1 73A 74A 76A 77A 00-- 0000 00-- 0000 uu-- uuuu
EEDATA 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
EEADR 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
EEDATH 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
EEADRH 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
EECON1 73A 74A 76A 77A x--- x000 u--- u000 u--- uuuu
EECON2 73A 74A 76A 77A ---- ---- ---- ---- ---- ----
TABLE 14-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Devices Power-on Reset,
Brown-out Reset MCLR Resets,
WDT Reset Wake-up via WDT or
Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition,
r = reserved, maintain clear. Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 14-5 for Reset value for specific condition.
TPWRT
TOST
VDD
MCLR
Interna l POR
PWRT Time-out
OST Time-out
Internal Reset
PIC16F87XA
DS39582C-page 152 2001-2013 Microchip Technology Inc.
FIGURE 14-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 14-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 14-9: SLOW RISE TIME (MCLR TIED TO VDD VIA RC NETWORK)
TPWRT
TOST
VDD
MCLR
Interna l POR
PWRT Time-out
OST Time-out
Internal Reset
VDD
MCLR
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
TPWRT
TOST
VDD
MCLR
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
0V 1V
5V
TPWRT
TOST
2001-2013 Microchip Technology Inc. DS39582C-page 153
PIC16F87XA
14.11 Interrupts
The PIC16F87XA family has up to 15 sources of
interrupt. The Interrupt Control register (INTCON)
records individual interrupt requests in flag bits. It also
has individual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled and an
inter rupt’s flag bit and mask bit are s et, the int errupt will
vector immediately. Individual interrupts can be
disabled through their corresponding enable bits in
various registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on Reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enable s inte rrup t s.
The RB0/INT pin interrupt, the RB port change interru pt
and the TMR 0 over flo w interru pt f lag s are co nt a ine d in
the INTCON register.
The peripheral interrupt flags are contained in the
Special Function Registers, PIR1 and PIR2. The
corresponding interrupt enable bits are contained in
Special Function Registers, PIE1 and PIE2, and the
peripheral interrupt enable bit is contained in Special
Function Register, INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pu sh ed onto the st ack and the PC is lo ade d
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the i nterr upt flag bits. T he inte rrupt flag bi t(s) mu st be
cleared in software before re-enabling interrupts to
avoid recursive inte rrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the s ame for one or tw o-cy cle in struct ion s. Indi vidua l
interrupt flag bits are set regardless of the st atus of their
corresponding mask bit, PEIE bit or GIE bit.
FIGURE 14-10: INTERRUP T LOGIC
Note: Indiv idual in terrupt flag bit s are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
PSPIF(1)
PSPIE(1)
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
TMR0IF
TMR0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake-up (If in Sleep mode)
Interrupt to CPU
CCP2IE
CCP2IF
BCLIE
BCLIF
EEIF
EEIE
CCP1IF
CCP1IE
CMIE
CMIF
Note 1: PSP interrupt is implemented only on PIC16F874A/877A devices.
PIC16F87XA
DS39582C-page 154 2001-2013 Microchip Technology Inc.
14.11.1 INT INTERRUPT
External interrupt on the RB0/INT p in is edg e triggere d,
either ris ing if bit INTEDG (OPTION_REG<6> ) is set or
falling if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit, INTF
(INTCON<1 >), i s s et. T his in terru pt c an b e d isa bl ed b y
clear ing en abl e bi t, I NTE (IN TCON <4 >). Fla g bi t IN TF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT
interrupt can wake-up the processor from Sleep if bit
INTE was set prior to going into Sleep. The status of
global in terrupt enable bit, GIE, decides whe ther or not
the proces sor branches to the inter rupt vector foll owing
wake-up. See Section 14.14 “Power-down Mode
(Sleep)” for detail s on Sleep mode.
14.11.2 TMR0 INTERRUPT
An overflow (FFh 00h) in the TMR0 register will set
flag bit, TMR0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON<5>). See Section 5.0 “Timer0
Module”.
14.11.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<4>). See
Section 4.2 “PORTB and the TRISB Register”.
14.12 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. T y pically, users m ay wish to s ave key re g-
isters during an interrupt (i.e., W register and Status
register). This w il l hav e to be i mp lemented in softwar e.
For the PIC16F873A/874A devices, the register
W_TEMP must be defined in both Banks 0 and 1 and
must be de fine d at the same of fs et from the bank b ase
address (i.e., If W_TEMP is defined at 0x20 in Bank 0,
it must a lso be def ined at 0xA 0 in Bank 1). T he regis-
ters, PCLATH_TEMP and STATUS_TEMP, are only
defined in Bank 0.
Since the upper 16 bytes of each bank ar e common in
the PIC16F876A/877A devices, temporary holding reg-
isters, W_TEMP, STATU S_TEMP and PCLATH_TEMP,
should be placed in here. These 16 locations don’t
require banking and therefore, make it easier for con-
text save and restore. The same code shown in
Example 14-1 can be used.
EXAMPLE 14-1: SAVING STATUS, W AND PCLATH REGISTERS IN RAM
MOVWF W_TEMP ;Copy W to TEMP register
SWAPF STATUS,W ;Swap status to be saved into W
CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3
MOVWF PCLATH_TEMP ;Save PCLATH into W
CLRF PCLATH ;Page zero, regardless of current page
:
:(ISR) ;(Insert user code here)
:
MOVF PCLATH_TEMP, W ;Restore PCLATH
MOVWF PCLATH ;Move W into PCLATH
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W
2001-2013 Microchip Technology Inc. DS39582C-page 155
PIC16F87XA
14.13 Wat chdog Timer (WDT)
The Watchdog Timer is a free running, on-chip RC
oscillator which does not require any external
components. This RC oscillator is separate from the
RC oscillator of the OSC1/CLKI pin. That means that
the WDT will run even if the clock on the OSC1/CLKI
and OSC 2/C LKO pins o f th e devi ce has been s toppe d,
for example, by execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device Reset (Watchdog Timer Reset). If the device is
in Sleep mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the Status register
will be cleared upon a Watchdog Timer time-out.
The WDT can be permanently disabled by clearing
configuration bit, WDTE (Section 14.1 “Configuration
Bits”).
WDT time-out period values may be found in
Section 17.0 “Electrical Characteristics” under
param ete r #31 . Values for the WD T p resc al er (ac tua ll y
a posts caler but shared with the T imer0 pres caler) may
be assigned using the OPTION_REG register.
FIGURE 14-11: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 14-7: SUMMARY OF WATCHDOG TIMER REGISTERS
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and the postscaler, if
assigned to the WDT and prevent it from
timing out and gen erat ing a devic e Res et
condition.
2: When a CLRWDT instruction is executed
and the pre scaler is assi gned to the WDT,
the prescaler count will be cleared but the
presc al er ass ig nme nt is not changed.
From TMR0 Clock Source
(Figure 5-1)
To TMR0 (Figure 5-1)
Postscaler
WDT Timer
WDT
Enable Bit
0
1M
U
X
PSA
8-to-1 MUX PS2:PS0
01
MUX PSA
WDT
Time-out
8
Note: P SA and PS2:PS0 are bits in the OPTION_RE G register.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2007h Config. bits (1) BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0
81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
Legend: Shaded cells are not used by the Watchdog T i mer .
Note 1: See Register 14-1 for operation of these bits.
PIC16F87XA
DS39582C-page 156 2001-2013 Microchip Technology Inc.
14.14 Power-down Mode (Sleep)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (Status<3>) is cleared, the
TO (Status<4>) bit is set and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low o r high-imped ance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external
circuitry is drawing current from the I/O pin, power-
down the A/D and disable external clocks. Pull all I/O
pins that are high-impedance inputs, high or low
externally, to avoid switching currents caused by
floating inputs. The T0CKI input should also be at VDD
or VSS for lowest current consumption. The
contribution from on-chip pull-ups on PORTB should
also be considered.
The MCLR pin must be at a logic high level (VIHMC).
14.14.1 WAKE-UP FROM SLEEP
The devi ce can wa ke-up from Sleep through on e of the
following events:
1. External Reset input on MCLR pin.
2. Watchd og Timer wake-up (if WDT was enable d).
3. Interrupt from INT pin, RB port change or
peripheral interrupt.
External MCLR Reset will cause a device Reset. All other
even ts are considered a continuation of program execu-
tion and cause a “wake-up”. The TO and PD bits in the
Status register can be used to determine the cause of
device Reset. The PD bit, which is set on power-up, is
cleared when Sleep is invoked. The TO bit is clear ed if a
WDT time-out occurred and caused wake-up.
The follo wing periph eral interrupt s can wake the device
from Sleep:
1. PSP read or write (PIC16F874/877 only).
2. TMR1 i nterrupt. T imer1 must be operating a s an
asynchronous counter.
3. CCP Capture mode interrupt.
4. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
5. SSP (Start/Stop) bit detect interrupt.
6. SSP transmit or receive in Slav e mode (SPI/I2C).
7. USART RX or TX (Synchronous Slave mode).
8. A/D conv ersion (when A/D clock source is RC).
9. EEPROM write operation completion.
10. Comparator output changes state.
Other peripherals cannot generate interrupts since
during Sleep, no on-chip clocks are present.
When the SLEEP instruction is being e xecuted, the next
instruction (PC + 1) is prefetched. For the device to
wake-up thro ugh an int errup t eve nt, the co rres pon din g
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
ins tructi on after t he SLEEP instruction. If the GIE bit is
set (enabled), the device e x ecutes the instr uction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
14.14.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and inte rrupt fla g bit s et, one of the fo llow ing wil l occu r:
• If the interrupt occurs before the ex ecution of a
SLEEP instruction, the SLEEP instruction will
comple te as a NOP. Therefore, the WDT an d WDT
pos tsc aler w ill not be cleared, the TO bit will not
be set and PD bits will not be cle are d.
• If the interrupt occurs during or after the
execution of a SLEEP ins truc tio n, the dev ic e wi ll
immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postsc aler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT
instruction should be executed before a SLEEP
instruction.
2001-2013 Microchip Technology Inc. DS39582C-page 157
PIC16F87XA
FIGURE 14-12: WAKE-UP FROM SLEEP THROUGH INTERRUPT
14.15 In-Circuit Debugger
When the DEBUG bit in the configuration word is pro-
gram med to a ‘ 0’, the in-c ircuit debugge r functional ity is
enabled. This function allows simple debugging
functions when used with MPLAB® ICD. When the
microcontroller has this feature enabled, some of the
resourc es ar e not ava ilable for genera l use. Table 14-8
shows which features are consumed by the
background debugger.
TABLE 14-8: DEBUGGER RESOURCES
To use the in-c ircuit de bugger func tion of the microco n-
troller, the design m ust i mplemen t In-Circ uit Seri al Pro-
gramming connections to MCLR /VPP, VDD, GND, RB 7
and RB6. This will interface to the in-circuit debugger
module available from Microchip or one of the third
party development tool companies.
14.16 Program Verification/Code
Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
14.17 ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations, where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during program/verify. It is
recommended that only the 4 Least Significant bits of
the ID location are used.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKO(4)
INT pin
INT F Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
PC PC+1 PC+2
Inst(PC) = Sleep
Inst(PC - 1)
Inst(PC + 1)
Sleep
Processor in
Sleep
Interrupt Latency(2)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2 0004h 0005h
Dummy cycle
TOST(2)
PC+2
Note 1: XT, HS or LP Oscillator mode assumed.
2: TOST = 1024 TOSC (drawing not to scale). This delay will not be there for RC Oscillator mode.
3: GIE = 1 assumed. In this case, after wake- up, the processor jumps to the interrupt routine.
If GIE = 0, execution will continue in-line.
4: CLKO is not available in these oscillator modes but shown here for timing reference.
I/O pins RB6, RB7
Stack 1 level
Program Memory Address 0000h must be NOP
Last 100h word s
Data Memory 0x070 (0x0F0, 0x170, 0x1F0)
0x1EB-0x1EF
PIC16F87XA
DS39582C-page 158 2001-2013 Microchip Technology Inc.
14.18 In-Circuit Serial Programming
PIC16F87XA microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with tw o lines for cl ock and dat a and thre e
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
When usin g IC SP, the part mu st be supp li ed at 4. 5V to
5.5V if a bulk erase will be executed. This includes
reprogramming of the code-protect, both from an on
stat e to an off stat e. For all other cases of ICSP, the p art
may be programmed at the normal operating voltages.
This me ans c alibration value s, u niq ue u se r IDs o r us er
code can be reprogrammed or added.
For complete details of serial programming, please
refer to the “PIC16F87XA Flas h Memory Programmin g
Specification” (DS39589).
14.19 Low-Voltage (Single-Supply)
ICSP Programming
The LVP bit of the configuration word enables low-
voltage ICSP programming. This mode allows the
microcontroller to be programmed via ICSP using a
VDD source in the operating voltage range. This only
means that VPP does not have to be brought to VIHH but
can instead be left at the normal operating voltage. In
this mode, the RB3/PGM pin is dedicated to the pro-
grammi ng functio n and cease s to be a gene ral purpose
I/O pin. During programming, VDD is applied to the
MCLR pin. To enter Programming mode, VDD must be
applied to the RB3/PGM provided the LVP bit is set.
The LVP bit defaults to on (‘1’) from the factory.
If Low-V olt age Programming mode is not used, the L VP
bit can be programmed to a ‘0’ an d RB3/PGM becomes
a digital I/O pin. Ho wev er, the LVP bit may only b e pro-
grammed when programming is entered with VIHH on
MCLR. The LVP bit can only be charged when using
high voltage on MCLR.
It should be noted, tha t once the L VP bit is programmed
to ‘0’, only the High-Voltage Programming mode is
available and only High-Voltage Programming mode
can be used to program the device.
When using lo w-voltage IC SP, the part mus t be supplied
at 4.5V to 5.5V if a bulk erase will be executed. This
includes reprogramming of the code-protect bit s from an
on state to an of f state. For all other cases of low-volt age
ICSP, the part may be programmed at the normal oper-
ating voltage. This means calibration values, unique
user IDs or user code can be reprogrammed or adde d.
Note 1: The High-Voltage Programming mode is
always available, regardless of the state
of the LVP bit, by applying VIHH to the
MCLR pin.
2: While in Low-Voltage ICSP mode, the
RB3 pin can no longer be used as a
general purpose I/O pin.
3: When using Low-Voltage ICSP Program-
ming (LVP) and the pull-ups on PORTB
are enabled, bit 3 in the TRISB register
must be cleared to disable the pull-up on
RB3 and ensure the proper operation of
the device.
4: RB3 should not be allowed to floa t if LVP
is enabled. An external pull-down device
should be used to default the device to
normal operating mode. If RB3 floats
high, the PIC16F87XA device will enter
Programming mode.
5: LVP mode is enabled by default on all
device s shi pped from Microchi p. It can b e
disabled by clearing the LVP bit in the
CONFIG register.
6: Disabling LVP will provide maximum
compatibility to other PIC16CXXX
devices.
2001-2013 Microchip Technology Inc. DS39582C-page 159
PIC16F87XA
15.0 INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is
comprised of three basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
Each PIC16 instruction is a 14-bit word divided into an
opcode which specifies the instruction type and one or
more operands whic h further specify the operation of
the instruction. The formats for each of the categories
is presented in Figure 15-1, while the various opcode
fields are sum m ariz ed in Table 15-1.
Table 15-2 lists the instructions recognized by the
MPASM™ Assembler. A complete description of each
instruction is also a vailable in the PIC® Mid-Range M CU
Family Reference Manual (D S33023).
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The desti nation designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W regis ter . If ‘d’ is one, the res ult is place d
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator which selects the bit affected by the opera-
tion, w hi le ‘f’ represents the a ddre ss of the file in whic h
the bit is located.
For literal and control operations, ‘k’ represents an
eight or eleven-bit constant or literal value
One instr uction cycle co nsists of four os cillator periods ;
for an oscillator frequency o f 4 MHz, t his gives a normal
instruction execution time of 1 s. All instructions are
executed within a single instruction cycle, unless a
conditional test is true, or the program counter is
change d as a result of an instruction. When this occurs,
the execution takes two instruction cycles with the
second cycle executed as a NOP.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
15.1 READ-MODIFY-WRITE
OPERATIONS
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
For example, a “CLRF PORTB” instruction will read
PORTB, clear all the data bits, then write the result
back to PORTB. This example would have the unin-
tended resu lt that the condition that sets the RBIF flag
would be cleared.
TABLE 15-1: OPCODE FIELD
DESCRIPTIONS
FIGURE 15-1: GENERAL FORMAT FOR
INSTRUCTIONS
Note: To maintain upward compatibility with
future PIC16F87XA products, do not use
the OPTION and TRIS instructions.
Field Description
fRegister file address (0x00 to 0x7F)
WWorking register (accumulator)
bBit address within an 8-bit file register
kLiteral field, constant da ta or label
xDon't care loc ati on (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
dDestination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
PC Program Counter
TO Time-out bit
PD Power-down bit
Byte-oriented file regi s ter opera tions
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriente d file register operations
13 10 9 7 6 0
OPCODE b (B IT # ) f (FIL E #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (litera l )
k = 8-bit immediate value
13 11 10 0
OPCODE k (litera l )
k = 11-bit immediate value
General
CALL and GOTO instructions only
PIC16F87XA
DS39582C-page 160 2001-2013 Microchip Technology Inc.
TABLE 15-2: PIC16F87XA INSTRUCTION SET
Mnemonic,
Operands Description Cycles 14-Bit Opcode Status
Affected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERAT IONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add Literal and W
AND Literal with W
Call Subroutine
Clear Watchdog Timer
Go to Address
Inclusiv e OR Litera l wi th W
Mov e L i te ra l to W
Return from Interrupt
Return with Literal in W
Return from Subroutine
Go into Standby mode
Subtract W from Literal
Exclusive OR Literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1) , the prescaler will be cleared if
assigned to the Timer0 module.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Addit ional informati on on the mid-range in struction set is available in the PIC® M id-Range MCU Family Ref-
erence Manual (DS33023).
2001-2013 Microchip Technology Inc. DS39582C-page 161
PIC16F87XA
15.2 Instructi on Descriptions
ADDLW Add Literal and W
Syntax: [ label ] ADDLW k
Operands: 0 k 255
Operation: (W) + k (W)
Status Affected: C, DC, Z
Description: The contents of the W register
are added to the eight-bit literal ‘k’
and the result is placed in the W
register.
ADDWF Add W and f
Synta x: [ label ] ADDWF f,d
Operands: 0 f 127
d
Operation: (W) + (f) (destination)
Status Affected: C, DC, Z
Desc ription: Add the con tents of the W re gister
with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W registe r . I f
‘d’ is ‘1’, the result is stored back
in register ‘f’.
ANDLW AND Literal with W
Syntax: [ label ] ANDLW k
Operands: 0 k 255
Operation: (W) .AND. (k) (W)
Status Affected: Z
Description: The contents of W regi ster are
AND’ed with the eight-bi t literal
‘k’. The result is placed in the W
register.
ANDWF AND W with f
Syntax: [ label ] ANDWF f,d
Operands: 0 f 127
d
Operation: (W) .AND. (f) (destination)
Status Affected: Z
Description: AND the W register with register
‘f’. If ‘d’ is ‘0’, the result is stored in
the W register. If ‘d’ is ‘1’, the
result is sto r ed bac k in regi ste r ‘f’.
BCF Bit Clear f
Syntax: [ label ] BCF f,b
Operands: 0 f 127
0 b 7
Operation: 0 (f<b>)
Status Af fe cted: None
Description: Bit ‘b’ in register ‘f’ is cleared.
BSF Bit Set f
Syntax: [ label ] BSF f,b
Operands: 0 f 127
0 b 7
Operation: 1 (f<b>)
Status Af fe cted: None
Description: Bit ‘b’ in register ‘f’ is set.
BTFSS Bit Test f, Skip if Set
Syntax: [ label ] BTFSS f,b
Operands: 0 f 127
0 b < 7
Operation: skip if (f<b>) = 1
Status Af fe cted: None
Descr iption: If bit ‘b’ in register ‘f’ is ‘0’, the next
instructi on is ex ecuted.
If bit ‘b’ is ‘1’, then the next instruc-
tion is discarded and a NOP is
executed instead, making this a
2T
CY instruction.
BTFSC Bit Test, Skip if Clear
Syntax: [ label ] BTFSC f,b
Operands: 0 f 127
0 b 7
Operation: skip if (f<b>) = 0
Status Af fe cted: None
Descr iption: If bit ‘b’ in register ‘f’ is ‘1’, t he ne xt
instruction is executed.
If bit ‘b’ in reg ister ‘f’ is ‘0’, the next
instr uct ion is discarded and a NOP
is exec uted ins tea d, m ak ing thi s a
2T
CY instruction.
PIC16F87XA
DS39582C-page 162 2001-2013 Microchip Technology Inc.
CALL Call Subroutine
Syntax: [ label ] CALL k
Operands: 0 k 204 7
Operation: (PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
Status Affected: None
Description: Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven-bit
immediate address is loaded into
PC bits <10:0>. The upper bits of
the PC are loa ded from PCLATH.
CALL is a two-cycle instruction.
CLRF Clear f
Syntax: [ label ] CLRF f
Operands: 0 f 127
Operation: 00h (f)
1 Z
Status Affected: Z
Desc ript ion : The contents of register ‘f’ are
cleared and the Z bit is set.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h (W)
1 Z
Status Affected: Z
Description: W register is clea red. Zero bit (Z)
is set.
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h WDT
0 WDT prescaler,
1 TO
1 PD
Status Af fe cted: TO, PD
Description: CLRWDT instruction resets the
W atchdog T imer . It also resets the
prescaler of the WDT. Status b it s ,
TO and PD, are set.
COMF Complement f
Syntax: [ label ] COMF f,d
Operands: 0 f 127
d [0,1 ]
Operation: (f) (destination)
Status Af fe cted: Z
Description: The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’,
the result is stored back in
register ‘f’.
DECF Decrement f
Syntax: [ label ] DECF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - 1 (destination)
Status Af fe cted: Z
Description: Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
2001-2013 Microchip Technology Inc. DS39582C-page 163
PIC16F87XA
DECFSZ Decrement f, Skip if 0
Syntax: [ label ] DECFSZ f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - 1 (destination);
skip if result = 0
Status Affected: None
Description: The contents of register ‘f’ are
decrem ented. If ‘d’ is ‘0’, th e result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next instruc-
tion is ex ecute d. If the resu lt is ‘0’,
then a NOP is executed instead,
making it a 2 TCY instruction.
GOTO Unconditional Branch
Syntax: [ label ] GOTO k
Operands: 0 k 2047
Operation: k PC<10:0>
PCLATH<4:3> PC<12:11>
Status Affected: None
Description: GOTO is an unconditional branch.
The e le ven -bi t im me dia t e v al ue i s
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a
two-cycle instruction.
INCF Increment f
Syntax: [ label ] INCF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination)
Status Affected: Z
Description: The contents of register ‘f’ are
incremen ted. If ‘d’ is ‘ 0’, the result
is placed in the W regi ste r. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
INCFSZ Increment f, Skip if 0
Syntax: [ label ] INCFSZ f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination),
skip if result = 0
Status Af fe cted: None
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f ’.
If the result is ‘1’, the next instruc-
tion is executed. If the result is ‘0’,
a NOP is executed instead, making
it a 2 TCY instruction.
IORLW Inclusive OR Literal with W
Syntax: [ label ] IORLW k
Operands: 0 k 255
Operation: (W) .OR. k (W)
Status Af fe cted: Z
Descr iption: The c ontents of the W regis ter are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .OR. (f) (destination)
Status Af fe cted: Z
Description: Inclusi ve OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is
‘1’, the result is pla ce d back in
register ‘f’.
PIC16F87XA
DS39582C-page 164 2001-2013 Microchip Technology Inc.
RLF Rotate Left f through Carry
Syntax: [ label ] RLF f,d
Operands: 0 f 127
d [0,1]
Operation: See description below
Status Affected: C
Description: The cont ents of regis ter ‘f’ are
rotated one bit to the left through the
Carry fl ag. If ‘d’ is ‘0’, t h e r e su l t i s
placed in the W register . If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
RETURN Return from Subroutin e
Syntax: [ label ] RETURN
Operands: None
Operation: TOS PC
Status Affected: None
Description: Return f rom subroutine. The stack
is POPed an d the top o f the stack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
RRF Rotate Right f through Carry
Syntax: [ label ] RRF f,d
Operands: 0 f 127
d [0,1]
Operation: See description below
Status Affected: C
Desc ript ion : The content s of regis te r ‘f’ are
rotat ed one bit to the r ight throug h
the Carry flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the resu lt is place d
back in register ‘f’.
Register fC
Register fC
SLEEP
Syntax: [ label ] SLEEP
Operands: None
Operation: 00h WDT,
0 WDT prescaler,
1 TO,
0 PD
Status Af fe cted: TO, PD
Description: The power-down status bit, PD,
is cleared. Time-out status bit,
TO, is set. Watchdog Timer and
its prescaler are cleared.
The processor is put into Sleep
mode with th e oscillat or stopped.
SUBLW Subtract W from Literal
Syntax: [ label ] SUBLW k
Operands: 0 k 255
Operation: k - (W) W)
Status Affected: C, DC, Z
Description: The W register is subtracted (2’s
complement method) from the
eight-bit literal ‘k’. The result is
placed in t he W register.
SUBWF Subtract W from f
Syntax: [ label ] SUBWF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - (W) destination)
Status
Affected: C, DC, Z
Description: Subtract (2’s complement method)
W register from register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
2001-2013 Microchip Technology Inc. DS39582C-page 165
PIC16F87XA
SWAPF Swap Nibbles in f
Syntax: [ la bel ] SWAPF f,d
Operands: 0 f 127
d [0,1]
Operation: (f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Status Affected: None
Description: The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in the W
register. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
XORLW Exclusive OR Literal with W
Syntax: [ label ] XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k W)
Status Affected: Z
Description: The contents of the W register
are XOR’ed with the eight-b it
literal ‘k’. The result is placed in
the W register.
XORWF Exclusive OR W with f
Syntax: [ label ] XORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .XOR. (f) destination)
Status Af fe cted: Z
Description: Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
PIC16F87XA
DS39582C-page 166 2001-2013 Microchip Technology Inc.
NOTES:
2001-2013 Microchip Technology Inc. DS39582C-page167
PIC16F87XA
16.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C17 and MPLAB C18 C Compilers
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB C30 C Compiler
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
- MPLAB dsPIC30 Software Simulator
•Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB ICE 4000 In-Circuit Emulator
• In-Circuit Debugger
- MPLAB ICD 2
• Device Progra mmers
-PRO MATE
® II Universal D evi ce Programm er
- PICSTART® Plus Development Programmer
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM.netTM De monstration Board
- PICDEM 2 Plus Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 4 Demonstration Board
- PICDEM 17 Demonstration Board
- PICDEM 18R Demonstration Board
- PICDEM L IN Demo nstration Board
- PICDEM USB Demonstration Board
• Evaluation Kits
-K
EELOQ®
- P ICDEM MSC
-microID
®
-CAN
- PowerSmart®
-Analog
16.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
based application that contains:
• An interface to debugging tools
- simulator
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor with color coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High level source code debugging
• Mouse over variable inspection
• Exten si ve on-l in e help
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all projec t information)
• Debug us ing :
- source files (as sembl y or C)
- absolute listing file (mixed assembly and C)
- machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost effective
simulators, through low cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve whe n upgrading to tools w ith increasin g flexibi lity
and power.
16.2 MPASM Assembler
The MPASM assembler is a full-featured, universal
macro assembler for al l PIC MCUs.
The MPASM assembler generates relocatable object
files for the MPLINK object linker, Intel® standard HEX
files, M AP files to detail memory u sage and symbol re f-
erence, a bsolute LST files that contain source lines and
generated machine code and COFF files for
debugging.
The MPASM assembler features include:
• Integration into MPLAB IDE projects
• User de fined m acros to strea mline asse mbly c ode
• Condit ion al as sem bl y for mult i-p urpo se sourc e
files
• Directives that allow complete control over the
assembly pr ocess
PIC16F87XA
DS39582C-page 168 2001-2013 Microchip Technology Inc.
16.3 MPLAB C17 and MPLAB C18
C Compilers
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI C compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol info rmation tha t is optimized to the MPLAB IDE
debugger.
16.4 MPLINK Object Linker/
MPLIB Object Librari an
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB object librarian manages the creation and
modific ation of li brary fil es of pre-co mpiled c ode. When
a routine from a library is called from a source file , only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
16.5 MPLAB C30 C Compiler
The MPLAB C30 C compiler is a full-featured, ANSI
compliant, optimizing compiler that translates standard
ANSI C programs into dsPIC30F assembly language
source. The compiler also supports many command-
line options and language extensions to take full
adv antage of the dsPIC 30F dev ice hardw are capab ili-
ties, and afford fine control of the compiler code
generator.
MPLAB C30 is distributed with a complete ANSI C
standard library. All library functions have been vali-
dated an d c on form to the ANSI C li brary s t an dard . Th e
library includes functions for string manipulation,
dynamic memory allocation, data conversion, time-
keeping, and math functions (trigonometric, exponen-
tial and hyperbolic). The compiler provides symbolic
information for high level source debugging with the
MPLAB IDE.
16.6 MPLAB ASM30 Assembler , Linker,
and Librarian
MPLAB ASM30 assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 compiler uses the
assembler to produce it’s object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
arch ives to c rea te an e xecu tabl e fil e. N otab le fe atu res
of the assembler include:
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich dire cti ve set
• Flexible macro language
• MPLAB IDE compatibility
16.7 MPLAB SIM Software Simulator
The MPLAB SIM sof tware s imulator allows c ode deve l-
opment in a PC hosted environm ent by simulating the
PIC series microcontrollers on an instruction level. On
any given instruction, the data areas can be examined
or modified and stimuli can be applied from a file, or
user defined key press, to any pin. The execution can
be performed in Single-Step, Execute Until Break, or
Trace mode.
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and MPLAB C18
C Compilers, as well as the MPASM assembler. The
software simulator offers the flexibility to develop and
debug code outside of the laboratory environment,
making it an excellent, economical software
development tool.
16.8 MPLAB SIM30 Software Simulator
The MPLAB SIM30 software simulator allows code
develop ment in a PC hosted environment by simulating
the dsPIC30F series microcontrollers on an instr uction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any of the pins.
The MPLAB SIM30 simulator fully supports symbolic
debugging using the MPLAB C30 C Compiler and
MPLAB ASM30 assembler. The simulator runs in either
a Command Line mode for automated tasks, or from
MPLAB IDE. This hi gh speed simulator is designed to
debug, analyze and optimize time intensive DSP
routines.
2001-2013 Microchip Technology Inc. DS39582C-page169
PIC16F87XA
16.9 MPLAB ICE 2000
High Performance Universal
In-Circuit Emulator
The MPLAB ICE 2000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for PIC
microcontrollers. Software control of the MPLAB ICE
2000 in-circuit emulator is advanced by the MPLAB
Integrated Development Environment, which allows
editing, building, downloading and source debugging
from a single environment.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
featur es. Interchangea ble processo r modules al low the
system to be easi ly reconfi gured for emula tion of d iffer-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
16.10 MPLAB ICE 4000
High Performance Universal
In-Circuit Emulator
The MPLAB ICE 4000 universal in-circuit emulator is
intended to provide the product development engineer
with a co mplete micro controller de sign tool se t for high-
end PIC microcontrollers. Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment, which
allows editing, building, downloading and source
debuggi ng from a singl e envi ronm ent.
The MPLAB ICD 4000 is a premium emulator sy stem,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high speed perfor-
mance for dsPIC30F and PIC18XXXX devices. Its
advanc ed emulator fe atures inc lude complex t riggering
and timing, up to 2 Mb of emulation memory, and the
ability to view variables in real-time.
The MPLAB ICE 4000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were cho-
sen to best make t hes e fe atur es av ail able i n a si mple ,
unified application.
16.11 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC micr ocontro llers. The M PLAB ICD 2 utilizes the in-
circuit debug ging capab ility built into t he Flash de vices.
This feature, along with Microchip’s In-Circuit Serial
ProgrammingTM (ICSPTM) pro toco l, offers cost effective
in-circuit Flash debugging from the graphical user inter-
face of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by setting breakpoints, single-
stepping and watching variables, CPU status and
periphera l registers. Running at full speed ena bles test-
ing hardware and applications in real-time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.
16.12 PRO MATE II Universal Device
Programmer
The PRO MATE II is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maximum re liabi lit y. It features
an LCD display for instructions and error messages
and a modular detachable socket as sembly to support
various package types. In Stand-Alone mode, the
PRO MATE II device pr ogra mmer ca n re ad, verify, and
program PIC devices without a PC connection. It can
also set code protection in this mode.
16.13 PICSTART Plus Development
Programmer
The PICSTART Plus development programmer is an
easy-to-use, low-cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus development programmer supports
most PIC devices up to 40 pins. Larger pin count
devices, such as the PIC16C92X and PIC17C76X,
may be supported with an adapter socket. The
PICSTART Plus development programmer is CE
compliant.
PIC16F87XA
DS39582C-page 170 2001-2013 Microchip Technology Inc.
16.14 PICD EM 1 PIC MCU
Demonstration Board
The PICDE M 1 demo nstrat ion boa rd de monstrate s the
capabilities of the PIC16C5X (PIC16C54 to
PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,
PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All
necessary hardware and software is included to run
basic demo programs. The sample microcontrollers
provi d ed wi t h t he PI C DE M 1 de mo ns t rat i on b o ar d c an
be pro gramme d with a PRO MATE II devic e progr am-
mer, or a PICSTART Plus development programmer.
The PICDE M 1 demonstrati on board can be conne cted
to the MPLAB ICE i n-circ uit emulato r for testi ng. A pro-
totype area extends the circuitry for additional applica-
tion components. Features include an RS-232
interface, a potentiometer for simulated analog input,
push button switches and eight LEDs.
16.15 PICDEM.net Internet/Ethernet
Demonstration Board
The PICDEM.net demonstration board is an Internet/
Ethernet demonstration board using the PIC18F452
microcontroller and TCP/IP firmware. The board
supports any 40-pin DIP device that conforms to the
standard pinout used by the PIC16F877 or
PIC18C452. This kit features a user friendly TCP/IP
stack, web server with HTML, a 24L256 Serial
EEPROM for Xmodem download to web pages into
Serial EEPROM, ICSP/MPLAB ICD 2 interface con-
nector, an Ethernet interface, RS-232 interface, and a
16 x 2 LCD display. Also included is the book and
CD-ROM “TCP/IP Lean, Web Servers for Embedded
Systems,” by Jere my Bentham.
16.16 PICDEM 2 Plus
Demonstration Board
The PICDEM 2 Plus demonstration board supports
many 18-, 28-, and 40-pin microcontrollers, including
PIC16F87X and PIC18FXX2 devices. All the neces-
sary ha rdware and s oftwa re is include d to run the dem-
onstration programs. The sample microcontrollers
provi d ed wi t h t he PI C DE M 2 de mo ns t rat i on b o ar d c an
be pro gramme d with a PRO MATE II devic e progr am-
mer, PICSTART Plus development programmer, or
MPLAB ICD 2 with a Universal Programmer Adapter.
The MPLAB I CD 2 and MPLAB I CE in-circuit emul ators
may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area extends the
circuitry for additional application components. Some
of the features include an RS-232 interface, a 2 x 16
LCD display , a piezo speaker , an on-board temperature
sensor, four LEDs, and sample PIC18F452 and
PIC16F877 Flash microcontrollers.
16.17 PICDEM 3 PIC16C92X
Demonstration Board
The PICDEM 3 demonstration board supports the
PIC16C923 and PIC16C924 in the PLCC package. All
the necessary hardware and software is included to run
the demonstration programs.
16.18 PICDEM 4 8/14/18-Pin
Demonstration Board
The PICDEM 4 can be used to demonstrate the capa-
bilities of the 8, 14, and 18-pin PIC16XXXX and
PIC18XXXX MCUs, including the PIC16F818/819,
PIC16F87/88, PIC16F62XA and the PIC18F1320 fam-
ily of microc ontrollers. PICDEM 4 is intended to show-
case the many features of these low pin count parts,
including LIN and Motor Control using ECCP. Special
provisions are made for low power operation with the
supercapacitor circuit, and jumpers allow on-board
hardware to be disabled to eliminate current draw in
this mode. Included on the demo board are provisions
for Crystal, RC or Canned Oscillator modes, a five volt
regulato r for use with a ni ne volt wall ad apter or battery,
DB-9 RS-232 interface, ICD connector for program-
ming via ICSP and development with MPLAB ICD 2,
2x16 liquid crystal display, PCB footprints for H-Bridge
motor driver, LIN transceiver and EEPROM. Also
included are: header for expansion, eight LEDs, four
potentiometers, three push buttons and a prototyping
area. Included with the kit is a PIC16F627A and a
PIC18F1320. Tutorial firmware is included along with
the User’s Guide.
16.19 PICDEM 17 Demonstration Board
The P ICDEM 17 de mo ns t r at i on bo a r d is an ev al u ati on
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. A pro-
grammed sample i s included. T he PRO MA TE II device
programmer, or the PICSTART Plus development pro-
grammer, can b e used to repro gram the device f or user
tailored application development. The PICDEM 17
demonstration board supports program download and
execution from external on-board Flash memory. A
generous proto typ e area is av ailab le for user h ardware
expansion.
2001-2013 Microchip Technology Inc. DS39582C-page171
PIC16F87XA
16.20 PICDEM 18R PIC18C601/801
Demonstration Board
The PICDEM 18R demonstration board serves to assist
development of the PIC18C601/801 family of Microchip
microcontrollers. It provides hardware implementation
of both 8-bit Multiplexed/Demultiplexed and 16-bit
Memory modes. The board includes 2 Mb external
Flash memory and 128 Kb SRAM memory, as well as
serial EEPROM, allowing access to the wide range of
memory types supported by the PIC18C601/801.
16.21 PICDEM LIN PIC16C43X
Demonstration Board
The pow erfu l LIN h ardw a re an d so ftware kit inclu des a
series of boards and three PIC microcontrollers. The
small footprint PIC16C432 and PIC16C433 are used
as slaves in the LIN communication and feature on-
board LIN transceivers. A PIC16F874 Flash microcon-
troller serves as the master. All three microcontrollers
are pro grammed with firmware to prov ide LIN bus com -
munication.
16.22 PICkitTM 1 Flash Starter Kit
A complete “development system in a box”, the PICkit
Flash Starter Kit includes a convenient multi-section
board for p rogramming, evaluation and d evelopment of
8/14-pin Flash PIC® microcontrollers. Powered via
USB, the board operates under a simple Windows GUI.
The PICkit 1 Starter Kit includes the user's guide (on
CD ROM), PICkit 1 tutorial software and code for vari-
ous applications. Als o included ar e M PLAB® IDE (Inte-
grated Development Environment) software, software
and hardware “Tips 'n Tricks for 8-pin Flash PIC®
Microcontrollers” Handbook and a USB Interface
Cable. Supports all current 8/14-pin Flash PIC
microcontrollers, as well as many future planned
devices.
16.23 PICDEM USB PIC16C7X5
Demonstration Board
The PICDEM U SB Demo ns trati on Board shows off th e
capabilities of the PIC16C745 and PIC16C765 USB
microcontrollers. This board provides the basis for
future USB products.
16.24 Evaluation and
Programming Tools
In additio n to the PICDEM seri es of circuits, Microchip
has a line of evaluation kits and demonstration software
for the s e p roducts.
•K
EELOQ evaluation and prog ram mi ng too ls for
Microchip’s HCS Secure Data Products
• CAN developers kit for automotive network
applications
• Analog design boards and filter design software
• PowerSmart batter y char ging evaluation /
calibration kits
•IrDA
® development kit
• microID development and rfLabTM development
software
• SEEVAL® designer kit f or m em ory ev al uation and
endurance calculations
• PICDEM MSC demo boards for Switching mode
power supply, high power IR driver, delta sigma
ADC, and flow rate sensor
Check the Microchip w eb page and the latest Product
Line Card for the complete list of demonstration and
evaluation kits.
PIC16F87XA
DS39582C-page 172 2001-2013 Microchip Technology Inc.
NOTES:
2001-2013 Microchip Technology Inc. DS39582C-page 173
PIC16F87XA
17.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias.................................................................................................................-55 to +125°C
Storage temperature.............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4) .........................................-0.3V to (VDD + 0.3V)
Volta ge on VDD with resp ect to VSS ............................................................................................................ -0.3 to +7.5V
Volta ge on MC LR with respect to VSS (Note 2)................................................................................................. 0 to +14V
Voltage on RA4 with respect to Vss..................................................................................................................0 to +8.5V
Total power di ssipati on (Note 1) ...............................................................................................................................1.0W
Maximum current out o f V SS pin ...........................................................................................................................300 mA
Maximum current into VDD pin..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk byPORTA, PORTB and PORTE (combined) (Note 3)....................................................200 mA
Maximum current sourced by PORTA, PORTB and PORTE (combined) (Note 3)...............................................200 mA
Maximum current sunk by PORTC and PORTD (combined) (Note 3) .................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) (Note 3) ............................................................200 mA
Note 1: Power diss ipation is calcu late d a s fo ll ow s: Pdis = VDD x { IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL)
2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a s eri es re si sto r of 50-100 should be us ed when applying a “low” l ev el to the MCLR pin rather than
pulling this pin directly to VSS.
3: PORTD and PORTE are not implemented on PIC16F873A/876A devices.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
PIC16F87XA
DS39582C-page 174 2001-2013 Microchip Technology Inc.
FIGURE 17-1: PI C16F87 XA VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED)
FIGURE 17-2: PIC16LF87XA VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
Frequency
Voltage
6.0V
5.5V
4.5V
4.0V
2.0V
20 MHz
5.0V
3.5V
3.0V
2.5V
PIC16F87XA
Frequency
Voltage
6.0V
5.5V
4.5V
4.0V
2.0V
5.0V
3.5V
3.0V
2.5V
FMAX = (6.0 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz
Note 1: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
4 MHz 10 MHz
Note 2: FMAX has a maximum frequency of 10 MHz.
PIC16LF87XA
2001-2013 Microchip Technology Inc. DS39582C-page 175
PIC16F87XA
17.1 DC Characteristi cs: PIC16F873A/874A/876A/877A (Industrial, Extended)
PIC16LF873A/874A/876A/877A (Industrial)
PIC16LF873A/874A/876A/877A
(Industrial) Standard Operating Conditions (unless otherwise stated)
Ope rating temperature -40°C TA +85°C for industrial
PIC16F873A/874A/876A/877A
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Symbol Characteristic/
Device Min Typ† Max Units Conditions
VDD Supply Voltage
D001 16LF87XA 2.0 — 5.5 V All configurations
(DC to 10 MHz)
D001 16F87XA 4.0 —5.5 VAll configurations
D001A VBOR 5.5 VBOR enabled, FMAX = 14 MHz(7)
D002 VDR RAM Data Retention
Voltage(1) —1.5— V
D003 VPOR VDD Start Voltage to
ensure internal Power-on
Reset signal
—V
SS —VSee Section 14.5 “Power-on
Reset (POR)” for details
D004 SVDD VDD Rise Rate to ens ure
internal Power-on Reset
signal
0.05 — — V/ms See Section 14.5 “Power-on
Reset (POR)” for details
D005 VBOR Brown-out Reset
Voltage 3.65 4.0 4.35 V BODEN bit in configuration word
enabled
Legend: Rows with standard voltage device data only are shaded for improved readability.
† Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidanc e
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supp ly current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading, switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2REXT (mA) with REXT in k.
5: Timer1 oscillator (when enabled) adds approximately 20 A to the specific ati on. Thi s value is from
characterization and is for design guidance only. This is not tested.
6: The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
PIC16F87XA
DS39582C-page 176 2001-2013 Microchip Technology Inc.
IDD Supply Current(2,5)
D010 16LF87XA — 0.6 2.0 mA XT, RC osc configurations,
FOSC = 4 MHz, VDD = 3.0V
D010 16F87XA —1.6 4mA XT, RC osc configurations,
FOSC = 4 MHz, VDD = 5.5V
D010A 16LF87XA — 20 35 A LP osc configuration,
FOSC = 32 kHz, VDD = 3.0V,
WDT disab led
D013 16F87XA — 7 15 mA HS osc configuration,
FOSC = 20 MHz, VDD = 5.5V
D015 IBOR Brown-out
Reset Curre nt(6) — 85 200 A BOR enabled, VDD = 5.0V
17.1 DC Characteristi cs: PIC16F873A/874A/876A/877A (Industrial, Extended)
PIC16LF873A/8 74A/876A/877A (Industrial) (Continued)
PIC16LF873A/874A/876A/877A
(Industrial) Standard Operating Conditions (unless otherwise stated)
Ope rating temperature -40°C TA +85°C for industrial
PIC16F873A/874A/876A/877A
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Symbol Characteristic/
Device Min Typ† Max Units Conditions
Legend: Rows with standard voltage device data only are shaded for improved readability.
† Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supp ly current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading, switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2REXT (mA) with REXT in k.
5: Timer1 oscillator (when enabled) adds approximately 20 A to the specific ati on. Thi s value is from
characterization and is for design guidance only. This is not tested.
6: The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
2001-2013 Microchip Technology Inc. DS39582C-page 177
PIC16F87XA
IPD Power-down Current(3,5)
D020 16LF87XA — 7.5 30 AVDD = 3.0V, WDT enabled,
-40C to +85C
D020 16F87XA —10.5 42
60
A
A
VDD = 4.0V, WDT enabled,
-40C to +85C
VDD = 4.0V, WDT enabled,
-40C to +125C (extended)
D021 16LF87XA — 0.9 5 AV
DD = 3.0V, WDT disabled,
0C to +70C
D021 16F87XA —1.5 16
20
A
A
VDD = 4.0V, WDT disabled,
-40C to +85C
VDD = 4.0V, WDT disabled,
-40C to +125C (extended)
D021A 16LF87XA 0.9 5 AV
DD = 3.0V, WDT disabled,
-40C to +85C
D021A 16F87XA 1.5 19 A VDD = 4.0V, WDT disa bled,
-40C to +85C
D023 IBOR Brown-out
Reset Curre nt(6) — 85 200 A BOR enabled, VDD = 5.0V
17.1 DC Characteristi cs: PIC16F873A/874A/876A/877A (Industrial, Extended)
PIC16LF873A/874A/876A/877A (Industrial) (Continued)
PIC16LF873A/874A/876A/877A
(Industrial) Standard Operating Conditions (unless otherwise stated)
Ope rating temperature -40°C TA +85°C for industrial
PIC16F873A/874A/876A/877A
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Symbol Characteristic/
Device Min Typ† Max Units Conditions
Legend: Rows with standard voltage device data only are shaded for improved readability.
† Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidanc e
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supp ly current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading, switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2REXT (mA) with REXT in k.
5: Timer1 oscillator (when enabled) adds approximately 20 A to the specific ati on. Thi s value is from
characterization and is for design guidance only. This is not tested.
6: The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
PIC16F87XA
DS39582C-page 178 2001-2013 Microchip Technology Inc.
17.2 DC Characteristics: PIC16F873A/874A/87 6A/877A (Industrial, Extended)
PIC16LF873A/874A/876A/877A (Industria l)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating t emperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Operating voltage VDD range as described in DC specification
(Section 17.1)
Param
No. Sym Characteristic Min Typ† Max Units Conditions
VIL Input Low Voltag e
I/O ports:
D030 with TTL buffer VSS —0.15 VDD V For entire VDD range
D030A VSS —0.8V V4.5V VDD 5.5V
D031 with Schmitt Trigger buffer VSS — 0.2 VDD V
D032 MCLR, OSC1 (in RC mode) VSS — 0.2 VDD V
D033 OSC1 (in XT and LP modes) VSS —0.3V V(Note 1)
OSC1 (in HS mode) VSS — 0.3 VDD V
Ports RC3 and RC4: —
D034 with Schmitt Trigger buffer VSS — 0.3 VDD V For entire VDD range
D034A with SMBus -0.5 — 0.6 V For VDD = 4.5 to 5.5V
VIH Input High Volta ge
I/O ports: —
D040 with TTL buffer 2.0 — VDD V4.5V VDD 5.5V
D040A 0.25 VDD
+ 0.8V —VDD V For entire VDD range
D041 with Schmitt Trigger buffer 0.8 VDD —VDD V For entire VDD range
D042 MCLR 0.8 VDD —VDD V
D042A OSC1 (in XT and LP modes) 1.6V — VDD V(Note 1)
OSC1 (in HS mode) 0.7 VDD —VDD V
D043 OSC1 (in RC mode) 0.9 VDD —VDD V
Ports RC3 and RC4:
D044 with Schmitt Trigger buffer 0.7 VDD —VDD V For entire VDD range
D044A with SMBus 1.4 — 5.5 V For VDD = 4.5 to 5.5V
D070 IPURB PORTB Weak Pull-up Current 50 250 400 AVDD = 5V, VPIN = VSS,
-40°C TO +85°C
IIL Input Leak age Current(2, 3)
D060 I/O port s — — 1AVSS VPIN VDD,
pin at high-impedance
D061 MCLR, RA 4/T0 CKI — — 5AVSS VPIN VDD
D063 OSC1 — — 5AVSS VPIN VDD, XT, HS
and LP osc configuration
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note 1: In RC oscillator configurati on, the OSC1/C LKI pin is a Schmitt T r igger input . It is not recommen ded that the
PIC16F87XA be driven with external cloc k in RC mode.
2: The leakage c urrent on the MCLR pin is strongly depen dent on the applied voltage leve l. The specified levels
represent normal operating condi tions. Higher leaka ge current may be meas ured at dif ferent input v oltages.
3: Negative current is defined as current sourced by the pin.
2001-2013 Microchip Technology Inc. DS39582C-page 179
PIC16F87XA
VOL Output Low Voltage
D080 I/O port s — — 0.6 V IOL = 8.5 mA, VDD = 4.5V,
-40C to +85C
D083 OSC2/CLKO (RC osc config) — — 0.6 V IOL = 1.6 mA, VDD = 4.5V,
-40C to +85C
VOH Output High Voltage
D090 I/O port s(3) VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V,
-40C to +85C
D092 OSC2/CLKO (RC osc config) VDD – 0.7 — — V IOH = -1.3 mA, VDD = 4.5V,
-40C to +85C
D150* VOD Open-Drain High Voltage — — 8.5 V RA4 pin
Capacitive Loading Specs on
Output Pins
D100 COSC2 OSC2 pin — — 15 pF In XT, HS and L P mo de s w h en
exte rnal clock is used to drive
OSC1
D101
D102 CIO
CBAll I/O pins and OSC2 (RC mode)
SCL, SDA (I2C mode) —
——
—50
400 pF
pF
Data EEPROM Memory
D120 EDEndurance 100K 1M — E/W -40C to +85C
D121 VDRW VDD for read/write VMIN — 5.5 V Using EECON to read/write ,
VMIN = min. operating voltage
D122 TDEW Erase/wr ite cycle time — 4 8 ms
Program Flash Memory
D130 EPEndurance 10K 100K — E/W -40C to +85C
D131 VPR VDD for read VMIN —5.5 VVMIN = min. opera ting voltage
D132A VDD for erase/write VMIN — 5.5 V Using EECON to read/write,
VMIN = min. operating voltage
D133 TPEW Erase/ Write cy cle t ime — 4 8 ms
17.2 DC Characteristics: PIC16F873A/874A/87 6A/877A (Industrial, Extended)
PIC16LF873A/874A/876A/877A (Industri al) (Continued)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating t emperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Operating voltage VDD range as described in DC specification
(Section 17.1)
Param
No. Sym Characteristic Min Typ† Max Units Conditions
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note 1: In RC oscillator configurati on, the OSC1/C LKI pin is a Schmitt T r igger input . It is not recommen ded that the
PIC16F87XA be driven with external cloc k in RC mode.
2: The leakage c urrent on the MCLR pin is strongly depen dent on the applied voltage leve l. The specified levels
represent normal operating condi tions. Higher leaka ge current may be measu red at different input voltages.
3: Negative current is defined as current sourced by the pin.
PIC16F87XA
DS39582C-page 180 2001-2013 Microchip Technology Inc.
TABLE 17-1: COMPARATOR SPECIFICATIONS
TABLE 17-2: VOLTAGE REFERENCE SPECIFICATIONS
Operating Condit ions : 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated)
4.0V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated)
Param
No. Sym Characteristics Min Typ Max Units Comments
D300 VIOFF Input Offset Voltage — ± 5.0 ± 10 mV
D301 VICM Input Common Mode Voltage* 0 - VDD – 1.5 V
D302 CMRR Common Mode Rejection Ra tio* 55 - — dB
300
300A TRESP Response Time*(1) —150400
600 ns
ns PIC16F87XA
PIC16LF87XA
301 TMC2OV Comparator Mode Change to
Output Valid* ——10s
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2 while the other inp ut transi tions from
VSS to VDD.
Operating Condit ions : 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated)
4.0V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated)
Spec
No. Sym Characteristics Min Typ Max Units Comments
D310 VRES Resolution VDD/24 — VDD/32 LSb
D311 VRAA Absolute Accuracy —
——
—1/2
1/2 LSb
LSb Low Range (VRR = 1)
High Range (VRR = 0)
D312 VRUR Unit Resistor Value (R)* — 2k —
310 TSET Settling Time*(1) — — 10 s
* These parameters are characterized but not tested.
Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’.
2001-2013 Microchip Technology Inc. DS39582C-page 181
PIC16F87XA
17.3 Timing Parameter Symbology
The timing parameter symbols have been created
following one of the following formats:
FIGURE 17-3: LOA D CONDITIONS
1. TppS2ppS 3. TCC:ST (I2C specifications only)
2. TppS 4. Ts (I2C specifications only)
TF Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKO rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meani ngs:
SFFall PPeriod
HHigh RRise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
I2C only
AA output access High High
BUF Bus free Low Low
TCC:ST (I2C specifications only)
CC
HD Hold SU Setup
ST
DAT Data input hold STO Stop condition
STA Start condition
VDD/2
CL
RL
Pin Pin
VSS VSS
CL
RL= 464
CL= 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports,
15 pF for OSC2 output
Note: PORTD and PORTE are not implemented on PIC16F873A/876A devices.
Load Condition 1 Load Condition 2
PIC16F87XA
DS39582C-page 182 2001-2013 Microchip Technology Inc.
FIGURE 17-4: EX TERN AL CLOCK TIMING
OSC1
CLKO
Q4 Q1 Q2 Q3 Q4 Q1
1
23344
TABLE 17-3: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
FOSC External CLKI Frequency
(Note 1) DC — 1 MHz XT and RC Osc mode
DC — 20 MHz HS Osc mode
DC — 32 kHz LP Osc mode
Oscillator Frequency
(Note 1) DC — 4 MHz RC Osc mode
0.1 — 4 MHz XT Osc mode
4
5—
—20
200 MHz
kHz HS Osc mode
LP Osc mode
1TOSC External CLKI Period
(Note 1) 1000 — — ns XT and RC Osc mode
50 — — ns HS Osc mode
5——sLP Osc mode
Oscillator Period
(Note 1) 250 — — ns R C Osc mode
250 — 1 s XT Osc mode
100 — 250 ns HS Osc mode
50 — 250 ns HS Osc mode
31.25 — — sLP Osc mode
2T
CY Instruction Cycle Time
(Note 1) 200 TCY DC ns TCY = 4/FOSC
3T
OSL,
TOSHExternal Clock in (OSC1) High or
Low Time 100 — — ns XT oscillator
2.5 — — s LP oscillator
15 — — ns HS oscillator
4T
OSR,
TOSFExternal Clock in (OSC1) Rise or
Fall Time — — 25 ns XT oscillator
— — 50 ns LP oscillator
— — 15 ns HS oscillator
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note 1: Instruction cycle period (TCY) equ als four ti mes the in put oscil lator time base perio d. All spec ified val ues are
based on characterization data for that particular oscillator type, under standard operating conditions, with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or highe r than ex pected curr ent consum ption . All dev ices a re tested to op erate at “min. ” values with an
external cl ock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time
limit is “DC” (no clock) for all devices.
2001-2013 Microchip Technology Inc. DS39582C-page 183
PIC16F87XA
FIGURE 17-5: CLKO AND I/O TIMING
TABLE 17-4: CLKO AND I/O TIMING REQUIREMENTS
Note: Refer to Figure 17-3 for load conditions.
OSC1
CLKO
I/O pin
(Input)
I/O pin
(Output)
Q4 Q1 Q2 Q3
10
13 14
17
20, 21
19 18
15
11
12 16
Old Value New Value
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
10* TOSH2CKLOSC1 to CLKO — 75 200 ns (Note 1)
11* TOSH2CKHOSC1 to CLKO — 75 200 ns (Note 1)
12* TCKR CLKO Rise T ime — 35 100 ns (Note 1)
13* TCKF CLKO Fa ll Time — 35 100 ns (Note 1)
14* TCKL2IOVCLKO to Port Out Valid — — 0.5 TCY + 20 ns (Note 1)
15* TIOV2CKH Port In Valid before CLKO TOSC + 200 — — n s (Note 1)
16* TCKH2IOI Port In Hold after CLKO 0——ns(Note 1)
17* TOSH2IOVOSC1 (Q1 cycle) to Port Out Valid — 100 255 ns
18* TOSH2IOIOSC1 (Q 2 c ycle) to Port Input
Invalid (I/O in hol d time) Standard (F) 100 — — ns
Extended (LF) 200 — — ns
19* TIOV2OSH P ort Input Valid to OSC1 (I/ O i n se tu p ti me) 0 — — ns
20* TIOR Port Output Rise Time Standard (F) — 10 40 ns
Extended (LF) — — 145 ns
21* TIOF Port Output Fall Time Standard (F) — 10 40 ns
Extended (LF) — — 145 ns
22††* TINP INT pin High or Low Time TCY ——ns
23††* TRBP RB7:RB4 Change INT High or Low Time TCY ——ns
* T hes e parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
no t te sted.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode where CLKO output is 4 x TOSC.
PIC16F87XA
DS39582C-page 184 2001-2013 Microchip Technology Inc.
FIGURE 17-6: RES E T, WATC HDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIME R TIMING
FIGURE 17-7: BROWN-OUT RESET TIMING
TABLE 17-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O pins
34
Note: Refer to Figure 17-3 for load conditions.
VDD VBOR
35
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
30 TMCLMCLR Pulse Width (low) 2 — — sVDD = 5V, -40°C to +85°C
31* TWDT Watchdog Timer Time-out Period
(no prescaler) 71833msVDD = 5V, -40°C to +85°C
32 TOST O scillation Start-up Timer Period — 1024 TOSC ——TOSC = OSC1 period
33* TPWRT Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +85°C
34 TIOZ I/O High-Impedance from MCLR Low
or Watchdog Timer Reset ——2.1s
35 TBOR Brown-out Reset Pulse Width 100 — — sVDD VBOR (D005)
* T hes e parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
no t te sted.
2001-2013 Microchip Technology Inc. DS39582C-page 185
PIC16F87XA
FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 17-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns Must also meet
parameter 42
With Pre scaler 10 — — ns
41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns Must also meet
parameter 42
With Pre scaler 10 — — ns
42* TT0P T0CKI Period No Prescaler TCY + 40 — — ns
With Prescaler Greater of:
20 or TCY + 40
N
— — ns N = prescale value
(2, 4,.. ., 256)
45* TT1H T1CKI High
Time Synchronous, Prescaler = 1 0.5 TCY + 20 — — ns Must also meet
parameter 47
Synchronous,
Prescaler = 2, 4, 8 Standard(F)15——ns
Extended(LF)25 ——ns
Asynchronous Standard(F)30——ns
Extended(LF)50 ——ns
46* TT1L T1CKI Low Time Synchronous, Prescaler = 1 0.5 TCY + 20 — — ns Must also meet
parameter 47
Synchronous,
Prescaler = 2, 4, 8 Standard(F)15——ns
Extended(LF)25 ——ns
Asynchronous Standard(F)30——ns
Extended(LF)50 ——ns
47* TT1P T 1CK I Input
Period Synchronous Standard(F) G reater of:
30 or TCY + 40
N
— — ns N = prescale value
(1, 2, 4, 8)
Extended(LF) Greater of:
50 or TCY + 40
N
N = prescale value
(1, 2, 4, 8)
Asynchronous Standard(F)60——ns
Extended(LF) 100 — — ns
FT1 Tim er1 Os cillator Input Frequency Range
(oscillator enabled by setting bit T1OSCEN) DC — 200 kHz
48 TCKEZTMR1 Delay from External Clock Edge to Timer Increment 2 TOSC —7 TOSC —
* T hes e parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
no t te sted.
Note: Refer to Figure 17-3 for load conditions.
46
47
45
48
41
42
40
RA4/T0CKI
RC0/T1OSO/T1CKI
TMR0 or TMR1
PIC16F87XA
DS39582C-page 186 2001-2013 Microchip Technology Inc.
FIGURE 17-9: CAP TURE/ COMPARE/PWM TIMINGS (CCP1 AND CCP2)
TABLE 17-7: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Note: Refer to Figure 17-3 for load conditions.
and RC2/CCP1
(Capture Mode)
50 51
52
53 54
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
RC1/T1OSI/CCP2
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
50* TCCL CCP1 and CCP2
Input Low Ti me No Prescaler 0.5 TCY + 20 — — ns
With Prescaler Standard(F)10——ns
Extended(LF)20——ns
51* TCCH CCP1 and CCP2
Input High Time No Prescaler 0.5 TCY + 20 — — ns
With Prescaler Standard(F)10——ns
Extended(LF)20——ns
52* TCCP CCP1 and CCP2 Input Period 3 TCY + 40
N— — ns N = prescale value
(1, 4 or 16)
53* TCCR CCP1 and CCP2 Output Rise Time S tandard(F) — 10 25 ns
Extended(LF) — 25 50 ns
54* TCCF CCP1 and CCP2 Output Fall Time Standard(F) — 10 25 ns
Extended(LF) — 25 45 ns
* T hes e parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
no t te sted.
2001-2013 Microchip Technology Inc. DS39582C-page 187
PIC16F87XA
FIGURE 17-10: PARALLEL SLAVE PORT TIMING (PIC16F874A/877A ONLY)
TABLE 17-8: PARALLEL SLAVE PORT REQUIREMENTS (PIC16F874A/877A ONLY)
Note: Refer to Figure 17-3 for load conditions.
RE2/CS
RE0/RD
RE1/WR
RD7:RD0
62
63
64
65
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
62 TDTV2WRH Data In Valid before WR or CS (setup time) 20 — — ns
63* TWRH2DTIWR or CS to Data–in Invalid
(hold time) Standard(F)20——ns
Extended(LF)35——ns
64 TRDL2DTVRD and CS to Data–out Valid — — 80 ns
65 TRDH2DTIRD or CS to Data–out Invalid 10 — 30 ns
* T hes e parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
no t te sted.
PIC16F87XA
DS39582C-page 188 2001-2013 Microchip Technology Inc.
FIGURE 17-11: SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
FIGURE 17-12 : SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76
78
79
80
79
78
MSb LSb
Bit 6 - - - - - -1
MSb In LSb In
Bit 6 - - - -1
Note: Refer to Figure 17-3 for load conditions.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
MSb In
Bit 6 - - - - - -1
LSb In
Bit 6 - - - -1
LSb
Note: Refer to Figure 17-3 for load conditions.
2001-2013 Microchip Technology Inc. DS39582C-page 189
PIC16F87XA
FIGURE 17-13 : SPI SLAVE MODE TIMING (CKE = 0)
FIGURE 17-14 : SPI SLAVE MODE TIMING (CKE = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76 77
78
79
80
79
78
SDI
MSb LSb
Bit 6 - - - - - -1
MSb In Bit 6 - - - -1 LSb In
83
Note: Refer to Figure 17-3 for load conditions.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
82
SDI
74
75, 76
MSb Bit 6 - - - - - -1 LSb
77
MSb In Bit 6 - - - -1 LSb In
80
83
Note: Refer to Figure 17-3 for load conditions.
PIC16F87XA
DS39582C-page 190 2001-2013 Microchip Technology Inc.
TABLE 17-9: SPI MODE REQUIREMENTS
FIGURE 17-15 : I2C BUS START/STOP BITS TIMING
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
70* TSSL2SCH,
TSSL2SCLSS to SC K or SCK Input TCY ——ns
71* TSCH SCK Input High Time (Slave mode) TCY + 20 — — ns
72* TSCL SCK Input Low Time (Slave mode) TCY + 20 — — ns
73* TDIV2SCH,
TDIV2SCLSetup Time of SDI Data Input to SCK Edge 100 — — ns
74* TSCH2DIL,
TSCL2DILHold T ime of SDI Data Input to SCK Edge 100 — — ns
75* TDOR SDO Data Output Rise Time Standard(F)
Extended(LF)—
—10
25 25
50 ns
ns
76* TDOF SDO Data Output Fall Time — 10 25 ns
77* TSSH2DOZSS to SDO Output High-Impedance 10 — 50 ns
78* TSCR SCK Output Rise Ti me
(Master mode) Standard(F)
Extended(LF)—
—10
25 25
50 ns
ns
79* TSCF SCK Output Fall Time (Master mode) — 10 25 ns
80* TSCH2DOV,
TSCL2DOVSDO Data Out pu t Valid after
SCK Ed ge Standard(F)
Extended(LF)—
——
—50
145 ns
81* TDOV2SCH,
TDOV2SCLSDO Data Output Setup to SCK Edge TCY ——ns
82* TSSL2DOV SDO Data Output Valid after SS Edge — — 50 ns
83* TSCH2SSH,
TSCL2SSHSS after SCK Edge 1.5 TCY + 40 — — ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note: Refer to Figure 17-3 for load conditions.
91 93
SCL
SDA
Start
Condition Stop
Condition
90 92
2001-2013 Microchip Technology Inc. DS39582C-page 191
PIC16F87XA
TABLE 17-10: I2C BUS START/STOP BITS REQUIREMENTS
FIGURE 17-16 : I2C BUS DATA TIMING
Param
No. Symbol Characteristic Min Typ Max Units Conditions
90 TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated Start
condition
Setup time 400 kHz mode 600 — —
91 THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first clock pulse
is generated
Hold time 400 kHz mode 600 — —
92 TSU:STO Stop condition 100 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
93 THD:STO Stop condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
Note: Refer to Figure 17-3 for load conditions.
90
91 92
100 101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
PIC16F87XA
DS39582C-page 192 2001-2013 Microchip Technology Inc.
TABLE 17-11: I2C BUS DATA REQUIREMENTS
Param
No. Sym Characteristic Min Max Units Conditions
100 THIGH Clock High Time 100 kHz mode 4.0 — s
400 kHz mode 0.6 — s
SSP Module 0.5 TCY —
101 TLOW Clock Low Tim e 100 kHz mode 4.7 — s
400 kHz mode 1.3 — s
SSP Module 0.5 TCY —
102 TRSDA and SCL Rise
Time 100 kHz mode — 1000 ns
400 kHz mode 20 + 0.1 CB300 ns Cb is specified to be from 10 to
400 pF
103 TFSDA and SCL Fall
Time 100 kHz mode — 300 ns
400 kHz mode 20 + 0.1 CB300 ns CB is specified to be from 10 to
400 pF
90 TSU:STA Start Condition Setup
Time 100 kHz mode 4.7 — s Only relevant for Repeated Start
condition
400 kHz mode 0.6 — s
91 THD:STA Start Condition Hold
Time 100 kHz mode 4.0 — s After this period, the first clock
pulse is generated
400 kHz mode 0.6 — s
106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
92 TSU:STO Stop Condition Setup
Time 100 kHz mode 4.7 — s
400 kHz mode 0.6 — s
109 TAA Output Valid from
Clock 100 kHz mode — 3500 ns (Note 1)
400 kHz mode — — ns
110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free before
a new transmission can start
400 kHz mode 1.3 — s
CBBus Capacitive Loading — 400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region ( min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A fast mode (400 kHz) I2C bus device can be used in a standard mode (100 kHz) I2C bus system, but the requirement
that, TSU:DAT 250 ns, must then be met. This will aut omatically be the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line, TR MAX. + TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification),
before the SCL line is released.
2001-2013 Microchip Technology Inc. DS39582C-page 193
PIC16F87XA
FIGURE 17-17: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 17-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 17-18: USA RT SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 17-13: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Note: Refer to Figure 17-3 for load conditions.
121 121
122
RC6/TX/CK
RC7/RX/DT
pin
pin
120
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
120 TCKH2DTV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid Standard(F)——80ns
Extended(LF) — — 100 ns
121 TCKRF Clock Out Rise Time and Fall Time
(Master mo de) Standard(F)——45ns
Extended(LF)——50ns
122 TDTRF Data Out Rise Time and Fall Time Standard(F)——45ns
Extended(LF)——50ns
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note: Refer to Figure 17-3 for load conditions.
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
125 TDTV2CKL SYNC RCV (MASTER & SLAVE)
Data Setup before CK (DT setup time) 15 — — ns
126 TCKL2DTL Data Hold afte r CK (DT hold time) 15 — — ns
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested .
PIC16F87XA
DS39582C-page 194 2001-2013 Microchip Technology Inc.
TABLE 17-14: A/D CONVERTER CHARACTERISTICS:PIC16F873A/874A/876A/877A (INDUSTRIAL)
PIC16LF873A/ 87 4 A/ 87 6A / 87 7A (I ND U STR IA L )
Param
No. Sym Characteristic Min Typ† Max Units Conditions
A01 NRResolution — — 10-bits bit VREF = VDD = 5.12V,
VSS VAIN VREF
A03 EIL Integral Linearity Error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS VAIN VREF
A04 EDL Different ial Linearity Error — — < ± 1 LSb VREF = VDD = 5.12V,
VSS VAIN VREF
A06 EOFF Offset Error — — < ± 2 LSb VREF = VDD = 5.12V,
VSS VAIN VREF
A07 EGN Gain Error — — < ± 1 LS b VREF = VDD = 5.12V,
VSS VAIN VREF
A10 — Monotonicity — guaranteed(3) ——VSS VAIN VREF
A20 VREF Ref erence Voltage (VREF+ – VREF-) 2.0 — VDD + 0.3 V
A21 VREF+ Reference Voltage High AVDD – 2.5V AVDD + 0.3V V
A22 VREF- Reference Voltage Low AVSS – 0.3V VREF+ – 2.0V V
A25 VAIN Analog Input Voltage VSS – 0.3V — VREF + 0.3V V
A30 ZAIN Recommended Impedance of
Analog Voltage Source ——2.5k(Note 4)
A40 IAD A/D Conversion
Current (VDD)PIC16F87XA — 220 — A Ave rage current
consumption when A/D is
on (Note 1)
PIC16LF87XA — 90 — A
A50 IREF VREF Input Current (Note 2) —
—
—
—
5
150
A
A
During VAIN acquisition.
Based on differential of
VHOLD to VAIN to charge
CHOLD, see Section 11.1
“A/D Acquisition
Requirements”.
During A/D conversion
cycle
* T hes e parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
no t te sted.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec
includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
4: Maximum allowed impedance for analog voltage source is 10 kThis requires higher acquisition time.
2001-2013 Microchip Technology Inc. DS39582C-page 195
PIC16F87XA
FIGURE 17-19: A/D CONVE RSION TIMING
TABLE 17-15: A/D CONVERSION REQUIREMENTS
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
Sampling St opped
DONE
NEW_DATA
(TOSC/2)(1)
987 210
Note: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock start s. This allows the SLEEP
instruction to be executed.
1 TCY
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
130 TAD A/D Clock Per iod PIC16F87XA 1.6 — — sTOSC based, VREF 3.0V
PIC16LF87XA 3.0 — — sT
OSC based, VREF 2.0V
PIC16F87XA 2.0 4.0 6.0 s A/D RC mode
PIC16LF87XA 3.0 6.0 9.0 s A/D RC mode
131 TCNV Conversion Time (not including S/H time)
(Note 1) —12TAD
132 TACQ Acquisition Time (Note 2)
10*
40
—
—
—
s
s The minimum time is the
amplifier settling time. This may
be used if the “new” input volt-
age has not changed by more
than 1 LSb (i.e., 20.0 mV @
5.12V) from the last sampled
voltage (as stated on CHOLD).
134 TGO Q4 to A/D Clock Start — TOSC/2 § — — I f the A/D clock sourc e is
selected as RC, a time of TCY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
* T hes e parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
no t te sted.
§ This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 11.1 “A/D Acquisition Requirements” for minimum conditions.
PIC16F87XA
DS39582C-page 196 2001-2013 Microchip Technology Inc.
NOTES:
2001-2013 Microchip Technology Inc. DS39582C-page 197
PIC16F87XA
18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
“T ypical” represents the mean of the distribution at 25C. “Maximum” or “minimum” represents (mean + 3) or (mean – 3)
respectively, where is a standard deviation, ov er the whole temperature range.
FIGURE 18-1: TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
FIGURE 18-2: MAXI MU M IDD vs. FOSC OVER VDD (HS MODE)
Note: The g r ap hs and t ables provide d f oll ow in g th is no te a r e a s t ati sti ca l s um ma ry bas ed on a limited n um ber of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
0
1
2
3
4
5
6
7
4 6 8 10 12 14 16 18 20
FOSC (MHz)
IDD (mA)
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0
1
2
3
4
5
6
7
8
4 6 8 10 12 14 16 18 20
FOSC (MHz)
IDD (mA)
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
PIC16F87XA
DS39582C-page 198 2001-2013 Microchip Technology Inc.
FIGURE 18-3: TYPICAL IDD vs. FOSC OVER VDD (XT MODE)
FIGURE 18-4: MAXI MU M IDD vs. FOSC OVER VDD (XT MODE)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0 500 1000 1500 2000 2500 3000 3500 4000
FOSC (MHz)
IDD (mA)
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0.0
0.5
1.0
1.5
2.0
2.5
0 500 1000 1500 2000 2500 3000 3500 4000
FOSC (MHz)
IDD (mA)
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
2001-2013 Microchip Technology Inc. DS39582C-page 199
PIC16F87XA
FIGURE 18-5: TYPICAL IDD vs. FOSC OVER VDD (LP MODE)
FIGURE 18-6: MAXI MU M IDD vs. FOSC OVER VDD (LP MODE)
0
10
20
30
40
50
60
70
20 30 40 50 60 70 80 90 100
FOSC (kHz)
IDD (uA)
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0
20
40
60
80
100
120
20 30 40 50 60 70 80 90 100
FOSC (kHz)
IDD (uA)
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
PIC16F87XA
DS39582C-page 200 2001-2013 Microchip Technology Inc.
FIGURE 18-7: AVERAGE FOSC vs. VDD FOR V ARIOUS V A LUES OF R (RC MODE, C = 20 pF, +25C)
FIGURE 18-8: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 100 pF, +25C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Freq (MHz)
100 k O hm
10 kOhm
5.1 kO hm
Oper ation above 4 MHz is not recommended
0.0
0.5
1.0
1.5
2.0
2.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Freq (MHz)
100 k O hm
10 kOhm
5.1 kOhm
3.3 kOhm
2001-2013 Microchip Technology Inc. DS39582C-page 201
PIC16F87XA
FIGURE 18-9: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 300 pF, +25C)
FIGURE 18-10 : IPD vs. VDD, -40C TO +125C (SLEEP MODE, ALL PERIPHERALS DISABLED)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Freq (MHz)
100 kOhm
10 kOhm
5.1 kOhm
3.3 kOhm
0.001
0.01
0.1
1
10
100
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (uA)
Typ (25°C)
Max ( 85°C)
Max (125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
PIC16F87XA
DS39582C-page 202 2001-2013 Microchip Technology Inc.
FIGURE 18-1 1: T YPICAL AND MAXIMUMITMR1 vs. VDD OVER TEMPERATURE (-10C T O +70 C,
TIMER1 WITH OSCILLATOR, XTAL = 32 kHz, C1 AND C2 = 47 pF)
FIGURE 18-12: TYPICAL AND MAXIMUM IWDT vs. VDD OVER TEMPERATURE (WDT ENABLED)
0
2
4
6
8
10
12
14
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (uA)
Typ (25C)
Max (70C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-10°C to +70°C)
Minimum: mean – 3 (-10°C to +70°C)
IPD (A)
Max (+ 70°C)
Typ (+25°C)
0.1
1
10
100
2.02.53.03.54.04.55.05.5
VDD (V)
IPD (uA)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
Max (+ 125°C)
Max (+85°C)
Typ (+25°C )
2001-2013 Microchip Technology Inc. DS39582C-page 203
PIC16F87XA
FIGURE 18-13 : IBOR vs. VDD OVER TEMPERATURE
FIGURE 18-14: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40C TO +125C)
10
100
1,000
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IDD (A)
Device in
Reset
Device in
Sleep
Indeterminant
State
Max (125°C)
Typ (2 5°C )
Max (125°C)
Typ (25°C)
Typical: statistical mean @ 25°C
Maxi mum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
Note: Device current in Reset
depends on oscillator mode,
frequency and circuit.
0
5
10
15
20
25
30
35
40
45
50
2.02.53.03.54.04.55.05.5
VDD (V)
WDT Period (ms)
Max
(125°C)
Typ
(25°C)
Min
(-40°C)
Typical: statistical mean @ 25°C
Maxi mum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
PIC16F87XA
DS39582C-page 204 2001-2013 Microchip Technology Inc.
FIGURE 18-15: AVERAGE WDT PERIOD vs. VDD OVER TEMPERATURE (-40C TO +125 C)
FIGURE 18-16: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40C TO +125C)
0
5
10
15
20
25
30
35
40
45
50
2.02.53.03.54.04.55.05.5
VDD (V)
WDT Period (ms)
125°C
85°C
25°C
-40°C
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Mini mum: mean – 3 (-4 0°C to +125 °C )
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0 5 10 15 20 25
IOH (-mA)
VOH (V)
Max
Ty p (25 °C)
Min
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40° C to +125°C )
Minimum: mean – 3 (-40°C to +125°C)
2001-2013 Microchip Technology Inc. DS39582C-page 205
PIC16F87XA
FIGURE 18-17: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40C TO + 125C)
FIGURE 18-18: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40C TO +125C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0 5 10 15 20 25
IOH (-mA)
VOH (V)
Max
Typ (25°C )
Min
Typical: statistical mean @ 25°C
Maximu m: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 5 10 15 20 25
IOL (-mA)
VOL (V)
Max (125°C)
Max (85°C)
Ty p (25 °C)
Min (-40°C)
Typical: statistical mean @ 25°C
Maxi mum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
PIC16F87XA
DS39582C-page 206 2001-2013 Microchip Technology Inc.
FIGURE 18-19: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40C TO +125C)
FIGURE 18-20: MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40C TO +125C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0 5 10 15 20 25
IOL (-mA)
VOL (V)
Max (125° C)
Max (85° C)
Typ (25°C )
Min (-40°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
VIN (V)
VTH Max (-40°C)
VTH Min (125°C)
VTH Typ (25°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
2001-2013 Microchip Technology Inc. DS39582C-page 207
PIC16F87XA
FIGURE 18-21: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO +125C)
FIGURE 18-22: MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40C TO +125C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
VIN (V)
VIH Max (125°C)
VIH Mi n (-40° C)
VIL Max (-40°C)
VIL Min (125°C)
Typical: statistic al mean @ 25°C
Maximu m: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
VIN (V)
VIH Max
VIH Min
VILMax
VIL Min
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
VIL Max
PIC16F87XA
DS39582C-page 208 2001-2013 Microchip Technology Inc.
FIGURE 18-23: A/D NONLINEARITY vs. VREFH (VDD = VREFH, -40C TO + 125C)
FIGURE 18-24: A/D NONLINEARITY vs. VREFH (VDD = 5V, -40C TO +125C)
0
0.5
1
1.5
2
2.5
3
3.5
4
22.533.544.555.5
VDD and VREFH (V)
Differential or In tegral Nonlinearity (LSB)
-40C
25C
85C
125C
-40°C
+25°C
+85°C
+125°C
0
0.5
1
1.5
2
2.5
3
22.533.544.555.5
VREFH (V)
Differential or Integral Nonlinearilty (LSB)
Max (-40C to 125C)
Typ (25C)
Typ (+25°C)
Max (-40°C to +125°C)
2001-2013 Microchip Technology Inc. DS39582C-page 209
PIC16F87XA
19.0 PACKAGING INFORMATION
19.1 Package Marking Information
40-Lead PDIP
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC16F877A/P
0310017
44-Lead TQFP
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Example
PIC16F877A
/PT 0310017
44-Lead PLCC
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Example
PIC16F877A
-20/L
0310017
Legend: XX...X Customer-specifi c info rma tio n
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microc hip p art num ber cann ot be marked on one lin e, it wi ll
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
PIC16F87XA
DS39582C-page 210 2001-2013 Microchip Technology Inc.
Package Marking Information (Cont’d)
XXXXXXXXXX
44-Lead QFN
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Example
28-Lead PDIP (Skinny DIP)
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC16F876A/SP
0310017
28-Lead SO IC
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC16F876A/SO
0310017
28-Lead SS O P
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
Example
PIC16F876A/
SS 0310017
Example28-Lead QF N
XXXXXXXX
XXXXXXXX
YYWWNNN
PIC16F877A
-I/ML
0310017
16F873A
-I/ML
0310017
2001-2013 Microchip Technology Inc. DS39582C-page 211
PIC16F87XA
40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)
1510515105
Mold Draft Angle Bottom 1510515105
Mold Draft Angle Top 17.2716.5115.75.680.650.620
eB
Overall Row S pacing § 0.560.460.36.022.018.014BLower Lea d Width 1.781.270.76.070.050.030B1Upper Lea d Width 0.380.290.20.015.012.008
c
Lead Thic kness 3.433.303.05.135.130.120LTip to Seating Plane 52.4552.2651.942.0652.0582.045DOverall Length 14.2213.8413.46.560.545.530E1Molded Package Width 15.8815.2415.11.625.600.595EShoulder to Shoulder Width 0.38.015A1Base to Seating Plane 4.063.813.56.160.150.140A2Molded Package Thickness 4.834.454.06.190.175.160ATop to Seating Plane 2.54
.100
p
Pitch 4040
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
A2
1
2
D
n
E1
c
eB
E
p
L
B
B1
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016
§ Significant Characteristic
Note: For the most current package drawings, please see the Microc hip Packaging Specific ation located
at http://www.microc hip .c om /p ac kagi ng
PIC16F87XA
DS39582C-page 212 2001-2013 Microchip Technology Inc.
44-Lead Plastic Thin Quad Flatp ack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
* Controlling Parameter
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
1.140.890.64.045.035.025CHPin 1 Corner Chamfer
1.00.039
(F)
Footprint (Reference)
(F)
A
A1 A2
E
E1
#leads=n1
p
B
D1 D
n
1
2
c
L
Units INCHES MILLIMETERS*
Dim ension Limits MIN NOM MAX MIN NOM MAX
Numb er of Pin s n44 44
Pitch p.031 0.80
Overall Height A .039 .043 .047 1.00 1.10 1.20
Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05
Standoff § A1 .002 .004 .006 0.05 0.10 0.15
Foot Length L .018 .024 .030 0.45 0.60 0.75
Foot A ngle 03.5 7 03.5 7
Overall Width E .463 .472 .482 11.75 12.00 12.25
Overall Length D .463 .472 .482 1 1.75 12.00 12.25
Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10
Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10
Pins per Side n1 11 11
Lead Thickness c.004 .006 .008 0.09 0.15 0.20
Lead Width B .012 .015 .017 0.30 0.38 0.44
Mold Draft Angle Top 51015 51015
Mold Draft Angle Bottom 51015 51015
CH x 45
§ Significant Characteristic
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
2001-2013 Microchip Technology Inc. DS39582C-page 213
PIC16F87XA
44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
CH2 x 45CH1 x 45
10501050
Mold Draft Angle Bottom 10501050
Mold Draft Angle Top 0.530.510.33.021.020.013B0.810.740.66.032.029.026B1Upper Lead Width 0.330.270.20.013.011.008
c
Lead Thickness
1111n1P ins per Side
16.0015.7514.99.630.620.590
D2
Footprint Length 16.0015.7514.99.630.620.590E2Footprint Width 16.6616.5916.51.656.653.650D1Molded Package Length 16.6616.5916.51.656.653.650E1Molded Package Width 17.6517.5317.40.695.690.685DOverall Length 17.6517.5317.40.695.690.685EOverall Width 0.250.130.00.010.005.000
CH2Corner Chamfer (others) 1.271.141.02.050.045.040CH1Corner Chamfer 1 0.860.740.61.034.029.024
A3
Side 1 Chamfer Height 0.51.020A1Standoff § A2
Molded Package Thickness 4.574.394.19.180.173.165AOverall Height
1.27.050
p
Pitch 4444
n
Number of Pins MAXNOMMINMAXNOMMINDime nsion Limits MILLIMETERSINCHES*Units
A2
c
E2
2
D
D1
n
#leads=n1
E
E1
1
p
A3
A
35
B1
B
D2
A1
.145 .153 .160 3.68 3.87 4.06
.028 .035 0.71 0.89
Lower Lead Width
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-048
§ Significant Characteristic
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
PIC16F87XA
DS39582C-page 214 2001-2013 Microchip Technology Inc.
44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN)
Lead Width
*Controlling Parameter
Drawing No. C04-103
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
B .012 .013 .013 0.30 0.33 0.35
Pitch
Number of Pins
Overall Width
Standoff
Overall Length
Overall Height
MAX
Units
Dimension Limits
A1
D
E
n
p
A
.315 BSC
.000
INCHES
.026 BSC
MIN
44
NOM MAX
.002 0
8.00 BSC
MILLIMETERS*
.039
MIN
44
0.65 BSC
NOM
0.05
1.00
.010 REFBase Thickness A3 0.25 REF
JEDEC equivalent: M0-220
0.90.035
.001 0.02
.315 BSC 8.00 BSC
Lead Length L .014 .016 .018 0.35 0.40 0.45
E2
D2
Exposed Pad Width
Exposed Pad Length .262 .268 .274 6.65 6.80 6.95
.262 .268 .274 6.65 6.80 6.95
D2
D
A1
A3
A
TOP VIEW
n
1
L
E2
BOTTOM VIEW
B
E
2
PAD
METAL
EXPOSED
p
PIN 1
INDEX ON
EXPOSED PAD
TOP MARKING
INDEX ON
OPTIONAL PIN 1
.031 0.80
Note: For the most cu rr e nt pac ka ge dr aw i ngs, p le ase se e t he Mi c ro c hi p Pa ck ag ing Specifica t i on lo ca t ed
at http:/ /www.microchip.com/packaging
2001-2013 Microchip Technology Inc. DS39582C-page 215
PIC16F87XA
28-Lead Skinny Plastic Dua l In- lin e (SP) – 300 mil (PDIP)
1510515105
Mold Draft Angle Bottom 1510515105
Mold Draft Angle Top 10.928.898.13.430.350.320
eB
Overall Row Spacing § 0.560.480.41.022.019.016BLower Lead Width 1.651.331.02.065.053.040B1Upper Lea d Width 0.380.290.20.015.012.008
c
Lead Thickness 3.433.303.18.135.130.125LTip to Seating Plane 35.1834.6734.161.3851.3651.345DOverall Leng th 7.497.246.99.295.285.275E1Molded Package Width 8.267.877.62.325.310.300EShoulder to Shoulder Width 0.38.015A1Base to Seating Plane 3.433.303.18.135.130.125A2Molded Package Thickness 4.063.813.56.160.150.140ATop to Seating Plane 2.54
.100
p
Pitch 2828
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
n
E1
c
eB
E
p
L
A2
B
B1
A
A1
Notes:
JEDEC Equivalent: MO-095
Drawing No. C04-070
* Controlling Parameter
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
§ Significant Characteristic
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microc hi p.c om/p ackagi ng
PIC16F87XA
DS39582C-page 216 2001-2013 Microchip Technology Inc.
28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
Foot Angle Top 048048
1512015120
Mold Draft Angle Bottom 1512015120
Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.330.280.23.013.011.009
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 18.0817.8717.65.712.704.695DOverall Length 7.597.497.32.299.295.288E1Molded Package Width 10.6710.3410.01.420.407.394EOverall Width 0.300.200.10.012.008.004A1Standoff § 2.392.312.24.094.091.088A2Molded Package Thickness 2.642.502.36.104.099.093AOverall Height 1.27.050
p
Pitch 2828
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
p
n
B
E
E1
L
c
45
h
A2
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
§ Significant Characteristic
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
2001-2013 Microchip Technology Inc. DS39582C-page 217
PIC16F87XA
28-Lead Plastic Shrink Small Outl ine (SS) – 209 mil, 5.30 mm (SSOP)
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-150
Drawing No. C04-073
10501050Mold Draft Angle Bottom 10501050
Mold Draft Angle Top 0.380.320.25.015.013.010BLead Width 203.20101.600.00840
Fo ot Angle 0.250.180.10.010.007.004
c
Lead Thickness 0.940.750.56.037.030.022LFoot Length 10.3410.2010.06.407.402.396DOverall Length 5.385.255.11.212.207.201E1Molded Packa ge Width 8.107.857.59.319.309.299EOverall Width 0.250.150.05.010.006.002A1Standoff § 1.831.731.63.072.068.064A2Mol d ed Packa ge Thickness 1.981.851.73.078.073.068AOverall Height 0.65.026
p
Pitch 2828
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERS*INCHESUnits
2
1
D
p
n
B
E1
E
L
c
A2
A1
A
§ Significant Characteristic
Note: For the most current pack age drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
PIC16F87XA
DS39582C-page 218 2001-2013 Microchip Technology Inc.
28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body, Punch Singulated (QFN)
Lead Width
*Controlling Parameter
Drawing No. C04-114
Notes:
Mold Draft Angle Top
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
B
α
.009
12°
.011 .014 0.23
12°
0.28 0.35
Pitch
Number of Pins
Overall Width
Standoff
Molded Package Length
Overall Length
Molded Package Width
Molded Package Thickness
Overall Height
MAX
Units
Dimension Limits
A2
A1
E1
D
D1
E
n
p
A
.026
.236 BSC
.000
.226 BSC
INCHES
.026 BSC
MIN
28
NOM MAX
0.65
.031
.002 0.00
6.00 BSC
5.75 BSC
MILLIMETERS*
.039
MIN
28
0.65 BSC
NOM
0.80
0.05
1.00
.008 REFBase Thickness A3 0.20 REF
JEDEC equivalent: mMO-220
0.85.033
.0004 0.01
.236 BSC
.226 BSC
6.00 BSC
5.75 BSC
Lead Length
Tie Bar Width
L .020 .024 .030 0.50 0.60 0.75
R .005 .007 .010 0.13 0.17 0.23
Tie Bar Length Q.012 .016 .026 0.30 0.40 0.65
Chamfer CH .009 .017 .024 0.24 0.42 0.60
E2
D2
Exposed Pad Width
Exposed Pad Length .140 .146 .152 3.55 3.70 3.85
.140 .146 .152 3.55 3.70 3.85
D
E
E1
n
1
2
D1
A
A2
EXPOSED
METAL
PADS
BOTTOM VIEW
TOP VIEW
Q
L
R
p
A1
A3
α
CH X 45°
B
D2
E2
Note: For the most cu rr e nt pac ka ge dr aw i ngs, p le ase se e t he Mi c ro c hi p Pa ck ag ing Specifica t i on lo ca t ed
at http:/ /www.microchip.com/packaging
2001-2013 Microchip Technology Inc. DS39582C-page 219
PIC16F87XA
APPENDIX A: REVISION HISTORY
Revision A (November 2001)
Original data sheet for PIC16F87XA devices. The
devices presented are enhanced versions of the
PIC16F87X microcontrollers discussed in the
“PIC16F87X Data Sheet” (DS30292).
Revision B (October 2003)
This revision includes the DC and AC Characteristics
Graphs and Tables. The Electrical Specifications in
Section 1 7.0 “Electrical Characteristics” have been
updated and there have been minor corrections to the
data sheet text.
Revision C (January 2013)
Added a note to each package outline drawing.
APPENDIX B: DEVICE
DIFFERENCES
The differences betwe en th e dev ic es in th is dat a she et
are listed in Table B-1.
TABLE B-1: DIFFERENCES BETWEEN DEVICES IN THE PIC16F87XA FAMILY
PIC16F873A PIC16F874A PIC16F876A PIC16F877A
Flash Program Memory
(14-bit words) 4K 4K 8K 8K
Data Memory (bytes) 192 192 368 368
EEPROM Data Memory (bytes) 128 128 256 256
Interrupts 14 15 14 15
I/O Ports Ports A, B, C Ports A, B, C, D, E Ports A, B, C Ports A, B, C, D, E
Serial Communications MSSP, USART MSSP, USART MSSP, USART MSSP, USART
Parallel Slave Port No Yes No Yes
10-bit Analog-to-Digital Module 5 input channels 8 input channels 5 input channels 8 input channels
Packages 28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QF N
40-pin PDIP
44-pin PLCC
44-pin TQ FP
44-pin Q FN
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
40-pin PDIP
44-pin PLCC
44-pin TQFP
44-pin QFN
PIC16F87XA
DS39582C-page 220 2001-2013 Microchip Technology Inc.
APPENDIX C: CONVERSION
CONSIDERATIONS
Considerations for converting from previous versions
of de vices to the one s listed in th is dat a sheet are liste d
in Table C-1.
TABLE C-1: CONVERSION CONSIDERATIONS
Characteristic PIC16C7X PIC16F87X PIC16F87XA
Pins 28/40 28/40 28/40
Timers 3 3 3
Interrupts 11 or 12 13 or 14 14 or 15
Communication PSP, USART, SSP
(SPI, I2C Slave) PSP, USART, SSP
(SPI, I2C Master/Slave ) PSP, USAR T, SSP
(SPI, I2C Master/Slave)
Frequency 20 MHz 20 MHz 20 MHz
Voltage 2.5V-5.5V 2.2V-5.5V 2.0V-5.5V
A/D 8-bit,
4 conversion clock selects 10-bit,
4 conver si on clo ck selects 10-bit,
7 conve rsi on clock select s
CCP 2 2 2
Comparator — — 2
Comparator Voltage
Reference ——Yes
Prog ram Memory 4K, 8K EPROM 4K, 8K Flash
(Erase/Write on
single-word)
4K, 8K Flash
(Erase/Write on
four-word blo cks)
RAM 192, 368 bytes 192, 368 bytes 192, 368 bytes
EEPROM Data None 128, 256 bytes 128, 256 bytes
Code Protectio n On/Off Segmented , starting at end
of pr ogram me mory On/Off
Program Memory
Write Protection — On/Off Segmented, starting at
beginning of
program memory
Other In-Circuit Debugger,
Low-Voltage Programming In-Circuit De bugger,
Low-Voltage Programming
2001-2013 Microchip Technology Inc. DS39582C-page 221
PIC16F87XA
INDEX
A
A/D ...................................................................................127
Acquisition Requirements ........................................130
ADCON0 Register ....................................................127
ADCON1 Register ....................................................127
ADIF Bit ....................................................................129
ADRESH Register ....................................................127
ADRESL Register ....................................................127
Analog Port Pins .................................................. 49, 51
Associated Registers and Bits .................................133
Calculating Acquisition Time ....................................130
Configuring Analog Port Pins ...................................131
Configuring the Interrupt ..........................................129
Configuring the Module ............................................129
Conversion Clock .....................................................131
Conversions .............................................................132
Converter Characteristics ........................................194
Effects of a Reset .....................................................133
GO/DONE Bit ...........................................................129
Internal Sampling Switch (Rss) Impedance .............130
Operation During Sleep ...........................................133
Result Registers .......................................................132
Source Impedance ...................................................130
A/D Conversion Requirements .........................................195
Absolute Maximum Ratings .............................................173
ACKSTAT .........................................................................101
ADCON0 Register ..............................................................19
ADCON1 Register ..............................................................20
Addressable Universal Synchronous Asynchronous
Receiver Transmitter. See USART.
ADRESH Register ..............................................................19
ADRESL Register ..............................................................20
Analog-to-Digital Converter. See A/D.
Application Notes
AN552 (Implementing Wake-up
on Key Stroke) ...................................................44
AN556 (Implementing a Table Read) ........................30
Assembler
MPASM Ass e mbler ..................................................167
Asynchronous Reception
Associated Registers ....................................... 118, 120
Asynchronous Transmission
Associated Registers ...............................................116
B
Banking, Data Memory ................................................. 16, 22
Baud Rate Generator .........................................................97
Associated Registers ...............................................113
BCLIF .................................................................................28
BF .....................................................................................101
Block Diagrams
A/D ...........................................................................129
Analog Input Model .......................................... 130, 139
Baud Rate Generator .................................................97
Capture Mode Operation ...........................................65
Comparator I/O Operating Modes ............................136
Comparator Output ..................................................138
Comparator Voltage Reference ...............................142
Compare Mode Operation .........................................66
Crystal/Ceramic Resonator Operation
(HS, XT or LP Osc Configuration) ....................145
External Clock Input Operation
(HS, XT or LP Osc Configuration) ....................145
Interrupt Logic .......................................................... 153
MSSP (I2C Mode) ...................................................... 80
MSSP (SPI Mode) ..................................................... 71
On-Chip Reset Circuit .............................................. 147
PIC16F873A/PIC16F 876A Arc hitecture ...................... 6
PIC16F874A/PIC16F 877A Arc hitecture ...................... 7
PORTC
Peripheral Output Override
(RC2:0, RC7:5) Pins .................................. 46
Peripheral Output Override (RC4:3) Pins .......... 46
PORTD (in I/O Port Mode) ......................................... 48
PORTD and PORTE (Parallel Slave Port) ................. 51
PORTE (In I/O Port Mode) ......................................... 49
RA3:RA0 Pins ............................................................ 41
RA4/T0CKI Pin .......................................................... 42
RA5 Pin ..................................................................... 42
RB3:RB0 Pins ............................................................ 44
RB7:RB4 Pins ............................................................ 44
RC Oscillator Mode .................................................. 146
Recommended MCLR Ci rcuit .................................. 148
Simplified PWM Mode ............................................... 67
Timer0/WDT Prescaler .............................................. 53
Timer1 ....................................................................... 58
Timer2 ....................................................................... 61
USART Receive ................................................117, 119
USART Transmit ...................................................... 115
Watchdog Timer ...................................................... 155
BOR. See Brown-out Reset.
BRG. See Baud Rate Generator.
BRGH Bit ......................................................................... 113
Brown-out Reset (BOR) .................... 143, 147, 148, 149, 150
BOR Status (BOR Bit) ............................................... 29
Bus Collision During a Repeated Start Condition ............ 108
Bus Collision During a Start Condition ............................. 106
Bus Collision During a Stop Condition ............................. 109
Bus Collision Interrupt Flag bit, BCLIF ............................... 28
C
C Compilers
MPLAB C17 ............................................................. 168
MPLAB C18 ............................................................. 168
MPLAB C30 ............................................................. 168
Capture/Compare/PWM (CCP) ......................................... 63
Associated Registers
Capture, Compare and Timer1 .......................... 68
PWM and Timer2 ............................................... 69
Capture Mode ............................................................ 65
CCP1IF .............................................................. 65
Prescaler ........................................................... 65
CCP Timer Resources ............................................... 63
Compare
Special Event Trigger Output of CCP1 .............. 66
Special Event Trigger Output of CCP2 .............. 66
Compare Mode .......................................................... 66
Software Interrupt Mode .................................... 66
Special Event Trigger ........................................ 66
Interaction of Two CCP Modules (table) .................... 63
PWM Mo de ................................................................ 67
Duty Cycle ......................................................... 67
Example Frequencies/Resolution s (table) ......... 68
PWM Period ...................................................... 67
Special Event Trigger and A/D Conversions ............. 66
PIC16F87XA
DS39582C-page 222 2001-2013 Microchip Technology Inc.
Capture/Compare/PWM Requirements
(CCP1 and CCP2) ....................................................186
CCP. See Captur e/Compare/ PWM.
CCP1CON Register ...........................................................19
CCP2CON Register ...........................................................19
CCPR1H Register ........................................................19, 63
CCPR1L Register .........................................................19, 63
CCPR2H Register ........................................................19, 63
CCPR2L Register .........................................................19, 63
CCPxM0 Bit ........................................................................64
CCPxM1 Bit ........................................................................64
CCPxM2 Bit ........................................................................64
CCPxM3 Bit ........................................................................64
CCPxX Bit ..........................................................................64
CCPxY Bit ..........................................................................64
CLKO and I/O Timing Requirements ...............................183
CMCON Register ...............................................................20
Code Examples
Call of a Subroutine in Page 1 from Page 0 ...............30
Indirect Addressing ....................................................31
Initiali z ing P O RTA ......................................................41
Loading the SSPBUF (SSPSR ) Register ...................74
Reading Data EEPROM .............................................35
Reading Flash Program Memory ...............................36
Saving Status, W and PCLATH Registers
in RAM ............................................................154
Writing to Data EEPROM ...........................................35
Writing to Flash Program Memory .............................38
Code Protection .......................................................143, 157
Comparator Module .........................................................135
Analog Input Connection
Considerations .................................................139
Associated Registers ...............................................140
Configuration ............................................................136
Effects of a Reset .....................................................139
Interrupts ..................................................................138
Operation .................................................................137
Operation During Sleep ............................................139
Outputs .....................................................................137
Reference .................................................................137
Response Time ........................................................137
Comparator Specifications ...............................................180
Comparator Voltage Reference .......................................141
Associated Registers ...............................................142
Computed GOTO ...............................................................30
Configuration Bits .............................................................143
Configuration Word ..........................................................144
Conversion Considerations ..............................................220
CVRCON Register .............................................................20
D
Data EEPROM and Flash Program Memory
EEADR Register ........................................................33
EEADRH Register ......................................................33
EECON1 Register ......................................................33
EECON2 Register ......................................................33
EEDATA Register ......................................................33
EEDATH Register ......................................................33
Data EEPROM Memory
Associated Registers ................................................. 39
EEADR Register ........................................................ 33
EEADRH Register ..................................................... 33
EECON1 Register ...................................................... 33
EECON2 Register ...................................................... 33
Operation During Code-Protect ................................. 39
Protection Against Spurious Writes ........................... 39
Reading ..................................................................... 35
Write Complete Flag Bit (EEIF) ................................. 33
Writing ........................................................................ 35
Data Memory ..................................................................... 16
Ban k Selec t (RP1:RP0 Bit s) .................................16, 22
General Purpose Registers ....................................... 16
Register File Map ..................................................17, 18
Special Function Registers ........................................ 19
DC and AC Characteristics Graphs and Tables .............. 197
DC Characteristics ....................................................175–179
Demonstration Boards
PICDEM 1 ................................................................ 170
PICDEM 17 .............................................................. 170
PICDEM 18R PIC18C601/801 ................................. 171
PICDEM 2 Plus ........................................................ 170
PICDEM 3 PIC16C92X ............................................ 170
PICDEM 4 ................................................................ 170
PICDEM LIN PIC16C43X ........................................ 171
PICDEM USB PIC16C7X5 ...................................... 171
PICDEM.net Internet/Ethernet ................................. 170
Development Support ...................................................... 167
Device Differences ........................................................... 219
Device Overview .................................................................. 5
Direct Addressing ............................................................... 31
E
EEADR Register ...........................................................21, 33
EEADRH Register .........................................................21, 33
EECON1 Register .........................................................21, 33
EECON2 Register .........................................................21, 33
EEDATA Register .............................................................. 21
EEDATH Register .............................................................. 21
Electrical Characteristics .................................................. 173
Errata ................................................................................... 4
Evaluation and Programming Tools ................................. 171
External Clock Timing Requirements ............................... 182
External Interrupt Input (RB0/INT). See Interrupt Sources.
External Reference Signal ............................................... 137
F
Firmware In structions ....................................................... 159
Flash Program Memory
Associated Registers ................................................. 39
EECON1 Register ...................................................... 33
EECON2 Register ...................................................... 33
Reading ..................................................................... 36
Writing ........................................................................ 37
FSR Register ..........................................................19, 20, 31
G
General Call Address Support ........................................... 94
2001-2013 Microchip Technology Inc. DS39582C-page 223
PIC16F87XA
I
I/O Por ts .............................................................................41
I2C Bus Data Requirements ............................................192
I2C Bus Start/Stop Bits Requirements .............................191
I2C Mode
Registers ....................................................................80
I2C Mode ............................................................................80
ACK Pulse ............................................................ 84, 85
Acknowledge Sequence Timing ...............................104
Baud Rate Generator .................................................97
Bus Collision
Repeated Start Condition .................................108
Start Condition .................................................106
Stop Condition .................................................109
Clock Arbitration .........................................................98
Effect of a Reset ......................................................105
General Call Address Support ...................................94
Master Mode ..............................................................95
Operation ...........................................................96
Repeated Start Timing .....................................100
Master Mode Reception ...........................................101
Master Mode Start Condition .....................................99
Master Mode Transmission ......................................101
Multi-Master Communication, Bus Collision
and Arbitration ..................................................105
Multi-Master Mode ...................................................105
Read/Write Bit Information (R/W Bit) ................... 84, 85
Serial Clock (RC3/SCK/SCL) .....................................85
Slave Mode ................................................................84
Addressing .........................................................84
Reception ...........................................................85
Transmission ......................................................85
Sleep Operation .......................................................105
Stop Condition Timing ..............................................104
ID Locations ............................................................. 143, 157
In-Circuit Debugger .................................................. 143, 157
Resources ................................................................157
In-Circuit Serial Programming (ICSP ) ...................... 143, 158
INDF Register .........................................................19, 20, 31
Indirect Addressing ............................................................31
FSR Register .............................................................16
Instruction Format ............................................................159
Instruction Set ..................................................................159
ADDLW ....................................................................161
ADDWF ....................................................................161
ANDLW ....................................................................161
ANDWF ....................................................................161
BCF ..........................................................................161
BSF ..........................................................................161
BTFSC .....................................................................161
BTFSS .....................................................................161
CALL ........................................................................162
CLRF ........................................................................162
CLRW ......................................................................162
CLRWDT ..................................................................162
COMF ......................................................................162
DECF .......................................................................162
DECFSZ ...................................................................163
GOTO ......................................................................163
INCF .........................................................................163
INCFSZ ....................................................................163
IORLW .....................................................................163
IORWF .....................................................................163
RETURN ..................................................................164
RLF ..........................................................................164
RRF ......................................................................... 164
SLEEP ..................................................................... 164
SUBLW .................................................................... 164
SUBWF .................................................................... 164
SWAPF .................................................................... 165
XORLW ................................................................... 165
XORWF ................................................................... 165
Summary Table ....................................................... 160
INT Interrup t (R B0 / IN T). See Interrupt Sources.
INTCON Register ............................................................... 24
GIE Bit ....................................................................... 24
INTE Bit ..................................................................... 24
INTF Bit ..................................................................... 24
PEIE Bit ..................................................................... 24
RBIE Bit ..................................................................... 24
RBIF Bit ................................................................24, 44
TMR0IE Bit ................................................................ 24
TMR0IF Bit ................................................................. 24
Inter-Integrated Circuit. See I2C.
Internal Reference Signal ................................................ 137
Internal Sampling Switch (Rss) Impedance ..................... 130
Interrupt Sources ......................................................143, 153
Interrupt-on-Change (RB7:RB4) ................................ 44
RB0/INT Pin, External .....................................9, 11, 154
TMR0 Overflow ........................................................ 154
USART Receive/Transmit Complete ....................... 111
Interrupts
Bus Collision Interrupt ................................................ 28
Synchronous Serial Port Interrupt .............................. 26
Interrupts, Context Saving During .................................... 154
Interrupts, Enable Bits
Global Interrupt Enable (GIE Bit) ........................24, 153
Interrupt-on-Change (RB7:RB4)
Enable (RBIE Bit) .......................................24, 154
Peripheral Interrupt Enable (PEIE Bit) ....................... 24
RB0/INT Enable (INTE Bit) ........................................ 24
TMR0 Overflow Enable (TMR0IE Bit) ........................ 24
Interrupts, Flag Bits
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit) ..............................................24, 44, 154
RB0/INT Flag (INTF Bit) ............................................ 24
TMR0 Overflow Flag (TMR0IF Bit) .....................24, 154
L
Loading of PC .................................................................... 30
Low-Voltage ICSP Programm ing ..................................... 158
Low-Voltage In-Circuit Serial Programming ..................... 143
M
Master Clear (MCLR) ........................................................... 8
MCLR Reset, Normal Operation ...............147, 149, 150
MCLR Reset, Sleep ..................................147, 149, 150
Master Synchronous Serial Port (MSSP). See MSSP.
MCLR ............................................................................... 148
MCLR/VPP ......................................................................... 10
Memory Organization ........................................................ 15
Data EEPROM Memory ............................................. 33
Data Memory ............................................................. 16
Flash Program Memory ............................................. 33
Program Memory ....................................................... 15
MPLAB ASM30 Assembler, Linker, Librarian .................. 168
MPLAB ICD 2 In-Circuit Debugger .................................. 169
MPLAB ICE 2000 High-Perf orm ance Univers al
In-Circuit Emulator ................................................... 169
PIC16F87XA
DS39582C-page 224 2001-2013 Microchip Technology Inc.
MPLAB ICE 4000 High-Performance Universal
In-Circuit Emulator ...................................................169
MPLAB Integrated Development
Environment Software ..............................................167
MPLINK Object Linker/MPLIB Object Librarian ...............168
MSSP .................................................................................71
I2C Mode. See I2C.
SPI Mode ...................................................................71
SPI Mode. See SP I.
MSSP Module
Clock Stretching .........................................................90
Clock Synchronization and the CKP Bit .....................91
Control Registers (General) .......................................71
Operation ...................................................................84
Overview ....................................................................71
SPI Master Mode .......................................................76
SPI Slave Mode .........................................................77
SSPBUF .....................................................................76
SSPSR .......................................................................76
Multi-Master Mode ...........................................................105
O
Opcode Field Descriptions ...............................................159
OPTION_REG Register .....................................................23
INTEDG Bit ................................................................23
PS2:PS0 Bits ..............................................................23
PSA Bit .......................................................................23
RBPU Bit ....................................................................23
T0CS Bit .....................................................................23
T0SE Bit .....................................................................23
OSC1/CLKI Pin ..............................................................8, 10
OSC2/CLKO Pin ............................................................8, 10
Oscillator Configuration
HS ....................................................................145, 149
LP .....................................................................145, 149
RC ............................................................ 145, 146, 149
XT .....................................................................145, 149
Oscillator Selection ..........................................................143
Oscillator Start-up Timer (OST) ...............................143, 148
Oscillator, WDT ................................................................155
Oscillators
Capacitor Selection ..................................................146
Ceramic Resonator Selection ..................................145
Crystal and Ceramic Resonators .............................145
RC ............................................................................146
P
Package Information
Marking ....................................................................209
Packaging Information .....................................................209
Paging, Program Memory ..................................................30
Parallel Slave Port (PSP) ....................................... 13, 48, 51
Associated Registers .................................................52
RE0/RD/AN5 Pin ..................................................49, 51
RE1/WR/AN6 Pi n .................................................49, 51
RE2/CS/AN7 Pin ..................................................49, 51
Select (PSPMODE Bit) ..............................48, 49, 50, 51
Parallel Slave Port Requirements
(PIC16F874A/ 877A Only) .......................................187
PCL Register .......................................................... 19, 20, 30
PCLATH Register ................................................... 19, 20, 30
PCON Register .................................................... 20, 29, 149
BOR Bit ......................................................................29
POR Bit ......................................................................29
PIC16F87XA Product Identification System .....................231
PICkit 1 Flash Starter Kit ..................................................171
PICSTART Plus Deve lopment Program mer .................... 169
PIE1 Register ................................................................20, 25
PIE2 Register ................................................................20, 27
Pinout Descriptions
PIC16F873A/PIC16F876A ........................................... 8
PIR1 Register ...............................................................19, 26
PIR2 Register ...............................................................19, 28
POP ................................................................................... 30
POR. See Power-on Reset.
PORTA ...........................................................................8, 10
Associated Registers ................................................. 43
Functions ................................................................... 43
PORTA Register ...................................................19, 41
TRISA Register .......................................................... 41
PORTB ...........................................................................9, 11
Associated Registers ................................................. 45
Functions ................................................................... 45
PORTB Register ...................................................19, 44
Pull-up Enable (RBPU Bit) ......................................... 23
RB0/INT Edge Select (INTEDG Bit) .......................... 23
RB0/INT Pin, External .....................................9, 11, 154
RB7:RB4 Interrupt-on-Change ................................ 154
RB7:RB4 Interrupt-on-Change Enable
(RBIE Bit) ....................................................24, 154
RB7:RB4 Interrupt-on-Change Flag
(RBIF Bit) ..............................................24, 44, 154
TRISB Register .....................................................21, 44
PORTB Register ................................................................ 21
PORTC ...........................................................................9, 12
Associated Registers ................................................. 47
Functions ................................................................... 47
PORTC Register ...................................................19, 46
RC3/SCK/SCL Pin ..................................................... 85
RC6/TX/CK Pin ........................................................ 112
RC7/RX/DT Pin .................................................112, 113
TRISC Register ...................................................46, 111
PORTD .........................................................................13, 51
Associated Registers ................................................. 48
Functions ................................................................... 48
Parallel Slave Port (PSP) Function ............................ 48
PORTD Register ...................................................19, 48
TRISD Register .......................................................... 48
PORTE .............................................................................. 13
Analog Port Pins ...................................................49, 51
Associated Registers ................................................. 50
Functions ................................................................... 49
Input Buffer Full Status (IBF Bit) ................................ 50
Input Buffer Overflow (IBOV Bit) ................................ 50
Output Buffer Full Status (OBF Bit) ........................... 50
PORTE Register ...................................................19, 49
PSP Mode Selec t (PS PM ODE Bit) ...........48, 49, 50, 51
RE0/RD/AN5 Pin ..................................................49, 51
RE1/WR/AN6 Pin ..................................................49, 51
RE2/CS/AN7 Pin ...................................................49, 51
TRISE Register .......................................................... 49
Postscaler, WDT
Assignment (PSA Bit) ................................................ 23
Rate Select (PS2:P S0 Bits) ....................................... 23
Power-down Mode. See Sleep.
Power-on Reset (POR) .....................143, 147, 148, 149, 150
POR Status (POR Bit) ............................................... 29
Power Control (PCON) Register .............................. 149
Power-down (PD Bit) ..........................................22, 147
Power-up Timer (PW RT ) ......................................... 143
Time-out (TO Bit) ................................................22, 147
2001-2013 Microchip Technology Inc. DS39582C-page 225
PIC16F87XA
Pow er-up Timer (PWRT) ..................................................148
PR2 Register ................................................................ 20, 61
Prescaler, Timer0
Assignment (PSA Bit) ................................................23
Rate Select (PS2:P S0 Bi t s) .......................................23
PRO MATE II Universal Device Programmer ..................169
Program Counter
Reset Conditions ......................................................149
Program Mem ory ...............................................................15
Interrupt Vector ..........................................................15
Paging ........................................................................30
Program Memo ry Map and Stack
(PIC16F873A/874A) ...........................................15
Program Memo ry Map and Stack
(PIC16F876A/877A) ...........................................15
Reset Vector ..............................................................15
Program Verification .........................................................157
Programming Pin (VPP) ........................................................8
Programming, Device Instructions ...................................159
PSP. See Para llel Sl ave Port.
Pulse Width Modulation. See Capture/Compare/PWM ,
PWM Mode.
PUSH .................................................................................30
R
RA0/AN0 Pin .................................................................. 8, 10
RA1/AN1 Pin .................................................................. 8, 10
RA2/AN2/VREF-/CVREF Pin ............................................ 8, 10
RA3/AN3/VREF+ Pin ....................................................... 8, 10
RA4/T0CKI/C1OUT Pin .................................................. 8, 10
RA5/AN4/SS/C2OUT Pin ............................................... 8, 10
RAM. See Data Memory .
RB0/INT Pin ................................................................... 9, 11
RB1 Pin .......................................................................... 9, 11
RB2 Pin .......................................................................... 9, 11
RB3/PGM Pin ................................................................. 9, 11
RB4 Pin .......................................................................... 9, 11
RB5 Pin .......................................................................... 9, 11
RB6/PGC Pin ................................................................. 9, 11
RB7/PGD Pin ................................................................. 9, 11
RC0/T1OSO/T1CKI Pin ................................................. 9, 12
RC1/T1OSI/CCP2 Pin .................................................... 9, 12
RC2/CCP1 Pin ............................................................... 9, 12
RC3/SCK/SCL Pin ......................................................... 9, 12
RC4/SDI/SDA Pin .......................................................... 9, 12
RC5/SDO Pin ................................................................. 9, 12
RC6/TX/CK Pin .............................................................. 9, 12
RC7/RX/DT Pin .............................................................. 9, 12
RCREG Register ................................................................19
RCSTA Register .................................................................19
ADDEN Bit ...............................................................112
CREN Bit ..................................................................112
FERR Bit ..................................................................112
OERR Bit .................................................................112
RX9 Bit .....................................................................112
RX9D Bit ..................................................................112
SPEN Bit .......................................................... 111, 112
SREN Bit ..................................................................112
RD0/PSP0 Pin ....................................................................13
RD1/PSP1 Pin ....................................................................13
RD2/PSP2 Pin ....................................................................13
RD3/PSP3 Pin ....................................................................13
RD4/PSP4 Pin ....................................................................13
RD5/PSP5 Pin ....................................................................13
RD6/PSP6 Pin ....................................................................13
RD7/PSP7 Pin ....................................................................13
RE0/RD/AN5 Pin ............................................................... 13
RE1/WR/AN6 Pin ............................................................... 13
RE2/CS/AN7 Pin ................................................................ 13
Read-Modify-Write Operations ........................................ 159
Register File ....................................................................... 16
Register File Map (PIC16F873A/874A) ............................. 18
Register File Map (PIC16F876A/877A) ............................. 17
Registers
ADCON0 (A/D Control 0) ......................................... 127
ADCON1 (A/D Control 1) ......................................... 128
CCP1CON/CCP2CON (CCP Control 1
and CCP Control 2) ........................................... 64
CMCON (Comparator Control) ................................ 135
CVRCON (Comparator Voltage
Reference Control) .......................................... 141
EECON1 (EEPROM Control 1) ................................. 34
FSR ........................................................................... 31
INTCON ..................................................................... 24
OPTION_REG ......................................................23, 54
PCON (Power Control) .............................................. 29
PIE1 (Peripheral Interrupt Enable 1) .......................... 25
PIE2 (Peripheral Interrupt Enable 2) .......................... 27
PIR1 (Peripheral Interrupt Request 1) ....................... 26
PIR2 (Peripheral Interrupt Request 2) ....................... 28
RCSTA (Receive Status and Control) ..................... 112
Special Function, Summary ....................................... 19
SSPCON (MS SP Control 1, I2C Mode) ..................... 82
SSPCON (MS SP Control 1, SPI Mode) ..................... 73
SSPCON 2 (M SSP Control 2, I2C Mode) ................... 83
SSPSTAT (MSSP St atus, I2C Mode) ........................ 81
SSPSTA T (MSS P St atus, SPI Mode) ........................ 72
Status ........................................................................ 22
T1CON (Timer1 Control) ........................................... 57
T2CON (Timer2 Control) ........................................... 61
TRISE Register .......................................................... 50
TXSTA (Transmit Status and Control) ..................... 111
Reset ........................................................................143, 147
Brown-out Reset (BOR). See Brown-out Reset (BOR).
MCLR Reset. See MC LR.
Power-on Reset (POR). See Power-on Reset (POR ).
Reset Conditions for PCON Register ...................... 149
Reset Conditions for Program Counter .................... 149
Reset Conditions for Status Register ....................... 149
WDT Reset. See Watchdog Timer (WDT).
Reset, Watchdog Timer, Oscillator Start -up Time r,
Power-up Timer and Brown-out Reset
Requirements .......................................................... 184
Revision History ............................................................... 219
S
SCI. See USART.
SCK ................................................................................... 71
SDI ..................................................................................... 71
SDO ................................................................................... 71
Serial Clock, SCK .............................................................. 71
Serial Communication Interface. See USART.
Serial D a ta In, SDI ............................................................. 71
Serial D a ta O u t, S DO ........................................................ 71
Serial Peripheral Interface. See SP I.
Slave Select Synchronization ............................................ 77
Slave Select, SS ................................................................ 71
Sleep .................................................................143, 147, 156
Software Simulator (MPLAB SIM) ................................... 168
Software Simulator (MPLAB SIM30) ............................... 168
SPBRG Register ................................................................ 20
Special Features of the CPU ........................................... 143
PIC16F87XA
DS39582C-page 226 2001-2013 Microchip Technology Inc.
Special Function Registers ................................................19
Special Function Registers (SFRs ) ....................................19
Speed, Operating .................................................................1
SPI Mode ..................................................................... 71, 77
Associated Registers .................................................79
Bus Mode Compatibility .............................................79
Effects of a Reset .......................................................79
Enabling SPI I/O .........................................................75
Master Mode ..............................................................76
Master/Slave Connection ...........................................75
Serial Clock ................................................................71
Serial D a ta In .............................................................71
Serial Data Out ...........................................................71
Slave Select ...............................................................71
Slave Select Synchronization .....................................77
Sleep Operation .........................................................79
SPI Clock ...................................................................76
Typical Connection .....................................................75
SPI Mode Requirements ..................................................190
SS ......................................................................................71
SSP SPI Master/Slave Connection ....................................75
SSPADD Register ..............................................................20
SSPBUF Register ..............................................................19
SSPCON Register ..............................................................19
SSPCON2 Register ............................................................20
SSPIF .................................................................................26
SSPOV .............................................................................101
SSPSTAT Register ............................................................20
R/W Bit .................................................................84, 85
Stack ..................................................................................30
Overflows ...................................................................30
Underflow ...................................................................30
Status Register
C Bit ...........................................................................22
DC Bit .........................................................................22
IRP Bit ........................................................................22
PD Bit .................................................................22, 147
RP1:RP0 Bits .............................................................22
TO Bit ................................................................. 22, 147
Z Bit ............................................................................22
Synchronous Master Reception
Associated Registers ...............................................123
Synchronous Master Transmission
Associated Registers ...............................................122
Synchronous Serial Port Interrupt ......................................26
Synchronous Slave Reception
Associated Registers ...............................................125
Synchronous Slave Transmission
Associated Registers ...............................................125
T
T1CK P S 0 Bi t ......................................................................57
T1CK P S 1 Bi t ......................................................................57
T1CON Register .................................................................19
T1OSCEN Bit .....................................................................57
T1SYNC Bit ........................................................................57
T2CK P S 0 Bi t ......................................................................61
T2CK P S 1 Bi t ......................................................................61
T2CON Register .................................................................19
TAD ...................................................................................131
Time-out Sequence ..........................................................148
Timer0 ................................................................................ 53
Associated Registers ................................................. 55
Clock Source Edge Select (T0SE Bit ) ....................... 23
Clock Source Sele ct (T0CS Bit) ................................. 23
External Clock ............................................................ 54
Interrupt ..................................................................... 53
Overflow Enable (TMR0IE Bit) ................................... 24
Overflow Flag (TMR0IF Bit) ................................24, 154
Overflow Interrupt .................................................... 154
Prescaler .................................................................... 54
T0CKI ......................................................................... 54
Timer0 and Timer1 External Clock Requirements ........... 185
Timer1 ................................................................................ 57
Associated Registers ................................................. 60
Asynchronous Counter Mode .................................... 59
Reading and Writing to ...................................... 59
Counter Operation ..................................................... 58
Operation in Timer Mode ........................................... 58
Oscillator .................................................................... 59
Capacitor Selection ............................................ 59
Prescaler .................................................................... 60
Resetting of Timer1 Registers ................................... 60
Resetting Timer1 Using a CCP Trigger Output ......... 59
Synchronized Counter Mode ..................................... 58
TMR1H ...................................................................... 59
TMR1L ....................................................................... 59
Timer2 ................................................................................ 61
Associated Registers ................................................. 62
Output ........................................................................ 62
Postscaler .................................................................. 61
Prescaler .................................................................... 61
Prescaler and Postscaler ........................................... 62
Timing Diagrams
A/D Conversion ........................................................ 195
Acknowledge Sequence .......................................... 104
Asynchronous Mast er Transmission ........................ 116
Asynchronous Mast er Transm ission
(Back to Back) ................................................. 116
Asynchronous Recept ion ......................................... 118
Asynchronous Receptio n with
Address Byte Firs t ........................................... 120
Asynchronous Receptio n with
Address Detect ................................................ 120
Baud Rate Generator with Clock Arbitration .............. 98
BRG Reset Due to SDA Arbitration During
Start Condition ................................................. 107
Brown-out Reset ...................................................... 184
Bus Collision During a Repeated
Start Condition (Case 1) .................................. 108
Bus Collision During Repeated
Start Condition (Case 2) .................................. 108
Bus Collision During Start Condition
(SCL = 0) ......................................................... 107
Bus Collision During Start Condition
(SDA Only) ....................................................... 106
Bus Collision During Stop Condition
(Case 1) ........................................................... 109
Bus Collision During Stop Condition
(Case 2) ........................................................... 109
Bus Collision for Transmit and Acknowledge .......... 105
Capture/Compare/PWM (CCP1 and CCP2) ............ 186
CLKO and I/O .......................................................... 183
Clock Synchronization ............................................... 91
External Clock .......................................................... 182
First Start Bit .............................................................. 99
2001-2013 Microchip Technology Inc. DS39582C-page 227
PIC16F87XA
I2C Bus Data ............................................................191
I2C Bus Start/Stop Bits .............................................190
I2C Master Mode (Reception, 7-bit Address) ...........103
I2C Master Mode (Transmission,
7 or 10-bit Address) .........................................102
I2C Slave Mode (Transmission, 10-bit Address) ........89
I2C Slave Mode (Transmission, 7-bit Address) ..........87
I2C Slave Mode with SEN = 1 (Reception,
10-bit Address) ...................................................93
I2C Slave Mode with SEN = 0 (Reception,
10-bit Address) ...................................................88
I2C Slave Mode with SEN = 0 (Reception,
7-bit Address) .....................................................86
I2C Slave Mode with SEN = 1 (Reception,
7-bit Address) .....................................................92
Parallel Slave Port (PIC16F874A/877A Only) ..........187
Parallel Slave Port (PSP) Read .................................52
Parallel Slave Port (PSP) Write .................................52
Repeat Start Condition .............................................100
Reset, Watchdog Timer, Start-up Timer
and Power-up Timer ........................................184
Slave Mode General Call Address Sequence
(7 or 10-bit Address Mode) ................................94
Slave Synchronization ...............................................77
Slow Rise Time (MCLR Tied to VDD via
RC Network) ....................................................152
SPI Master Mode (CKE = 0, SMP = 0) ....................188
SPI Master Mode (CKE = 1, SMP = 1) ....................188
SPI Mode (Master Mode) ...........................................76
SPI Mode (Slave Mode with CKE = 0) .......................78
SPI Mode (Slave Mode with CKE = 1) .......................78
SPI Slave Mode (CKE = 0) ......................................189
SPI Slave Mode (CKE = 1) ......................................189
Stop Condition Receive or Transmit Mode ..............104
Synchronous Reception
(Master Mode, SREN) ......................................124
Synchronous Transmission ......................................122
Synchronous Transmission (T hrough TXEN) ..........122
Time-out Sequence on Power-up
(MCLR Not Tied to VDD)
Case 1 ..............................................................152
Case 2 ..............................................................152
Time-out Sequence on Power-up (MCLR Tied
to VDD via RC Network) ...................................151
Timer0 and Timer1 External Clock ..........................185
USART Synchronous Receive
(Master/Slave) ..................................................193
USART Synchronous Transmission
(Master/Slave) ..................................................193
Wake-up from Sleep via Interrupt ............................157
Timing Parameter Symbology ..........................................181
TMR0 Register ...................................................................19
TMR1CS Bit .......................................................................57
TMR1H Register ................................................................19
TMR1L Register .................................................................19
TMR1ON Bit .......................................................................57
TMR2 Register ...................................................................19
TMR2ON Bit .......................................................................61
TMRO Register ..................................................................21
TOUT P S 0 Bi t .....................................................................61
TOUT P S 1 Bi t .....................................................................61
TOUT P S 2 Bi t .....................................................................61
TOUT P S 3 Bi t .....................................................................61
TRISA Register ..................................................................20
TRISB Register .................................................................. 20
TRISC Register .................................................................. 20
TRISD Register .................................................................. 20
TRISE Register .................................................................. 20
IBF Bit ........................................................................ 50
IBOV Bit ..................................................................... 50
OBF Bit ...................................................................... 50
PSPMO D E Bi t ........................................... 48, 49, 50, 51
TXREG Register ................................................................ 19
TXSTA Register ................................................................. 20
BRGH Bit ................................................................. 111
CSRC Bit ................................................................. 111
SYNC Bit ................................................................. 111
TRMT Bit .................................................................. 111
TX9 Bit ..................................................................... 111
TX9D Bit .................................................................. 111
TXEN Bit .................................................................. 111
U
USART ............................................................................. 111
Address Detect Enable (AD DEN Bit ) ....................... 112
Asynchronous Mode ................................................ 115
Asynchronous Receive (9-bit Mode) ........................ 119
Asynchronous Receive with Address Detec t.
See Asynchronous Receive (9-bit Mode).
Asynchronous Receiver ........................................... 117
Asynchronous Recept ion ......................................... 118
Asynchronous Tra nsmit ter ....................................... 115
Baud Rate Generator (BRG) ................................... 113
Baud Rate Formula ......................................... 113
Baud Rates, Asynchronous Mode
(BRGH = 0) .............................................. 114
Baud Rates, Asynchronous Mode
(BRGH = 1) .............................................. 114
High Baud Rate Select (BRGH Bit) ................. 111
Sampling .......................................................... 113
Clock Source Select (CSRC Bit) .............................. 111
Continuous Receive Enable (CREN Bit) .................. 112
Framing Error (FERR Bit) ........................................ 112
Mode Selec t (SY NC Bit) .......................................... 111
Overrun Error (OERR Bit ) ........................................ 112
Receive Data, 9th Bit (RX9D Bit) ............................. 112
Receive Enable, 9-bit (RX9 Bit) ............................... 112
Serial Port Enable (SPEN Bit) ..........................111, 112
Single Receive Enable (SREN Bit) .......................... 112
Synchronous Master Mode ...................................... 121
Synchronous Master Reception ............................... 123
Synchronous Master Transmission ......................... 121
Synchronous Slave Mode ........................................ 124
Synchronous Slave Reception ................................. 125
Synchronous Slave Transmit ................................... 124
Transmit Data, 9th Bit (TX9D) ................................. 111
Transmit Enable (TXEN Bit) .................................... 111
Transmit Enable, 9-bit (TX9 Bit) .............................. 111
Transmit Shift Register Status (TRMT Bit) .............. 111
USART Synchronous Receive Requirem ents ................. 193
V
VDD Pin ...........................................................................9, 13
Voltage Reference Specifications .................................... 180
VSS Pin ...........................................................................9, 13
PIC16F87XA
DS39582C-page 228 2001-2013 Microchip Technology Inc.
W
Wake-up from Sleep ................................................143, 156
Interrupts ..........................................................149, 150
MCLR Reset .............................................................150
WDT Reset ...............................................................150
Wake-up Using Interrupts ................................................156
Watchdog Timer
Register Summary ...................................................155
Watchdog Timer (WDT) ...........................................143, 155
Enable (WDTE Bit) ...................................................155
Postscaler. See Postscaler, WDT.
Programming Considerations ...................................155
RC Oscillator ............................................................155
Time-out Period ........................................................155
WDT Reset, Normal Operation ................ 147, 149, 150
WDT Reset, Sleep ................................... 147, 149, 150
WCOL ................................................................ 99, 101, 104
WCOL Status Flag .............................................................99
WWW, On-Line Support .......................................................4
2001-2013 Microchip Technology Inc. DS39582C-page 229
PIC16F87XA
THE MICROCHIP WEB SITE
Microc hip pro vides onl ine s upport v ia our W WW site at
www.microchip.com. This web site is used as a m ean s
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
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•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
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program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specif ied produ ct family or develo pment tool of interes t.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPP ORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is avail able throug h the web si te
at: http://microchip.com/support
PIC16F87XA
DS39582C-page 230 2001-2013 Microchip Technology Inc.
READER RESP ONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
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Please list the following information, and use this outline to provide us with your comments about this document.
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DS39582CPIC16F87XA
1. What are the best features of this d ocument?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any inco rrect or misleading information (what and where)?
7. How would you improve this document?
2001-2013 Microchip Technology Inc. DS39582C-page 231
PIC16F87XA
PIC16F87XA PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device PIC16F87XA(1), PIC16F 87 X AT (2); VDD range 4.0V to 5.5V
PIC16LF87XA(1), PIC16LF87XAT(2); VDD range 2.0V to 5.5V
Temperatu re Rang e I = -40C to +85C (Industrial)
Package ML = QFN (Metal Lead Frame)
PT = TQFP (Thin Quad Flatpack)
SO = SOIC
SP = Skinny Plastic DIP
P=PDIP
L=PLCC
S = SSOP
Examples:
a) PIC16F873A-I/P 301 = Industrial temp., PDIP
package, normal VDD limits, QTP pattern #301.
b) PIC16LF876A-I/SO = Industrial temp., SOIC
package, Extended VDD limits.
c) PIC16F877A-I/P = Industrial temp., PDIP package,
10 MHz, normal VDD limits.
Note 1: F = CMOS Flash
LF = Low-Power CMOS Flash
2: T = in tape and reel - SOIC, PLCC,
TQFP packages only
2001-2013 Microchip Technology Inc. DS39582C-page 232
PIC16F87XA
NOTES:
2001-2013 Microchip Technology Inc. DS39582C-page 233
Information contained in this publication regarding device
applications and the lik e is p ro vided only for your convenien ce
and may be superseded by u pdates. I t is your res ponsibilit y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip T echnology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor ,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense , HI-TIDE, In-Circ u it Se r i a l
Programm ing, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II Gm bH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2001-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620769621
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contai ned in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPI C® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS39582C-page 234 2001-2013 Microchip Technology Inc.
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Taiwa n - Ka ohs iung
Tel: 886-7-213-7828
Fax: 886-7-330-9305
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangko k
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Cop e nha gen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-14 4-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08 -91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Worldwide Sales and Service
11/29/12
