TLE7242-2G
4 Channel Fixed Frequency Constant Current
Control IC
Data Sheet, Rev. 1.1, May 2011
Automotive Power
Data Sheet 2 Rev. 1.1, 2011-05-27
TLE7242-2G
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3.1 On / Off Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3.2 Constant Current Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 Functional Description and Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Supply and Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Input / Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3.1 On-State Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3.2 Off-State Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.4 Output Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.5 Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.6 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.6.1 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.6.2 SPI Message Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.6.2.1 SPI Message #0 - IC Version / Manufacturer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.6.2.2 SPI Message #1 - Main Period Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.6.2.3 SPI Message #2 - PWM Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.6.2.4 SPI Message #3 - Current Set Point and Dither Amplitude Set . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.6.2.5 SPI Message #4 - Dither Period Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.6.2.6 SPI Message #5 - Control Variable Set (KP and KI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.6.2.7 SPI Message #6 - Dynamic Threshold Value Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.6.2.8 SPI Message #7 - On/Off Control and Fault Mask Configuration . . . . . . . . . . . . . . . . . . . . . . . . 38
5.6.2.9 SPI Message #8 - Diagnostic Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.6.2.10 SPI Message #9 - Diagnostic Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.6.2.11 SPI Message #10 - Current Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.6.2.12 SPI Message #11 - Autozero Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.6.2.13 SPI Message #12 - Duty Cycle Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1 Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table of Contents
PG-DSO-28
Type Package Marking
TLE7242-2G PG-DSO-28 TLE7242-2G
Data Sheet 3 Rev. 1.1, 2011-05-27
4 Channel Fixed Frequency Constant Current Control
IC
TLE7242-2G
1Overview
1.1 Features
• Low side constant current control pre-driver integrated circuit
• Four independent channels
• Output current programmable with 11 bit resolution
– Current range = 0 to 1.2A (typ) with a 0.2 sense resistor
– Resolution = 0.78125 mA/bit (typ) with a 0.2 sense resistor
– +/- 2% full scale error over temperature when autozero is used
• Programmable PWM frequency via SPI from approximately
50 Hz to 4 KHz (typ)
• Programmable KP and KI coefficients for the PI controller for each
channel
• Programmable Transient Mode of operation to reduce settling time when large changes in the current set point
are commanded.
• Programmable superimposed dither.
– Dither programmed by setting a dither step size and the number of PWM periods in each dither period
– Programmed via the SPI interface
– The dither for each channel can be enabled and programmed independently
• Programmable synchronization of the PWM control signals.
– Phase delay time set via the SPI interface
– Synchronization initiated via signal at the PHASE_SYNC input pin.
– Channels within one device and between multiple devices can be synchronized.
• Each channel can be configured to function as a simple on/off predriver or a constant current predriver via SPI
• Interface and Control
– 32 Bit SPI (Serial Peripheral Interface) - Slave only
– ENABLE pin to disable all channels or freeze all channels
– Active low RESET_B pin resets internal registers to their default state and disables all channels.
– Open drain FAULT pin can be programmed to transition low when various faults are detected.
– 5.0V and 3.3V logic compatible I/O
• Protection
– Over current shutdown - monitored at POSx pin.
– Programmable over current threshold
– Programmable over current delay time
– Programmable over current retry time
– Battery pin (BAT) overvoltage shutdown.
• Diagnostics
– Over current
TLE7242-2G
Overview
Data Sheet 4 Rev. 1.1, 2011-05-27
– Open load in on state
– Open load in off state
– Short to ground
– Test complete bit - indicates that fault detection test has completed
• Control loop monitor capabilities
– The average current measurement over the last completed PWM cycle of each channel can be accessed
via SPI.
– The PWM duty cycle of each channel can be accessed via SPI
– The auto zero values used to null the offsets of the input amplifiers can be accessed via SPI
• Required External Components:
– N-Channel Logic level (5V) MOSFET transistor with typical Ron 100 m (e.g. BSO604NS2)
– Recirculation diode (ultrafast)
– Sense resistor (0.2for 1.2A average output current range)
• Green Product (RoHS compliant)
• AEC Qualified
1.2 Applications
• Variable Force Solenoids (e.g. automatic transmission solenoids)
• Other constant current solenoids
– Idle Air Control
– Exhaust Gas Recirculation
– Vapor Management Valve
– Suspension Control
1.3 General Description
The TLE7242 2G IC is a four channel low-side constant current control predriver IC. Each channel can be
configured to function either in on/off mode or in constant current mode by setting the appropriate MODE bit in SPI
message #7.
1.3.1 On / Off Mode Operation
For On/Off operation, the POSx and NEGx pins must be connected to the circuit in either of the configurations
shown in Figure 1. If the sense resistor is included, the load current can be monitored by the microcontroller via
a SPI command. The open load in on state fault detection feature is disabled in on/off mode.
Note: An external flyback clamp is required in this configuration otherwise the IC may be damaged.
Data Sheet 5 Rev. 1.1, 2011-05-27
TLE7242-2G
Overview
Figure 1 External Circuit Diagram for On/Off Mode Operation
1.3.2 Constant Current Mode Operation
During constant current operation, the POSx and NEGx pins must be connected to the circuit in the configuration
shown in Figure 2.
Note: An external recirculation diode is required in this configuration otherwise the IC may be damaged.
Figure 2 External Circuit Diagram for Constant Current Mode Operation
The constant current control circuit can operate in two modes; steady state mode and transient mode.
Steady-State Mode
During steady-state operation, the PWM control signal driven at the OUTx pin is controlled by the control loop
shown in Figure 3. The PWM Frequency is programmed via the SPI message # 1. In this message the main period
divider, N, can be set to any value between 79 and 214 -1. The equation for calculating the PWM frequency is:
Solenoid
RSENSE
POSx
NEGx
OUTx
POSx
NEGx
OUTx
RG
RG
QDRV
QDRV
Solenoid
CESD CESD
VBAT
VBAT
POSx
NEGx
OUTx
Solenoid
RSENSE
DRECIRC
QDRV
CESD
VBAT
RG
N
F
FCLK
PWM
*32
TLE7242-2G
Overview
Data Sheet 6 Rev. 1.1, 2011-05-27
The 11 bit Current Set Point is programmed via the SPI message #3. The equation for calculating the current
setpoint is:
The Proportional coefficient (KP) and the Integral coefficient (KI) of the control loop are programmed in SPI
message #5. The KP and KI values should be set to values that result in the desired transient response of the
control loop. The duty cycle of the OUTx pin can be calculated from the difference equations:
where error is the difference between the commanded average current and measured average current in units of
Amps.
where k indicates the integral number of PWM periods that have elapsed since current regulation was initiated.
Figure 3 Control Loop - Steady-State Mode
Auto Zero
When a channel is configured for constant current operation and the current set point is 000h for 256 consecutive
PWM periods, an autozero sequence is initiated. The autozero sequence will measure the offset of the current
SENSE
setpoint R
(11bit)tsetpoin
mACurrent 320
2
][ 11
 

)1(1*
28.1
)(
)(1*
28.1
kINTkerror
N
Rsense
KIkINT
kINTkerror
N
Rsense
KPkDutyCycle
A/DAverage
Autozero
Value
“ON”
-
CURRENT SET
POINT
DITHER STEP SIZE Dither
Generation
+
++KP
KI
PWM
Block
PWM
CLK
+
+
DITHER STEPS
OUTx
POSx
NEGx
Amp
+
-
Auto Zero
Autozero
Value
“OFF”
DUTY
CYCLE
CURRENT
READ
PRE-
LOAD
Italics = CAN BE MONITORED VIA SPI
Underlined = CAN BE PROGRAMMED VIA SPI
Data Sheet 7 Rev. 1.1, 2011-05-27
TLE7242-2G
Overview
measurement amplifiers. If the autozero function is enabled in SPI message #7, then the measured offset will be
subtracted from the A/D converter output as shown in Figure 3 when the current set point is greater than 0.
Dither
A triangular dither waveform can be superimposed on the current set point by setting the Dither Enable bit in SPI
message #3. The amplitude and frequency of the dither waveform are programmed for each channel via SPI
messages #3 and #4. See the SPI message section for details.
The first programmed value is the step size of the dither waveform which is the number of bits added or subtracted
from the setpoint per PWM period. One LSb of the dither step size is 1/16 the magnitude of the nominal setpoint
current value. The second programmed value is the number of steps in one quarter of the dither waveform.
When dither is enabled, a new dither amplitude setting, a new dither frequency setting, or a dither disable
command will not be activated until the current dither cycle has completed - see Figure 4. The dither cycle is
completed on the positive zero crossing of the dither waveform. A change in the setpoint current, however, is
activated at the start of the next PWM period.
Figure 4 New Dither Values Programmed and the Resultant Waveform Timing
Note: the actual dither waveform is attenuated and phase shifted according to the frequency response of the
control loop.
If a channel enters transient mode operation while the dither waveform is active, the dither wave-form will pause
until transient mode is exited.
Transient Mode
When a large change in the current set point occurs, the device can be programmed to enter transient mode of
operation. The setpoint change threshold required to initiate transient mode can be programmed in
SPI message #6. The purpose of this mode of operation is to reduce the transition time of the load current after a
large change in setpoint. In this mode of operation the OUTx pin signal is controlled by the state machine shown
in Figure 5. The control method in this mode is similar to hysteretic control, the OUTx signal transitions high or
low based on the immediate value of the measured output current. The PWM frequency is not fixed in this mode
of operation. The device will automatically switch from transient mode of operation to steady state operation at the
start of the first PWM period after the new set point has been reached.
PWM_START
Dither
Dither
Parameter
Change
TLE7242-2G
Overview
Data Sheet 8 Rev. 1.1, 2011-05-27
Figure 5 Transient Mode State Diagram
A typical current waveform during transient mode operation is shown in Figure 6. Starting from a set point I, the
new set point II is accepted a short time after the rising edge on CS_B. The OUTx pin remains high until the
measured load current has reached the new set point. The OUTx pin is then toggled on and off to maintain the
load current near the new set point until the next PWM period begins. The device will then switch back to steady
state control and the OUTx pin will be controlled by the control loop shown in Figure 3.
During the transition from transient mode operation to steady state operation, the integrator is pre-loaded with a
SPI programmable value. This value should be chosen to give an initial PWM duty cycle approximately equal to
the duty cycle required to regulate the load current at the new set point.
Figure 6 Transient Mode Timing Diagram
PWM
iL
setpoint 
setpoint
t
SPI CS_B
setpoint accepted
Steady State
Mode Begins
Transient Mode
Begins
Data Sheet 9 Rev. 1.1, 2011-05-27
TLE7242-2G
Block Diagram
2 Block Diagram
Figure 7 Block Diagram
POS0
OUT0
NEG0
POS1
OUT1
NEG1
POS2
OUT2
NEG2
POS3
OUT3
NEG3
SPI
Interface
SCK
SI
SO
CS_B
FAULT
RESET_B
BAT
PHASE_SYNC
V5D
V5A
GND_D
GND_A
CLK
ENABLE
V_SIGNAL
TEST
Supply
Biasing
Monitoring
Logic
V_SIGNAL
V_SIGNAL
Current
Control
Block
Diagnostics
V5D
Current
Control
Block
Diagnostics
V5D
Current
Control
Block
Diagnostics
V5D
Current
Control
Block
Diagnostics
V5D
TLE7242-2G
Pin Configuration
Data Sheet 10 Rev. 1.1, 2011-05-27
3 Pin Configuration
3.1 Pin Assignment
Figure 8 Pin Configuration
3.2 Pin Definitions and Functions
Pin Symbol I/O Analog
/Digital
Function
1 OUT3 O A Gate driver output for channel #3. Connect to the gate of the
external MOSFET.
2 OUT2 O A Gate driver output for channel #2. Connect to the gate of the
external MOSFET.
3 POS3 I A Channel #3 Positive sense pin. Connect to the "load" side of the
external sense resistor.
4 NEG3 I A Channel #3 Negative sense pin. Connect to the "FET" side of the
external sense resistor.
5 NEG2 I A Channel #2 Negative sense pin. Connect to the "FET" side of the
external sense resistor.
6 POS2 I A Channel #2 Positive sense pin. Connect to the "load" side of the
external sense resistor.
7 GND_A - - Analog Ground
8 V5A - - 5V supply pin for analog. An external capacitor is to be connected
between this pin and GND_A near this pin.
9 POS1 I A Channel #1 Positive sense pin. Connect to the "load" side of the
external sense resistor.
TLE7242 2G
OUT 3
OUT 2
NEG 3
POS 3
FAULT
RESET_B
CS_B
ENABLE
NEG 2
POS 2
V5A
GND_A
SCK
V5D
GND_D
CLK
SO
V_SIGNAL
TEST
SI
PHASE_SYNC
BAT
NEG 1
POS 1
NEG 0
POS 0
OUT 1
OUT 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Data Sheet 11 Rev. 1.1, 2011-05-27
TLE7242-2G
Pin Configuration
10 NEG1 I A Channel #1 Negative sense pin. Connect to the "FET" side of the
external sense resistor.
11 NEG0 I A Channel #0 Negative sense pin. Connect to the "FET" side of the
external sense resistor.
12 POS0 I A Channel #0 Positive sense pin. Connect to the "load" side of the
external sense resistor.
13 OUT1 O A Gate driver output for channel #1. Connect to the gate of the
external MOSFET.
14 OUT0 O A Gate driver output for channel #0. Connect to the gate of the
external MOSFET.
15 BAT I A Battery sense input for over voltage detection. Connect through a
series resistor (e.g. 1 Kohm) to the solenoid supply voltage. A
large electrolytic capacitor (e.g. 47uF) should be placed between
the BAT supply and ground.
16 PHASE_SYNC I D Used to synchronize the rising edges of the PWM signal on the
OUTx pins for each channel.
17 TEST I D Used for IC Test. Must be connected to GND_D for specified
operation of the IC.
18 SI I D SPI Serial data in
19 V_SIGNAL I - Supply pin for the SPI SO output and the pull-ups of the digital
inputs CS_B and RESET_B. An external capacitor must be con-
nected between this pin and GND_D near this pin.
20 SO O D SPI Serial data out
21 GND_D - - GND pin for digital and driver circuitry.
22 CLK I D Main clock input for the IC. A clock input of 20 MHz to 40 MHz is
required.
23 V5D - - 5V supply pin for the digital circuit blocks and the OUT pin driver
circuits. A pair of external capacitors is to be connected between
this pin and GND_D very near this pin. Example values of the
external capacitors are 100nF and 100pF.
24 SCK I D SPI Clock input
25 CS_B I D SPI Chip Select Bar (low active signal)
26 ENABLE I D When this input pin is low all channels are turned off (zero current)
or remain in their last state, depending on how the channel is
programmed to respond
27 RESET_B I D When this input pin is low all channels are turned off and all
internal registers are reset to their default state. The part must be
held in reset by an external source until all supplies are stable and
within tolerance.
28 FAULT O D This open drain output pin is pulled low when a fault condition is
detected. Certain faults can be masked via SPI.
Pin Symbol I/O Analog
/Digital
Function
TLE7242-2G
General Product Characteristics
Data Sheet 12 Rev. 1.1, 2011-05-27
4 General Product Characteristics
4.1 Maximum Ratings
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Absolute Maximum Ratings 1)
Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
1) Not subject to production test, specified by design.
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Max.
Voltages
4.1.1 Battery Input (VBAT) VBAT -13 50 V –
4.1.2 Supply Voltage (logic) V5D,V5A,
Vsignal
-0.3 6.0 V –
4.1.3 POSx, NEGx Vpos, Vneg -0.3 50 V –
4.1.4 POSx-NEGx Vpos-Vneg -0.2 13 V –
4.1.5 OUTx Vout -0.3 min(V5D+
0.3; 6)
V–
4.1.6 RESET_B, SI, SCK, CS_B, CLK, TEST,
PHASE_SYNC, ENABLE
Vio -0.3 min(V5D+
0.3; 6)
V–
4.1.7 SO, FAULT Vio -0.3 min(Vsignal
+ 0.3; 6)
V–
4.1.8 Maximum difference between V5D and
V5A
-500 500 mV –
Currents
4.1.9 Input Clamp Current ICLAMP 5–5mA–
Temperatures
4.1.10 Storage Temperature Tstg -65 150 C–
4.1.11 Junction Temperature Tj-40 150 C–
ESD Susceptibility
4.1.12 HBM – -2 2 kV 2)
2) ESD Susceptability HBM according to EIA/JESD 22-A 114B
4.1.13 CDM all pins – -500 500 V 3)
3) ESD Susceptability CDM according to EIA/JESD22-C101
4.1.14 CDM corner pins – -750 750 V 3)
Data Sheet 13 Rev. 1.1, 2011-05-27
TLE7242-2G
General Product Characteristics
4.2 Functional Range
Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3 Thermal Resistance
Tj = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Max.
4.2.1 Supply Voltage (VBAT)
- Full Parametric Operation on all
functions except FET Pre-drivers
VBAT 5.5 42 V –
4.2.2 Supply Voltage (V5D) VV5D 4.75 5.25 V –
4.2.3 Supply Voltage (V5A) VV5A 4.75 5.25 V –
4.2.4 V_SIGNAL VV_SIGNAL 3.0 5.25 V –
4.2.5 Clock Frequency fCLK 20 40 MHz
4.2.6 PWM Frequency fPWM 50 4000 Hz
4.2.7 Common Mode Voltage on POSx,
NEGx pins
Vpos ,Vneg –42V–
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
4.3.1 Junction to Ambient RthJA –50–K/W
1)
1) Specified RthJA value according to natural convestion on FR4 2s0p board; The Product (Chip + Package) was simulated
on a 60.0 X 45.0 X1.5 mm board (2 X 70um).
TLE7242-2G
Functional Description and Electrical Characteristics
Data Sheet 14 Rev. 1.1, 2011-05-27
5 Functional Description and Electrical Characteristics
Note: The listed characteristics are ensured over the operating range of the integrated circuit.
Typical characteristics specify mean values expected over the production spread. If not otherwise specified,
typical characteristics apply at TA = 25 oC and the given supply voltage.
5.1 Supply and Reference
The device includes a power-on reset circuit. This feature will disable the channels and reset the internal registers
to their default values when the voltage on V5A and/or V5D are below their respective reset thresholds.
The V5D pin and GND_D pin are the supply and ground pins for the digital circuit blocks and the OUTx pin driver
circuits. The current through these pins contain high frequency components. Decoupling with ceramic capacitors
and careful PCB layout are required to obtain good EMC performance.
The V5A pin and GND_A pin are the supply and ground pins for the analog circuit blocks.
The V_SIGNAL pin supplies the SPI output pin (SO) and is the source voltage for the pull up currents on the CS_B
and RESET_B pins. V_SIGNAL should be connected to the I/O supply of the microcontroller (3.3V or 5.0V).
The BAT pin is an input pin used to detect over voltage faults. This pin is not a power supply input. A series resistor
should be connected between this pin and the solenoid supply voltage for transient protection.
Electrical Characteristics:
V5D = 4.75V to 5.25V, Vbat = 5.5V to 42V, Tj = -40 C to +150 C, all voltages with respect to ground, positive
current flowing into pin (unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.1.1 Undervoltage reset (internally
triggered)
VV5A 3.5 – 4.5 V Internal reset
occurs if V5A is
under the
undervoltage limit
5.1.2 Undervoltage reset (internally
triggered)
VV5D 1.0 – 4.5 V Internal reset
occurs if V5D is
under the
undervoltage limit
5.1.3 V5D supply current IV5D ––30
50
mA
mA
fCLK=20MHz
fCLK=40MHz
5.1.4 V5A supply current IV5A ––25mA
5.1.5 V_SIGNAL supply current IV_SIGNAL – – 1.0 mA SO pin in hi-Z state,
digital inputs in
default state
5.1.6 VBAT current IVBAT – – 150
50
5
A
A
A
full operating range
V5A=5V, BAT=14V1)
V5A=0V, BAT=14V1)
1) Not subject to production test, specified by design.
Data Sheet 15 Rev. 1.1, 2011-05-27
TLE7242-2G
Functional Description and Electrical Characteristics
5.2 Input / Output
All digital inputs are compatible with 3.3 V and 5 V I/O logic levels. The supply voltage for the SPI output SO is the
V_SIGNAL pin. All digital inputs are pulled to a known state by a weak internal current source or current sink when
not connected. However, unused digital input pins should be connected to ground or to V_SIGNAL (according to
the desired functionality) by an external connection or resistor. All input pin weak internal current sources are
supplied by the V_SIGNAL pin.
The RESET_B pin is an active low input pin. When this pin is low, all channels are off, and all internal registers
are reset to their default states. The device must be held in reset by an external source until all the power supplies
have stabilized. The IC contains an internal power on and undervoltage reset which becomes active when V5D or
V5A fall below the undervoltage reset threshold (VUVA, VUVD).
The ENABLE pin is an active high input pin which must be held high for normal operation of the device. When this
pin is held low all channels are either turned off or will remain in the last state, depending on how the enable
behavior of the channel is programmed via SPI. The default condition is that all channels are turned off when the
ENABLE pin is low.
The CLK pin is the main clock input for the device. The input thresholds are compatible with 3.3 V and 5.0 V logic
levels. No synchronization is required between the clock signal connected to the CLK pin and the SPI clock signal
(SCK). All frequencies of operation (PWM signals, A/D sampling, diagnostics, etc.) are based on this clock input.
Also, this clock is required in order for the device to accept and respond to SPI messages.
Figure 9 CLK Timing Diagram
The PHASE_SYNC pin is an input pin that can be used by the microcontroller to synchronize the PWM control
signals of multiple channels. The desired phase delay between the rising edge of the signal applied to the
PHASE_SYNC pin and the rising edge of the PWM signal of each channel can be programmed independently via
SPI message #2. The equation for calculating the offset is:
Each time the phase sequence occurs, the IC will latch a bit which is reported via the response to SPI message
#11. (See SPI interface section for bit/message location.) This latch is cleared when the message is read.
Note: The PWM periods are restarted when a rising edge is detected on the PHASE_SYNC pin. A periodic pulse
train on this pin will disturb the current regulation.
CLK
t14
1/fclk
t15
VIHmin
VILmax
PWM
offset F
OffsetPhaseSynch
T*32
TLE7242-2G
Functional Description and Electrical Characteristics
Data Sheet 16 Rev. 1.1, 2011-05-27
Figure 10 Phase Synchronization Diagram
The TEST pin is an input pin that is used during IC level test. This pin should be connected directly to ground for
normal device operation.
The FAULT pin is an open drain output pin. This pin will be pulled low by the device when an unmasked fault has
been detected. The fault masks are programmed via SPI message #7.
Electrical Characteristics:
V5D = 4.75V to 5.25V, Vbat = 5.5V to 42V, Tj = -40 C to +150 C, all voltages with respect to ground, positive
current flowing into pin (unless otherwise specified)
5.3 Diagnostics
The TLE7242 2G includes both on-state and off-state diagnostics. On-state diagnostics are active when the OUTx
pin is driven high and off-state diagnostics are active when the OUTx pin is driven low. A detected fault can be
used to activate the open drain FAULT pin on the IC. This pin can be used to interrupt the microcontroller when a
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.2.1 Logic input low voltage VILMAX ––0.8V
5.2.2 Logic input high voltage VIHMIN 2.0 – – V
5.2.3 Logic output low voltage VOLMAX ––0.2VIL=200A
5.2.4 Logic output high voltage VOHMIN 0.8*V_
SIGNAL
––VIL=-200A
5.2.5 Pull down digital input (SI, CLK,
SCK, PHASE_SYNC, ENABLE,
TEST)
Ipd 10 – 50 AVin=V_SIGNAL
(current drain to
ground)
5.2.6 Pull up digital input (CS_B,
RESET_B)
Ipu -10 – -50 AVin=0V (Current
drain from
V_SIGNAL)
5.2.7 Fault Pin voltage Vfault – – 0.4 V Active state;
Ifault=2mA
5.2.8 CLK high time (rise 2.0V to fall
2.0V)
t14 8––ns
5.2.9 CLK low time (fall 0.8V to rise 0.8V) t15 8––ns
OUTx
PWM/32 CLK
PHASE_SYNC
T1
T1
gate turns off
on-time cut
short
normal
turn off
time
Programmed delay =
8/32 PWM periods
Data Sheet 17 Rev. 1.1, 2011-05-27
TLE7242-2G
Functional Description and Electrical Characteristics
fault is detected. Certain faults can be prevented from activating the FAULT pin by setting the fault mask register
in SPI message #7.
Once a fault is detected it is latched into the FAULT register. The microcontroller can access the FAULT register
by sending SPI message #9.
If the RESET_B line transitions high-to-low, a RL bit is latched into the FAULT register. The register is cleared after
it is read from the SPI. The RL bit in the FAULT register will not be set again until the next high-to-low transition
occurs on the RESET_B pin.
If the ENABLE pin voltage is low, the ENL bit is latched in the FAULT register. The ENL bit is cleared when the
ENABLE pin returns to a high state and the FAULT register is accessed by SPI message #9.
The diagnostic delay timers for the on-state and off-state diagnostic functions are derived from the master clock
signal applied to the pin CLK using a programmable predivider. This predivider is programmable by the DT1 and
DT0 bits in SPI message #7.
Three fault types in 4 different fault bits are defined:
The fault bit is 1 if the fault is detected.
Note: In order to differentiate between a Short to Ground Failure and an Open Load Failure, the channel must be
turned off (setpoint = 0ma).
Tested Diagnostic Bits
The tested bits allow the distinction between a true No Fault and a No Fault due to an untested state (the detection
interval has yet to occur). For instance when the calculated duty cycle is too low to complete the short to battery
test.
Table 1 Timebase for Diagnostics
DT1 DT0 Pre-divider Tested Timer and Fault Detection Timer
Period.
FCLK=20 MHz FCLK=40 MHz
0012864sec 32sec
0119296sec 48sec
1019296sec 48sec
1 1 256 128sec 64sec
Table 2 Diagnostic Flags / Bits
Fault Type Abr. Gate is ON Gate is OFF
Short to Ground Fault SG OL-ON-F reported (=0 in
ON/OFF mode)
Bit SG-F
Short to Battery Fault SB Bit SB-F
Open Load Fault OL BIT OL-ON-F
(=0 in ON/OFF mode)
Bit OL-OFF-F
109
*
_ fault
CLK
fault
PERIODDIAG n
F
predividern
t
TLE7242-2G
Functional Description and Electrical Characteristics
Data Sheet 18 Rev. 1.1, 2011-05-27
Two fault tested bits are defined:
The tested bit is set to 1 when the fault test has completed successfully.
Each fault type can be described by the two bits: FAULT and TESTED.
Figure 11 Diagnostic Block Diagram
Table 3 Diagnostics Tested Bits / Flags
Tested Type OUTx High OUTx Low
Short to Ground and Open load OFF
tested
Bit OFF-T
Short to Battery tested Bit SB-T
Table 4 FAULT vs. TESTED Bits Matrix and Interpretation
FAULT TESTED Interpretation by microcontroller
0 0 This fault type has not been tested
0 1 No Fault - The fault type has been tested and no fault is present
1 0 This combination cannot occur
1 1 Fault - This particular fault type has occurred
Predivider
1:128
1:192
1:256
Tested timer
1..10
(shared)
digital filter
open load OFF
(only while OFF)
digital filter
short to ground
(only while OFF)
digital filter
short to battery
(only while ON)
Gate On Counter
1..64
fault filter timer
(1..10) (shared)
VPOS
VOL
VPOS
VSG
VPOS
VSB
OL-FA
SG-FA
SB-FA
PWM mode enabled
PWM Start
clear LOGIC
Divider Select
(SPI register)
Masterclock
OL-OFF-FD
SG-FD
SB-FD
OL-ON-F
OL-OFF-F (Open Load Off Fault)
SG-F (Short to Ground Fault)
SB-F (Short to Battery Fault)
OL-ON-F (Open Load On Fault)
OFF-T (Short to Ground and Open
Load Off Tested)
SB-T (Short to Battery Tested)
read SPI fault
register
Gate is ON
clearclear clear
Data Sheet 19 Rev. 1.1, 2011-05-27
TLE7242-2G
Functional Description and Electrical Characteristics
5.3.1 On-State Diagnostics
When the OUTx pin transitions high, the fault timers are cleared to 0 and the tested timer starts. If the tested timer
expires, the Bit SB-T (in the SPI register #9) is set to 1. If the OUTx pin transitions low, the tested timer is cleared
and then used for the off-state diagnostics.
If the analog SB fault signal (SB-FA) changes to 1, the fault filter timer starts. If the fault filter timer expires, the
digitally filtered SB fault signal (SB-FD) is set to one. If SB-FA changes to 0, SB-FD changes immediately to 0 and
the filter timer is cleared to 0.
A SB-FD=1 and SB-T=1 switches off the OUTx signal and the SB-F bit in the FAULT register will be set. The OUTx
pin remains in the off state until the fault retry PWM period counter expires.
If the SPI fault register is read, then the SB-F bit and the SB-FT bit in the FAULT register are cleared. Also, the
tested timer is cleared to 0.
The Short to Battery (SB) detection functions in both on/off and constant current mode. The SG-FD and OL-OFF-
FD signals are held to 0 while the OUTx pin is high.
If the TLE7242 2G IC is in ON/OFF mode, Open Load ON detection is disabled (OL-ON-F = 0).
If the TLE7242 2G IC is not in ON/OFF mode and the OUTx pin is high for 64 PWM periods, then open load fault
ON mode is detected and the OL-ON-F bit in the FAULT register is set. This bit will be cleared when a SPI fault
read occurs. If the OUTx pin remains in a high state, then the open load - on fault condition is detected again after
another 64 PWM cycles.
Figure 12 On-State Diagnostic Timing - Short to Vbat
PWM_Start
OUTx
Vpos
Load
Current
SB-T
SB-F
SPI READ
ADDR 9
Tested
Timer
Fault
Filter
Fault Retry Time
(Address #8)
Short to Vbat
Load ok
short
Vsb
Tested
Timer
Fault
Filter
TLE7242-2G
Functional Description and Electrical Characteristics
Data Sheet 20 Rev. 1.1, 2011-05-27
Figure 13 Open - On
5.3.2 Off-State Diagnostics
The off-state diagnostics function in both constant current mode and in on/off mode.
When the OUTx pin transitions low, the fault timers are cleared to 0 and the tested timer starts to count up. If the
tested timer expires, the Bit OFF-T in the FAULT register is set. If a SPI fault register read occurs, the tested timer
is cleared to 0 and starts again to count up. If the OUTx pin transitions high, the tested-timer is cleared to zero and
then used for on-state diagnostics.
If the analog OL fault signal (OL-FA) changes to 1, the fault filter timer starts to count up. If the fault filter timer
expires, the digitally filtered OL fault signal (OL-ON-FD) is set to one.
If OL-FA changes to 0, OL-FD changes immediately to 0 and the fault filter timer is cleared to 0.
If the analog SG fault signal (SG-FA) changes to 1, the fault filter timer is cleared to 0 and starts to count up. If the
fault filter timer expires, the digitally filtered SG fault signal (SG-FD) is set to one. If SG-FA changes to 0, SG-FD
changes immediately to 0 and the fault filter timer is cleared to 0.
If SG-FD = 1 and the tested timer is expired then the SG-F bit in the FAULT register is set and the OL-OFF-F bit
in the FAULT register remains unchanged (independently from OL-OFF-FD).
If SG-FD = 0 and OL-OFF-FD = 1 then the OL-F Bit in the FAULT register is set.
If a SPI fault read occurs, the OFF-T Bit, the SG-F Bit and the OL-F Bit in the SPI registers are cleared to zero
(and the timers are cleared to 0).
PWM_Start
OUTx
Vpos
OL-ON-F
SPI Message
Diagnostic Read
64 * PWM period
Data Sheet 21 Rev. 1.1, 2011-05-27
TLE7242-2G
Functional Description and Electrical Characteristics
Figure 14 Off-State Diagnostics
Figure 15 Off-State Diagnostics Timing Diagram - open
NEGx
OUTx
POSx
VSUPPLY
Solenoid
V5A
(Vol+Vsg)/2
(2.5V)
+
-
-
+
Vol (3V)
Vsg (2V)
+
OA
CMP
CMP
-
Digital
Filter
Digital
Filter
OL-FAOL-OFF-FD
SG-FASG-FD
Tested Timer
(OFF)
OL-OFF-
FAULT
SG-
FAULT
Ipu(sg)
(100ua)
Ipd(ol)
(100ua)
latch
latch
latch
SG/OL-OFF
TESTED
Cneg
Cpos
VPOS
OUTx
OFF-T
OL-OFF-F
SPI Message
Diagnostic Read
Tested
Timer
Fault
Filter
Tested
Timer
Fault
Filter
LOAD ok
open
Vol
Vsg
TLE7242-2G
Functional Description and Electrical Characteristics
Data Sheet 22 Rev. 1.1, 2011-05-27
Figure 16 Off-State Diagnostics Timing Diagram - short to ground
Over voltage Shutdown and Diagnostics
If the voltage at the BAT pin is above VBATOV, the output drivers set all OUTx pins to low, and a diagnostic bit is
set (SPI Message +11 bit OVL). During over voltage condition the integrator of the steady state current control is
halted (actual value of the duty cycle is not changed during over voltage). All other functions operate normally (e.g.
ADC, Dithering, Auto zero, Filters, …).
Electrical Characteristics:
V5D = 4.75V to 5.25V, Vbat = 5.5V to 42V, Tj = -40 C to +150 C, all voltages with respect to ground, positive
current flowing into pin (unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.3.1 Over voltage shutdown VBATOV 42 – – V Raise VBAT until all
outputs shut down
5.3.2 Open load detection voltage VPOS(OL) V5A-2.5 –V5A-1.5 V
5.3.3 POS pin OL pull down current IPD(OL) 60 100 150 AV5A=5V,
VPOS=VNEG=V5A
5.3.4 Short to GND detection voltage VPOS(SHG) V5A-3.5 – V5A-2.5 V
5.3.5 POS pin SG pull-up current IPD(SHG) -60 -100 -150 AV5A=5V,
VPOS=VNEG=0V
5.3.6 NEG bias current - Low common
mode
INEG(L) -40 – 10 AV5A=5V,
VPOS=VNEG=0V
5.3.7 NEG bias current - High common
mode
INEG(H) 0–60AV5A=5V,
VPOS=VNEG=V5A
VPOS
OUTx
OFF-T
SG-F
SPI READ
ADDR 9
Tested
Timer
Fault
Filter
Tested
Timer
Fault
Filter
LOAD
ok
Short to
ground
Vol
Vsg
Data Sheet 23 Rev. 1.1, 2011-05-27
TLE7242-2G
Functional Description and Electrical Characteristics
5.3.8 POS Fault Threshold Voltage VFLT 0.6 0.7 0.8 V POS voltage
required to trigger a
short to battery
fault: config bits =
00
5.3.9 POS Fault Threshold Voltage VFLT 0.8 0.9 1.0 V POS voltage
required to trigger a
short to battery
fault: config bits =
01
5.3.10 POS Fault Threshold Voltage VFLT 1.0 1.1 1.2 V POS voltage
required to trigger a
short to battery
fault: config bits =
10
5.3.11 POS Fault Threshold Voltage VFLT 1.2 1.3 1.4 V POS voltage
required to trigger a
short to battery
fault: config bits =
11
5.3.12 Fault Filter Timer nfault 910clocks
5.3.13 Fault Filter Time Tff Clock Divider (SPI
Message 7)
00 - Predivider 128
01, 10 - Predivider
192
11 - Predivider 256
5.3.14 Tested Timer Time Ttt Clock Divider (SPI
Message 7)
00 - Predivider 128
01, 10 - Predivider
192
11 - Predivider 25
6
V5D = 4.75V to 5.25V, Vbat = 5.5V to 42V, Tj = -40 C to +150 C, all voltages with respect to ground, positive
current flowing into pin (unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
CLK
fault
f
predividern
CLK
fault
f
predividern
TLE7242-2G
Functional Description and Electrical Characteristics
Data Sheet 24 Rev. 1.1, 2011-05-27
5.4 Output Driver
The OUTx pins of the device are connected to the gates of the external MOSFET transistors. The OUTx pin driver
circuits charge and discharge the MOSFET gate capacitance with a constant current source and sink. The supply
for the current source is the V5D pin. Internal resistors to ground are included on the OUTx pins so that the external
MOSFET is held in the off state when power is not applied to the device.
An external resistor is typically placed between the OUTx pin and the gate of the external MOSFET in order to set
the MOSFET turn-on and turn-off times. The value of the resistor must be chosen such that the turn-on and turn-
off times of the MOSFET are no longer than 1/(Fpwm*32).
Electrical Characteristics:
V5D = 4.75V to 5.25V, Vbat = 5.5V to 42V, Tj = -40 C to +150 C, all voltages with respect to ground, positive
current flowing into pin (unless otherwise specified)
5.5 Current Control
Electrical Characteristics:
V5D = 4.75V to 5.25V, Vbat = 5.5V to 42V, Tj = -40 C to +150 C, all voltages with respect to ground, positive
current flowing into pin (unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.4.1 Passive Gate Pull Down
Resistance
RPD 50 – 200 kInternal pull down
resistor present at
each OUTx pin
5.4.2 OUTx source current IO_SRC -15– -30mAV
OUT = V5D-2V
5.4.3 OUTx sink current IO_SNK 15 – 30 mA VOUT = 2V
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.5.1 Offset Error
Output from Average block in
Figure 3.
1 count = 320/Rsense * 2-14 mA
0 – 240 counts Autozero
disabled.Vpos-
Vneg=0mV
Vpos, Vneg 30V
5.5.2 Gain Error -2% – 2% % Autozero
Enabled.Vpos-
Vneg=300mV
Vpos, Vneg 30V
Data Sheet 25 Rev. 1.1, 2011-05-27
TLE7242-2G
Functional Description and Electrical Characteristics
5.6 Serial Peripheral Interface (SPI)
SPI messages for the TLE7242 2G IC are 32-bit values broken down into the following fields.
Bit 31: Read/Write Bit - 0 = Read 1 = Write
Bits 30-26: Message Identifier
Bits 25-24: Channel Number (00, 01, 10, 11)
Bits 23-0: Message Data
The message from the microcontroller must be sent MSB first. The data from the SO pin is sent MSB first. The
TLE7242 2G will sample data from the SI pin on the rising edge of SCK and will shift data out of the SO pin on the
rising edge of SCK.
All SPI messages must be exactly 32-bits long, otherwise the SPI message is discarded. The response to an
invalid message (returned in the next SPI message) is the message with identifier 00000 (Manufacturer ID).
When the ENABLE pin is low, all SPI writes commands are executed as read commands.
When RESET_B pin is low, the SPI port is disabled. No SPI messages are received and no responses are sent.
The SO pin remains in a high impedance state.
There is a one message delay in the response to each message (i.e. the response for message N will be returned
during message N+1).
Read/Write operation is referenced from the SPI master. The TLE7242 2G IC is the slave device.
Some messages, such as diagnostic information, do not use the channel number field. In these cases the channel
number is not part of the response.
When bit 31 is = 0 to denote a read operation to the IC, the message data in bits 23-0 of the sent message are
ignored, but will contain valid data in the response message.
All response data (either from a read or write operation) is the direct contents of the addressed internal register,
and is not an echo of the data sent in the previous SPI message.
The response to the first SPI message after a reset is message #0 (IC Version / Manufacturer).
TLE7242-2G
Functional Description and Electrical Characteristics
Data Sheet 26 Rev. 1.1, 2011-05-27
5.6.1 SPI Signal Description
Electrical Characteristics:
V5D = 4.75V to 5.25V, Vbat = 5.5V to 42V, Tj = -40 C to +150 C, all voltages with respect to ground, positive
current flowing into pin (unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.6.1 TLEAD t1140 – – ns CS_B falling (0.8V)
to SCK rising (0.8V)
5.6.2 TLAG t250 – – ns SCK falling (0.8V)
to CS_B rising
(0.8V)
5.6.3 t3450 – – ns CS_B rise (2.0V) to
CS_B fall (2.0V)
5.6.4 1/FSCK Period of SCK t4100 – – ns SCK rise to rise
5.6.5 t510 – – ns SCK falling (0.8V)
to CS_B fall (2.0V)
5.6.6 t640 – – ns SCK high time (rise
2.0V to fall 2.0V)
5.6.7 t740 – – ns SCK low time (fall
0.8V to rise 0.8V)
5.6.8 t810 – – ns CS_B rise (2.0V) to
SCK rise (0.8V)
5.6.9 TSU_SI t920 – – ns SI setup time to
SCK rise (0.8V)
5.6.10 THOLD_SI t10 20 – – ns SI hold time after
SCK rise (2.0V)
5.6.11 TSO_ENABLE t11 – – 110 ns CS_B fall (2.0V) to
SO Bit0 valid
5.6.12 TVALID t12 – – 80 ns SO data valid after
SCK rise (2.0V)
5.6.13 TSO_DISABLE t13 – – 110 ns SO tristate after
CS_B rise (2.0V)
5.6.14 Number of clock pulses while CS_B
low
32 – 32
5.6.15 SO rise time TSO_RISE – – 50 ns (20% to 80%)
5.6.16 SO fall time TSO_FALL – – 50 ns (80% to 20%)
5.6.17 Input pin capacitance. CS_B, SI,
and SCK
Cin ––20pF
5.6.18 SO pin capacitance Cso – – 25 pF Tristate
Data Sheet 27 Rev. 1.1, 2011-05-27
TLE7242-2G
Functional Description and Electrical Characteristics
Figure 17 SPI Timing Diagram
Bit 31
MSB
Bit 0
LSB
don’t care don’t care
clock
1
clock
2
clock
3
clock
31
clock
32
Bit 3 0 Bit 2 9 Bit 1
don’t care
LSB
high impedancehigh impedance
time
time
time
time
don’t care
don’t care
SCK
SI
SO
t6
t4
t7
t1
t5
t10
t9
t11 t12
t
2t3
t8
t13
CS_B
Bit 3 1
MSB Bit 30 Bit 29 Bit 0
Bit 1
TLE7242-2G
Functional Description and Electrical Characteristics
Data Sheet 28 Rev. 1.1, 2011-05-27
5.6.2 SPI Message Structure
5.6.2.1 SPI Message #0 - IC Version / Manufacturer
Sent Values:
IC Version / Manufacturer Reset Value: 00 C1 00 00H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R/W MSG_ID not used
1514131211109876543210
not used
Field Bits Type Description
R/W 31 Read / Write Bit
0 = Read
1 = Write
MSG_ID 30:26 Message Identifier
0 0000 = IC Version / Manufacturer
Response:
IC Version / Manufacturer Reset Value: 00 C1 00 00H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0MSG_ID00 IC Manuf ID
1514131211109876543210
Version Number 00000000
Field Bits Type Description
MSG_ID 30:26 Message Identifier
0 0000 = IC Version / Manufacturer
IC Manuf ID 16:23 IC Manufacturer ID Number
1100 0001= Infineon Technologies
Version
Number
8:15 Version Number
0000 0010 = K11
Data Sheet 29 Rev. 1.1, 2011-05-27
TLE7242-2G
Functional Description and Electrical Characteristics
5.6.2.2 SPI Message #1 - Main Period Set
Sent Values:
Main Period Set Reset Value: 00 00 02 71H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R/W MSG_ID CH1 CH0 unused
1514131211109876543210
not used PWM Divider - N
Field Bits Type Description
R/W 31 Read / Write Bit
0 = Read
1 = Write
MSG_ID 30:26 Message Identifier
0 0001 = Main Period Set
Channel 25:24 Channel Number
N13:0 PWM Divider N
Response:
Main Period Set Reset Value: 00 00 02 71H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 MSG_ID CH1CH000000000
1514131211109876543210
0 0 PWM Divider - N
Field Bits Type Description
MSG_ID 30:26 Message Identifier
0 0001 = Main Period Set
Channel 25:24 Channel Number
N13:0 PWM Divider N
N
F
FCLK
PWM
*32
TLE7242-2G
Functional Description and Electrical Characteristics
Data Sheet 30 Rev. 1.1, 2011-05-27
5.6.2.3 SPI Message #2 - PWM Offset
Sent Values:
PWM Offset Reset Value: 00 00 00 00H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R/W MSG_ID CH1 CH0 unused
1514131211109876543210
not used Phase Sync Offset
Field Bits Type Description
R/W 31 Read / Write Bit
0 = Read
1 = Write
MSG_ID 30:26 Message Identifier
0 0010 = PWM Offset
Channel 25:24 Channel Number
Phase Synch 4:0 Phase Synch Offset
Response:
PWM Offset Reset Value: 00 00 00 00H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 MSG_ID CH1CH000000000
1514131211109876543210
00000000000 Phase Sync Offset
Field Bits Type Description
MSG_ID 30:26 Message Identifier
0 0010 = PWM Offset
Channel 25:24 Channel Number
Phase Synch 4:0 Phase Synch Offset
PWM
offset F
OffsetPhaseSynch
T*32
Data Sheet 31 Rev. 1.1, 2011-05-27
TLE7242-2G
Functional Description and Electrical Characteristics
5.6.2.4 SPI Message #3 - Current Set Point and Dither Amplitude Set
Dither
Sent Values:
Current Set Point and Dither Amplitude Set Reset Value: 00 00 00 00H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R/W MSG_ID CH1 CH0 EN ON/
OFF Dither Step Size
1514131211109876543210
Dither Step Size
Dither
ON/
OFF
Current Set Point
Field Bits Type Description
R/W 31 Read / Write Bit
0 = Read
1 = Write
MSG_ID 30:26 Message Identifier
0 0011 = Current Set Point and Dither Amplitude Set
Channel 25:24 Channel Number
EN 23 Sets behavior of channel when the pin ENABLE is low.
0 = channel turned off
1 = channel remains at last current set point.
ON/OFF 22 Used when the channel is configured for on/off operation
0 = off
1 = on
Step Size 21:12 Dither Step Size
(LSB value is 2-4 of the Current Set point LSB)
Dither
ON/OFF
11 Dither Enable
0=Disabled 1=Enabled
Current
Setpoint
10:0 Average Current Set Point
Resolution = 0.78125 mA / bit when 0.2 ohm external resistor is used.
TLE7242-2G
Functional Description and Electrical Characteristics
Data Sheet 32 Rev. 1.1, 2011-05-27
Dither amplitude is the peak to peak amplitude of the dither waveform. Note: the actual dither waveform is
attenuated and phase shifted according to the frequency response of the control loop.
Dither Steps is the number of PWM periods in ¼ of the dither waveform, set in SPI message #4.
RSENSE is the value of the external sense resistor
Response:
Current Set Point and Dither Amplitude Set Reset Value: 00 00 00 00H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R/W MSG_ID CH1 CH0 EN ON/
OFF Dither Step Size
1514131211109876543210
Dither Step Size
Dither
ON/
OFF
Current Set Point
Field Bits Type Description
MSG_ID 30:26 Message Identifier
0 0011 = Current Set Point and Dither Amplitude Set
Channel 25:24 Channel Number
EN 23 Sets behavior of channel when the pin ENABLE is low.
0 = channel turned off
1 = channel remains at last current set point.
ON/OFF 22 Used when the channel is configured for on/off operation
0 = off
1 = on
Step Size 21:12 Dither Step Size
(LSB value is 2-4 of the Current Set point LSB)
Dither
ON/OFF
11 Dither Enable
0=Disabled 1=Enabled
Current
Setpoint
10:0 Average Current Set Point
Resolution = 0.78125 mA / bit when 0.2 ohm external resistor is used.
SENSE
amplitude R
sDitherStepSizeDitherStep
mAppDither 320
2
**2
][ 15
SENSE
setpoint R
Setpoint
mACurrent 320
2
][ 11
Data Sheet 33 Rev. 1.1, 2011-05-27
TLE7242-2G
Functional Description and Electrical Characteristics
5.6.2.5 SPI Message #4 - Dither Period Set
Sent Values:
Dither Period Set Reset Value: 00 00 00 00H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R/W MSG_ID CH1 CH0 unused
1514131211109876543210
not used Dither Steps
Field Bits Type Description
R/W 31 Read / Write Bit
0 = Read
1 = Write
MSG_ID 30:26 Message Identifier
0 0100 = Dither Period Set
Channel 25:24 Channel Number
Dither Steps 5:0 Dither Steps - # of Dither Steps in 1/4 of the dither waveform period.
Response:
Dither Period Set Reset Value: 00 00 00 00H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 MSG_ID CH1CH000000000
1514131211109876543210
0000000000 Dither Steps
Field Bits Type Description
MSG_ID 30:26 Message Identifier
0 0100 = Dither Period Set
Channel 25:24 Channel Number
Dither Steps 5:0 Dither Steps - # of Dither Steps in 1/4 of the dither waveform period.
PWM
Period F
sDitherStep
Dither *4
[sec]
TLE7242-2G
Functional Description and Electrical Characteristics
Data Sheet 34 Rev. 1.1, 2011-05-27
5.6.2.6 SPI Message #5 - Control Variable Set (KP and KI)
Sent Values:
Control Variable Set (KP and KI) Reset Value: 00 80 08 00H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R/W MSG_ID CH1 CH0 KP
1514131211109876543210
KP KI
Field Bits Type Description
R/W 31 Read / Write Bit
0 = Read
1 = Write
MSG_ID 30:26 Message Identifier
0 0101 = Control Variable Set (KP and KI)
Channel 25:24 Channel Number
KP 23:12 KP - Proportional Coefficient
KI 11:0 KI - Integral Coefficient
Response:
Control Variable Set (KP and KI) Reset Value: 00 80 08 00H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R/W MSG_ID CH1 CH0 KP
1514131211109876543210
KP KI
Field Bits Type Description
MSG_ID 30:26 Message Identifier
0 0101 = Control Variable Set (KP and KI)t
Channel 25:24 Channel Number
KP 23:12 KP - Proportional Coefficient
KI 11:0 KI - Integral Coefficient
Data Sheet 35 Rev. 1.1, 2011-05-27
TLE7242-2G
Functional Description and Electrical Characteristics
The duty cycle of the OUTx pin can be calculated from the difference equations:
where error is the difference between the commanded average current and the measured average current in units
of Amps,
where k indicates the integral number of PWM periods that have elapsed since current regulation was initiated.
 

)1(1*
28.1
)(
)(1*
28.1
kINTkerror
N
Rsense
KIkINT
kINTkerror
N
Rsense
KPkDutyCycle
TLE7242-2G
Functional Description and Electrical Characteristics
Data Sheet 36 Rev. 1.1, 2011-05-27
5.6.2.7 SPI Message #6 - Dynamic Threshold Value Set
Sent Values:
Dynamic Threshold Value Set) Reset Value: 00 7F F4 00H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R/W MSG_ID CH1 CH0 unused Transient Mode Threshold
1514131211109876543210
Transient Mode Threshold Integrator Preload Value
Field Bits Type Description
R/W 31 Read / Write Bit
0 = Read
1 = Write
MSG_ID 30:26 Message Identifier
0 0110 = Dynamic Threshold Value Set
Channel 25:24 Channel Number
Transient
Mode Thresh
22:12 Transient Mode Threshold
Setpoint changes grater than this threshold will activate the transient
mode of operation.
Int. Preload 11:0 Integrator Preload Value
This value will be loaded into the integrator when the controller
transitions from transient mode to steady state mode.
Response:
Dynamic Threshold Value Set Reset Value: 00 7F F4 00H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R/W MSG_ID CH1 CH0 0 Transient Mode Threshold
1514131211109876543210
Transient Mode Threshold Integrator Preload Value
Field Bits Type Description
MSG_ID 30:26 Message Identifier
0 0110 = Dynamic Threshold Value Set
Channel 25:24 Channel Number
Data Sheet 37 Rev. 1.1, 2011-05-27
TLE7242-2G
Functional Description and Electrical Characteristics
The Preload value is limited to a maximum value of N * 217
Transient
Mode Thresh
22:12 Transient Mode Threshold
Setpoint changes grater than this threshold will activate the transient
mode of operation.
Int. Preload 11:0 Integrator Preload Value
This value will be loaded into the integrator when the controller
transitions from transient mode to steady state mode.
Field Bits Type Description
SENSE
Threshold R
ldodeThreshoTransientM
mACurrent 320
2
][ 11
8
2 PointSetCurrentValueIntPreloadPreload
TLE7242-2G
Functional Description and Electrical Characteristics
Data Sheet 38 Rev. 1.1, 2011-05-27
5.6.2.8 SPI Message #7 - On/Off Control and Fault Mask Configuration
Sent Values:
On/Off Control and Fault Mask Configuration Reset Value: 00 00 00 00H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R/W MSG_ID unused CM0 CM1 CM2 CM3 FM0 FM1 FM2 FM3
1514131211109876543210
FMR FME DIAG_TMR AZ
Disable unused
Field Bits Type Description
R/W 31 Read / Write Bit
0 = Read
1 = Write
MSG_ID 30:26 Message Identifier
0 0111 = On/Off Control and Fault Mask Configuration
CMx 23, 22, 21,
20
Control Mode for Channel #x
0 = Current Control
1 = On/off
FMx 19, 18, 17,
16
Fault Mask for Channel #x
0 = faults don’t trigger FAULT pin
1 = fault triggers FAULT pin
FMR 15 Fault Mask for RESET_B pin
0 = A low state on the ENABLE pin does not activate the FAULT pin.
1 = A low state on the ENABLE pin does activate the FAULT pin.
Note: when a high to low transition is detected on the ENABLE pin,
the ENABLE fault will be latched until the ENABLE pin returns high
AND a diagnostic read message is received.
FME 14 Fault Mast for ENABLE pin
0 = A low state on the RESET_B pin does not activate the FAULT pin.
1 = A low state on the RESET_B pin does activate the FAULT pin.
DIAG_TMR 13:12 Diagnostic Timer
00 = TIME_1 pre-divider = 128
01 = TIME_2 pre-divider = 192
10 = TIME_2 pre-divider = 192
11 = TIME_3 pre-divider = 256
AZ Disable 11 Auto-Zero Disable
0 = Auto-Zero Enabled
1 = Auto-Zero Disabled
Data Sheet 39 Rev. 1.1, 2011-05-27
TLE7242-2G
Functional Description and Electrical Characteristics
Response:
On/Off Control and Fault Mask Configuration Reset Value: 00 00 00 00H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R/W MSG_ID 0 0 CM0 CM1 CM2 CM3 FM0 FM1 FM2 FM3
1514131211109876543210
FMR FME DIAG_TMR AZ
Disable 00000000000
Field Bits Type Description
MSG_ID 30:26 Message Identifier
0 0111 = On/Off Control and Fault Mask Configuration
CMx 23, 22, 21,
20
Control Mode for Channel #x
0 = Current Control
1 = On/off
FMx 19, 18, 17,
16
Fault Mask for Channel #x
0 = faults don’t trigger FAULT pin
1 = fault triggers FAULT pin
FMR 15 Fault Mask for RESET_B pin
0 = A low state on the ENABLE pin does not activate the FAULT pin.
1 = A low state on the ENABLE pin does activate the FAULT pin.
Note: when a high to low transition is detected on the ENABLE pin,
the ENABLE fault will be latched until the ENABLE pin returns high
AND a diagnostic read message is received.
FME 14 Fault Mask for ENABLE pin
0 = A low state on the RESET_B pin does not activate the FAULT pin.
1 = A low state on the RESET_B pin does activate the FAULT pin.
DIAG_TMR 13:12 Diagnostic Timer
00 = TIME_1 pre-divider = 128
01 = TIME_2 pre-divider = 192
10 = TIME_2 pre-divider = 192
11 = TIME_3 pre-divider = 256
AZ Disable 11 Auto-Zero Disable
0 = Auto-Zero Enabled
1 = Auto-Zero Disabled
TLE7242-2G
Functional Description and Electrical Characteristics
Data Sheet 40 Rev. 1.1, 2011-05-27
5.6.2.9 SPI Message #8 - Diagnostic Configuration
Sent Values:
Diagnostic Configuration Reset Value: xx FF FF FFH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R/W MSG_ID unused SB0 SB_RETRY0 SB1
1514131211109876543210
SB_RETRY1 SB2 SB_RETRY2 SB3 SB_RETRY3
Field Bits Type Description
R/W 31 Read / Write Bit
0 = Read
1 = Write
MSG_ID 30:26 Message Identifier
0 1000= Diagnostic Configuration
SBx 23:22
17:16
11:10
5:4
Short To Battery Threshold
00 = 0.7 V
01 = 0.9 V
10 = 1.1 V
11 = 1.3 V
SB_RETRYx 21:18
15:12
9:6
3:0
Short to Battery Retry Time
Retry after 4 * SB_RETRY * PWM periods
Response Values:
Diagnostic Configuration Reset Value: xx FF FF FFH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 MSG_ID 0 0 SB0 SB_RETRY0 SB1
1514131211109876543210
SB_RETRY1 SB2 SB_RETRY2 SB3 SB_RETRY3
Field Bits Type Description
MSG_ID 30:26 Message Identifier
0 1000= Diagnostic Configuration
Data Sheet 41 Rev. 1.1, 2011-05-27
TLE7242-2G
Functional Description and Electrical Characteristics
If the SB_RETRY field is programmed to the value 0, the short to battery retry period is identical to the programmed
the PWM period as programmed in SPI message #1.
SBx 23:22
17:16
11:10
5:4
Short To Battery Threshold
00 = 0.7 V
01 = 0.9 V
10 = 1.1 V
11 = 1.3 V
SB_RETRYx 21:18
15:12
9:6
3:0
Short to Battery Retry Time
Retry after 4 * SB_RETRY * PWM periods
Field Bits Type Description
PWM
x
f
SB_Retry4
PeriodRetry
TLE7242-2G
Functional Description and Electrical Characteristics
Data Sheet 42 Rev. 1.1, 2011-05-27
5.6.2.10 SPI Message #9 - Diagnostic Read
Sent Values:
Diagnostic Read Reset Value: xx 00 00 03H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R/W MSG_ID unused
1514131211109876543210
unused
Field Bits Type Description
R/W 31 Read / Write Bit
0 = Read
1 = Write (interpreted as a read)
MSG_ID 30:26 Message Identifier
0 1001 = Diagnostic Read
Response Values:
Diagnostic Read Reset Value: xx 00 00 03H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0MSG_IDSG0
OFF-
TST0 SB0 SB-
TST0
OL-
OFF0
OL-
ON0 SG1 OFF-
TST1 SB1 SB-
TST1
1514131211109876543210
OL-
OFF1
OL-
ON1 SG2 OFF-
TST2 SB2 SB-
TST2
OL-
OFF2
OL-
ON2 SG3 OFF-
TST3 SB3 SB-
TST3
OL-
OFF3
OL-
ON3 ENL RBL
Field Bits Type Description
MSG_ID 30:26 Message Identifier
0 1001= Diagnostic Read (channel 0-3)
SGx 25,19,13,7 Short to Ground - Fault
OFF-TSTx 24,18,12,6 Short to Ground & Open Load (Gate Off) - Tested
SBx 23,17,11,5 Short to Battery - Fault
SB-TSTx 22,16,10,4 Short to Battery - Tested
OL-OFFx 21,15,9,3 Open Load (Gate Off) - Fault
OL-ONx 20,14,8,2 Open Load (Gate On) - Fault
ENL 1 Enable Pin Latch
RBL 0 Reset_B Pin Latch
Data Sheet 43 Rev. 1.1, 2011-05-27
TLE7242-2G
Functional Description and Electrical Characteristics
5.6.2.11 SPI Message #10 - Current Read
Sent Values:
Current Read Reset Value: xx 00 00 00H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R/W MSG_ID CH1 CH0 unused
1514131211109876543210
unused
Field Bits Type Description
R/W 31 Read / Write Bit
0 = Read
1 = Write (interpreted as a read)
MSG_ID 30:26 Message Identifier
0 1010 = Current Read
Channel 25:24 Channel Number
Response Values:
Current Read Reset Value: xx 00 00 00H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 MSG_ID CH1CH000000000
1514131211109876543210
0 0 Current Read
Field Bits Type Description
MSG_ID 30:26 Message Identifier
0 1010 = Current Read
Channel 25:24 Channel Number
Current Read 13:0 Current Read
SENSE
Read R
dCurrentRea
mACurrent 320
2
][ 14
TLE7242-2G
Functional Description and Electrical Characteristics
Data Sheet 44 Rev. 1.1, 2011-05-27
5.6.2.12 SPI Message #11 - Autozero Read
Sent Values:
Autozero Read Reset Value: xx 00 00 00H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R/W MSG_ID CH1 CH0 unused
1514131211109876543210
unused
Field Bits Type Description
R/W 31 Read / Write Bit
0 = Read
1 = Write (interpreted as a read)
MSG_ID 30:26 Message Identifier
0 1011 = Autozero Read
Channel 25:24 Channel Number
Response Values:
Autozero Read Reset Value: xx 00 00 00H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 MSG_ID CH1CH000000000
1514131211109876543210
OVL PSL AZon AZoff Autozero (on) value Autozero (off) value
Field Bits Type Description
MSG_ID 30:26 Message Identifier
01011 = Autozero Read
Channel 25:24 Channel Number
OVL 15 Overvoltage latch
This latch is set when the voltage on the BAT pin exceeds the
overvoltage threshold. The latch is reset when the BAT pin voltage is
below the threshold and the Autozero Read message is received.
Data Sheet 45 Rev. 1.1, 2011-05-27
TLE7242-2G
Functional Description and Electrical Characteristics
PSL 14 Phase sync latch
This latch is set when a rising edge occurs on the PHASE_SYNC pin.
The latch is reset when the Autozero Read message is received.
AZ on 13 Autozero (on) occurred
This latch is set when an autozero sequence has completed with a
low common mode input voltage. The latch is reset when the
Autozero Read message is received
AZ off 12 Autozero (off) occurred
This latch is set when an autozero sequence has completed with a
high common mode input voltage. The latch is reset when the
Autozero Read message is received
AZ (on) value 11:6 Autozero (on) value
The stored Autozero value used when the POS and NEG pin common
mode voltage is low.
AZ (off) value 5:0 Autozero (off) value
The stored Autozero value used when the POS and NEG pin common
mode voltage is high
Field Bits Type Description
TLE7242-2G
Functional Description and Electrical Characteristics
Data Sheet 46 Rev. 1.1, 2011-05-27
5.6.2.13 SPI Message #12 - Duty Cycle Read
Sent Values:
Duty Cycle Read Reset Value: xx 00 00 00H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R/W MSG_ID CH1 CH0 unused
1514131211109876543210
unused
Field Bits Type Description
R/W 31 Read / Write Bit
0 = Read
1 = Write (interpreted as a read)
MSG_ID 30:26 Message Identifier
0 1100 = Duty Cycle Read
Channel 25:24 Channel Number
Response Values:
Autozero Read Reset Value: xx 00 00 00H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 MSG_ID CH1 CH0 0 0 0 0 0 Duty Cycle
1514131211109876543210
Duty Cycle
Field Bits Type Description
MSG_ID 30:26 Message Identifier
0 1100 = Duty Cycle Read
Channel 25:24 Channel Number
Duty Cycle 18:0 Duty Cycle
Duty cycle of the PWM output of the selected channel.
%100
32
N
DutyCycle
CycleDuty
Data Sheet 47 Rev. 1.1, 2011-05-27
TLE7242-2G
Application Information
6 Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
Figure 18 Application Diagram
Note: This is a very simplified example of an application circuit. The function must be verified in the real application.
6.1 Further Application Information
• Please contact us to get the Pin FMEA
• For further information you may contact http://www.infineon.com/
TLE7242-2G
BAT
GND_A
ENABLE
V_SIGNAL
SI
SO
SCK
NEG0
OUT0
POS0
CS_B
10nF
10nF
Controller
TC1766
(AUDO-NG)
TEST
330
10nF
GND_D
FAULT
CLK
1K
0.2
SPD15N06S2L-64
NEG1
OUT1
POS1
10nF
1K
0.2
SPD15N06S2L-64
NEG2
OUT2
POS2
10nF
1K
0.2
SPD15N06S2L-64
Constant
Current
Solenoid
NEG3
OUT3
POS3
10nF
1K
SPD15N06S2L-64
On/Off
Solenoid
+3.3V or +5V
C I/O Voltage Level)
V5A
10nF
V5D
100nF
+5V Digi tal
PHASE_SYNC
RESET_B
SPI
PERIPHERAL
CLOCK
OUT I/O PORTS
+5V Analog
36V
Constant
Current
Solenoid
Constant
Current
Solenoid
10K
47uF
V
BAT
V
BAT
V
BAT
V
BAT
V
BAT
V
BAT
V
BAT
V
BAT
Power Supply
e.g. TLE6368
100pF
TLE7242-2G
Package Outlines
Data Sheet 48 Rev. 1.1, 2011-05-27
7 Package Outlines
Figure 19 PG-DSO-28
Green Product (RoHS-compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-
free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.Dimensions in mm
Data Sheet 49 Rev. 1.1, 2011-05-27
TLE7242-2G
Revision History
8 Revision History
0
Version Date Changes
1.0 July 9, 2008 Release of datasheet
1.1 May 27, 2011 Added new package drawing to include latest suffix codes
1.1 May 27, 2011 Corrected description of setpoint change - occurs at next PWM cycle not dither
cycle
Edition 2011-05-27
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2011 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.