87946I-147 1-to-10 Low Skew, 1, 2 LVCMOS/LVTTL 2.5V, 3.3V Fanout Buffer Datasheet General Description Features The 87946I-147 is a low skew, /1, /2 LVCMOS/LVTTL Fanout Buffer. The 87946I-147 has two selectable single ended clock inputs. The single ended clock inputs accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 10 to 20 by utilizing the ability of the outputs to drive two series terminated lines. * Ten single ended LVCMOS/LVTTL outputs, 7 typical output impedance * * Selectable LVCMOS/LVTTL CLK0 and CLK1 inputs Maximum input frequency: 250MHz The 87946I-147 is characterized at full 3.3V for input VDD, and mixed 3.3V and 2.5V for output operating supply mode. Guaranteed bank, output and part-to-part skew characteristics make the 87946I-147 ideal for those clock distribution applications demanding well defined performance and repeatability. * * * * * * * * Block Diagram Pin Assignment The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the /1, /2 or a combination of /1 and /2 modes. The master reset input, MR/nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL Bank skew: 30ps (maximum) Output skew: 175ps (maximum) Part-to-part skew: 850ps (maximum) Multiple frequency skew: 200ps (maximum) 3.3V core, 3.3V or 2.5V output supply modes -40C to 85C ambient operating temperature Lead-free packaging 3 32 31 30 29 28 27 26 25 QA[0:2] 3 QB[0:2] 1 DIV_SELB Pulldown 23 QB0 CLK0 3 22 VDDB CLK1 4 21 QB1 DIV_SELA 5 20 GND DIV_SELB 6 19 QB2 DIV_SELC 7 18 VDDB GND 8 17 VDDC 9 10 11 12 13 14 15 16 QC3 QC2 GND QC[0:3] QC1 4 1 87946I-147 DIV_SELC Pulldown 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View MR/nOE Pulldown (c)2016 Integrated Device Technology, Inc. GND 2 VDDC 0 24 VDD GND 0 1 QC0 DIV_SELA Pulldown CLK_SEL VDDC 1 VDDA /2 QA2 1 GND 0 QA1 /1 VDDA 0 Pullup CLK1 Pullup QA0 CLK0 Pullup GND MR/nOE CLK_SEL Pulldown 1 Revision C, September 19, 2016 87946I-147 Datasheet Pin Descriptions and Characteristics Table 1. Pin Descriptions Number Name 1 CLK_SEL Input 2 VDD Power 3, 4 CLK0, CLK1 Input Pullup Single-ended clock inputs. LVCMOS/LVTTL interface levels. 5 DIV_SELA Input Pulldown Controls frequency division for Bank A outputs. See Table 3 LVCMOS/LVTTL interface levels. 6 DIV_SELB Input Pulldown Controls frequency division for Bank B outputs. See Table 3. LVCMOS/LVTTL interface levels. 7 DIV_SELC Input Pulldown Controls frequency division for Bank C outputs. See Table 3. LVCMOS/LVTTL interface levels. 8, 11, 15, 20, 24, 27, 31 GND Power Power supply ground. 9, 13, 17 VDDC Power Output supply pins for Bank C outputs. 10, 12, 14, 16 QC0, QC1, QC2, QC3 Output Single-ended Bank C clock outputs. LVCMOS/LVTTL interface levels. 7 typical output impedance. 18, 22 VDDB Power Output supply pins for Bank B outputs. 19, 21, 23 QB2, QB1, QB0 Output Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels. 7 typical output impedance. 25, 29 VDDA Power Output supply pins for Bank A outputs. 26, 28, 30 QA2, QA1, QA0 Output Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels. 7 typical output impedance. 32 MR/nOE Type Input Description Pulldown Clock select input. When HIGH, selects CLK1. When LOW, selects CLK0. LVCMOS / LVTTL interface levels. Positive supply pin. Pulldown Active HIGH Master Reset. Active LOW Output Enable. When logic HIGH, the internal dividers are reset and the outputs are (High-Impedance). When logic LOW, the internal dividers and the outputs are enabled. See Table 3. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance VDD = VDDA = VDDB = VDDC = 3.6V 25 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k ROUT Output Impedance 7 (c)2016 Integrated Device Technology, Inc. Test Conditions 2 Minimum Typical Maximum Units 4 pF Revision C, September 19, 2016 87946I-147 Datasheet Function Tables Table 3. Clock Input Function Table Inputs Outputs MR/nOE DIV_SELA DIV_SELB DIV_SELC QA0:QA2 QB0:QB2 QC0:QC3 1 X X X High-Impedance High-Impedance High-Impedance 0 0 X X fIN/1 Active Active 0 1 X X fIN/2 Active Active 0 X 0 X Active fIN/1 Active 0 X 1 X Active fIN/2 Active 0 X X 0 Active Active fIN/1 0 X X 1 Active Active fIN/2 Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDX+ 0.5V Package Thermal Impedance, JA 47.9C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C Junction Temperature 125C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = VDDA = VDDB = VDDC = 3.3V 0.3V, TA = -40C to 85C Symbol Parameter VDD Minimum Typical Maximum Units Positive Supply Voltage 3.0 3.3 3.6 V VDDA, VDDB, VDDC Output Supply Voltage 3.0 3.3 3.6 V IDD Power Supply Current 55 mA IDDA, IDDB, IDDC Output Supply Current 23 mA (c)2016 Integrated Device Technology, Inc. Test Conditions 3 Revision C, September 19, 2016 87946I-147 Datasheet Table 4B. Power Supply DC Characteristics, VDD = 3.3V 5%, VDDA = VDDB = VDDC = 2.5V 5%, TA = -40C to 85C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 3.135 3.3 3.465 V VDDA, VDDB, VDDC Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 55 mA IDDA, IDDB, IDDC Output Supply Current 22 mA Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = VDDB = VDDC = 3.3V 0.3V, TA = -40C to 85C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current Test Conditions Minimum Typical Maximum Units 2 VDD + 0.3 V MR/nOE, DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL -0.3 0.8 V CLK0, CLK1 -0.3 1.3 V MR/nOE, DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL VDD = VIN = 3.6V 150 A CLK0, CLK1 VDD = VIN = 3.6V 5 A MR/nOE, DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL VDD = 3.6V, VIN = 0V -5 A CLK0, CLK1 VDD = 3.6V, VIN = 0V -150 A 2.6 V VOH Output High Voltage; NOTE 1 VDDA = VDDB = VDDC = 3.6V VOL Output Low Voltage; NOTE 1 VDDA = VDDB = VDDC = 3.63V IOZL Output Hi-Z Current Low VDDA = VDDB = VDDC = 3.63V IOZH Output Hi-Z Current High VDDA = VDDB = VDDC = 3.63V 0.5 -5 V A 5 A NOTE 1: Outputs terminated with 50 to VDDx/2. See Parameter Measurement Information section. Load Test Circuit diagrams. (c)2016 Integrated Device Technology, Inc. 4 Revision C, September 19, 2016 87946I-147 Datasheet Table 4D. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5%, VDDA = VDDB = VDDC = 2.5V 5%, TA = -40C to 85C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current Test Conditions Minimum Typical Maximum Units 2 VDD + 0.3 V MR/nOE, DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL -0.3 0.8 V CLK0, CLK1 -0.3 1.3 V MR/nOE, DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL VDD = VIN = 3.465V 150 A CLK0, CLK1 VDD = VIN = 3.465V 5 A MR/nOE, DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL VDD = 3.465V, VIN = 0V -5 A CLK0, CLK1 VDD = 3.465V, VIN = 0V -150 A 1.8 V VOH Output High Voltage; NOTE 1 VDDA = VDDB = VDDC = 2.625V VOL Output Low Voltage; NOTE 1 VDDA = VDDB = VDDC = 2.625V IOZL Output Hi-Z Current Low VDDA = VDDB = VDDC = 2.625V IOZH Output Hi-Z Current High VDDA = VDDB = VDDC = 2.625V 0.5 -5 V A 5 A NOTE 1: Outputs terminated with 50 to VDDx/2. See Parameter Measurement Information section. Load Test Circuit diagrams. (c)2016 Integrated Device Technology, Inc. 5 Revision C, September 19, 2016 87946I-147 Datasheet AC Electrical Characteristics Table 5A. AC Characteristics, VDD = VDDA = VDDB = VDDC = 3.3V 0.3V, TA = -40C to 85C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 tsk(b) Bank Skew, NOTE 2, 7 tsk(o) Test Conditions Maximum Units 250 MHz 5 ns Measured on rising edge at VDDX/2 30 ps Output Skew; NOTE 3, 7 Measured on rising edge at VDDX/2 175 ps tsk(w) Multiple Frequency Skew; NOTE 4, 7 Measured on rising edge at VDDX/2 275 ps tsk(pp) Part-to-Part Skew; NOTE 5, 7 Measured on rising edge at VDDX/2 850 ps t R / tF Output Rise/Fall Time; NOTE 6 950 ps tPW Output Pulse Width tPERIOD/2 + 1 % tEN Output Enable Time; NOTE 6 = 10MHz 3 ns tDIS Output Disable Time; NOTE 6 = 10MHz 3 ns 250MHz 20% to 80% Minimum Typical 2 400 tPERIOD/2 - 1 tPERIOD/2 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from VDD/2 of the input to VDDX/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltage and with equal load conditions. Measured at VDDX/2. NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltage and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDX/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. (c)2016 Integrated Device Technology, Inc. 6 Revision C, September 19, 2016 87946I-147 Datasheet Table 5B. AC Characteristics, VDD = 3.3V 5%, VDDA = VDDB = VDDC = 2.5V 5%, TA = -40C to 85C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 tsk(b) Bank Skew, NOTE 2, 7 tsk(o) Test Conditions Maximum Units 250 MHz 5 ns Measured on rising edge at VDDX/2 35 ps Output Skew; NOTE 3, 7 Measured on rising edge at VDDX/2 175 ps tsk(w) Multiple Frequency Skew; NOTE 4, 7 Measured on rising edge at VDDX/2 200 ps tsk(pp) Part-to-Part Skew; NOTE 5, 7 Measured on rising edge at VDDX/2 875 ps t R / tF Output Rise/Fall Time; NOTE 6 950 ps tPW Output Pulse Width tPERIOD/2 + 1 % tEN Output Enable Time; NOTE 6 = 10MHz 3 ns tDIS Output Disable Time; NOTE 6 = 10MHz 3 ns 250MHz 20% to 80% Minimum Typical 2 400 tPERIOD/2 - 1 tPERIOD/2 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from VDD/2 of the input to VDDX/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltage and with equal load conditions. Measured at VDDX/2. NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltage and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDX/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. (c)2016 Integrated Device Technology, Inc. 7 Revision C, September 19, 2016 87946I-147 Datasheet Parameter Measurement Information 2.05V 5% 1.65V0.15V 1.25V 5% SCOPE VDD, VDDA, VDDB, VDDC SCOPE VDD VDDA, VDDB, VDDC Qx Qx GND GND -1.65V0.15V -1.25V 5% 3.3V Core/2.5V Output Load AC Test Circuit 3.3V Core/3.3V Output Load AC Test Circuit Part 1 V DDO Qx V DDO 2 2 Qx Part 2 V DDO Qy V DDO 2 tsk(o) Qy Part-to-Part Skew Output Skew VDDx 2 QX0:QXx 2 tsk(pp) QBx, QCx VDDx 2 QX0:QXx QAx tsk() tsk(b) Where X = Bank A, B or C Multiple Frequency Skew Bank Skew (c)2016 Integrated Device Technology, Inc. 8 Revision C, September 19, 2016 87946I-147 Datasheet Parameter Measurement Information, continued QAx, QBx, QCx VDDx VDDx VDDx 2 2 2 VDDx 2 CLK0, CLK1 t PW t PERIOD odc = QAx, QBx, QCx t PW t PERIOD tPW & tPERIOD t PD Propagation Delay 80% QAx, QBx, QCx VDDx 2 80% 20% 20% tR tF Output Rise/Fall Time (c)2016 Integrated Device Technology, Inc. 9 Revision C, September 19, 2016 87946I-147 Datasheet Applications Information Recommendations for Unused Input and Output Pins Inputs: OUTputs: LVCMOS Control Pins LVCMOS Outputs All control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused LVCMOS output can be left floating. There should be no trace attached. CLK Inputs For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. Reliability Information Table 6. JA vs. Air Flow Table for a 32-Lead LQFP JA vs. Air Flow Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8C/W 55.9C/W 50.1C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9C/W 42.1C/W 39.4C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Transistor Count The transistor count for 87946I-147 is: 1204 Pin compatible to the MPC9446 and MPC946 (c)2016 Integrated Device Technology, Inc. 10 Revision C, September 19, 2016 87946I-147 Datasheet Package Outline and Package Dimensions Package Outline - Y Suffix for 32-Lead LQFP Table 7. Package Dimensions for 32-Lead LQFP Symbol N A A1 A2 b c D&E D1 & E1 D2 & E2 e L ccc JEDEC Variation: BBC - HD All Dimensions in Millimeters Minimum Nominal 32 0.05 1.35 0.30 0.09 0.45 0 0.10 1.40 0.37 9.00 Basic 7.00 Basic 5.60 Ref. 0.80 Basic 0.60 Maximum 1.60 0.15 1.45 0.45 0.20 0.75 7 0.10 Reference Document: JEDEC Publication 95, MS-026 (c)2016 Integrated Device Technology, Inc. 11 Revision C, September 19, 2016 87946I-147 Datasheet Ordering Information Table 8. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 87946AYI-147LF ICS7946AI147L "Lead-Free" 32-Lead LQFP Tray -40C to 85C 87946AYI-147LFT ICS7946AI147L "Lead-Free" 32-Lead LQFP Tape & Reel -40C to 85C 87946AYI-147LF/W ICS7946AI147L "Lead-Free" 32-Lead LQFP Tape & Reel, Pin1 Orientation: EIA-481-D -40C to 85C (c)2016 Integrated Device Technology, Inc. 12 Revision C, September 19, 2016 87946I-147 Datasheet Revision History Sheet Rev Table Page T2 1 2 8 A A A A Date Features section added Lead-Free bullet. Pin Description Table - corrected description for VDDA, VDDB and VDDC. Parameter Measurement Information Section - added part-to-part skew, bank skew, and multiple frequency skew diagrams. Application Section - added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free marking. Updated format throughout the datasheet. 7/22/08 AC Tables - added thermal note. Ordering Information Table - corrected the Part/Order Numbers and corrected the non-LF marking. Updated Header/Footer of the datasheet. 8/7/09 T8 10 12 T5A - T5B T8 6-7 12 T8 12 Removed leaded orderable parts from Ordering Information table 11/15/12 T8 12 14 Ordering Information Table - Added 87946AYI-147LF/W Ordering option. Updated Technical Support Contact Info to: clocks@idt.com 4/30/14 3 Absolute Maximum Ratings Table - added Junction Temperature. Updated datasheet header/footer. Deleted "ICS" prefix from part number. 2/24/16 B 1 C Description of Change Corrected datasheet title. Corrected General Description, first sentence from Clock Generator to Fanout Buffer. (c)2016 Integrated Device Technology, Inc. 13 Revision C, September 19, 2016 Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright (c)2016 Integrated Device Technology, Inc. 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