FSTD3125MTCX_NL - Fairchild Semiconductor

March 2008

FSTD3125 • Rev. 1.0.2

FSTD3125 — 4-Bit Bus Switch with Level Shifting

Features

 4Ω Switch Connection between Two Ports

 Minimal Propagation Delay through the Switch

 Low ICC

 Zero Bounce in Flow-through Mode

 Control Inputs Compatible with TTL Level

 TruTranslation Voltage Translation from 5.0V

Inputs to 3.3V Outputs

Description

Fairchild switch FSTD3125 provides four high-speed

CMOS TTL-compatible bus switches. The low on

resistance of the switch allows inputs to be connected

to outputs without adding propagation delay or

generating additional ground bounce noise. A diode to

VCC has been integrated into the circuit to allow for level

shifting between 5V inputs and 3.3V outputs.

The device is organized as four one-bit switches with

separate /OE inputs. When /OE is LOW, the switch is

ON and port A is connected to port B. When /OE is

HIGH, the switch is OPEN and a high-impedance state

exists between the two ports.

Ordering Information

Part Number Operating

Temperature

Range Package Packing

Method

FSTD3125MTC -40 to 85°C 14-Lead, Thin Shrink Small Outline Package (TSSOP) JEDEC

MO-153, 4mm Wide Tube

FSTD3125MTCX -40 to 85°C 14-Lead, Thin Shrink Small Outline Package (TSSOP), JEDEC

MO-153, 4mm Wide Tape and Reel

All pac kages are lead free per J EDEC: J-S T D-020B standard.

Technology Description

The Fairchild switch family derives from and embodi es Fairchild’ s proven switch technology used for s everal years in its

74LVX3L384 (FST3384) bus switc h product.

1A

/OE1

/OE2

/OE4

/OE3

4A

3A

2A

1B

2B

3B

4B

1

23

4

56

8

10

9

13

1112

Figure 1. Logic Diagram

FST3D125 • Rev. 1.0.2 2

FSTD3125 — 4-Bit Bus Switch with Level Shifting

Pin Configuration

/OE

1

1A

1B

/OE

2

2A

2B

GND

V

CC

/OE

4

4A

4B

/OE

3

3A

3B

14

13

12

11

10

9

8

1

2

3

4

5

6

7

Figure 2. TSSOP Pin Assignments

Pin Descriptions

Pin # Pin Names Description

1,4,10,13 /OE1, /OE2, /OE3, /OE4 Bus Switch Enables

2,5,9,12 1A, 2A, 3A, 4A Bus A

3,6,8,11 1B, 2B, 3B, 4B Bus B

14 VCC Supply Voltage

7 GND Ground

Truth Table

Inputs Inputs/Outputs

/OE A, B

LOW A = B

HIGH High Impedance

FST3D125 • Rev. 1.0.2 3

FSTD3125 — 4-Bit Bus Switch with Level Shifting

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VCC Supply Voltage -0.5 7.0 V

VS DC Switch Voltage -0.5 7.0 V

VIN DC Input Voltage(1) -0.5 7.0 V

IIK DC Input Diode Current, VIN<0V -50 mA

IOUT DC Output Sink Current 128 mA

ICC / IGND DC VCC / GND Current ±100 mA

TSTG Storage Temperature Range -65 +150 °C

Note:

1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are

observed.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Max. Unit

VCC Power Supply Operating 4.5 5.5 V

VIN Input Voltage 0 5.5 V

VOUT Output Voltage 0 5.5 V

Switch Control Input(2) 0 5

tr, tf Input Rise and Fall Time Switch I/O 0 DC ns/V

TA Operating Temperature, Free Air -40 +85 °C

Note:

2. Unused control inputs must be held HIGH or LOW. They may not float.

FST3D125 • Rev. 1.0.2 4

FSTD3125 — 4-Bit Bus Switch with Level Shifting

DC Electrical Characteristics

Typical values are at VCC = 5.0V and TA = 25°C.

TA=-40 to +85°C

Symbol Parameter Conditions VCC (V) Min. Typ. Max.

Units

VIK Clamp Diode Voltage IIN = -18mA 4.5 -1.2 V

VIH High-Level Input Voltage 4.5 to 5.5 2.0 V

VOH High-Level Figure 5, Figure 6, and

Figure 7 4.0 to 5.5 V

VIL Low-Level Input Voltage 4.5 to 5.5 0.8 V

0 ≤ VIN ≤ 5.5V 5.5 ±1.0 µA

IIN Input Leakage Current VIN = 5.5V 0 10 µA

IOZ Off-state Leakage

Current 0 ≤ A, B ≤ VCC 5.5 ±1.0 µA

VIN = 0V, IIN = 64mA 4.5 4 7

VIN = 0V, IIN = 30mA 4.5 4 7

RON Switch On Resistance(3)

VIN = 2.4V, IIN = 15mA 4.5 35 50

Ω

/OE1 = /OE2 = GND

VIN = VCC or GND,

IOUT = 0 1.5

ICC Quiescent Supply Current /OE1 = /OE2 = VCC

VIN = VCC or GND,

IOUT = 0

5.5

10

µA

ΔICC Increase in ICC per Input One Input at 3.4V, Other

Inputs at VCC or GND 5.5 2.5 mA

Note:

3. Measured by the voltage drop between the A and B pins at the indicated current through the switch. On

resistance is determined by the lower of the voltages on the A or B pins.

AC Electrical Characteristics

TA = -40 to +85°C, CL = 50pF, and RU = RD = 500Ω.

VCC = 4.5 – 5.5V

Symbol Parameter Conditions

Min. Max.

Units Figure

tPHL, tPLH Propagation Delay, Bus-to-Bus(4) V

IN = Open 0.25 ns Figure 3

Figure 4

tPZH ,tPZL Output Enable Time VIN = 7V for tPZL

VIN = Open for tPZH 1.0 6.1 ns

Figure 3

Figure 4

tPHZ, tPLZ Output Disable Time VIN = 7V for tPLZ

VIN = Open for tPHZ 1.5 6.4 ns

Figure 3

Figure 4

Note:

4. This parameter is guaranteed by design, but is not tested. The bus switch contributes no propagation delay

other than the RC delay of the typical on resistance of the switch and the 50pF load capacitance when driven by

an ideal voltage source (zero output impedance).

Capacitance

TA = +25°C, f = 1MHz. Capacitance is characterized, but not tested.

Symbol Parameter Conditions Typ. Units

CIN Control Pin Input Capacitance VCC = 5.0V 3 pF

CI/O Input/Output Capacitance VCC, /OE = 5.0V 6 pF

FSTD3125 • Rev. 1.0.2 5

FSTD3125 — 4-Bit Bus Switch with Level Shifting

AC Loadings and Waveforms

Notes: Input driven by 50Ω source terminated in 50Ω.

CL includes load and stray capacitance.

Input PRR = 1.0MHz, tw = 500ns.

Figure 3. AC Test Circuit

Figure 4. AC Waveforms

FSTD3125 • Rev. 1.0.2 6

FSTD3125 — 4-Bit Bus Switch with Level Shifting

Performance Characteristics

Figure 5. Output Voltage vs. Supply Voltage, VIN = VCC, TA = 85°C

Figure 6. Output Voltage vs. Supply Voltage, VIN = VCC, TA = 25°C

Figure 7. Output Voltage vs. Supply Voltage, VIN = VCC, TA = 0°C

FSTD3125 • Rev. 1.0.2 7

FSTD3125 — 4-Bit Bus Switch with Level Shifting

Physical Dimensions

C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,

AND TIE BAR EXTRUSIONS

F. DRAWING FILE NAME: MTC14REV6

R0.09 min

12.00°TOP & BOTTOM

0.43 TYP

1.00

D. DIMENSIONING AND TOLERANCES PER ANSI

Y14.5M, 1982

R0.09min

E. LANDPATTERN STANDARD: SOP65P640X110-14M

0.65

6.10

1.65

0.45

A. CONFORMS TO JEDEC REGISTRATION MO-153,

VARIATION AB, REF NOTE 6

B. DIMENSIONS ARE IN MILLIMETERS

Figure 8. 14-Lead, Thin Shrink Small Outline Package (TSSOP) MO-153, 4mm Wide

Pack age drawings are provi ded as a servic e to customers considering Fairc h i l d components. Drawi ngs may change in any manner

without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emic onductor representative to v er ify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

FSTD3125 • Rev. 1.0.2 8

FSTD3125 — 4-Bit Bus Switch with Level Shifting