AM28F512-95FEB - Advanced Micro Devices

FINAL

Publication# 11561 Rev: GAmendment/+2

Issue Date: January 1998

Am28F512

512 Kilobi t ( 64 K x 8-Bit)

CMOS 12.0 Volt, Bulk Erase Flash Memory

DISTINCTIVE CHARACTERISTICS

■High perfo rmance

— 70 ns maximum access time

■CMOS Low power consumption

— 30 mA maximum active current

— 100 µA maximum standby current

— No data retention power consumption

■Compatible with JEDEC-standard byte-wide

32-Pin EPROM pinouts

— 32-pin PDIP

— 32-pin PLCC

— 32-pin TSOP

■10,000 write/erase cycles minimum

■Write and erase voltage 12.0 V ±5%

■Latch-up protected to 100 mA

from -1 V to VCC +1 V

■Flasherase Electrical Bulk Chip-Erase

— One second typical chip-erase

■Flashrite Pro gramming

— 10 µs typical byte-program

— One second typical chip program

■Command register arch itecture for

microprocessor/microcontroller compatible

write interface

■O n- chi p add r es s and dat a lat c he s

■Advanced CMOS flash memory technology

— Low cost single transistor memory cell

■Automatic wr ite/erase pulse stop timer

GENERAL DESCRIPTION

The Am28F512 is a 512 K bit Flash memory orga-

nized as 64 Kbytes of 8 bits each. AMD’s Flash mem-

ories offer the most cost-effective and reliable read/

write non-volatile random access memory. The

Am28F512 is packaged in 32-pin PDIP, PLCC, and

TSOP versions. It is designed to be reprogrammed

and erased in-system or in standard EPROM pro-

grammers. The Am28F512 is erased when shipped

from the factor y.

The standard Am28F512 offers access times as f ast as

70 ns, allowing operation of high-speed microproces-

sors without wait states. To eliminate bus contention,

the Am28F512 has separate chip enable (CE#) and

output enable (OE#) controls.

AMD ’s Flash memories augment EPROM functional ity

wit h in-circuit electrical erasure and programming. The

Am28F512 uses a command register to manage this

functionality, while maintaining a standard JEDEC

Flash Standard 32-pin pinout. The command register

allows for 100% TTL level control inputs and fixed

power supply levels during erase and programming.

AMD’s Flash technology reliably stores memory con-

tents even after 10,000 erase and program cycles. The

AMD cell is designed to optimize the erase and pro-

gr a mmi n g mec h an is ms . I n ad dit i o n, t h e co mbi n a tio n of

advanced tunnel oxide processing and low internal

electric fields for erase and programming operations

produces reliable cycling. The Am28F512 uses a

12.0 V± 5% VPP high voltage input to perform the

Fl ash era se and Flas hr i te algorit hm s.

The highest degree of latch-up protection is achieved

with AM D’s prop r ietary non -e pi pr oce ss . Lat ch- up pro-

tection is provided for stresses up to 100 mA on ad-

dress and data pins from -1 V to VCC +1 V.

The Am28F512 is byte programmable using 10 ms pro-

gram ming pulses in accordan ce with AMD’s Flash rite

programming algorithm. The typical room temperature

programming time of the Am28F512 is one second.

The ent ire chip is b ul k er ased usi ng 10 ms era se pu ls es

according to AMD’s Flasherase algorithm. Ty pical era-

sure at room temperature is accomplished in less than

one second. The windowed package and the 15-20

minutes r equired f or EPROM erasure using ul tra- violet

light are elimin ated.

Commands are wr itten to the command register using

standard microprocessor write timings. Register con-

tents serv e as inputs to an internal state-machine which

controls the erase and programming circuitry. During

2 Am28F512

write cycles, the command register internally latches

address and data needed for the programming and

erase operations. For system design simplification, the

Am28F512 is designed to support either WE# or CE#

controlled writes. During a system write cycle, ad-

dresses are latched on the fa lling edge of WE# or CE#

whichev er occurs last. Data is latched on the rising edge

of WE# or CE# whiche ver occurs first. To simpli fy the f ol-

lowing discussion, the WE# pin is used as the write cycle

control pin throughout the rest of this text. All setup and

hold times are with respect to the WE# si gnal.

AMD’s Flash technology combines years of EPROM

and EEPROM experience to produce the highest levels

of quality, reliability, and cost effectiveness. The

Am28F512 electrically erases all bits simultaneously

using Fowler-Nordheim tunneling. The bytes are pro-

grammed one byte at a time using the EPROM

programming mechanism of hot electron injection.

BLOCK DIAGRAM

PR ODUCT SELECTOR GUIDE

Family Part Number Am28F512

Speed Options (VCC = 5.0 V ± 10%) -70 -90 -120 -150 -200

Max Access Time (ns) 70 90 120 150 200

CE# (E#) Access (ns) 70 90 120 150 200

OE# (G#) Access (ns) 35 35 50 55 55

Erase

Voltage

Switch

State

Control

Command

Voltage

Switch Chip Enable

Output Enable

Logic

Y-Decoder

X-Decoder

Y-Gating

524,288

Bit

Cell Matrix

11561G-1

A0–A15

OE#

CE#

WE#

VSS

VCC

To Array

DQ0–DQ7

Input/Output

Buffers

Data

Latch

VPP

Address

Latch

Low VCC

Detector Program/Erase

Pulse Timer

Am28F512 3

CONNECTION DIAGRAMS

Note:

Pin 1 is marked for orientation.

VPP VCC

DQ0

A12 A14

A15

16 18

DQ1

DQ2

VSS

WE# (W#)

A13

A11

OE# (G#)

A10

CE# (E#)

DQ7

DQ6

DQ5

DQ4

DQ3

11561G-2

PDIP

DQ6

VPP

DQ5

DQ4

DQ3

131 30

13 17 18 19 2016

DQ0

A14

A13

A11

OE# (G#)

A10

CE# (E#)

DQ7

A12

A15

VCC

WE# (W#)

DQ1

DQ2

VSS

PLCC

11561G-3

4 Am28F512

CONNECTION DIAGRAMS (continu ed)

32-Pin — Standard Pinout

32-Pin — Reverse Pinout

LOGIC SYMB OL

A11

A13

A14

WE#

VCC

VPP

A15

A12

OE#

A10

CE#

VSS

A11

A13

A14

WE#

VCC

VPP

A15

A12

OE#

A10

CE#

VSS

11561G-4

A0–A15

CE# (E#)

OE# (G#)

WE# (W#)

11561G-5

DQ0–DQ7

Am28F512 5

ORD ER IN G INFOR MA TI ON

St a nda rd Product s

AMD standard products are a vailable in sev eral pac kages and operating ranges. The order number (Valid Combination) is f ormed

by a combination of:

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this de vice . Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

DEVICE NUMBER/DESCRIPTION

Am28F512

512 Kilobit (64 K x 8-Bit) CMOS Flash Memory

AM28F512 -70 J C

OPTIONAL PROCESSING

Blank = Standard Processing

B = Burn-In

Contact an AMD representative for more information.

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

P = 32-Pin Plastic DIP (PD 032)

J = 32-Pin Rectangular Plastic Leaded Chip

Carrier (PL 032)

E = 32-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 032)

F = 32-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

Valid Combinations

AM28F256-70

PC, PI, PE,

JC, JI, JE,

EC, EI, EE,

FC, FI, FE

AM28F256-90

AM28F256-120

AM28F256-150

AM28F256-200

6 Am28F512

PIN DESCRIPTION

A0–A15

Address Inputs for memor y locations. Internal latches

hold addresses during write cycles.

CE# (E#)

Chip Enable active lo w input activates the chip’ s control

logic and input buffers. Chip Enable high will deselect

the device and operates the chip in stand-by mode.

DQ0–DQ7

Data Inputs during memory write cycles. Internal

latches hold data during write cycles. Data Outputs

during memory read cycles.

No Conn ect- corre spond ing pin i s no t conn ec ted in ter-

nally to the die.

OE# (G#)

Output Enable active low input gates the outputs of the

device through the data buffers during memory read

cycles. Output Enable is high during command se-

quencing and program/erase operations.

VCC

P o wer supp ly f or d e vice oper ati on. ( 5.0 V ± 5% or 10%)

VPP

Pro gram voltag e inpu t. VPP mu s t be at hi g h volt a ge in

order to write to the command register. The command

ory array contents . Memory contents cannot be altered

when VPP ≤ VCC +2 V.

VSS

Ground

WE# (W#)

Write En ab le activ e low input cont rols the write function

of the command register to the memory array. The tar-

get addre ss is latched on the falling edge of the Wr ite

Enab le pulse and the appropriate data is latched on the

rising edge of the pulse. Write Enable high inhibits writ-

ing to the de vice.

Am28F512 7

BASIC PRINCIPLES

The device uses 100% TTL-level control inputs to

manage the command register. Erase and repro-

gramming operations use a fixed 12.0 V ± 5% high

voltage input.

Read Only Memory

Without high VPP voltage, the device functions as a

read only memory and operates like a standard

EPROM. The control inputs still manage traditional

read, standby, output disable, and Auto select modes.

Command Register

The command register is enabled only when high volt-

age is applied to the VPP pin. The erase and repro-

gramming operations are only accessed via the

for erase and reprogramming operations. The tradi-

tional read, standby, output disable, and Auto select

modes are available via the register.

The device’s com mand regi ster is wr itten us ing stan-

dard microprocessor write timings. The register con-

trols an internal state machine that manages all device

operations. For system design simplification, the de-

vice is designed to support either WE# or CE# con-

trolled writes. During a system write cycle, addresses

are latched o n the fa lling edge of WE # or CE # w hich-

ever occurs last. Data is latched on the rising edge of

WE# or CE# whichever occur first. To simplify the fol-

lowing discussion, the WE# pin is used as the write

cycle control pin throughout the rest of this text. All

setup and hold times are with respect to the WE# sig-

nal.

Overview of Erase/Pr ogram Operations

Flasherase™ Sequence

A multiple step command sequence is required to

erase the Flash device (a two-cycle Erase command

and repeated one cycle verify commands).

Note: The Flash memory array must be completely

programmed to 0’s prior to erasure. Refer to the

Flashrite™ Programming Algorithm.

1. Erase Setup: Write the Setup Erase command to

the command register .

2. Erase: Wr it e the Erase com mand (sam e as Setu p

Erase command) to the command register again.

The s ec o nd co mm an d in i ti at es t he er a se o pe r at io n.

The system software routines must now time-out

the erase pulse width (10 ms) prior to issuing the

Erase-verify command. An integrated stop timer

pre vents any possibility of overerasure.

3. Erase-Verify: Write the Erase-verify command to

the command register. This command terminates

the erase operation. After the erase operation,

each byte of the array must be verified. Address in-

formation must be supplied with the Erase-verify

command. This command ver ifies the margin and

outpu ts t he addre ss ed b yte i n o rde r to co mpa re th e

array data with FFh data (Byte erased).

After successful data verification the Erase-verify

command is written again with new address infor-

mation. Each by te of the array is sequentially veri-

fied in this manner.

If data of the addressed location is not verified, the

Erase sequence is repeated until the entire array is

successfully verified or the sequence is repeated

1000 times.

Flashrite Programming Sequence

A three step command sequence (a two-cycle Program

command and one cycle Verify command) is required

to pr ogram a byte o f t h e Fla sh ar r a y. Re fer to the Fl a sh-

rite Algorithm.

1. Program Setup: Write the Setup Program com-

mand to the command re gist er.

2. Program: Write the Program command to the com-

mand register with the appropriate Address and

Data. The system software routines must now time-

out the progra m pulse width (10 µs) prio r to issuing

the Program-verify command. An integrated stop

timer pr events any possibility of overprogramming.

3. Program-Verify: Write the Program-verify com-

man d to th e com ma nd re gis t er. Th is c o mm a nd ter -

minates the programming operation. In addition,

this command verifies the margin and outputs the

byte just programmed in order to compare the array

data with the original data programmed. After suc-

cessful data verification, the programming se-

quence is initiated again f or the next byte address to

be programmed.

If data is not verified successfully, the Program se-

quence is repeated until a successful comparison is

verified or the sequence is repeated 25 times.

Data Protection

The devic e is des igned to offer protecti on aga inst acci-

dental erasure or programming caused by spurious

system lev el signals that may exist during power transi-

ti on s. Th e d evice po w er s up in i ts r ea d o nly st at e . Als o,

with its control register architecture, alteration of the

memory contents only occurs after successful comple-

tion of specif ic command s equences.

The device als o incor porates several feat ures to pre-

v ent in advertent write cycles resulting fromVCC power-

up and power-do wn transitions or system noise.

Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up

and p ower-down, th e device locks out write cycles for

8 Am28F512

VCC < VLKO (see DC Characteristics section for

voltag es ) . Wh en VCC < VLKO, the comm an d r eg is ter is

disabled, all internal program/erase circuits are

dis abled , and th e d evice resets t o th e r ea d m od e. Th e

device ignores all writes until VCC > VLKO. The user

must ensure that the control pins are in the correct logic

st at e when VCC > V LKO to prevent uninitentional writes.

Write Pulse “Glitch” P rotection

No ise p ul se s of less tha n 10 ns (typ i cal) on OE#, CE#

or WE# will not initiate a write cycle.

Logical Inhibit

Writi ng is inhi bited by holding an y one of OE# = VIL, CE#

= VIH or WE# = VIH. To initiate a write cycle C E# and

WE# must be a logical zero while OE# is a logical one.

Power-Up Wr ite Inhibi t

Power-up of the device with WE# = CE# = VIL and

OE# = VIH will not accept commands on the rising

edge of WE#. The internal state machine is automat-

ically reset to the read mode on power-up.

FUNCTIONAL DESCRIPTION

Descripti on of User Modes

Table 1. Am28F512 User Bus Operations (Notes 7 and 8)

Legend:

X = Don’t care, where Don’t Care is either VIL or VIH levels. VPPL = VPP

< VCC + 2 V. See DC Characteristics for voltage

levels of VPPH. 0 V < An < VCC

+ 2 V, (normal TTL or CMOS input levels, where n = 0 or 9).

Notes:

1. VPPL may be grounded, connected with a resistor to ground, or < VCC +2.0 V. VPPH is the programming voltage specified

for the device. Refer to the DC characteristics. When VPP = VPPL, memory contents can be read but not written or erased.

2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 2.

3. 11.5 < VID < 13.0 V. Minimum VID rise time and fall time (between 0 and VID voltages) is 500 ns.

4. Read operation with VPP = VPPH may access array data or the Auto select codes.

5. With VPP at high voltage, the standby current is ICC + IPP (standby).

6. Refer to Table 3 for valid DIN during a write operation.

7. All inputs are Don’t Care unless otherwise stated, where Don’t Care is either VIL or VIH levels. In the Auto select mode all

addresses except A9 and A0 must be held at VIL.

8. If VCC

≤

1.0 Volt, the voltage difference between VPP and VCC should not exceed 10.0 Volts. Also , the Am28F512 has a VPP

rise time and fall time specification of 500 ns minimum.

Operation CE# (E#)OE

(G#)WE

(W#)VPP

(Note 1) A0 A9 I/O

Read-Only

Read VIL VIL XV

PPL A0 A9 DOUT

Standby VIH XXV

PPL X X HIGH Z

Output Disable VIL VIH VIH VPPL X X HIGH Z

Auto-select Manufacturer

Code (Note 2) VIL VIL VIH VPPL VIL VID

(Note 3) CODE

(01H)

Auto-select Device Code

(Note 2) VIL VIL VIH VPPL VIH VID

(Note 3) CODE

(25H)

Read/Write

Read VIL VIL VIH VPPH A0 A9 DOUT

(Note 4)

Standby (Note 5) VIH XXV

PPH X X HIGH Z

Output Disable VIL VIH VIH VPPH X X HIGH Z

Write VIL VIH VIL VPPH A0 A9 DIN

(Note 6)

Am28F512 9

READ ONLY MODE

When VPP is less than VCC + 2 V, the comm and regis ter

is inactive. The de vice can either read array or autose-

lect data, or be standby mode.

Read

The devi ce f u nc ti on s as a r ea d o nly m emory w h en V PP

< VCC + 2 V. T he de v ice ha s tw o cont rol f unct ion s. B oth

must be satisfied in order to output data. CE# controls

power to the device. This pin should be use d for spe-

cific device sele ction. OE # con trol s the devi ce outpu ts

and s h ou ld be use d to gate dat a to th e ou tp ut pin s if a

device is selected.

Address access time tACC is equal to the delay from

sta ble ad dresse s to va li d ou tpu t da ta . Th e c h ip en abl e

access time tCE is the dela y from stab le addresses and

stable CE# to valid data at the output pins. The output

enable access time is the dela y from the f alling edge of

OE# to valid data at the output pins (assuming the ad-

dresses have been stable at least tACC–tOE).

Stand by Mode

The device has two standby modes. The CMOS

standby mode (CE# input held at VCC ± 0.5 V), con-

sumes less t han 100 µA o f curr ent . TTL s tandb y mod e

(CE# is held at VIH) reduc es the current requirements

to les s than 1mA. When in the standby mode the out-

puts ar e in a h ig h impeda nce s tate , i ndepend ent o f th e

OE# input.

If the device is deselected during erasure, program-

ming, or program/erase verification, the device will

draw active current until the operation is terminated.

Output D is a ble

Output from the device is disabled when OE# is at a

logic high level. When disabled, output pins are in a

high impedance state.

Auto Select

Flash memories can be programmed in-system or in a

standard PROM programmer. The device may be sol-

dered to the circuit board upon receipt of shipment and

programmed in-system. Alternatively, the device may

initially be programmed in a PROM programmer prior

to soldering the device to the board.

The Auto select mode allows the reading out of a binary

code from the device that will identify its manufactu rer

and type. This mode is intended for the purpose

of automatically matching the device to be pro-

grammed with its corresponding programming algo-

rithm. This mode is functional over the entire

temperature range of the device.

Programming In A PROM Prog rammer

To activate this mode, the programming equipment

must force VID (11.5 V to 13 .0 V) on add ress A 9. Two

id enti fie r b ytes ma y th en be seque nce d fr om th e de vi ce

out put s b y tog glin g ad dres s A0 from VIL to VIH. All other

address lines must be held at VIL, and VPP must be

less than or equal to VCC + 2.0 V while using this Auto

select mode. Byte 0 (A0 = VIL) r epr esen ts the m anuf ac -

turer code and byte 1 (A0 = VIH) the device identifier

code. For the de vice these two bytes are given in Table

2 below. All identifiers for manufacturer and device

codes will exhibit odd parity with the MSB (DQ7) de-

fined as the parity bit.

Tabl e 2. Am28F512 Auto Select Code

Type A0 Code (HEX)

Manufacturer Code VIL 01

Device Code VIH 25

10 Am28F512
ERASE, PROGRAM, AND READ MODE
When VPP is equal to 12.0 V  ± 5%,  the comman d reg-
ister is active. All functions are available. That is, the
device can program, erase, read array or autoselect
data, or be standby mode.
Write Operations
High voltage must  be applied to the VPP pin in order to
activate the command register. Data written to the reg-
ister serves as input to the internal state machine. The
output of the state machine determines the operational
func t ion of the  device.
The command register does not occup y an address ab le
memor y location. The register is a latch that stores the
command , along with the address and data infor m ation
needed to ex ecute the command. The register is written
by bringing  WE# and  CE# to VIL, while OE# is at VIH.
Addresses are latched on the f alling edge of  WE#,  while
data is latched on the rising edge of the WE# pulse.
Standard microprocessor write timings are used.
The device requires the OE# pin to be VIH f or write op-
erations. This condition eliminates the possibility for
bus contention during programming operations. In
order to write, OE# must be VIH, and CE# and WE#
must be VIL. If any pin is not in the correct state a write
command will not be executed.
Refer to AC Write Characteristics and the E rase/Pro -
gramming Waveforms for specific timing parameters.
Command Definitions 
The contents of the command register default to 00h
(Read Mode) in the absence of high voltage a pplied to
the VPP pin . The  device op era tes as  a rea d only  mem -
ory. High voltage on the VPP p i n enables t he co mma nd
reg i st er. De v ic e  op er a t ion s  ar e s e lec t e d b y  writ i n g s pe-
cific data  codes into the co mmand register. Table 3 de-
fin es the s e re gister com m and s.
Read Command
Mem ory contents can be accessed via the read com-
mand when VPP is high. To read from the device, write
00h into the command register. Standard microproces-
sor read cycles access data from the memory. The de-
vice will remain in the read mode until the command
register contents are altered.
The command register defaults to 00h (read mode)
upon VPP pow er -up . The 00 h (Re ad Mode ) regis ter de-
fault helps ensure that inadvertent alteration of the
memory contents does not occur during  the VPP po w er
transition. Refer to the AC Read Characteristics and
Waveform s  for the spe c ifi c timi n g para m ete rs.  
Tab le 3. Am28F512 Command De finitions
Notes:
1. Bus operations are defined in Table 1.
2. RA = Address of the memory location to be read.
EA = Address of the memory location to be read during erase-verify.
PA = Address of the memory location to be programmed.
X = Don’t care. Addresses are latched on the falling edge of the WE
#
 pulse.
3. RD = Data read from location RA during read operation.
EVD = Data read from l ocation EA during erase-verify.
PD = Data to be programmed at location PA. Data latched on the rising edge of WE
#.
PVD = Data read from location PA during program-verify. PA is latched on the Program command.
4. Refer to the appropriate section for algorithms and timing diagrams.
Command (Note 4)
First Bus Cycle Second Bus Cycle
Operation 
(Note 1) Address 
(Note 2) Data 
(Note 3) Operation 
(Note 1) Address 
(Note 2) Data 
(Note 3)
Read Memory Write X 00H/FFh Read RA RD
Read Auto select Write X 80h or 90h Read 00h/01h 01h/25h
Erase Set-up/Erase Write  Write X 20h Write X 20h
Erase-Verify Write EA A0h Read X EVD
Program Set-up/ Program  Write X 40h Write PA PD
Program-Verify Write X C0h Read X PVD
Reset Write X FFh Write X FFh

Am28F512 11

FLASHERASE E RA SE SE QUENCE

Erase Setup

Erase Setup is the first of a two-cycle erase command.

It is a com mand -only o perati on th at stag es the device

for bulk chi p erase. T he array cont ent s are no t altere d

wi th t hi s c o mma nd. 20 h i s w ritt e n t o th e c om ma nd re g-

ister in order to perform the Erase Setup operation.

Erase

The second two-cycle erase command initiates the

bulk erase operation. You must write the Erase com-

mand (20h) again to the register. The erase operation

begins with the rising edge of the WE# pulse. The

erase operation must be terminated by writing a new

command (Erase-v erify) to the register.

Thi s two ste p seq uenc e o f the Set up an d E rase c om-

man ds helps to ensure that memo ry contents are not

ac cide ntally eras ed . A lso, c hip e rasu re c a n on ly o ccu r

whe n hig h vol tag e is appl ied to t he VPP p in an d all c o n-

trol pins are in their proper state. In absence of this high

voltage, memory contents c annot be altered. Refer to

AC Erase Characteristics and Waveforms for specific

timing par amete rs.

Note: The Flash memory device must be fully

programmed to 00h data prior to erasure. This

equalizes the charge on all memory cells ensuring

re liable era sure.

Erase-Verify Command

The erase operation erases all bytes of the array

in pa rall el. A fte r th e e ras e op era ti on , all byte s mu s t b e

sequentially verified. The Erase-v erify operation is initi-

ate d b y w riti n g A0 h t o t he reg is t er. The b y te ad dr es s to

be verified must be supplied with the command. Ad-

dresses are latched on the falling edge of the WE#

pulse or CE# pulse, whichever occurs later. The rising

edge of the WE# pulse terminates the erase operation.

Margin Ver ify

During the Erase-verify operation, the device applies

an internally generated margin voltage to the

addressed byte. Reading FFh from the addressed byte

indicates that all bi ts in the by te are prop erly erased.

Verify Next Addre ss

You must write the Erase-verify command with the ap-

propriate address to the register prior to verification of

each address. Each new address is latched on the fall-

ing edge of WE# or CE# pu lse, whiche ver occurs l ater.

The process continues for each byte in the memor y

array until a byte does not retur n FFh data or all the

bytes in the array are accessed and verified.

If an address is not verified to FFh data, the entire chip

is erased again (refer to Erase Setup/Erase). Erase

verification then resumes at the address that failed to

verify. Erase is complete when all bytes in the array

have been verified. The device is now ready to be pro-

grammed. At this point, the verification operation is ter-

minated by writing a valid command (e.g. Program

Setup) to the command register. Figure 1 and Table 4,

the Flasherase electrical era se algorithm, illustrate how

commands and bus operations are combined to per-

form electrical erasure. Refer to AC Erase Characteris-

tics and Wa veforms for specific timing parameters.

12 Am28F512

Figure 1. Flasherase Electrical Erase Algor ithm

Start

Program All Bytes to 00h

Apply VPPH

Address = 00h

PLSCNT = 0

Write Erase Setup Command

Write Erase Command

Time out 10 ms

Write Erase Verify

Time out 6 µs

Read Data from Device

Data = FFh

Last Address

Write Reset Command

Apply VPPL

Erasure Completed

PLSCNT =

1000

Increment Address

Apply VPPL

Erase Error

Yes

11559G-6

Yes

Yes Yes

Increment

PLSCNT

Data = 00h

Am28F512 13

Flasherase Electri cal Erase Algorithm

This Flash memory device erases the entire array in

paral le l . Th e era se ti m e de pe nd s on VPP

, temperature,

and numbe r o f erase /program cycle s on th e device. In

general, reprogramming time increases as the number

of erase/program cycles increases.

The Flasherase electrical erase algorithm employs an

int era ct ive clo sed lo op flow to simul ta ne ou s ly erase all

bits in the array. Erasure begins with a read of the mem-

or y conte nt s. The dev ice i s era sed wh en shipp ed from

the factory. Reading FFh data from the device would

imm ed iat e l y be fol lo w ed b y e xecu tin g t he Fla s hrit e pr o-

gramming algorithm with the appropriate data pattern.

Should the device be currently programmed, data other

than FFh will be returned from address locations.

Follow the Flasherase algorithm. Unifor m and reliable

erasure is ensured by first programming all bits in the

device to their charged state (Data = 00h). This is

accomplished using the Flashrite Programming

algorithm. Erasure then continues w ith an initial erase

operation. Erase verification (Data = FFh) begins at

addr ess 0 00 0h a nd co nti nu es th ro ugh t he a rray to the

last address, or until data other than FFh is

encountered. If a byte fails to verify, the device is

erased again. With each erase operation, an

increasing number of bytes verify to the erased state.

Typically, devices are erased in less than 100 pulses

(one second). Erase efficiency may be improved by

storing the address of the last byte that f ails to verify in

a register. Following the next erase operation,

verifica tion may star t at the store d addre ss loca tion. A

total of 1000 erase pulses are allowed per reprogram

cycle, which corresponds to appro ximately 10 seconds

of cu mul ati v e era se tim e. The e nti re sequ enc e of er ase

and byte verification is performed with high voltage

applied to the VPP pin. Figu re 1 illustr ates the electrical

erase a lgori thm.

Table 4. Flasherase Electrical Erase Algorithm

Notes:

1. See AC and DC Characteristics for values of VPP parameters. The VPP power supply can be hard-wired to the device or

switchable. When VPP is switched, VPPL may be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V.

2. Erase V erify is performed only after chip erasure. A final read compare may be performed (optional) after the register is written

with the read command.

3. The erase algorithm Must Be Followed to ensure proper and reliable operation of the device.

Bus Operations Command Comments

Entire memory must = 00h before erasure (Note 3)

Note: Use Flashrite programming algorithm (Figure 3) for

programming.

Standby

Wait for VPP Ramp to VPPH (Note 1)

Initialize:

Addresses

PLSCNT (Pulse count)

Write Erase Setup Data = 20h

Erase Data = 20h

Standby Duration of Erase Operation (tWHWH2)

Write Erase-Verify (Note 2) Address = Byte to Verify

Data = A0h

Stops Erase Operation

Standby Write Recovery Time before Read = 6 µs

Read Read byte to verify erasure

Standby Compare output to FFh

Increment pulse count

Write Reset Data = FFh, reset the register for read operations

Standby Wait for VPP Ramp to VPPL (Note 1)

14 Am28F512

Figure 2. AC W avef orms For Erase Operations

ANALYSIS OF ERASE TIMING WAVEFORM

Note: T his analys is doe s n ot incl ude t he re quir emen t

to pr og r a m th e en ti re ar r ay t o 00 h da t a p rior t o er a s ur e .

Refer to the Flashrite

Programming algorithm.

Erase Setup/Erase

This analysis illustrates the use of two-cycle erase

commands (section A and B). The first erase com-

mand (20h) i s a Setup c ommand and does not affect

the array data (section A). The second erase com-

mand (20h) initiates the erase operation (section B)

on the rising edge of this WE# pulse. All bytes of the

memory arr a y are erased in paral lel . No address inf or-

mation is required.

The erase pulse occurs in section C.

Time-Out

A software timing routine (10 ms duration) must be ini-

ti ate d on the ris ing ed ge of the WE# pu ls e of se ctio n B .

Note: An integrated stop timer prevents any possibil-

ity of overerasure by limiting each time-out period of

10 ms.

Erase-Verify

Up on co mpl etion of the eras e sof tware timing rout ine,

the microprocessor must write the Erase-verify com-

mand (A0 h). Th is co mmand termina tes the er as e ope r-

ation on the rising edge of the WE# pulse (section D).

The Erase-verify command also stages the device for

data verification (section F).

After each erase operation each byte must be verified.

The byte address to be verified must be supplied with

Addresses

CE#

OE#

WE#

Data

VPP

VCC

11559G-7

20h

Section

A0h Data

Out

Bus Cycle Write Write Time-out Write Time-out Read Standby

Command 20h 20h N/A A0h N/A Compare

Data N/A

Function Erase

Setup Erase Erase

(10 ms) Erase-

Verify Transition

(6 µs) Erase

Verification

Proceed per

Erase

Algorithm

AB DEFCG

Am28F512 15

the E rase-ver ify co mma nd (sec tion D). Ad dresse s are

latched on the falling edge of the WE# pulse.

An othe r soft w are ti min g routi ne (6 µs du rati on) m ust be

executed to allow for generation of internal vol tages for

margin checking and read ope ration (secti on E).

During Erase-v erification (section F) each address that

returns F Fh data is successfully erased. Each address

of the arra y is sequentially verified in this manner by re-

peat ing sections D thru F until the entire array is veri-

fied or an address fails to verify. Should an address

location fail to verify to FFh data, erase the device

again. Repeat sections A thru F. Resume verification

(s ect i on D) wi th the faile d add re s s.

Each data change sequ ence allows the device to use

up to 1,000 erase pulses to completely erase. Typically

100 erase pulses are required.

Note: All address locations must be programmed to

00h prior to erase. This equalizes the charge on all

mem ory cell s an d ensu res reli able era sur e.

FLASHRITE PROGRAMMING SEQUENCE

Program Setup

The device is programmed byte by byte. Bytes may be

programmed sequentially or at random. Program Setup

is the first of a two-cycle program command. It stages

the d evice for byte programming. The Pr ogram Setup

operation is performed by writing 40h to the command

Program

Only after the program Setup operation is completed

will the ne xt WE# pulse initiate the activ e pr ogramming

operation. The appropriate address and data for pro-

gramming must be av ailable on the second WE# pulse.

Addresses and data are internally latched on the falling

and rising edge of the WE# pulse respectively. The ris-

ing edg e o f WE # also be gin s t he p ro gram min g op era-

tion. You must write the Program-verify command to

terminate the programming operation. This two step

se qu en ce o f the Setu p and Pr ogra m c o mm a nds hel p s

to ensure that memory contents are not accidentally

written. Also, programming can only occur when high

v ol tage is applie d to th e VPP pi n an d all con tr ol pi ns a re

in their proper state. In absence of this high voltage,

memory content s cannot be pro grammed.

Ref er to A C Characteristics and Wave f orms f or specific

timing par amete rs.

Program Verify Command

Following each programming operation, the byte just

programm e d must be ver if ie d.

Write C0h into the comman d registe r in order to initiate

the Program-verify operation. The rising edge of this

WE pu lse te rm ina tes the p rogram min g opera tion. Th e

Program-verify operation stages the device for verifica-

tion of the last byte progra mmed. Addresses were pre-

viously latched. No new information is requir ed.

Margin Ver ify

Duri ng t he Pr ogr am- v erify ope rati on, the de vic e ap pli es

an internally generated margin voltage to the ad-

dressed b yte. A normal microprocessor read cycle out-

puts the data. A successful comparison between the

programmed byte and the true data indicates that the

byte was successfully programmed. The original pro-

grammed data should be stored for comparison. Pro-

gramming then proceeds to the next desired byte

loc atio n. S h ou ld the byte fail to veri fy, re pr ogra m ( refer

to Program Setup/Program). Figure 3 and Table 5 indi-

ca te h ow ins tr u ctions a re com bin ed w it h th e bus op er -

ations to perform byte programming. Refer to AC

Programming Characteristics and Wavefor ms for spe-

cific timing parameters.

Flashrite P rog rammin g Algori thm

The device Flashrite Programming algorithm employs

an inte ract ive closed loop flow to program da ta byte by

byte. Bytes ma y be programmed sequentially or at ran-

dom. The Flashrite Programming algorithm uses 10 µs

programming pulses. Each operation is followed by a

byte verification to determine when the addressed byte

has been successfully programmed. The program al-

gorithm allo ws f or up to 25 programming operations per

byte per reprogramming cycle. Most bytes verify after

the first or second pulse. The entire sequence of pro-

gramm ing and byte verification is performed with high

voltag e ap pli e d to th e VPP pin . Figure 3 and Table 5 i l-

lustrate the programming algorithm.

16 Am28F512

Figure 3. Flashrite Programming Algorit hm

Start

Apply VPPH

PLSCNT = 0

Write Program Setup Command

Write Program Command (A/D)

Time out 10 µs

Write Program Verify Command

Time out 6 µs

Read Data from Device

Last Address

Write Reset Command

Apply VPPL

Progr amming Completed

PLSCNT =

25?

Increment Address

Apply VPPL

Device Failed

11559G-8

Yes

No No

Ver ify Byte Increment PLSCNT

Yes

Am28F512 17

Table 5. Flashrite Programming Algorithm

Notes:

1. See AC and DC Characteristics for values of VPP parameters. The VPP power supply can be hard-wired to the device or

switchable. When VPP is switched, VPPL may be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V.

2. Program V e rify is performed only after b yte programming. A final read/compare may be perf ormed (optional) after the register

is written with the read command.

Bus Operations Command Comments

Standby Wait for VPP Ramp to VPPH (Note 1)

Initialize Pulse c ounter

Write Program Setup Data = 40h

Program Valid Address/Data

Standby Duration of Programming Operation (tWHWH1)

Write Program-Verify (Note 2) Data = C0h Stops Program Operation

Standby Write Recovery Time before Read = 6 µs

Read Read Byte to Verify Programming

Standby Compare Data Output to Data Expected

Write Reset Data = FFh, resets the register for read operations.

Standby Wait for VPP Ramp to VPPL (Note 1)

18 Am28F512

Figure 4. AC Waveforms for Prog ramming Operations

ANALYSIS OF PROGRAM TIMING

WAVEFORMS

Program Setup/Program

Two-cycle write commands are required for program

operations (section A and B). The first program com-

man d (40h ) is a Setup co mmand and does not affect

the array data (section A). The second program com-

man d latches addr ess and data required for program-

ming on the f alling and rising edge of WE# respectively

(section B). The rising edge of this WE# pulse (section

B) also initiates the pro gramming pulse. The devic e is

programmed on a byte by byte basis either sequentially

or randomly.

The program pulse occurs in section C.

Time-Out

A software timing routine (10 µs duration) must be initi-

ated on the rising edge of the WE# pulse of section B.

Note: An integr ated stop timer prev e nts any possibility

of overprogramming by limiting each time-out period of

10 µs.

Program-Verify

Upon completion of the program timing routine, the mi-

croprocessor must write the program-verify command

(C0h). This command terminates the programming op-

eration on the rising edge of the WE# pulse (section D).

The program-verify command also stages the device

f or data v erif icat ion (s ecti on F ). An oth er s oftw ar e tim ing

routine (6 µs duration) must be executed to allow for

Addresses

CE#

OE#

WE#

Data

VPP

VCC

11559G-9

Data

20h

Section

A0h Data

Out

Bus Cycle Write Write Time-out Write Time-out Read Standby

Command 40h Program

Address,

Program Data N/A C0h

(Stops

Program) N/A Compare

Data N/A

Function Program

Setup

Program

Command

Latch

Address and

Data

Program

(10 µs) Program

Verify Transition

(6 µs) Program

Verification

Proceed per

Programming

Algorithm

AB DEFCG

DE FCG

Am28F512 19

gen er a tion o f int e rnal vo l t ages for m ar gi n ch ecki ng a nd

read operations (section E).

During program-verification (section F) each byte just

programmed is read to compare array data with original

program data. When successfully verified, the next de-

sired address is programmed. Should a byte f ail to ver-

ify, r ep ro gram th e byte (r epea t s ecti o n A thru F ) . Each

data ch ange sequ ence al lows the devi ce to use up t o

25 pr ogr am pu ls es per b yte . Typ icall y, byt es are veri fied

within one or two pulses.

Algorithm Timing Delays

There are four different timing delays associated with

the Flasherase and Flashrite algorithms:

1. The first delay is associated with the VPP rise-time

when VPP first turns on. The ca pa ci to rs o n th e VPP

bus cau se an RC ram p. Afte r swi tchi n g on the V PP

the del ay req uired is p ropo r tiona l to th e numbe r of

devices being erased and the 0.1 mF/device. VPP

mus t re ach it s fin al valu e 10 0 ns be fore c om m and s

ar e executed.

2. The second dela y time is the erase time pulse width

(10 ms). A software timing routine should be run by

the l ocal m icropr ocessor to ti me out th e delay. Th e

erase operation must be term inated at the conclu-

sion of the ti ming routin e or pr ior to executing any

system interrupts that may occur during the erase

operation. To ens ure proper device oper ation, write

the Erase-verify operation after each pulse.

3. A third delay time is required for each programm ing

pulse width (10 ms). The programming algorithm is

interactive and verifies each byte after a program

pulse. The program operation must be terminated at

the conclusion of the timing routine or prior to exe-

cuting any s ystem interrupts that may occur during

the programming operation.

4. A fourth timing delay associated with both the

Flasherase and Flashrite algorithms is the write re-

covery time (6 ms). During this time internal circuitry

is ch angi ng volt age levels fro m the e ras e/ pr ogram

level to those used for margin verify and read oper-

ati o ns . A n a tt emp t t o r ead t he devi ce du ri ng thi s pe-

rio d will r esult in possible fa lse data (it may app ear

the device is not properly erased or programmed).

Note: Software timing routines should be written in

machine language for each of the delays. Code written

in machine language requires knowledge of the appro-

priate microprocessor clock speed in order to accu-

rately time each delay.

P arallel Device Erasure

Many applications will use more than one Flash

memory device. Total erase time may be mini mized by

implementing a parallel erase algorithm. Flash

memories may erase at different rate s. Therefore e ach

device must be verified separately. When a device is

completely erased and verified use a masking code to

prev ent fu rther er asure . The other de vices will contin ue

to era se until verifi ed. The masking code applied could

be the read command (00h ).

Power-Up/Power- Down Sequen ce

The device powers-up in the Re ad only mode. Power

supply sequencing is not required. Note that if VCC ≤

1.0 Volt, the voltage difference between VPP and VCC

should not exceed 10.0 Volts. Also, the de vice has VPP

rise ti me and f a l l t i me sp ec ifi cat i on of 500 n s mi ni mum.

Reset Command

The Re set comman d initializes the Flash memor y de-

vice to the Read mode. In addition, it also provides the

user with a safe method to abort any device operation

(including program or erase).

The Rese t comm and mu st b e wri tten two co nsecut ive

times after the setup Program command (40h). This will

reset the device to the Read mode.

Following any other Flash command write the Reset

command once to the de vice . This w ill saf el y a bort an y

previous operation and initialize the device to the

Read mode.

The Setup Program command (40h) is the only com-

mand that requires a two sequence reset cycle. The

first Reset command is interpreted as program data.

However, F F h data is c o nsi d er ed nu ll d at a du ring p ro -

gramming operations (memory cells are only pro-

grammed from a logical “1” to “0”). The second Reset

command safely aborts the programming operation

and resets the device to the Read mode.

Memory contents are not altered in any case.

This detailed information is for your reference. It may

prove easier to always issue the Reset command two

consecutive times. This eliminates the need to deter-

mine if you are in the setup Program state or not.

Programming In-System

Flash memories can be programmed in-system or in a

standard PROM programmer. The device may be sol-

dered to the circuit board upon receipt of shipment and

programmed in-system. Alternatively, the device may

initially be programmed in a PROM programmer prior

to soldering the device to the board.

20 Am28F512

Auto Select Command

AMD’ s Flash memories are designed f or use in applica-

tions where the local CPU alters memory contents. Ac-

cordingly, manufacturer and device codes must be

accessible while the device resides in the target sys-

tem. PROM programmers typically access the signa-

ture codes by raising A9 to a high voltage. However,

multiplexing high voltage onto address lines is not a

generally de sired syst e m des ign practice.

The device contains an Auto Select operation to sup-

plement traditional PROM programming methodology.

The operation is initiated by writing 80h or 90h into the

command register. Following this command, a read

cycle address 0000h retrieves the manufacturer code

of 01h. A read cycle from address 0001h returns the

device code. To terminate the operation, it is necessary

to w r ite a no the r valid c o mm an d, such a s Rese t ( FF h) ,

into the register.

Am28F512 21

ABSOLUTE MAXIMUM RATINGS

Storage Temperature . . . . . . . . . . . . –65°C to +150°C

Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C

Ambi ent Temperature

with Power Applied. . . . . . . . . . . . . .–55°C to + 125°C

Voltage with Respect To Ground

All pins except A9 and VPP (Note 1) .– 2.0 V to +7.0 V

VCC (Note 1). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V

A9 (Note 2). . . . . . . . . . . . . . . . . . . .–2.0 V to +14.0 V

VPP (Note 2). . . . . . . . . . . . . . . . . . .–2.0 V to +14.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

vo ltage transit ions, input s may o v e rshoot VSS to –2.0 V for

periods of up to 20 ns. Maximum DC voltage on input and

I/O pins i s VCC + 0.5 V. During voltage transitions, input and

I/O pins may overshoot to VCC + 2.0V for periods up to

20ns.

2. Minimum DC input voltage on A9 and VPP pins is -0.5 V.

During voltage transitions, A9 and VPP may overshoot

VSS to -2.0 V for periods of up to 20 ns. Maximum DC

input voltage on A9 and VPP is +13.0 V which may

overshoot to 14.0 V for periods up to 20 ns.

3. No more than one output shorted to ground at a time.

Duration of the short circuit should not be greater than

one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the de vice. This is

a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the op-

erational sections of this specification is not implied. Expo-

sure of the device to absolute maximum rating conditions for

extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambi ent Temp erature (TA). . . . . . . . . . . .0°C to +70°C

Industrial (I) Devices

Ambi ent Temp erature (TA). . . . . . . . . .–40°C to +85°C

Extended (E) Devices

Ambi ent Temp erature (TA). . . . . . . . .–55°C to +125°C

VCC Supply Voltages

VCC . . . . . . . . . . . . . . . . . . . . . . . . +4.50 V to +5.50 V

VPP Voltages

Read . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.6 V

Program, Erase, and Verify. . . . . . +11.4 V to +12.6 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

22 Am28F512

MAXIM UM OVERSHOOT

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

11561G-10

Maximum Negative Input Overshoot

20 ns

VCC + 0.5 V

2.0 V

20 ns 20 ns

VCC + 2.0 V

11561G-11

Maximum Positive Input Overshoot

11561G-12

Maximum VPP Overshoot

20 ns

13.5 V

VCC + 0.5 V

20 ns 20 ns

14.0 V

Am28F512 23

DC CHARACTERISTICS o ver operati ng range unless otherwise specified

TTL/NMOS Compatible

Notes:

1. Caution: The Am28F512 must not be remov ed from (or inserted into) a socket when VCC or VPP is applied. If VCC

1.0 Volt,

the voltage difference between VPP and VCC should not exceed 10.0 Volts. Also, the Am28F512 has a VPP rise time and fall

time specification of 500 ns minimum.

2. ICC1 is tested with OE

= VIH to simulate open outputs.

3. Maximum active power usage is the sum of ICC and IPP

4. Not 100% tested.

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

ILI Input Leakage Current VCC = VCC Max, VIN = VCC or VSS ±1.0 µA

ILO Output Leaka ge Cur rent V CC = VCC Max, VOUT = VCC or VSS ±1.0 µA

ICCS VCC Standby Current VCC = VCC Max, CE# = VIH 0.2 1.0 mA

ICC1 VCC Active Read Current VCC = VCC Max, CE# = VIL, OE# = VIH

IOUT = 0 mA, at 6 MHz 20 30 mA

ICC2 VCC Programming Current CE# = VIL

Programming in Progress (Note 4) 20 30 mA

ICC3 VCC Erase Current CE# = VIL

Erasure in Progress (Note 4) 20 30 mA

IPPS VPP Standby Current VPP = VPPL ±1.0 µA

IPP1 VPP Read Current VPP = VPPH 70 200 µA

VPP = VPPL ±1.0

IPP2 VPP Programming Current VPP = VPPH

Programming in Progress (Note 4) 10 30 mA

IPP3 VPP Erase Current VPP = VPPH

Erasure in Progress (Note 4) 10 30 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 2.0 VCC + 0.5 V

VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V

VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC Min 2.4 V

VID A9 Auto Select Voltage A9 = VID 11.5 13.0 V

IID A9 Auto Select Current A9 = VID Max, VCC = VCC Max 5 50 µA

VPPL VPP during Read-Only

Operations

Note: Erase/Program are inhibited

when VPP = VPPL

0.0 VCC +2.0 V

VPPH VPP during Read/Write

Operations 11.4 12.6 V

VLKO Low VCC Lock-out Voltage 3.2 3.7 V

24 Am28F512

DC CHARACTERISTI CS

CMOS Compatible

Notes:

1. Caution: The Am28F512 m ust not be remov ed from (or inserted into) a sock et when VCC or VPP is applied. If VCC ð 1.0 v olt,

the voltage difference between VPP and VCC should not exceed 10.0 volts. Also, the Am28F512 has a VPP rise time and fall

time specification of 500 ns minimum.

2. ICC1 is tested with OE

= VIH to simulate open outputs.

3. Maximum active power usage is the sum of ICC and IPP

4. Not 100% tested.

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

ILI Input Leakage Current VCC = VCC Max, VIN = VCC or VSS ±1.0 µA

ILO Output Leaka ge Cur rent VCC = VCC Max, VOUT = VCC or VSS ±1.0 µA

ICCS VCC Standby Current VCC = VCC Max, CE# = VCC + 0.5 V 15 100 µA

ICC1 VCC Active Read Current VCC = VCC Max, CE# = VIL, OE# = VIH

IOUT = 0 mA, at 6 MHz 20 30 mA

ICC2 VCC Programming Current CE# = VIL

Programming in Progress (Note 4) 20 30 mA

ICC3 VCC Erase Current CE# = VIL

Erasure in Progress (Note 4) 20 30 mA

IPPS VPP Standby Current VPP = VPPL ±1.0 µA

IPP1 VPP Read Current VPP = VPPH 70 200 µA

IPP2 VPP Programming Current VPP = VPPH

Programming in Progress (Note 4) 10 30 mA

IPP3 VPP Erase Current VPP = VPPH

Erasure in Progress (Note 4) 10 30 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 0.7 VCC VCC + 0.5 V

VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V

VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC Min 0.85 VCC V

VOH2 IOH = –100 µA, VCC = VCC Min VCC –0.4

VID A9 Auto Select Voltage A9 = VID 11.5 13.0 V

IID A9 Auto Select Current A9 = VID Max, VCC = VCC Max 5 50 µA

VPPL VPP during Read-Only

Operations

Note: Erase/Program are inhibited

when VPP = VPPL

0.0 VCC + 2.0 V

VPPH VPP during Read/Write

Operations 11.4 12.6 V

VLKO Low VCC Lock-out Voltage 3.2 3.7 V

Am28F512 25

Figure 5. Am28F512 —Average ICC Active vs. Frequency

VCC = 5.5 V, A ddressi ng Patt ern = M inmax

Data Pattern = Check erboard

TEST CONDITIONS

Tabl e 6. Test Specifica tions

ICC Active in mA

0123456789101112

Frequency in MHz 11561G-13

55°C

0°C

25°C

70°C

125°C

2.7 kΩ

CL6.2 kΩ

5.0 V

Device

Under

Test

11561G-14

Figure 6. Test Setup

Note: Diodes are IN3064 or equivalent

Test Condit ion -70 All others Un it

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig capacitance) 30 100 pF

Input Rise and Fall Times ≤10 ns

Input Pulse Levels 0.0–3.0 0.45–2.4 V

Input timing measurement

reference levels 1.5 0.8, 2.0 V

Output timing measurement

reference levels 1.5 0.8, 2.0 V

26 Am28F512

SWITCHING TEST WAVEF ORMS

SWITCHING CHARACTERISTICS over operati ng range unless otherwise specified

AC Characteristics—Read On ly Operation

Notes:

1. Guaranteed by design not tested.

2. Not 100% tested.

Parameter Symbols

Parameter Description

Am28F512

UnitJEDEC Standard -70 -90 -120 -150 -200

tAVAV tRC Read Cycle Time (Note 2) Min 70 90 120 150 200 ns

tELQV tCE Chip Enable Access Time Max 70 90 120 150 200 ns

tAVQV tACC Address Access Time Max 70 90 120 150 200 ns

tGLQV tOE Output Enable Access Time Max 35 35 50 55 55 ns

tELQX tLZ Chip Enable to Output in Low Z

(Note 2) Min00000ns

EHQZ tDF Chip Disable to Output in High Z

(Note 1) Max2020303535ns

GLQX tOLZ Output Enable to Output in Low Z

(Note 2) Min00000ns

GHQZ tDF Output Disable to Output in High Z

(Note 2) Max2020303535ns

AXQX tOH Output Hold from first of Address,

CE#, or OE# Change (Note 2) Min00000ns

WHGL Write Recovery Time before Read Min 6 6 6 6 6 µs

tVCS VCC Setup Time to Valid Read

(Note 2) Min5050505050µs

11561G-15

3 V

0 V Input Output

1.5 V 1.5 V

Test Points

AC Testing for -70 devices: Inputs are driven at 3.0 V for a

logic “1” and 0 V for a logic “0”. Input pulse rise and fall time

are

≤

10 ns.

2.4 V

0.45 V Input Output

Test Points

2.0 V 2.0 V

0.8 V0.8 V

AC Testing (all speed options e xcept -70): Inputs are driven at

2.4 V f or a logic “1” and 0.45 V for a logic “0”. Input pulse rise

and fall times are

≤

10 ns.

Am28F512 27

AC Characteristics—Write/Erase/Program Operations

Notes:

1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC

Characteristics for Read Only operations.

2. Maximum pulse widths not required because the on-chip program/erase stop timer will terminate the pulse widths internally

on the device.

3. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In

systems where Chip-Enable defines the Write Pulse Width (within a longer Write-Enable timing wav efo rm) all setup, hold and

inactive Write-Enable times should be measured relative to the Chip-Enable waveform.

4. Not 100% tested.

Parameter Symbols

Parameter Description

Am28F512 Speed Options

UnitJEDEC Standard -70 -90 -120 -150 -200

tAVAV tWC Write Cycle Time (Note 4) Min 70 90 120 150 200 ns

tAVWL tAS Address Setup Time Min 0 0 0 0 0 ns

tWLAX tAH Address Hold Time Min 45 45 50 60 75 ns

tDVWH tDS Data Setup Time Min 45 45 50 50 50 ns

tWHDX tDH Data Hold Time Min 10 10 10 10 10 ns

tWHGL tWR Write Recovery Time before Read Min 6 6 6 6 6 µs

tGHWL Read Recovery Time before Write Min 0 0 0 0 0 µs

tELWL tCS Chip Enable Setup Time Min 0 0 0 0 0 ns

tWHEH tCH Chip Enable Hold Time Min 0 0 0 0 0 ns

tWLWH tWP Write Pulse Width Min 45 45 50 60 60 ns

tWHWL tWPH Wr ite Pulse Width HIGH Min 20 20 20 20 20 ns

tWHWH1 Duration of Programming Operation

(Note 2) Min1010101010µs

WHWH2 Duration of Erase Operation (Note 2) Min 9.5 9.5 9.5 9.5 9.5 ms

tVPEL VPP Setup Time to Chip Enab le LO W

(Note 4) Min 100 100 100 100 100 ns

tVCS VCC Setup Time to Chip Enable LOW

(Note 4) Min5050505050µs

VPPR VPP Rise Time 90% VPPH (Note 4) Min 500 500 500 500 500 ns

tVPPF VPP Fall Time 10% VPPL (Note 4) Min 500 500 500 500 500 ns

tLKO VCC < VLKO to Reset (Note 4) Min 100 100 100 100 100 ns

28 Am28F512

KEY TO SWITCHING WAVEFORMS

SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

Addresses

CE# (E#)

OE# (G#)

WE# (W#)

Data (DQ)

5.0 V

VCC

0 V

Power-up, Standby Device and

Address Selection Outputs

Enabled Data

Valid Standby, Power-down

Addresses Stable

High Z High Z

tWHGL

tAVQV (tACC)

tEHQZ

(tDF)

tGHQZ

(tDF)

tELQX (tLZ)

tGLQX (tOLZ)

tELQV (tCE)

tGLQV (tOE)

tAXQX (tOH)

Output Valid

tAVAV (tRC)

tVCS

11561G-16

F igure 7. AC Waveforms for Read Operations

Am28F512 29

SWITCHING WAVEFORMS

Figure 8. AC Waveforms for Erase Operations

DA T A IN

= A0h VALID

DATA

OUT

Erase-Verify

Command Erase

Verification Standby,

Power-down

tWLAX (tAH)

tEHQZ (tDF)

tWHGL

tGHQZ (tDF)

tGLQX (tOLZ)

tGLQV (tOE)

tELQV (tCE)

11561G-17

tELQX (tLZ)

tAVAV (tRC)

tAXQX (tOH)

DATA IN

= 20 h DA T A IN

= 20 h

Setup Erase

Command Erase

Command

P o wer-up,

Standby

tAVWL (tAS)

tAVAV (tWC)

tELWL (tCS)

tGHW L (tOES)

tWHEH (tCH)

tWHWH2

tWHWL (tWPH)

tWHDX (tDH)

tWLWH (tWP)

tDVWH (tDS)

tVCS

tVPEL

Addresses

HIGH Z

CE# (E)#

OE# (G)#

WE# (W)#

Data (DQ)

5.0 V

VCC

0 V

VPPH

VPP

VPPL

Erasure

30 Am28F512

SWITCHING WAVEFORMS

Figure 9. AC Waveforms for Programmings Operations

D ATA IN

= C0h VALID

DAT A

OUT

Verify

Command Programming

Verification Standby,

Power-down

tWLAX (tAH)

tGHQZ (tDF)

tWHGL

tGHQZ (tDF)

tGLQX (tOLZ)

tGLQV (tOE)

tELQV (tCE)

11561G-18

tELQX (tLZ)

tAVAV (tRC)

tAXQX (tOH)

DATA IN

= 40 h DATA IN

Setup Program

Command

Program

Command

Latch Address

and Data

Power-up,

Standby

tAVWL (tAS)

tAVAV (tWC)

tELWL (tCS)

tGHWL (tOES)

tWHEH (tCH)

tWHWH1

tWHWL (tWPH)

tWHDX (tDH)

tWLWH (tWP)

tDVWH (tDS)

tVCS

tVPEL

Addresses

HIGH Z

CE# (E#)

OE# (G#)

WE# (W#)

Data (DQ)

5.0 V

VCC

0 V

VPPH

VPP

VPPL

Programming

Am28F512 31

ERASE AND PROGRAMMING PE RFORMANCE

Notes:

1. 25°C, 12 V VPP

2. Maximum time specified is lower than worst case. Worst case is derived from the Flasherase/Flashrite pulse count

(Flasherase = 1000 max and Flashrite = 25 max). Typical worst case for program and erase is significantly less than the actual

device limit.

LATCHUP CHARACTERISTICS

PIN CAPACITANCE

Note: Sampled, not 100% tested. Test conditions TA = 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter

Limits

CommentsMin Typ

(Note 1) Max

(Note 2) Unit

Chip Erase Time 1 10 sec Excludes 00H programming prior to erasure

Chip Programming Time 1 6 sec Excludes system-level overhead

Write/Erase Cycles 10,000 Cycles

Parameter Min Max

Input Voltage with respect to VSS on all pins except I/O pins (Including A9 and VPP) –1.0 V 13.5 V

Input Voltage with respect to VSS on all pins I/O pins –1.0 V VCC + 1.0 V

Current –100 mA +100 mA

Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.

Par ameter

Symbol Para meter Descr iption Tes t Conditions Typ Max Unit

CIN Input Capacitance VIN = 0 8 10 pF

COUT Output Capacitance VOUT = 0 8 12 pF

CIN2 VPP Input Capacitance VPP = 0 8 12 pF

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time 150°C 10 Years

125°C 20 Years

32 Am28F512

PH YSI CAL DIMENSIONS

PD032—32-Pin Plastic DIP (measured in inches)

PL032—32-Pin Plastic Leaded Chip Carrier (measured in inches)

Pin 1 I.D.

1.640

1.670

.530

.580

.005 MIN

.045

.065

.090

.110

.140

.225

.120

.160 .016

.022

SEATING PLANE

.015

.060

16-038-S_AG

PD 032

EC75

5-28-97 lv

32 17

16 .630

.700

0°

10°

.600

.625

.009

.015

.050 REF.

.026

.032 TOP VIEW

Pin 1 I.D.

.485

.495

.447

.453

.585

.595

.547

.553

16-038FPO-5

PL 032

DA79

6-28-94 ae

SIDE VIEW

SEATING

PLANE

.125

.140

.009

.015

.080

.095

.042

.056

.013

.021

.400

REF. .490

.530

Am28F512 33

PH YSI CAL DIMENSIONS

TS032—32-Pin Standar d Thin Small Outline Packa ge (measured in millimeters)

Pin 1 I.D.

18.30

18.50

7.90

8.10

0.50 BSC

0.05

0.15

0.95

1.05

16-038-TSOP-2

TS 032

DA95

3-25-97 lv

19.80

20.20

1.20

MAX

0.50

0.70

0.10

0.21

0°

5°

0.08

0.20

34 Am28F512

PH YSI CAL DIMENSIONS

TSR032—32-Pin Re versed Th in Small Outline Package (measured in millimeters)

18.30

18.50

19.80

20.20

7.90

8.10

0.50 BSC

0.05

0.15

0.95

1.05

16-038-TSOP-2

TSR032

DA95

8-15-96 lv

Pin 1 I.D.

1.20

MAX

0.50

0.70

0.10

0.21

0°

5°

0.08

0.20

0.17

0.27

Am28F512 35

DATA SHEET REVISION SUMMARY FOR

AM28F512

Deleted -75, -95, and -250 speed options . Matched f or-

matting to other current data sheets.

Amendment G+1

Removed reference to LCC package in Distinctive

Characteristics. Added A15 to PLCC and PDIP con-

nection diagrams.

Figure 3, Flashrite Programming Algorithm:

Mov e d end

of arrow originating from Increment Address box so

that it points to the PLSCNT = 0 bo x, not the Write Pro-

gram Verify Command box. This is a correction to the

diagram on page 6-189 of the 1998 Flash Memory

Da ta Book.

Revision G+2

Programming In A PROM Programmer:

Deleted the paragraph “(Refer to the AUTO SELECT

paragraph in the ERASE, PROGRAM, and READ

MODE section for programming the Flash memory de-

vice in-system).”

Trademarks

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.