PRELIMINARY TECHNICAL DATA +5V UPSTREAM CABLE LINE DRIVER a Preliminary Technical Data FEATURES Supports DOCSIS and EuroDOCSIS Standard for Reverse Path Transmission Systems Gain Programmable in 1 dB Steps over a 59dB Range Low Distortion at 60 dBmV Output -54 dBc SFDR at 21 MHz -52 dBc SFDR at 65 MHz Output Noise Level @ Minimum Gain 1.4nV/rtHz Maintains 300 Output Impedance TX-Enable and Transmit-Disable Condition Upper Bandwidth: 130 MHz (Full Gain Range) 5 V Supply Operation Supports SPI Interfaces AD8328 APPLICATIONS DOCSIS and EuroDOCSIS Cable Modems CATV Set-Top Boxes CATV Telephony Modems Coaxial and Twisted Pair line driver GENERAL DESCRIPTION The AD8328 is a low-cost, digitally controlled, variable gain amplifier optimized for coaxial line driving applications such as cable modems that are designed to the MCNSDOCSIS and EuroDOCSIS upstream standard. An 8-bit serial word determines the desired output gain over a 59dB range resulting in gain changes of 1dB/LSB. The AD8328 accepts a differential or single-ended input signal. The output is specified for driving a 75 load, through a 2:1 transformer. Distortion performance of -52 dBc is achieved with an output level up to 60 dBmV at 65 MHz bandwidth over a wide temperature range. GND VCC GND GND VIN+ VINGND DATEN SDATA CLK The AD8328 is packaged in a low cost 20-lead LFCSP package and a 20-lead QSOP package. The AD8328 operates from a single 5V supply, and has an operational temperature range of -40C to +85C. TXEN VCC GND GND VCC This device has a sleep mode function that reduces the quiescent current to 2.6mA, and a full power down function which reduces power down current to 10A. AD8329 AD8328 20-pin QSOP GND VCC TXEN RAMP VOUT+ VOUTBYP NC SLEEP GND GND RAMP GND VOUT+ VIN+ VIN-- AD8328 20LFCSP VOUT-BYP NC GND SLEEP GND CLK SDA TA DA TEN REV. PrA April 4, 2002 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002 PRELIMINARY TECHNICAL DATA AD8328-SPECIFICATIONS Parameter (T A = 25C, VS = 5 V, RL = RIN = 75 , (using differential input) VIN = 30 dBmV, VOUT measured through a 2:1 transformer1 with an insertion loss of 0.5 dB @ 10 MHz unless otherwise noted.) Conditions INPUT CHARACTERISTICS Specified AC Input Voltage Input Resistance Min Output = 60 dBmV, Max Gain Single-Ended Input Differential Input Input Capacitance GAIN CONTROL INTERFACE Voltage Gain Range Maximum Minimum Output Step Size TA = -40C to +85C OUTPUT CHARACTERISTICS Bandwidth (-3 dB) Bandwidth Roll-Off 1 dB Compression Point Gain Code = 60 Dec Gain Code = 1 Dec 0.6 Typ Max Unit 31 800 1600 2 dBmV pF 59 31 -28 dB dB dB 1.0 1.4 dB/LSB All Gain Codes (0-60 decimal codes) f = 65 MHz Max Gain, f = 10 MHz 130 1.0 TBD MHz dB dBm Output Noise Maximum Gain Minimum Gain Transmit Disable Noise Figure f = 10 MHz f = 10 MHz f = 10 MHz Max Gain, f = 10 MHz 160 1.4 1.4 TBD nV/rtHz nV/rtHz nV/rtHz Differential Output Impedance TX-Enable and TX-Disable 75 30%2 OVERALL PERFORMANCE Second Order Harmonic Distortion TA = -40C to +85C Third Order Harmonic Distortion TA = -40C to +85C f f f f f f = = = = = = 21 42 65 21 42 65 MHz, MHz, MHz, MHz, MHz, MHz, POUT POUT POUT POUT POUT POUT = = = = = = 60 60 60 60 60 60 dBmV dBmV dBmV dBmV dBmV dBmV @Max @Max @Max @Max @Max @Max Gain Gain Gain Gain Gain Gain -61 -61 -59 -54 -52 -52 ACPR 3 Isolation (Transmit Disable) POWER CONTROL TX-Enable Settling Time TX-Disable Settling Time Output Switching Transients Output Settling Due to Gain Change Due to Input Step Change POWER SUPPLY Operating Range Quiescent Current -55 -55 -55 -50 -50 -50 dBc dBc dBc dBc dBc dBc TBD dBc Max Gain, f = 65 MHz -60 dBc Max Gain, Max Gain, Equivalent Equivalent 3.5 3.5 s s mV p-p mV p-p VIN = 0 VIN = 0 Output = 31 dBmV Output = 60 dBmV 7 50 Min to Max Gain Max Gain, VIN = 30 dBmV TBD TBD 4.75 Maximum Gain Minimum Gain Transmit Disable, TXEN = 0 Sleep Mode (Power-Down) OPERATING TEMPERATURE RANGE -40 5 125 24 2.6 10 ns ns 5.25 V mA mA mA A +85 C NOTES 1 TOKO 458PT-1087 used for above specifications. 2 Measured through a 2:1 transformer. 3 V in = 30dBmV, QPSK modulation, 160ksps symbol rate -2- April 4, 2002 REV. PrA PRELIMINARY TECHNICAL DATA AD8328 LOGIC INPUTS (TTL/CMOS Compatible Logic) (DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 5 V: Full Temperature Range) Parameter Min Logic Logic Logic Logic Logic Logic Logic Logic 2.1 0 0 -600 50 -250 50 -250 "1" "0" "1" "0" "1" "0" "1" "0" Voltage Voltage Current (VINH = 5 V) CLK, SDATA, DATEN Current (VINL = 0 V) CLK, SDATA, DATEN Current (VINH = 5 V) TXEN Current (VINL = 0 V) TXEN Current (VINH = 5 V) SLEEP Current (VINL = 0 V) SLEEP TIMING REQUIREMENTS Max Unit 5.0 0.8 20 -100 190 -30 190 -30 V V nA nA A A A A (Full Temperature Range, VCC = 5 V, TR = TF = 4 ns, fCLK = 8 MHz unless otherwise noted.) Parameter Min Clock Pulsewidth (T WH ) Clock Period (TC) Setup Time SDATA vs. Clock (TDS) Setup Time DATEN vs. Clock (TES) Hold Time SDATA vs. Clock (TDH) Hold Time DATEN vs. Clock (TEH) Input Rise and Fall Times, SDATA, DATEN, Clock (TR, TF) 16.0 32.0 5.0 15.0 5.0 3.0 REV. PrA April 4, 2002 Typ -3- Typ Max Unit 10 ns ns ns ns ns ns ns PRELIMINARY TECHNICAL DATA AD8328 ABSOLUTE MAXIMUM RATINGS* Supply Voltage +V S Pins TBD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Input Voltages Pins TBD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V Pins TBD . . . . . . . . . . . . . . . . . . . . . . . . -0.8 V to +5.5 V Internal Power Dissipation LFCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD W QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD W Operating Temperature Range . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . -65C to +150C Lead Temperature, Soldering 60 seconds . . . . . . . 300C * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Range Package Description AD8328ACP AD8328ACP-REEL AD8328ARQ AD8328ARQ-REEL AD8328-EVAL -40C -40C -40C -40C 20-Lead LFCSP 20-Lead LFCSP 20-Lead QSOP 20-Lead QSOP Evaluation Board to to to to +85C +85C +85C +85C *Thermal Resistance measured on SEMI standard 4-layer board. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8325 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN FUNCTION DESCRIPTIONS (QSOP-20 Package) Pin No. Mnemonic Description 8 DATEN 9 SDATA 10 CLK 1, 3, 4, 7, 11, 20 GND Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previous gain state) and simultaneously enables the register for serial data load. Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the internal register with the MSB (Most Significant Bit) first. Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave. This requires the input serial data word to be valid at or before this clock transition. Common External Ground Reference. 2, 19 18 12 VCC TXEN SLEEP 15 16 14 17 5 VOUT- VOUT+ BYP RAMP V IN+ 6 VIN- Common Positive External Supply Voltage. A 0.1 F capacitor must decouple each pin. Logic "0" disables forward transmission. Logic "1" enables forward transmission. Low Power Sleep Mode. In the Sleep mode, the AD8328's supply current is reduced to 1 A. A Logic "0" powers down the part (High ZOUT State) and a Logic "1" powers up the part. Negative Output Signal. Positive Output Signal. Internal Bypass. This pin must be externally ac-coupled (0.1 F cap). This is the external RAMP capacitor (OPTIONAL) Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 F capacitor. Inverting Input. DC-biased to approximately VCC/2. -4- April 4, 2002 REV. PrA