REV. PrA April 4, 2002
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Preliminary Technical Data AD8328
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
+5V UPSTREAM
CABLE LINE DRIVER
FEATURES
Supports DOCSIS and EuroDOCSIS Standard for Reverse
Path Transmission Systems
Gain Programmable in 1 dB Steps over a 59dB Range
Low Distortion at 60 dBmV Output
–54 dBc SFDR at 21 MHz
–52 dBc SFDR at 65 MHz
Output Noise Level @ Minimum Gain
1.4nV/rtHz
Maintains 300Ω Output Impedance
TX-Enable and Transmit-Disable Condition
Upper Bandwidth: 130 MHz (Full Gain Range)
5 V Supply Operation
Supports SPI Interfaces
GENERAL DESCRIPTION
The AD8328 is a low-cost, digitally controlled, variable gain
amplifier optimized for coaxial line driving applications
such as cable modems that are designed to the MCNS-
DOCSIS and EuroDOCSIS upstream standard. An 8-bit
serial word determines the desired output gain over a 59dB
range resulting in gain changes of 1dB/LSB.
The AD8328 accepts a differential or single-ended input
signal. The output is specified for driving a 75Ω load,
through a 2:1 transformer.
Distortion performance of –52 dBc is achieved with an
output level up to 60 dBmV at 65 MHz bandwidth over a
wide temperature range.
This device has a sleep mode function that reduces
the quiescent current to 2.6mA, and a full power down
function which reduces power down current to 10µA.
The AD8328 is packaged in a low cost 20-lead LFCSP
package and a 20-lead QSOP package. The AD8328 oper-
ates from a single 5V supply, and has an operational
temperature range of –40°C to +85°C.
APPLICATIONS
DOCSIS and EuroDOCSIS Cable Modems
CATV Set-Top Boxes
CATV Telephony Modems
Coaxial and Twisted Pair line driver
a
GND
VCC
TXEN
RAMP
VOUT+
VOUT-
BYP
NC
SLEEP
GND
GND
VCC
GND
GND
VIN+
VIN-
GND
DATEN
SDATA
CLK
AD8328
20-p in Q SOP
GND
VCC
TXEN
VOUT+
VOUT-
BYP
NC
SLEEP
GND
GND
VCC
GND
GND
VIN+
VIN-
GND
DATEN
SDATA
CLK
AD8329
20-p in Q SOP
GND
VCC
TXEN
VOUT+
VOUT-
BYP
NC
SLEEP
GND
GND
VCC
GND
GND
VIN+
VIN-
GND
DATEN
SDATA
CLK
AD8328
20-p in Q SOP
GND
VCC
TXEN
VOUT+
VOUT-
BYP
NC
SLEEP
GND
GND
VCC
GND
GND
VIN+
VIN-
GND
DATEN
SDATA
CLK
AD8328
20-p in Q SOP
GND
VCC
TXEN
RAMP
VOUT+
VOUT-
BYP
NC
SLEEP
GND
GND
VCC
GND
GND
VIN+
VIN-
GND
DATEN
SDATA
CLK
AD8328
20-p in Q SOP
GND
VCC
TXEN
VOUT+
VOUT-
BYP
NC
SLEEP
GND
GND
VCC
GND
GND
VIN+
VIN-
GND
DATEN
SDATA
CLK
AD8329
20-p in Q SOP
GND
VCC
TXEN
VOUT+
VOUT-
BYP
NC
SLEEP
GND
GND
VCC
GND
GND
VIN+
VIN-
GND
DATEN
SDATA
CLK
AD8328
20-p in Q SOP
GND
VCC
TXEN
VOUT+
VOUT-
BYP
NC
SLEEP
GND
GND
VCC
GND
GND
VIN+
VIN-
GND
DATEN
SDATA
CLK
AD8328
20-p in Q SOP
GND
VCC
GND
VIN+
VIN-
DATEN
SDATA
CLK
GND
VCC
TXEN
RAMP
VOUT+
VOUT-
BYP
NC
SLEEP
GND
GND
AD8328
20LFCSP
VCC
GND
-
SDATA
CLK
VCC
TXEN
VOUT+
-
BYP
NC
SLEEP
GND
VCC
-
SDATA
CLK
VCC
TXEN
VOUT+
BYP
SLEEP
GND
AD8328
20LFCSP
GND
VCC
GND
VIN+
VIN-
DATEN
SDATA
CLK
GND
VCC
TXEN
RAMP
VOUT+
VOUT-
BYP
NC
SLEEP
GND
GND
AD8328
20LFCSP
VCC
GND
-
SDATA
CLK
VCC
TXEN
VOUT+
-
BYP
NC
SLEEP
GND
VCC
-
SDATA
CLK
VCC
TXEN
VOUT+
BYP
SLEEP
GND
AD8328
20LFCSP
PRELIMINARY TECHNICAL DATA
April 4, 2002 REV. PrA
–2–
AD8328–SPECIFICATIONS (T A = 25°C, VS = 5 V, RL = RIN = 75 Ω, (using differential input) VIN = 30 dBmV, VOUT
measured through a 2:1 transformer1 with an insertion loss of 0.5 dB @ 10 MHz
unless otherwise noted.)
Parameter Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Specified AC Input Voltage Output = 60 dBmV, Max Gain 31 dBmV
Input Resistance Single-Ended Input 800 Ω
Differential Input 1600 Ω
Input Capacitance 2pF
GAIN CONTROL INTERFACE
Voltage Gain Range 59 dB
Maximum Gain Code = 60 Dec 31 dB
Minimum Gain Code = 1 Dec –28 dB
Output Step Size
T
A
=
-40
°C to +85°C
0.6 1.0 1.4 dB/LSB
OUTPUT CHARACTERISTICS
Bandwidth (–3 dB) All Gain Codes (0-60 decimal codes) 130 MHz
Bandwidth Roll-Off f = 65 MHz 1.0 dB
1 dB Compression Point Max Gain, f = 10 MHz TBD dBm
Output Noise
Maximum Gain f = 10 MHz 160 nV/rtHz
Minimum Gain f = 10 MHz 1.4 nV/rtHz
Transmit Disable f = 10 MHz 1.4 nV/rtHz
Noise Figure Max Gain, f = 10 MHz TBD
Differential Output Impedance TX-Enable and TX-Disable 75 ± 30%
2
Ω
OVERALL PERFORMANCE
Second Order Harmonic Distortion
f = 21 MHz, P
OUT
= 60 dBmV @Max Gain –61 -55 dBc
T
A
=
-40
°C to +85°C
f = 42 MHz, P
OUT
= 60 dBmV @Max Gain –61 -55 dBc
f = 65 MHz, P
OUT
= 60 dBmV @Max Gain –59 -55 dBc
Third Order Harmonic Distortion
f = 21 MHz, P
OUT
= 60 dBmV @Max Gain –54 -50 dBc
T
A
=
-40
°C to +85°C
f = 42 MHz, P
OUT
= 60 dBmV @Max Gain –52 -50 dBc
f = 65 MHz, P
OUT
= 60 dBmV @Max Gain –52 -50 dBc
ACPR
3
TBD dBc
Isolation (Transmit Disable) Max Gain, f = 65 MHz –60 dBc
POWER CONTROL
TX-Enable Settling Time Max Gain, V
IN
= 0 3.5 µs
TX-Disable Settling Time Max Gain, V
IN
= 0 3.5 µs
Output Switching Transients Equivalent Output = 31 dBmV 7 mV p-p
Equivalent Output = 60 dBmV 50 mV p-p
Output Settling
Due to Gain Change Min to Max Gain TBD ns
Due to Input Step Change Max Gain, V
IN
= 30 dBmV TBD ns
POWER SUPPLY
Operating Range 4.75 5 5.25 V
Quiescent Current Maximum Gain 125 mA
Minimum Gain 24 mA
Transmit Disable, TXEN = 0 2.6 mA
Sleep Mode (Power-Down) 10 µA
OPERATING TEMPERATURE –40 +85 °C
RANGE
NOTES
1
TOKO 458PT-1087 used for above specifications.
2
Measured through a 2:1 transformer.
3
V
in
= 30dBmV, QPSK modulation, 160ksps symbol rate
PRELIMINARY TECHNICAL DATA
REV. PrA April 4, 2002
AD8328
–3–
LOGIC INPUTS (TTL/CMOS Compatible Logic)
Parameter Min Typ Max Unit
Logic “1” Voltage 2.1 5.0 V
Logic “0” Voltage 0 0.8 V
Logic “1” Current (V
INH
= 5 V) CLK, SDATA, DATEN 0 20 nA
Logic “0” Current (V
INL
= 0 V) CLK, SDATA, DATEN –600 –100 nA
Logic “1” Current (V
INH
= 5 V) TXEN 50 190 µA
Logic “0” Current (V
INL
= 0 V) TXEN –250 –30 µA
Logic “1” Current (V
INH
= 5 V) SLEEP 50 190 µA
Logic “0” Current (V
INL
= 0 V) SLEEP –250 –30 µA
TIMING REQUIREMENTS
Parameter Min Typ Max Unit
Clock Pulsewidth (T
WH
) 16.0 ns
Clock Period (T
C
) 32.0 ns
Setup Time SDATA vs. Clock (T
DS
) 5.0 ns
Setup Time DATEN vs. Clock (T
ES
) 15.0 ns
Hold Time SDATA vs. Clock (T
DH
) 5.0 ns
Hold Time DATEN vs. Clock (T
EH
) 3.0 ns
Input Rise and Fall Times, SDATA, DATEN, Clock (T
R
, T
F
)10ns
(Full Temperature Range, VCC = 5 V, TR = TF = 4 ns, fCLK = 8 MHz unless otherwise noted.)
(DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 5 V: Full Temperature Range)
PRELIMINARY TECHNICAL DATA
April 4, 2002 REV. PrA
AD8328
–4–
ORDERING GUIDE
Model Temperature Range Package Description
AD8328ACP –40°C to +85°C 20-Lead LFCSP
AD8328ACP-REEL –40°C to +85°C 20-Lead LFCSP
AD8328ARQ –40°C to +85°C 20-Lead QSOP
AD8328ARQ-REEL –40°C to +85°C 20-Lead QSOP
AD8328-EVAL Evaluation Board
*Thermal Resistance measured on SEMI standard 4-layer board.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage +V
S
Pins TBD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Input Voltages
Pins TBD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V
Pins TBD . . . . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V
Internal Power Dissipation
LFCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD W
QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD W
Operating Temperature Range . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering 60 seconds . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and
can discharge without detection. Although the AD8325 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected
to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS (QSOP-20 Package)
Pin No. Mnemonic Description
8 DATEN Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register.
A Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the
gain) and simultaneously inhibits serial data transfer into the register. A 1-to-0 transi-
tion inhibits the data latch (holds the previous gain state) and simultaneously enables
the register for serial data load.
9 SDATA Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded
into the internal register with the MSB (Most Significant Bit) first.
10 CLK Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit
master-slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 trans-
fers the data bit to the slave. This requires the input serial data word to be valid at or
before this clock transition.
1, 3, 4, 7, 11, GND Common External Ground Reference.
20
2, 19 V
CC
Common Positive External Supply Voltage. A 0.1 µF capacitor must decouple each pin.
18 TXEN Logic “0” disables forward transmission. Logic “1” enables forward transmission.
12 SLEEP Low Power Sleep Mode. In the Sleep mode, the AD8328’s supply current is reduced to
1 µA. A Logic “0” powers down the part (High Z
OUT
State) and a Logic “1” powers up
the part.
15 VOUT– Negative Output Signal.
16 VOUT+ Positive Output Signal.
14 BYP Internal Bypass. This pin must be externally ac-coupled (0.1 µF cap).
17 RAMP This is the external RAMP capacitor (OPTIONAL)
5V
IN+
Noninverting Input. DC-biased to approximately V
CC
/2. Should be ac-coupled with a 0.1
µF capacitor.
6V
IN–
Inverting Input. DC-biased to approximately V
CC
/2.
PRELIMINARY TECHNICAL DATA
