ACT-SF128K32 High Speed 128Kx32 SRAM / 128Kx32 Flash Multichip Module CIRCUIT TECHNOLOGY www.aeroflex.com FEATURES mw 4-128K x 8 SRAMs & 4 - 128K x 8 Flash Die FLASH MEMORY FEATURES in One MCM = Sector Architecture (Each Die) u Access Times of 25ns (SRAM) and 60ns Any Combination of sectors can be erased with e Sons (vlash) (SRAM) and 70ns or one command sequence. . m +5V Programing, +5V Supply m= Organized as 128K x 32 of SRAM and 128K x . 32 a Flash Memory with Common Data Bus m= Embedded Erase and Program Algorithms = Low Power CMOS = Hardware and Software Write Protection m= Page Program Operation and Internal Program Control Time. = 10,000 Erase/Program Cycles = Input and Output TTL Compatible Design = MIL-PRF-38534 Compliant MCMs Available = Decoupling Capacitors and Multiple Grounds for Low Noise = Commercial, Industrial and Military Temperature Ranges = Industry Standard Pinouts = TTL Compatible Inputs and Outputs m= Packaging Hermetic Ceramic e 66Lead, PGA-Type, 1.385"SQ x 0.245"max, Aeroflex code# P3,P7 without/with shoulders Block Diagram PGA Type Package (P3 & P7) FWE1 SWE1 FWE3 SWE3 FWE4 SWE4 PIN DESCRIPTION 00-31 Data I/O A0-16 Address Inputs FWE1-4 | Flash Write Enables SWE1-4 | SRAM Write Enables FCE | Flash Chip Enable OE Ao-A16 SCE FCs 128K x 8 FLASH 128K x8 FLASH 128K X 8 FLASH 128K x 8 FLASH 128K x 8 SRAM 128K x 8 SRAM 128K xX 8 SRAM 128K xX 8 SRAM SCE SRAM Chip Enable OE Output Enable NC Not Connected Vec Power Supply GND Ground 1/00-7 1/08-15 1/016-23 1/024-31 K\eroflex Circuit Technology - Advanced Multichip Modules SCD3850 REV A 5/20/98Absolute Maximum Ratings Symbol Rating Range Units Te Operating Temperature -55 to +125 C Tstq | Storage Temperature -65 to +150 C Ve Maximum Signal Voltage to Ground -0.5 to +7 Vv TL Maximum Lead Temperature (10 seconds) 300 C Parameter Flash Data Retention 10 Years Flash Endurance (Write/Erase Cycles) 10,000 Normal Operating Conditions Symbol Parameter Minimum Maximum Units Voc Power Supply Voltage +4.5 +5.5 Vv Vin Input High Voltage +2.2 Voc + 0.3 V Vit Input Low Voltage -0.5 +0.8 Vv Capacitance (Vin = OV, f = 1MHz, To = 25C) Symbol | Parameter Maximum Units Cao | AoAts Capacitance 80 pF Cot | OE Capacitance 80 pF Cwet-4 | F/S Write Enable Capacitance 30 pF Cce |F/S Chip Enable Capacitance 50 pF Cvo | \/Oo 1/031 Capacitance 30 pF This parameter is guaranteed by design but not tested DC Characteristics (Vcc = 5.0V, Vss = OV, Tc = -55C to +125C) Parameter Sym Conditions Min Max} Units Input Leakage Current lt | Veg = Max, Vin = 0 to Veo 10 | UA Output Leakage Current lLo Von oe Va OE = Vin, 10 | pA SRAM Operating Supply Current x 32 loox32 ee avin f = 5MHz, Vcc = 550| mA Standby Current Isp Ven _ vee = Vin, OE = Vin, f= SMHz, 80 | mA SRAM Output Low Voltage Vor [lop =8 MA, Veco = Min, FCE = Viy 0.4) V SRAM Output High Voltage Von |loy =-4.0 mA, , Voc = Min, FCE = Vy 2.4 Vv Flash Vcc Active Current for Read (1)|/ Icc1 | FCE = Vi, OE = Viy, SCE = Vin 220| mA erase) Current for Program loos |FCE = Vy, OE = Vy, SCE = Vy, 280] mA Flash Output Low Voltage VoL lo, = 12 MA, Voc = Min, SCE = Viy 0.45) V Flash Output High Voltage Vout |loy = -2.5 MA, , Voc = Min, SCE = Viy 0.85 x Vcc Vv Flash Low Vcc Lock Out Voltage ViKo 3.2 4.2 Vv Notes: 1) The Icc current listed includes both the DC operating current and the frequency dependent component (at SMHz). The frequency component typically is less than 2mA/MHz, with OE at VIH 2) Icc active while Embedded Algorithim (program or erase) is in progress 3) DC test conditions: VIL = 0.3V, VIH = Vcc - 0.3V Aeroflex Circuit Technology 2 SCD3850 REV A 5/20/98 Plainview NY (516) 694-6700SRAM AC Characteristics (Vcc = 5.0V, Vss= OV, Tc = -55C to +125C) Read Cycle 025 035 Parameter Symbol Min Max Min Max Units Read Cycle Time tre 25 35 ns Address Access Time tan 25 35 ns Chip Select Access Time tace 25 35 ns Output Hold from Address Change tou ) 0 ns Output Enable to Output Valid tor 15 20 ns Chip Select to Output in Low Z * teLz ns Output Enable to Output in Low Z * toLz ) 0 ns Chip Deselect to Output in High Z * touz 12 20 ns Output Disable to Output in High Z * touz 12 20 ns * Parameters guaranteed by design but not tested Write Cycle 025 035 : Parameter Symbol Min Max Min Max Units Write Cycle Time twe 25 35 ns Chip Select to End of Write tow 20 25 ns Address Valid to End of Write taw 20 25 ns Data Valid to End of Write tow 15 20 ns Write Pulse Width twe 20 25 ns Address Setup Time tas ns Output Active from End of Write * tow ns Write to Output in High Z * twuz 10 20 ns Data Hold from Write Time tou ns Address Hold Time taH ns * Parameters guaranteed by design but not tested SRAM Truth Table Mode SCE OE SWE Data I/O Power Standby H x x High Z Standby Read L L H Data Out Active Output Disable L H H High Z Active Write L x L Data In Active Aeroflex Circuit Technology 3 SCD3850 REV A 5/20/98 Plainview NY (516) 694-6700Timing Diagrams SRAM Read Cycle Timing Diagrams Read Cycle 1 (SCE = OE = ViL, SWE = Vin) /< taa Ao6 Duo Previous Data Valid Data Valid Read Cycle 2 (SWE = Vi) I trac | Ao-16 Ke _ ta _ SCE TACE tcLz __ SEE NOTE OE LL toe SEE NOTE toLz> SEE NOTE Duo _ High Z Data Valid UNDEFINED LT DONT CARE Write Cycle Timing Diagrams Write Cycle (SWE Controlled, OE = VIH) twc x XK Ars n mi tWwHz- SEE NOTE Duo : Data Valid Write Cycle (SCE Controlled, OE = VIH ) twc Aor6 twe +| << tw <t{DH Dio K Data Valid Note: Guaranteed by design, but not tested. n Mm AC Test Circuit Current Source | Io To Device Under Test CL = 50 pF T Vz ~ 1.5 V (Bipolar Supply) t. Current Source Notes: AC Test Conditions Parameter Typical Units Input Pulse Level 0-3.0 Vv Input Rise and Fall 5 ns Input and Output Timing Reference Level 1.5 Vv 1) Vz is programmable from -2V to +7V. 2) loL and IOH programmable from 0 to 16 mA. 3) Tester Impedance ZO = 75Q. 4) VZ is typically the midpoint of VOH and VoL. 5) IOL and IOH are adjusted to simulate a typical resistance load circuit. 6) ATE Tester includes jig capacitance. Aeroflex Circuit Technology 4 SCD3850 REV A 5/20/98 Plainview NY (516) 694-6700Flash AC Characteristics Read Only Operations (Vcc = 5.0V, Vss = OV, Tc = -55C to +125C) p t Symbol -60 -70 -90 Unit aramerer JEDEC Standd| Min Max| Min Max| Min Max| -"" > Read Cycle Time TAVAV tre 60 70 90 ns Address Access Time tavav tacc 60 70 90 ns Chip Enable Access Time tELav tce 60 70 90 ns Output Enable to Output Valid taLav toe 30 35 40 ns Chip Enable to Output High Z (1) tEHaz {DF 20 20 25 ns Output Enable High to Output High 2(1) taHaz {DF 20 20 25 ns Output Hold from Address, CE or OE Change, Whichever is First taxax tou 0 0 0 ns Note 1. Guaranteed by design, but not tested Flash AC Characteristics Write/Erase/Program Operations, FWE Controlled (Vcc = 5.0V, Vss = OV, Tc = -55C to +125C) p t Symbol -60 -70 -90 Unit aramerer JEDEC Standd | Min Max| Min Max| Min Max| Write Cycle Time tavac twe 60 70 90 ns Chip Enable Setup Time tELWL tcE 0 0 0 ns Write Enable Pulse Width tWLWH twp 30 35 45 ns Address Setup Time TAVWL tas 0 0 0 ns Data Setup Time tDVWH tps 30 30 45 ns Data Hold Time tWHDX {DH 0 0 0 ns Address Hold Time tWLAX taH 45 45 45 ns Chip Enable Hold Time tWHEH tcH 0 0 0 ns Write Enable Pulse Width High tWHWL tWPH 20 20 20 ns Duration of Byte Programming Operation tWHWH1 14 | TYP] 14] TYP] 14 | TYP ys Sector Erase Time tWHWH2 60 60 60 Sec Chip Erase Time tWHWH3 120 120 120 Sec Read Recovery Time before Write tGHWL 0 0 0 ys Vcc Setup Time tvcE 50 50 50 ys Output Enable Setup Time toes 12.5 12.5 12.5 Sec Output Enable Hold Time! toEH 10 10 10 ns Note: 1. For Toggle and Data Polling. Flash AC Characteristics Write/Erase/Program Operations, FCE Controlled (Vcc = 5.0V, Vss = OV, Tc = -55C to +125C) p t Symbol -60 -70 -90 Unit aramerer JEDEC Standd | Min Max| Min Max| Min Max| Write Cycle Time tavac twe 60 70 90 ns Write Enable Setup Time tWLeL tws 0 0 0 ns Chip Enable Pulse Width tELEH tep 35 35 50 ns Address Setup Time TAVEL tas 0 0 0 ns Data Setup Time {DVEH tps 30 30 50 ns Data Hold Time tEHDX {DH 0 0 0 ns Address Hold Time tELAX taH 45 45 50 ns Write Enable Hold from Write Enable High tEHWH twH 0 0 0 ns Chip Enable Pulse Width High TEHEL tcPH 20 20 20 ns Duration of Byte Programming tWHWH1 14 | TYP] 14] TYP] 14 | TYP ys Sector Erase Time tWHWH2 60 60 60 Sec Chip Erase Time tWHWH3 120 120 120 Sec Read Recovery Time T@HEL 0 0 0 ns Chip Programming Time 12.5 12.5 12.5 Sec 5 Aeroflex Circuit Technology SCD3850 REV A 5/20/98 Plainview NY (516) 694-6700AC Waveforms for Flash Memory Read Operations tre Addresses X Addresses Stable X tace. > FCE \ | \ +> tor OE \ V \ FWE _/ \L tce > toH>| High Z Outputs g Output Valid Write/Erase/Program Operation for Flash Memory, FWE Controlled Data Polling Addresses twHw1 > b| f* tou Data prot 5.0V Notes: 1. PAis the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the Output of the complement of the data written to the deviced. 4. Dout is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. Aeroflex Circuit Technology 6 SCD3850 REV A 5/20/98 Plainview NY (516) 694-6700AC Waveforms Chip/Sector Erase Operations for Flash Memory r| e tan Data Polling Addresses X ssssH 2AAAH 5555H XK 5555H X 2AAAH x SA x tas} a en a ee j taHwi+> OE j \ aa # twp me [NF AS \S \S VS NS Te -\ -\ \ \ Data / LAF AAH \__/ 55H \__/ 80H \__/AAH \__/55H \__/10H/30H ~| letpos Vec L tvcE>} Notes: 1. SAis the sector address for sector erase. AC Waveforms for Data Pollin During Embedded Algorithm Operations for Flash Memory =, be-tDF-| toEH > be twHwH1 or 2. _ DQO0-DQ6 DQO-DQ6z=Invalid DQ7= High Z Valid Data * DQ7=Valid Data (The device has completed the Embedded operation). Aeroflex Circuit Technology 7 SCD3850 REV A 5/20/98 Plainview NY (516) 694-6700Write/Erase/Program Operation for Flash Memory, FCE Controlled Data Polling Addresses X 5555H X PA be two rr] [tase TAH-m} + twHwH1 + =) d Data / 5.0V Notes: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the Output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. Aeroflex Circuit Technology 8 SCD3850 REV A 5/20/98 Plainview NY (516) 694-6700Function 1/08 /O9 1/O10 A14 A16 Ait Ao NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Ag 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pin Numbers & Functions 66 Pins PGA-T Function Pin # Function A15 35 1/025 Vcc 36 1/026 FCE 37 A7 SCE 38 Ai2 1/03 39 SWE1 1/015 40 A13 1/014 44 A8 1/013 42 1/016 1/012 43 1/017 OE 44 O18 NC 45 Vec FWE1 46 SWEa4 1/07 47 FWEa4 1/06 48 1/027 1/05 49 A4 1/04 50 AS 1/024 51 A6 "P3" 1.08" SQ PGA Type Package Standard (without shoulders) "P7" 1.08" SQ PGA Type Package (with shoulders on Pins 1, 11, 56 & 66) Side View (P7) _ 185 MAX 025 .035 .050 DIA TYP All dimensions in inches Function FWE3 SWE3 GND O19 1/031 1/030 1/029 1/028 At A2 A3 Bottom View (P7 & P3) Pint Side View 1.085 Sa (P3) "MAX 1.000 TYP .600 TYP . Of Pin 567 @@ 0@ @ @ @ @@O 100 TYP 229 + eo 1.000 | @eo+eeoe, Wp t O O@ FT O O@ 020 O @O@ .016 @@ fF Pin cto? ? oe 165 _| | soo ve MIN _ __.160 MAX Pin 11 Aeroflex Circuit Technology o SCD3850 REV A 5/20/98 Plainview NY (516) 694-6700(\EROFLEX CIRCUIT TECHNOLOGY, Ordering Information Model Number DESC Part Number Speed Package ACT-SF128K32N-26P1 X TBD 25(S) / 60(F) ns 1.08"sq PGA-Type ACT-SF128K32N-37P1X TBD 35(S) / 70(F) ns 1.08"sq PGA-Type ACT-SF128K32N-39P1 X TBD 35(S) / 90(F) ns 1.08"sq PGA-Type Note: (S) = Speed for SRAM, (F) = Speed for FLASH Part Number Breakdown ACT- SF 128K 32 N- 26 P1 M Aeroflex Circuit ___ Technology Memory Type SF = SRAM Flash Combo Module Screening C = Commercial Temp, 0C to +70C | = Industrial Temp, -40C to +85C T = Military Temp, -55C to +125C M = Military Temp, -55C to +125C Screened * Q = MIL-PRF-38534 Compliant/SMD Memory Depth, Locations Memory Width, Bits Pinout Options Package Types & Sizes N= none Thru-Hole Packages Memory Speed (Code) P3 = 1.08"SQ PGA 66 Pins WO/Shoulder 26 = 25ns SRAM /60ns FLASH P7 = 1.08"SQ PGA 66 Pins W/Shoulder 37 = 35ns SRAM / 70ns FLASH 39 = 35ns SRAM / 90ns FLASH * Screened to the individual test methods of MIL-STD-883 Specifications subject to change without notice. Aeroflex Circuit Technology Telephone: (516) 694-6700 35 South Service Road FAX: (516) 694-6715 Plainview New York 11830 Toll Free Inquiries: 1-(800) 843-1553 Aeroflex Circuit Technology 10 SCD3850 REV A 5/20/98 Plainview NY (516) 694-6700