Page 24
XDR DRAM
Version 1.0 Jan. 2005
K4Y5416(/08/04)4UF
Interleaved Transactions
Figure11 shows two examples of interleaved transactions. Interleaved transactions are overlapped with one another; a transac-
tion is started before an earlier one is completed.
The timing diagram at the top of the figure shows interleaved write transactions. Each transaction assumes a page-empty
access; that is, a bank is in a closed state prior to an access and is precharged after the access. With this assumption, each
transaction requires the same number of request packets at the same relative positions. If bank were allowed to be in an open
state, then each transaction would require a different number of request packets depending upon whether the transaction was
page-empty, page-hit or page-miss. This situation is more complicated for the memory controller and will not be analyzed in this
document.
In the interleaved page-empty write example, there are four sets of request pins RQ11...0 shown along the left side of the timing
diagram. The first three show the timing slots used by each of the three requests packet types (ACT, COL and PRE), and the
fourth set (ALL) shows the previous three merged together. This allows the pattern used for allocating request slots for the
different pa ckets to be seen more clearly.
The slots at {T0, T4, T8, T12 ...} are used for ROWA packets with ACT commands. This spacing is determined by the tRR param-
eter. There should not be interference between the interleaved transactions due to resource conflicts because each bank
address - Ba, Bb, Bc, Bd and Be - is assumed to be different from another. If two of the bank addresses are the same, the later
transaction would need to wait until the earlier transaction had completed its precharge operation. Five different banks are
needed because the effective tRC (tRC + ∆tRC) is 20*tCYCLE.
The slots at {T1, T3, T5, T7, T9, T11, ...} are used for COL packets with WR commands. This frequency of the COL packet
spacing is determined by the tCC parameter and by the fact that there are two column accesses per row access. The phasing of
the COL packet spacing is determined by the tRCD-W parameter. If the value of tRCD-W required the COL packets to occupy the
same request slots as the ROWA packets (this case is not shown), the DELC field in the COL packet could be used to place the
COL packet one tCYCLEs earlier.
The DQ bus slots at {T7, T9, T11, T13, ...} carry the write data packets {D(a1), D(a2), D( b1), D(b2) , ...}. Two write data packets are
written to a bank in each transaction. The DQ bus is completely filled with write data; no idle cycles need to be introduced
because there are no resource conflicts in this example.
The slots at {T14, T18, T22, ...} are used for ROWP packets with PRE commands. This frequency of ROWP packet spacing is
determined by the tPP parameter. The phasing of the ROWP packet spacing is determined by the tWRP paramter. If the value of
tWRP required the ROWP packets to occupy the same r equest slots as the ROWA or COL packets already assigned (this case is
not shown), the delay field in the ROWP packet could be used to place the ROWP packet one or more tCYCLE earlier.
There is an example of an interleaved page-empty read at the bottom of the figure. As before, there are four sets of request pins
RQ11...0 shown along the left side of the timing diagram, allowing the pattern used for allocating request slots for the different
packets to be seen more clearly.
The slots at {T0, T4, T8, T12, ...} are used for ROWA packets with ACT command. This spacing is determined by the tRR param-
eter. There should not be interference between the interleaved transactions due to resource conflicts because each bank
address - Ba, Bb, Bc and Bd - is assumed to be different from another. Four different banks are needed because the effective
tRC is 16 * tCYCLE.
The slots at {T5, T7, T9, T11, ...} are used for COL packets with RD commands. This frequency of the COL packet spacing is
determined by the tCC paramter and by the fact that there are two column accesses per row access. The phasing of the COL
packet spacing is determined by the tRCD-R parameter. If the value of tRCD-R required the COL packets to occupy the same
request slots as the ROW A packet s (this case is not shown), the DELC field in the COL p acket could be used to place the packet
one tCYCLE earlier.
The DQ bus slots at {T11, T13, T15, T17, ...} carry the read data packets {Q(a1), Q(a2), Q(b1), Q(b2), ...}, Two read data packets
are read from a bank in each transaction. The DQ bus is completely filled with read data - That is, no idle cycles need to be intro-
duced because there are no resource conflicts in this example.
The slots at {T10, T14, T18, T22, ...} are used for ROWP packets with PRE commands. This frequency of the ROWP packet
spacing is determined by the tPP parameter. The phasing of the ROWP packet spacing is determined by the tRDP parameter. If
the value of tRDP required the ROWP packet s to occupy the same request slots as the ROWA or COL packets already assigned
(this case is not shown), the delay field in the ROWP packet could be used to place the ROWP packet one or more tCYCLEs
earlier.