Document DS 13162 Rev. D, ECN 11507
Revision Date: 7/14/2012
SP2T PIN Diode Switches
The evaluation boards for the MSW2030 family of surface
mount silicon PIN diode SP2T T-R switches allow the full
exercise of each switch for small signal performance
analysis, as well as for large signal operation with
maximum input signal power of 45 dBm (CW or peak
power). Each evaluation board includes the appropriate
MSW203x-203 switch, DC blocking capacitors at each
RF port and bias decoupling networks at each RF port
which allow DC or low frequency control signals to be
applied to the switch.
Four complementary control signals are required for
proper operation. Bias voltages are applied to the B1 and
B2 bias ports, as well as to the J0, J1 and J2 RF ports to
control the state of the switch. A fixed bias voltage must
be applied to the J0 port (connect 5 V to pin 3 of multi-
pin connector P1) whenever the switch is in operation.
Caution: the evaluation board, as supplied from the
factory, is not capable of handling RF input signals larger
than 45 dBm. If performance of the switch under larger
input signals is to be evaluated several of the passive
components on the board must be changed in order to
safely handle the dissipated power as well as the high
bias voltage necessary for proper performance. The eval-
uation board must be connected to an adequate heat
sink for large signal operation. Contact the factory for
recommended components.
For the purposes of description, State 1 is defined to be
the condition in which the evaluation board is biased to
produce the low insertion condition between ports J0
and J1 while producing high isolation between ports J0
and J2. State 2 is the converse of State 1.
State 1
In State 1, the series PIN diode between the J0 and J1
ports is forward biased by applying 0 V to the J1 bias
input port (pin 1 of multi-pin connector P1). The magni-
tude of the resultant bias current through the diode is
primarily determined by the voltage applied to the J0 bias
port (pin 3 of P1), the magnitude of the forward voltage
across the PIN diode and the resistance of R1. This cur-
rent is nominally 100 mA. At the same time, the PIN
diode connected between J2 and B2 ports is also for-
ward biased by applying a high bias voltage, nominally 28
V, to the J2 bias port (pin 7 of P1) and 0 V to the B2 bias
port (pin 5 of P1). Under this condition, the PIN diode
connected between the J0 and J2 ports is reverse biased
and the PIN diode connected between the J2 and B2
ports is forward biased. The magnitude of the bias cur-
rent through this diode is primarily determined by the
voltage applied to the J2 bias port, the magnitude of the
forward voltage across the PIN diode and the resistance
of R4. This current is nominally 25 mA.
The series PIN diode which is connected between the J0
and J2 ports must be reverse biased during State 1. The
reverse bias voltage must be sufficiently large to maintain
the diode in its non-conducting, high impedance state
when large RF signal voltage may be present in the J0-to-
J1 path. The reverse voltage across this diode is the
arithmetic difference of the bias voltage applied to the J2
bias port and the DC forward voltage of the forward-
biased J0-to-J1 series PIN diode.
The minimum voltage required to maintain the series
diode between J0 and J2 out of conduction is a function
of the magnitude of the RF voltage present, the standing
wave present at the series diode’s anode, the frequency
of the RF signal and the characteristics of the series
diode, among other factors. Minimum control voltages
for several signal frequencies are shown in the table
“Minimum Reverse Bias Voltage”, assuming the input
power to the J0 or J1 port to be 100 W CW and the VSWR
on the J0-J1 path to be 1.5:1.
State 2
In the State 2, the series PIN diode between the J0 and
J2 ports is forward biased by applying 0 V to the J2 bias
input port (pin 7 of multi-pin connector P1). The magni-
tude of the resultant bias current through the diode is
primarily determined by the voltage applied to the J0 bias
port (pin 3 of P1), the magnitude of the forward voltage
across the PIN diode and the resistance of R1. This
current is nominally 100 mA. At the same time, the PIN
diode connected between J2 and B2 ports is reverse
biased by applying a high bias voltage, nominally 28 V, to
the B2 bias port (pin 5 of P1). A high voltage, nominally
28 V, is also applied to the J1 bias port (pin 1 of P1).
Under this condition, the PIN diode connected between
the J0 and J1 ports is reverse biased thus isolating the J1
RF port from the RF signal path between J0 and J2. The
reverse voltage across this diode is the arithmetic differ-
ence of the bias voltage applied to the J1 bias port and
the DC forward voltage of the forward-biased J0-to-J2
series PIN diode. The minimum voltage required to main-
tain the series diode on the J0-to-J1 side of the switch
out of conduction is a function of the magnitude of the RF
voltage present, the standing wave present at the diode’s
anode, the frequency of the RF signal and the character-
istics of the series diode, among other factors.
Evaluation Board Description