1
2
34
5
6
2.9mm x 1.6mm TSOT-23 (DDC)
(TOP VIEW)
R2
VOUT
VOUT
R1/C1
ON/OFF
VIN
TPS27081ADDC
VIN VOUT
R1/C1
ON/OFF
Q1
Q2
R1
C1
ESD ESD
ESD
ESD
R2
CL
(2, 3)
R2
(1)
(5)
(6)
(4)
GPIO/
Logic
Up to
8V
Supply LOAD
TPS27081A
www.ti.com
SLVSBE9D –APRIL 2012–REVISED APRIL 2013
1.2V - 8V, 3A PFET High Side Load Switch with Level Shift & Adjustable Slew Rate
Control
Check for Samples: TPS27081A
1FEATURES DESCRIPTION
• Low ON Resistance, High Current PFET The TPS27081A IC is a high side load switch that
– RON = 32mΩat VGS = –4.5V integrates a Power PFET and a Control NFET in a
tiny package.
– RON = 44mΩat VGS = –3.0V
– RON = 82mΩat VGS = –1.8V The TPS27081A features industry-standard ESD
protection on all pins providing better ESD
– RON = 93mΩat VGS = –1.5V compatibility with other on-board components.
– RON = 155mΩat VGS = –1.2V The TPS27081A level shifts ON/OFF logic signal to
• Adjustable Turn-ON and Turn-OFF Slew Rate VIN levels and supports as low as 1.0V CPU or MCU
Control Through External R1, R2, and C1 logic to control higher voltage power supplies without
• Supports a Wide Range of 1.2V up to 8V requiring an external level-shifter.
Supply Inputs Switching a large value output capacitor CL through a
• Integrated NMOS for PFET Control fast ON/OFF logic signal may result in an excessive
• NMOS ON/OFF Supports a Wide Range of 1.0V inrush current. To control the load inrush current,
up to 8V Control Logic Interface connect a resistor R2 as shown in Figure 2. To
further limit the inrush current add an external
• Full ESD Protection (All Pins) capacitor C1. To configure the TPS27081A to
– HBM 2kV, CDM 500V achieve a specific slew rate refer to the Application
• Ultra Low Leakage Current in Stand-by (Typ Information section.
100nA) A single pull-up resistor R1 is required in stand-by
• Available in Tiny 6-pin Package power switch applications that do not require inrush
– 2.9mm x 2.8mm x 0.75mm Thin SOT-23 current control. In such applications connect the
TPS27081A pin R2 to the system ground.
(DDC)
APPLICATIONS
• High Side Load Switch
• Inrush-current control
• Power Sequencing and Control
• Stand-by Power Isolation Figure 2. Simplified Block & Application Diagram
• Portable Power Switch
Component Table (Typical Application)
COMPONENT DESCRIPTION
R1 Level Shift/Pull-up Resistor
R2 Optional(1)
C1 Optional(1)
Figure 1. TPS27081A Packages (1) Required for load inrush current (slew rate) control
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2012–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS27081A
SLVSBE9D –APRIL 2012–REVISED APRIL 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
TAPART NUMBER PACKAGE TOP-SIDE MARKING (2)
–40°C to 85°C TPS27081ADDCR 6-Pin Thin SOT Reel of 3000 AU_
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) DDC: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Specified at TJ= –40°C to 105°C unless otherwise noted. VALUE UNIT
MIN MAX
VINmax,VIN, VOUT pin Maximum Voltage with reference to pin R2 –0.1 8 V
VOUTmax
VON/OFF ON/OFF Pin max Voltage with respect to Pin R2 –0.3 8 V
Max Continuous Drain Current of Q1 at TJ= 105°C 3
IQ1-ON A
Max Pulsed Drain Current of Q1 (3) at TJ= 105°C 9.5
Max power dissipation at TA
PD6 Pin - TSOT, θJA = 105°C/W 1190 mW
= 25°C, TJ= 150°C
ESD Rating – HBM 2000
All pins V
ESD Rating – CDM 500
TAOperating free-air ambient temperature range –40 85(4) °C
TJ-max(5) Operating virtual junction temperature 150 °C
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
(2) Refer to TI’s design support web page at www.ti.com/thermal for improving device thermal performance
(3) Pulse Width <300us, Duty Cycle <2%
(4) TJ-max limits and other related conditions apply. Refer to SOA charts, Figure 17 through Figure 21
(5) Operating at the absolute TJ-max of 150°C can affect reliability – for higher reliability it is recommended to ensure TJ<105°C
DISSIPATION RATINGS(1)(2)(3)
BOARD PACKAGE θJC θJA(4) TA< 25°C TA= 70°C TA= 85°C DERATING FACTOR
ABOVE TA= 25ºC
High- 6-Pin Thin SOT 43°C/W 105°C/W 1190 mW 760 mW 619 mW 9.55 mW/°C
K(JEDEC 51- (DDC)
7)
(1) Refer to TI’s design support web page at www.ti.com/thermal for improving device thermal performance.
(2) Maximum dissipation values for retaining a maximum allowable device junction temperature of 150°C
(3) Package thermal data based on a 76x114x1.6mm, 4-layer board with 2-oz Copper on outer layers
(4) Operating at the absolute TJ-max of 150°C can affect reliability; TJ ≤105°C is recommended
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SLVSBE9D –APRIL 2012–REVISED APRIL 2013
ELECTRICAL CHARACTERISTICS
Specified over the recommended junction temperature range TJ = -40°C to 105°C unless otherwise noted. Typical values
specified at TA = TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFF CHARACTERISTICS
Q1 drain-to-source
BVIN VON/OFF = 0 V, VGS(Q1) = 0V, ID(Q1) = 250 µA -8 V
breakdown voltage TJ= 25°C 0.15 0.75
ILOAD(1) VIN Pin total leakage current VIN= 8V, VON/OFF = 0V, R1 = 10k ΩµA
TJ= 85°C(2) 5 20
TJ= 25°C 0.05
ILOAD(1) VIN Pin total leakage current VIN= 5V, VON/OFF = 0V, R1 = 10k ΩµA
TJ= 85°C(2) 2
TJ= 25°C 0.030 0.050
Q2 drain-to-source leakage
IFQ2 VIN= 8V, VON/OFF = 0V uA
current TJ= 85°C(2) 0.350 0.600
TJ= 25°C 0.025
Q2 drain-to-source leakage
IFQ2 VIN= 5V, VON/OFF = 0V µA
current TJ= 85°C(2) 0.250
ON CHARACTERISTICS(3)
VIN = 5.0V, ID(Q1) < 2µA, R1 = 10kΩ, R2 TJ= 25°C 0.3
= RL = 0Ω
ON/OFF pin low-level input
VIL V
voltage VIN = 5.0V, ID(Q1) < 20µA, R1 = 10kΩ,TJ= 85°C(2) 0.2
R2 = RL = 0Ω
ON/OFF pin high-level input
VIH VIN=5.0V, R1=10kΩ1.0 V
voltage VGS = -4.5 V, ID(Q1) = 3.0 A 32 55
VGS = -3.0 V, ID(Q1) = 2.5 A 44 77
VGS = -2.5 V, ID(Q1) = 2.5 A 50 85
Q1 Channel ON
RQ1(ON) mΩ
resistance(4) VGS = -1.8 V, ID(Q1) = 2.0 A 82 147
VGS = -1.5 V, ID(Q1) = 1.0 A 93 166
VGS = -1.2 V, ID(Q1) = 0.5 A 155 260
VGS = 4.5 V, ID(Q2) = 0.4 A 1.8 3
VGS = 3.0 V, ID(Q2) = 0.3 A 2.3 6.2
VGS = 2.5 V, ID(Q2) = 0.2 A 2.6 6.1
RQ2(ON) Q2 Channel ON resistance Ω
VGS = 1.8 V, ID(Q2) = 0.1 A 3.8 10
VGS = 1.5 V, ID(Q2) = 0.05 A 4.4 8.5
VGS = 1.2 V, ID(Q2) = 0.03 A 6.25 13.5
Q1 DRAIN-SOURCE DIODE PARAMETERS(3)(5)
Source-drain diode peak
IFSD VFSD = 0.8 V, VON/OFF = 0 V 1.0 A
forward current
Source-drain diode forward
VFSD VON/OFF = 0 V, IFSD = –0.6A, 1.0 V
voltage
(1) Pull-up Resistor R1 dependent
(2) Guaranteed by design only
(3) Pulse width <300 µs, Duty Cycle <2.0%
(4) Refer to SOA charts for current rating
(5) Not rated for continuous current operation
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: TPS27081A
1
2
34
5
6
2.9mm x 1.6mm TSOT-23 (DDC)
(TOP VIEW)
R2
VOUT
VOUT
R1/C1
ON/OFF
VIN
TPS27081ADDC
TPS27081A
SLVSBE9D –APRIL 2012–REVISED APRIL 2013
www.ti.com
DEVICE INFORMATION
TPS27081A PIN DESCRIPTION
PIN DESCRIPTION
NAME NUMBER
R2 1 Source Terminal of NMOS (Q2) - Connect to system GND directly or through a slew rate control resistor
VOUT 2, 3 Drain Terminal of Power PFET (Q1) - Connect a slew control capacitor between pins VOUT and R1/C1
VIN 4 Source Terminal of Power PFET (Q1) - connect a pull-up resistor between the pins VIN/R1 and R1/C1
ON/OFF 5 Active high enable pin – when driven with a high impedance driver connect an external pull down resistor to GND
R1/C1 6 Gate Terminal of Power PFET (Q1)
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rise 2 3
3.9 R2 C1
t sec
VIN
´ ´
=
final initial
inrush load load
VOUT VOUT
I C C
Vout Slew Rate
dv
dt
-
= ´ = ´
Q1
R1
VGS VIN V
R1 R2
= - ´
+
VIN VOUT
R1/C1
ON/OFF
Q1
Q2
R1
C1
ESD ESD
ESD
ESD
R2
CL
(2, 3)
R2
(1)
(5)
(6)
(4)
GPIO/
Logic
Up to
8V
Supply LOAD
TPS27081A
www.ti.com
SLVSBE9D –APRIL 2012–REVISED APRIL 2013
APPLICATION INFORMATION
The TPS27081A IC is a high side load switch that integrates a Power PFET and a Control NMOS in a tiny
package. The TPS27081A internal components are rated for up to 8V supply and support up to 3A of load
current. The TPS27081A can be used in a variety applications. Figure 3 below shows a general application of
TPS27081A to control the load inrush current.
Figure 3. Typical Application Diagram
Configuring Q1 ON Resistance
The VGS-Q1 Gate-Source voltage across the PMOS transistor Q1 sets its ON resistance RQ1(ON). Directly
connecting the pin R2 to ground maximizes the ON state VGS-Q1 and thus minimizes the VIN to VOUT voltage
dropout. When a resistor R2 is installed to control the Turn-ON slew rate then VGS-Q1 is given by:
e.g. R1 = 10 x R2, VIN = 5V sets VGS-Q1 = –4.5V (1)
Note: It is recommended to keep R1 > 10 x R2. Higher value of resistor R1 minimizes quiescient current when is
PMOS is on, however may adversely impact off state leakage current. Refer to the ILoad parameter in the
ELECTRICAL CHARACTERISTICS.
Configuring Turn-ON Slew Rate
Switching a large capacitive load CL instantaneously results in a load inrush current given by the following
equation:
(2)
An uncontrolled fast rising ON/OFF logic input may result in a high slew rate at the output resulting in a very high
dv/dt thus leading to a higher inrush current. To control the inrush current connect a resistor R2 and a capacitor
C1 as shown in the Electrical Characteristics Table. Use the following equation to configure the TPS27081A slew
rate to a specific value. Refer to Table 1 for component values to configure TPS27081A to achieve standard slew
rates.
(3)
Where trise is the time delta starting from the ON/OFF signal’s rising edge to charge up the load capacitor CL
from 10% to 90% of VIN voltage.
Note: The trise equation is accurate to within +/-20% across full VIN range supported by TPS27081A. Ensure that
R1 > 10 x R2.
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SLVSBE9D –APRIL 2012–REVISED APRIL 2013
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Table 1. Component Values for VOUT Rise Time
Rise Time (µs)(2)(3)
R1=10kΩ, R2=1kΩR1=5.1kΩ, R2=510Ω
C1(1)
VIN = VIN =
VIN = 7V VIN = 5V VIN = 7V VIN = 5V VIN = 3.3V VIN = 1.2V
3.3V 1.2V
220pF .253 .316 .416 .810 .129 .161 .212 .413
1000pF 1.15 1.44 1.89 3.68 .586 .732 .963 1.88
4700pF 5.4 6.75 8.88 17.3 2.76 3.44 4.53 8.83
0.18uF 207 258 340 663 106 132 173 338
0.27uF 310 388 510 994 158 198 260 507
0.33uF 379 474 623 1220 194 242 318 620
1uF 1150 1440 1890 3680 586 732 963 1880
(1) Typical ceramic capacitor values
(2) CLoad=10uF. Output rise time is independent of CLoad when CLoad >> C1
(3) Rise Time is 250ns for R2=0Ωand C1=CLoad=0F
Configuring Turn-OFF Delay
TPS27081A PMOS turn-off delay from the falling edge of ON/OFF logic signal depends upon the component
values of resistor R1 & capacitor C1. Lower values of resistor R1 ensures quicker turn-off.
toff > 2 × R1 × C1 sec
Low Voltage ON/OFF Interface
The VGSQ2 is set by the ON/OFF logic level. To turn ON, the transistor Q2 requires a VGS > 1.0V (Typical). For
reliable operation apply ON/OFF logic that has the following VIH and VIL limits:
VIHON > 1.0V + IQ2 × R2 V
VILOFF < 0.2 V
Minimizing IQ2 x R2 drop helps achieve a direct interface with a low voltage ON/OFF logic. To minimize IQ2 x R2
voltage drop select a high R1/R2 ratio. E.g. When VIN= 1.8V, selecting R1/R2 = 40 will require VIH > 1.0 + 45mV
and thus allowing a 1.2V GPIO interface.
In applications where ON/OFF signal is not available connect ON/OFF pin to VIN. The TPS27081A will turn
ON/OFF in sync with the input supply connected to VIN.
Note: Connect a pull down resistor between ON/OFF pin to GND when ON/OFF is driven by a high-impedance
(tri-state) driver.
On-Chip Power Dissipation
Use the below equation to calculate TPS27081A on-chip power dissipation PD:
PD = IDQ12× RQ1(ON) +IDQ22× RQ2(ON)
Where, IDQ1 and IDQ2 are the DC current flowing through the transistors Q1 and Q2 respectively. Refer to the
ELECTRICAL CHARACTERISTICS table and/or Figure 10 through Figure 16 to estimate RQ1(ON) and RQ2(ON) for
various values of VGSQ1 and VGSQ2 respectively.
Note: MOS switches can get extremely hot when operated in saturation region. As a general guideline, to avoid
transistors Q1 and Q2 going into saturation region set VGS > VT +VDS. E.g. VGS > 1.5V and VDS < 200mV
ensures operation as a switch.
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Product Folder Links: TPS27081A
( )
J(MAX) A
(MAX) JA
T T
PD -
=q
TPS27081A
www.ti.com
SLVSBE9D –APRIL 2012–REVISED APRIL 2013
Thermal Reliability
For higher reliability it is recommended to limit TPS27081A IC’s die junction temperature to less than 105°C. The
IC junction temperature is directly proportional to the on-chip power dissipation. Use the following equation to
calculate maximum on-chip power dissipation to achieve the maximum die junction temperature target:
Where:
TJ(MAX) is the target maximum junction temperature.
TAis the operating ambient temperature.
RθJA is the package junction to ambient thermal resistance. (4)
Improving Package Thermal Performance
The package θJA value under standard conditions on a High-K board is listed in the DISSIPATION RATINGS.θJA
value depends on the PC board layout. An external heat sink and/or a cooling mechanism, like a cold air fan, can
help reduce θJA and thus improve device thermal capabilities. Refer to TI’s design support web page at
www.ti.com/thermal for a general guidance on improving device thermal performance.
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: TPS27081A
VIN VOUT
R1/C1
ON/OFF
Q1
Q2
R1
C1
R2
COUT
(2, 3)
R2
(1)
(5)
(6)
(4)
GPIO
3-5V
Input
TFT
LCD
Module
CIN VIN
TPS27081A
SLVSBE9D –APRIL 2012–REVISED APRIL 2013
www.ti.com
APPLICATION EXAMPLES
TFT LCD Module Inrush Current Control
Figure 4. Inrush Current Control Using TPS27081A
LCD panels require inrush current control to prevent permanent system damages during turn-ON and turn-OFF
events.
Standby Power Isolation
Figure 5. Standby Power Generation Using TPS27081A
Many applications have some always ON modules to support various core functions. However, some modules
are selectively powered ON or OFF to save power and multiplexing of various on board resources. Such
modules that are selectively turned ON or OFF require standby power generation. In such applications
TPS27081A requires only a single pull-up resistor. In this configuration the VOUT voltage rise time is
approximately 250ns when VIN = 5V.
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Product Folder Links: TPS27081A
LDO
SW Supply
(DC-DC)
CPU/MCU/SOC
VIN VOUT1
R1/C1
ON/OFF
Q1
Q2
R1
C1
R2
CVDDIO
(2, 3)
R2
(1)
(5)
(6)
(4)
CIN
VDDIO VDD
CVDD
DVDD
VIN VOUT
R1/C1
ON/OFF
Q1
Q2
R1 CIN
(2, 3)
R2
(1)
(5)
(6)
(4)
1.8 - 8V
Input
Boost Reg
CIN VIN SW
FB
GPIO
SHDN
TPS27081A
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SLVSBE9D –APRIL 2012–REVISED APRIL 2013
Boost Regulator with True Shutdown
Figure 6. True Shutdown Using TPS27081A
The most common boost regulator topology provides a current leakage path through inductor and diode into the
feedback resistor even when the regulator is shut down. Adding a TPS27081A in the input side power path
prevents this leakage current and thus providing a true shutdown.
Single Module Multiple Power Supply Sequencing
Figure 7. Power Sequencing Using TPS27081A, Example 1
Most modern SOCs and CPUs require multiple voltage inputs for its Analog, Digital cores and IO interfaces.
These ICs require that these supplies be applied simultaneously or in a certain sequence. TPS27081A when
configured, as shown in Figure 7, with the VOUT1 rise time adjusted appropriately through resistor R2 and
capacitor C1, will delay the early arriving LDO output to match up with late arriving DC-DC output and thus
achieving power sequencing.
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: TPS27081A
VIN VOUT
R1/C1
ON/OFF
Q1
Q2
R1
C1
R2
COUT1
(2, 3)
R2
(1)
(5)
(6)
(4)
Module1
CIN VDD1
Up to
8V
Input
VOUT
R1/C1
ON/OFF
Q1
Q2
R3
C1
R4
COUT2
(2, 3)
R2
(1)
(5)
(6)
(4)
Module2
VDD2
VIN VOUT1
R1/C1
ON/OFF
Q1
Q2
R1
C1
R2
COUT1
(2, 3)
R2
(1)
(5)
(6)
(4)
Module1
(CPU/MCU)
CIN VDD1
1.2 - 8V
Input VOUT2
R1/C1
ON/OFF
Q1
Q2
R3
C2
R4
COUT2
(2, 3)
R2
(1)
(5)
(6)
(4)
Module2
VDD2
GPIO
TPS27081A
SLVSBE9D –APRIL 2012–REVISED APRIL 2013
www.ti.com
Multiple Modules Interdependent Power Supply Sequencing
Figure 8. Power Sequencing Using TPS27081A, Example 2
For system integrity reasons a certain power sequencing may be required among various modules. As shown in
Figure 8, Module 2 will power up only after Module 1 is powered up and the Module 1 GPIO output is enabled to
turn ON Module 2. TPS27081A when used as shown in Figure 8 will not only sequence the Module 2 power, but
also it will help prevent inrush current into the power path of Module 1 and 2.
Multiple Modules Interdependent Supply Sequencing without a GPIO Input
Figure 9. Power Sequencing using TPS27081A, Example 3
When a GPIO signal is not available connecting the ON/OFF pin of TPS27081 connected to Module 2 will power
up Module 2 after Module 1, when resistor R4 and capacitor C1 are chosen appropriately. The two TPS27081A
in this configuration will also control load inrush current.
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TPS27081A
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SLVSBE9D –APRIL 2012–REVISED APRIL 2013
TPS27081A THIN SOT(DDC) SPECIFIC PACKAGE DIMENSIONS
NOTES:
• All linear dimensions are in millimeters.
• Body dimensions do not include mold flash or protrusion.
• Falls within JEDEC MO-193 variation AA (6 pin).
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: TPS27081A
0
0.03
0.06
0.09
0.12
0.15
0 0.5 1 1.5 2 2.5 3
Vdrop (V)
ILoad (A)
25 degC
85 degC
C003
0
0.03
0.06
0.09
0.12
0.15
0 0.5 1 1.5 2 2.5 3
Vdrop (V)
ILoad (A)
25 degC
85 degC
C003
0
0.04
0.08
0.12
0.16
0 0.5 1 1.5 2 2.5
Vdrop (V)
ILoad (A)
25 degC
85 degC
C003
0
0.03
0.06
0.09
0.12
0.15
0 0.5 1 1.5 2 2.5
Vdrop (V)
ILoad (A)
25 degC
85 degC
C003
0
0.025
0.05
0.075
0.1
0 0.1 0.2 0.3 0.4 0.5
Vdrop (V)
ILoad (A)
25 degC
85 degC
C001
0
0.05
0.1
0.15
0.2
0 0.5 1 1.5 2
Vdrop (V)
ILoad (A)
25 degC
85 degC
C003
TPS27081A
SLVSBE9D –APRIL 2012–REVISED APRIL 2013
www.ti.com
TYPICAL CHARACTERISTICS
Figure 10. Vdrop vs IL; VGSQ1=-1.2V Figure 11. Vdrop vs IL; VGSQ1=-1.8V
Figure 12. Vdrop vs IL; VGSQ1=-2.5V Figure 13. Vdrop vs IL; VGSQ1=-3.3V
Figure 14. Vdrop vs IL; VGSQ1=-4.5V Figure 15. Vdrop vs IL; VGSQ1=-5.5V
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Product Folder Links: TPS27081A
0
0.03
0.06
0.09
0.12
0.15
0 0.5 1 1.5 2 2.5 3
Vdrop (V)
ILoad (A)
25 degC
85 degC
C003
TPS27081A
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SLVSBE9D –APRIL 2012–REVISED APRIL 2013
TYPICAL CHARACTERISTICS (continued)
Figure 16. Vdrop vs IL; VGSQ1=-7V
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Product Folder Links: TPS27081A
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0 20 40 60 80 100 120
Load Current (A)
Ambient Temp ƒC
Load Current (A)
C008
0.00
0.50
1.00
1.50
2.00
2.50
3.00
0 20 40 60 80 100 120
Load Current (A)
Ambient Temp (ºC)
Load Current (A)
C001
0.00
0.50
1.00
1.50
2.00
2.50
0 20 40 60 80 100 120
Load Current (A)
Ambient Temp (ºC)
Load Current (A)
C001
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
0 20 40 60 80 100 120
Load Current (A)
Ambient Temp ƒC
Load Current (A)
C008
0.00
0.50
1.00
1.50
2.00
2.50
3.00
0 20 40 60 80 100 120
Load Current (A)
Ambient Temp (ºC)
Load Current (A)
C001
TPS27081A
SLVSBE9D –APRIL 2012–REVISED APRIL 2013
www.ti.com
PFET Q1 Minimum Safe Operating Area (SOA)
Figure 17. Q1 SOA @ VGS_Q1 = -4.5V Figure 18. Q1 SOA @ VGS_Q1 = -3.0V
Figure 19. Q1 SOA @ VGS_Q1 = -2.5V Figure 20. Q1 SOA @ VGS_Q1 = -1.8V
Figure 21. Q1 SOA @ VGS_Q1 = -1.2V
14 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS27081A
TPS27081A
www.ti.com
SLVSBE9D –APRIL 2012–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision B (September 2012) to Revision C Page
• Removed DRV package preview from datasheet. ................................................................................................................ 1
Changes from Revision C (January 2013) to Revision D Page
• Updated wording in document. ............................................................................................................................................. 1
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TPS27081A
PACKAGE OPTION ADDENDUM
www.ti.com 23-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
TPS27081ADDCR ACTIVE SOT DDC 6 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 AUA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS27081ADDCR SOT DDC 6 3000 180.0 9.5 3.17 3.1 1.1 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Apr-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS27081ADDCR SOT DDC 6 3000 180.0 180.0 30.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Apr-2013
Pack Materials-Page 2
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