3.3V 28Mbps-2.7Gbps AnyRate(R) CLOCK AND DATA RECOVERY WITH INTEGRATED CLOCK MULTIPLIER UNIT Micrel, Inc. DESCRIPTION FEATURES Recovers any data and clock from 28Mbps to 2.7Gbps * OC-1, OC-3, OC-12, OC-48, ATM * Gigabit Ethernet, Fast Ethernet * Fibre Channel, 2x Fibre Channel * P1394, Infiniband * SMPTE-259, SMPTE-292 * Proprietary optical transport Integrated clock multiplier unit with low jitter generation Complies with Bellcore, ITU/CCITT and ANSI specifications Selectable mux for pass through; avoids jitter accumulation when switching through backplanes Available in 64-Pin EPAD-TQFP package The SY87721L is a complete Clock Recovery and Data retiming integrated circuit for data rates from 28Mbps up to 2.7Gbps NRZ including SONET FEC data rates. Included in the device, is a fully integrated Clock Multiplier Unit (CMU) that is capable of generating frequencies that cover the same data rate range as the CDR. The device is ideally suited for SONET/SDH/ATM, Fibre Channel, and Gigabit Ethernet applications, as well as other high-speed data transmission applications. Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate or code group rate source as reference. SIMPLIFIED BLOCK DIAGRAM APPLICATIONS SONET/SDH/ATM-based transmission systems, modules, and test equipment Transponders and section repeaters Multiplexers: access, add drop (ADM), and terminal (TM) Terabit routers and broadband cross-connects Fiber optic test equipment SY87721L AnyRate Data Out AnyRate Data In 2 SY87721L SY87721L CDR 2 2 Recovered Clock Reference Clock 2 CMU 2 Transmit Clock AnyRate is a registered trademark of Micrel, Inc. M9999-012508 hbwhelp@micrel.com or (408) 955-1690 1 Rev.: D Amendment: /0 Issue Date: January 2008 Micrel, Inc. SY87721L PACKAGE/ORDERING INFORMATION RDIN+ RDIN-- LFIN BRD+ BRD-- VCCO VCC BRDMX GND VCC GND CD FREQSEL3 FREQSEL2 FREQSEL1 VCOSEL2 Ordering Information(1) Part Number Package Type Operating Range Package Marking Lead Finish SY87721LHI H64-1 Industrial SY87721LHI Sn-Pb SY87721LHITR(2) H64-1 Industrial SY87721LHI Sn-Pb SY87721LHY(3) H64-1 Industrial SY87721LHY with Pb-Free Pb-Free bar-line indicator Matte-Sn SY87721LHYTR(2, 3) H64-1 Industrial SY87721LHY with Pb-Free Pb-Free bar-line indicator Matte-Sn 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VCOSEL1 PLLRN+ PLLRN-- NC PLLRW+ PLLRW-- NC VCCA GNDA PLLSW-- PLLSW+ NC PLLSN-- PLLSN+ NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64-Pin EPAD-TQFP NC DIVSEL1 DIVSEL2 DIVSEL3 ALRSEL CLKSEL GND VCC GND GND GND GND VCC REFCLK-- REFCLK+ GND 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 M9999-012508 hbwhelp@micrel.com or (408) 955-1690 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GND ENPECL RDOUTE+ RDOUTE-- RDOUTC+ RDOUTC-- VCCO RCLKE+ RCLKE-- RCLKC+ RCLKC-- VCCO TCLKE+ TCLKE-- TCLKC+ TCLKC-- Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC electricals only. 2. Tape and Reel. 3. Recommended for new designs. 2 Micrel, Inc. SY87721L SYSTEM BLOCK DIAGRAM SY889x3 SY87721L SY87724L RDATA AnyRate(R) FIBER PIN DIODE TIA POST AMP 4, 5, 8, 10 bits RCLK DEMUX CDR LOCK TCLK SY87729L CMU REF_CLK AnyClockTM 27MHz Fractional Synthesizer SEL SY889x2 FIBER LASER DIODE LASER DIODE DRIVER OC-48 EYE DIAGRAM Time (100ps/div) M9999-012508 hbwhelp@micrel.com or (408) 955-1690 3 MUX 4, 5, 8, 10 bits Micrel, Inc. SY87721L BRDMX ALRSEL PLLRW+ PLLRW-- PLLRN+ PLLRN-- FUNCTIONAL BLOCK DIAGRAM BRD Mux BRD+ BRD-- RDOUTE+ RDIN+ RDIN-- RDOUTE-- Phase Detector/ Data Recovery RDOUTC+ Mux Charge Pump N/W VCO N/W1/W2/W3 RDOUTC-- Phase/ Frequency Detector RCLKE+ RCLKE-- RCLKC+ RCLKC-- Link Fault Detector CD LFIN REFCLK+ Phase/ Frequency Detector Charge Pump N/W Mux REFCLK-- VCO N/W1/W2/W3 TCLKE+ Divide by 1, 2, 4, 8, 10, 16, 20, 32 TCLKE-- TCLKC+ M9999-012508 hbwhelp@micrel.com or (408) 955-1690 4 CLKSEL ENPECL FREQSEL3 FREQSEL2 FREQSEL1 PLLSW-- PLLSW+ PLLSN+ PLLSN-- VCOSEL2 VCOSEL1 DIVSEL1 DIVSEL2 DIVSEL3 TCLKC-- Micrel, Inc. SY87721L PIN NAMES DIVSEL1, ..., DIVSEL3 [Divider Select] - TTL Inputs These inputs select the ratio between the output clock frequency (RCLK/TCLK) and the REFCLK input frequency as shown in Table 4. Please note that the divide by 32 selection, "011", is only available for use when FREQSEL are set to "000." INPUTS BRDMX [BRD Mux] - PECL Input This signal indicates what data appears at the BRD output. When logic HIGH, BRD is a direct copy of what appears at RDOUTC. When logic low, BRD is a copy of what appears at RDIN. Unlike RDOUTC, BRD conveys valid data even when ENPECL is logic LOW. Please refer to Table 1. DIVSEL1 DIVSEL2 DIVSEL3 REFCLK Multiplier 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 32 Table 1. BRDMX Truth Table 1 0 0 8 RDIN [Serial Data Input] - Differential PECL Input This differential input accepts the receive serial data stream. An internal receive PLL recovers the embedded clock (RCLK) and data (RDOUT) information. The incoming data rate can be within one of ten frequency ranges, or can be one of five specific frequencies, depending on the state of the FREQSEL and VCOSEL pins. The RDIN- pin has an internal 75K resistor tied to VCC. REFCLK [Reference Clock] - Differential PECL Input This input is used as the reference for the internal frequency synthesizer and the "training" frequency for the receiver PLL to keep it centered in the absence of data coming in on the RDIN input. The input frequency to REFCLK is limited to 340MHz or less, depending on the setting on the DIVSEL signals. The REFCLK- pin has an internal 75K resistor tied to VCC. CD [Carrier Detect] - PECL Input This input controls the recovery function of the Receive PLL and can be driven by the carrier detect output of optical modules or from external transition detection circuitry. When this input is HIGH, the input data stream (RDIN) is recovered normally by the Receive PLL. When this input is LOW, the data on the RDOUT output will be internally forced to a constant LOW, the Link Fault Indicator output LFIN forced LOW, and the clock recovery PLL forced to lock onto the synthesized clock frequency generated from REFCLK. VCOSEL1, VCOSEL2 [VCO Select] - TTL Inputs These inputs select the output clock frequency range via either one of three PLLs, or a SONET/SDH specific PLL. Only the selected PLL is enabled. All other PLLs are disabled. Refer to Table 3 for more details. 1 0 1 10 1 1 0 16 1 1 1 20 BRDMX (Input) BRD (Output) 0 RDIN 1 RDOUTC Table 2(1). Reference Clock Multiplier Truth Table Note: 1. Some combinations of FREQSEL and DIVSEL result in undefined behavior. Refer to Table 3 for more details. CLKSEL [Clock Select] - TTL Input This input is used to select either the recovered clock of the receiver PLL (CLKSEL = HIGH) or the clock of the frequency synthesizer (CLKSEL = LOW) to the TCLK outputs. Do not use for skew matching. ENPECL [Enable ECL] - TTL Input This input, when HIGH (ENPECL = 1), enables the differential PECL outputs TCLKE, RDOUTE, and RCLKE. It also disables the CML outputs, by setting TCLKC+, RDOUTC+, and RCLKC+ logic HIGH and setting TCLKC-, RDOUTC-, and RCLKC- logic LOW. When set LOW (ENPECL = 0), this signal enables the differential CML outputs TCLKC, RDOUTC, and RCLKC. It also disables the PECL outputs by setting TCLKE+, RDOUTE+, and RCLKE+ logic HIGH and setting TCLKE-, RDOUTE- and RCLKE- logic LOW. ALRSEL [Auto Lock Range Select] - TTL Input This pin defines the frequency difference, and the frequency difference hysteresis at which `in-lock' and `out of lock' conditions are declared. Please refer to the "AC Characteristics" for more details. FREQSEL1, ..., FREQSEL3 [Frequency Select] - TTL Inputs These inputs select the post divide ratio of the VCO. Refer to Table 3 for more details. M9999-012508 hbwhelp@micrel.com or (408) 955-1690 5 Micrel, Inc. SY87721L OUTPUTS External loop filter pins for the clock synthesis wide band PLL. PLLRN+, PLLRN- [Clock Recovery Loop Filter] External loop filter pins for the clock recovery narrow band PLL. PLLRW+, PLLRW- [Clock Recovery Loop Filter] External loop filter pins for the clock recovery wide band PLL. OTHERS BRD [Buffered Recovered Data] - Differential CML Output The signal is either a buffered RDIN or RDOUTC, depending on the state of the BRDMX input. This allows a user to selectively bypass the CDR or not, as warranted by architecture. This CML output has a voltage swing of 400mV loaded. LFIN [Link Fault Indicate] - O.C. TTL Output This output indicates the status of the input data stream RDIN. Active HIGH indicates that the internal clock recovery PLL has locked onto the incoming data stream. LFIN will go HIGH if CD is HIGH and RDIN is within the frequency range of the Receive PLL (as per ALRSEL). LFIN is an asynchronous output. RDOUTE [Receive Data Out] - Differential PECL Output These ECL 100K outputs (+3.3V referenced) represent the recovered data from the input data stream (RDIN). It is specified on the rising edge of RCLK. VCC VCCO VCCA GND GNDA NC RDOUTC [Receive Data Out] - Differential CML Output This is the CML version of RDOUTE. RCLKE [Receive Clock Out] - Differential PECL Output These ECL 100K outputs (+3.3V referenced) represent the recovered clock used to sample the recovered data (RDOUT). RCLKC [Receive Clock Out] - Differential CML Output This is the CML version of RCLKE. TCLKE [Transmit Clock Out] - Differential PECL Output These ECL 100K outputs (+3.3V referenced) represent either the recovered clock (CLKSEL = HIGH) used to sample the recovered data (RDOUT) or the transmit clock of the frequency synthesizer (CLKSEL = LOW). TCLKC [Transmit Clock Out] - Differential CML Output This is the CML version of TCLKE. PLLSN+, PLLSN- [Clock Synthesis Loop Filter] External loop filter pins for the clock synthesis narrow band PLL. PLLSW+, PLLSW- [Clock Synthesis Loop Filter] M9999-012508 hbwhelp@micrel.com or (408) 955-1690 6 Supply Voltage Output Supply Voltage Analog Supply Voltage Ground Analog Ground These pins are for factory test, and are to be left unconnected during normal use. Micrel, Inc. SY87721L DESCRIPTION reference. Once the recovery PLL is within the specified lock range, determined by the state of ALRSEL, the SY87721L will switch from a phase-frequency comparison with the synthesized reference, to a phase-only comparison with the incoming data stream. When the recovery PLL is locked to this incoming data stream (that is, after phase step recovery), then data recovery may proceed and LFIN asserts. Once locked and accepting data, the LFIN signal may de-assert should the data input frequency deviate too far from the synthesized reference frequency. VCO Selection SY87721L sports four complete VCO circuits. Depending on the application and the frequency range, any one of these four perform data recovery. As indicated by the VCO selection table, there are three general purpose VCOs each covering one of three frequency ranges. However, to extend the range of the device, the output of the VCO may be divided down. In the case of the two highest frequency general purpose VCOs (VCOSEL = 1, 0 or 0,1 ), this divisor is always set to 1. For the lowest frequency VCO, the FREQSEL pins select which divisor, and hence, which range of frequencies the VCO will work over. In addition, for SONET/SDH applications, there is a narrow band, extremely low jitter PLL. It also uses the FREQSEL divisor to choose the correct SONET/SDH frequency. The valid modes of operation are shown in Table 3. General The SY87721L is a complete clock and data recovery circuit, capable of handling NRZ data rates from 28MHz through to 2.7GHz. A reference PLL is used as a frequency synthesizer, both to multiply a reference clock to the desired transmit rate, and to train the recovery PLL in preparation for actual data recovery. Link Fault Algorithm The SY87721L includes a Link Fault Detection circuit. This circuit provides the following functions: Under Loss-ofLock (LOL) conditions, which can occur when the Carrier Detect (CD) input is active HIGH, the output of the RCLK approximates the output of the TCLK, within a lock range as specified by the state of ALRSEL. Under Loss-of-Signal (LOS) conditions, enabled by driving the Carrier Detect (CD) input to inactive logic LOW, the output of the RCLK becomes an exact copy of the TCLK output. This is the result of forcing the recovery PLL to lock to the synthesized reference. Under LOL and LOS conditions, the LFIN output is an inactive logic LOW. SY87721L follows a prescribed procedure, to acquire and recover the clock of the incoming data stream. This procedure is triggered either by a falling edge on CD, or by the recovered clock PLL indicating a frequency error, compared to the synthesized reference, of greater than 500ppm or 4,500ppm, as selected by ALRSEL. With the CD input set active HIGH, the algorithm begins by phase and frequency training the recovery PLL to the synthesized VCOSEL1 VCOSEL2 FREQSEL1 FREQSEL2 FREQSEL3 Range (MHz) 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 0 0 0 1 1 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0 0 1 1 0 0 1 1 0 1 0 0 0 0 0 0 1 0 1 0 1 0 1 2488 (OC48)-2700 1244-1350 622 (OC12)-675 311-337 155 (OC3)-168 1800-2700 1250-1800 650-1300(1) 325-650(2) 163-325 109-216 82-162 55-108 41-81 28-54 Table 3 (3). Frequency Range Selection Truth Table Notes: 1. REFCLK multiplier of 1 or 2 is not allowed in this range. 2. REFCLK multiplier of 1 is not allowed in this range. 3. Combinations of VCOSEL and FREQSEL other then those in this table result in undefined behavior, and should not be used. M9999-012508 hbwhelp@micrel.com or (408) 955-1690 7 Micrel, Inc. SY87721L CML OUTPUT DIAGRAM(1) LOOP FILTER COMPONENTS R VCC C 50 PLLSN+ or PLLSW+ 50 100 PLLSN- or PLLSW- Figure 1. Narrow Band and Wide Band Synthesizer Loop Filter 16mA SY87721L C R Figure 3. 50 Load CML Output PLLRN+ or PLLRW+ NOTE: 1. VOSW is defined as |VOH-VOL| on any one pin (either the true or the complement pin). As opposed to the single-ended swing, differential swing, VOSW (true pin) + VOSW (complement pin) is double the VOSW value. PLLRN- or PLLRW- Figure 2. Narrow Band and Wide Band CDR Loop Filter PLL PLLSN+, PLLSN- PLLRN+, PLLRN- PLLSW+, PLLSW- PLLRW+, PLLRW- R 1.2k 390 845 455 C 1F 1F 1F 1F Table 4. Synthesizer and Clock Recovery Loop Filter Values OC-48 JITTER TRANSFER AND TOLERANCE 100 Amplitude UI Jitter Ratio (dB) 10 0 -10 10 1 .1 -20 1000 10000 100000 1.E+6 1000 1.E+7 100000 1.E+6 Modulation Frequency (Hz) Modulation Frequency (Hz) OC-48 Jitter Transfer M9999-012508 hbwhelp@micrel.com or (408) 955-1690 10000 OC-48 Jitter Tolerance 8 1.E+7 Micrel, Inc. SY87721L ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Rating Unit VCC Power Supply Voltage -0.5 to +5.0 V VIN Input Voltage -0.5 to VCC V IOUT ECL Output Current 50 100 mA ICMLOUT CML Output Current 30 mA +260 C - Continuous - Surge Lead Temperature (soldering, 20 sec.) Tstore Storage Temperature Range -65 to +150 C TA Operating Temperature Range -40 to +85 C 22.3 17.2 15.1 C/W C/W C/W JA Resistance(2) Package Thermal (Junction-to-Ambient) - 0lfpm - 200lfpm - 500lfpm Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Jedec standard test boards with die attach pad soldered to pcb. Tested at 1W. DC ELECTRICAL CHARACTERISTICS VCC =VCCO = VCCA = 3.3V 5%; GND = GNDA = 0V; TA = -40C to +85C Symbol Parameter Min. Typ. Max. Unit VCC Power Supply Voltage 3.15 3.3 3.45 V ICC Power Supply Current -- 360 450 mA Condition 100K PECL DC ELECTRICAL CHARACTERISTICS VCC =VCCO = VCCA = 3.3V 5%; GND = GNDA = 0V; TA = -40C to +85C Symbol Parameter Min. Typ. Max. Unit -- VCC - 0.880 V Condition VIH Input HIGH Voltage VCC - 1.165 VIL Input LOW Voltage VCC - 1.810 -- VCC - 1.475 V IIL Input LOW Current -0.5 -- -- A VIN = VIL(Min) VOH Output HIGH Voltage VCC - 1.075 -- VCC - 0.830 V 50 to VCC -2V VOL Output LOW Voltage VCC - 1.860 -- VCC - 1.570 V 50 to VCC -2V Note: 1. All PECL inputs have an internal 75k resistor to VEE. In addition, the complement inputs of all differential PECL inputs have a 75k resistor to VCC. Thus, unconnected PECL inputs behave like static logic LOW. CML DC ELECTRICAL CHARACTERISTICS VCC =VCCO = VCCA = 3.3V 5%; GND = GNDA = 0V; TA = -40C to +85C Symbol Parameter Min. Typ. Max. Unit Condition VOH Output HIGH Voltage VCC - 0.050 -- VCC V No Load VOL Output LOW Voltage -- -- VCC - 0.65 V No Load VOSW Output Voltage Swing -- 0.4 -- V 50 to VCC Note: 1. VOSW is defined as |VOH-VOL| on any one pin (either the true or the complement pin). As opposed to the single-ended swing, differential swing, VOSW (true pin) + VOSW (complement pin) is double the VOSW value. M9999-012508 hbwhelp@micrel.com or (408) 955-1690 9 Micrel, Inc. SY87721L TTL DC ELECTRICAL CHARACTERISTICS VCC =VCCO = VCCA = 3.3V 5%; GND = GNDA = 0V; TA = -40C to +85C Symbol Parameter Min. Typ. Max. Unit Condition VIH Input HIGH Voltage 2.0 -- -- V VIL Input LOW Voltage -- -- 0.8 V IIH Input HIGH Current -- -- -- -- +20 +100 A A VIN = 2.7V, VCC = 3.45V VIN = VCC, VCC = 3.45V IIL Input LOW Current -300 -- -- A VIN = 0.5V, VCC = Max. IOLK Output Leakage Current -- -- 500 A VOUT = VCC VOL Output LOW Voltage -- -- 0.5 V IOL = 4mA AC ELECTRICAL CHARACTERISTICS VCC =VCCO = VCCA = 3.3V 5%; GND = GNDA = 0V; TA = -40C to +85C Symbol Parameter Min. Typ. Max. Unit -- -- 0.01 UI rms Frequency Difference, LFIN shows Out of Lock 500 1500 -- ppm ALRSEL High Frequency Difference, LFIN shows Out of Lock 4500 6500 -- ppm ALRSEL Low RDIN Maximum Data Rate 2.7 -- -- Gbps REFCLK Maximum Frequency -- -- 340 MHz tCPWH REFCLK Pulse Width High 1.2 -- -- ns tCPWL REFCLK Pulse Width Low 1.2 -- -- ns tIRF REFCLK Input Rise/Fall Time (20% to 80%) -- -- 1.0 ns tODC Output Duty Cycle (RCLK/TCLK) 45 -- 55 % of UI tRE tFE ECL Output Rise/Fall Time (20% to 80%) -- -- 600 ps 50 to VCC-2V tRC tFC CML Output Rise/Fall Time (20% to 80%) -- -- 120 ps 50 Load tDV Data Valid 100 -- -- ps tDH Data Hold 100 -- -- ps TCLK Output Jitter M9999-012508 hbwhelp@micrel.com or (408) 955-1690 10 Condition REFCLK Multiplier 16 VCOSEL = 0, 0 Micrel, Inc. SY87721L TIMING WAVEFORMS tCPWL tCPWH REFCLK- tDV tDH RDOUT tODC tODC RCLK CML VOSW DIAGRAM VOSW (Single-Ended Swing) VOH CML Pin (True or Complement) M9999-012508 hbwhelp@micrel.com or (408) 955-1690 VOL 11 Micrel, Inc. SY87721L EVALUATION BOARD SCHEMATIC VCC 5k D2 1 3 5 C3 D3 RDIN+: FORCE RDIN+: SENSE RDIN--: FORCE RDIN--: SENSE BRD+: PIN 52 VEE: PIN 56 VEE: PIN 57 49 50 51 52 RDIN+ RDIN-- LFIN BRD+ VCC GND BRDMX 53 BRD-- 54 VCCO 55 56 57 R16, 5k JP2 PLLRN-- RDOUTE+ NC RDOUTE-- PLLRW+ RDOUTC+ PLLRW-- RDOUTC-- VCCO RCLKE+ SY87721L 15 RDOUTE+ 45 RDOUTE-- 44 RDOUTC+ 43 RDOUTC-- 42 VCCO: PIN 42 41 PLLSW-- RCLKC+ PLLSW+ RCLKC-- 38 RCLKE+ RCLKE-- 39 VCCO 37 PLLSN-- TCLKE+ 36 PLLSN+ TCLKE-- 35 NC TCLKC+ RCLKC+ RCLKC-- VCCO: PIN 37 TCLKE+ TCLKE-- 34 TCLKC+ TCLKC-- 33 TCLKC-- GND REFCLK+ REFCLK-- VCC GND GND GND VCC GND GND CLKSEL ALRSEL DIVSEL3 NC DIVSEL2 NC VEE 46 RCLKE-- 40 DIVSEL1 16 VEE: PIN 48 47 GNDA NC 13 C8 VCC R23, 5k R22, 5k R21, 5k R20, 5k R19, 5k 12 14 VCC 58 11 R10 VCC ENPECL VCCA 10 C7 GND R9 VCC NC 9 R18, 5k SW DIP-6 7 8 12 11 10 9 8 7 59 6 C6 VEE 4 5 S3 VCC: PIN 58 VEE: PIN 59 R8 CD C5 R17, 1.7k GND 48 PLLRN+ 3 2 4 6 8 10 12 60 C10 FREQSEL3 C9 HEADER 6X2 JP1 VCOSEL1 2 61 R7 FREQSEL2 1 VCCA 62 VCOSEL2 L3 FREQSEL1 VCC 63 64 R5, 5k R4, 5k R3, 5k R2, 5k R1, 5k SW DIP-5 VEE C1 LED VEE 10 9 8 7 6 C2 C4 2 4 6 VCC S1 1 2 3 4 5 L1 BRD--: PIN 53 R47, 130 1 2 3 4 5 6 L2 HEADER 3X2 JP4 VCC 1 3 5 7 9 11 VCC VCCO D1 R48, 20 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 L7 VEE VEE VEE:PIN 32 12 REFCLK+: FORCE REFCLK+: SENSE M9999-012508 hbwhelp@micrel.com or (408) 955-1690 REFCLK--: FORCE REFCLK--: SENSE Notes: 1. C11, C17, C10, C4, C2 = 0.1F 2. C18, C12, C9, C3, C1 = 1F 3. C2, C4, C10, C11, and C17 need to be located right at device pin. If vias to power GND used--use overlapping multiple vias to lower inductance. R11, 1.2k VEE R12, 1.2k R13, 1.2k R14, 1.2k SW DIP-8 VCC R15, 1.2k 10 9 8 7 6 VEE:PIN 26 S2 1 2 3 4 5 VCC:PIN 24 C17 VEE:PIN 25 VEE:PIN 23 C18 L4 VCC C11 C12 Micrel, Inc. SY87721L EVALUATION BOARD I/O TERMINATION SCHEMES TCLK OUTPUTS RCLK OUTPUTS RDOUT OUTPUTS RDIN INPUTS VCC C19 TCLKC- J14 1 C23 J10 RCLKC- C27 RDOUTC- 1 2 2 R36, 68.5 J6 1 C31 RDIN+:FORCE 2 J1 1 2 R37, 185.2 VEE C20 TCLKC+ J13 1 C24 RCLKC+ J9 1 2 C28 RDOUTC+ J5 1 2 C32 RDIN+: SENSE J2 1 2 2 VCC R38, 68.5 C21 TCLKE- J12 1 2 R30, 330 J11 1 2 2 VEE 2 VEE VEE Notes: 1. For AC coupling, include capacitors C19 thru C31, C33, C35 and C37. 2. If DC coupling, remove resistors R36 thru R43. M9999-012508 hbwhelp@micrel.com or (408) 955-1690 13 2 R39, 185.2 J3 1 R35, 330 J17 1 VEE C30 RDOUTE+ C33 RDIN-:FORCE 2 R34, 330 J7 1 R33, 330 J4 1 VEE C26 RCLKE+ C29 RDOUTE+ VEE C22 R31, 330 J8 1 R32, 330 VEE TCLKE+ C25 RCLKE- 2 RDIN-: SENSE C34 J18 1 2 Micrel, Inc. SY87721L REFCLK BRD INPUTS OUTPUTS VCC R40, 68.5 BRD+: PIN 52 C35 REFCLK+:FORCE C39 J15 1 J21 1 2 2 R41, 185.2 VEE: PIN 59 VCC: PIN 58 VEE VEE: PIN 57 VEE: PIN 48 C36 REFCLK+: SENSE J16 1 2 BRD--: PIN 53 C40 J22 1 VCCO: PIN 42 2 VCCO: PIN 37 VEE: PIN 32 VCC VEE: PIN 26 R42, 68.5 C37 REFCLK-:FORCE J19 1 VEE: PIN 25 2 R43, 185.2 VCC: PIN 24 VEE VEE: PIN 23 C45 0.01 F C46 0.01 F C47 0.01 F C49 0.01 F C50 0.01 F C51 0.01 F C52 0.01 F C53 0.01 F C54 0.01 F C55 0.01 F C56 0.01 F REFCLK-: SENSE C38 J20 1 2 M9999-012508 hbwhelp@micrel.com or (408) 955-1690 14 Micrel, Inc. SY87721L 64 LEAD EPAD-TQFP (DIE UP) (H64-1) +0.05 -0.05 +0.002 -0.002 +0.05 -0.05 +0.012 -0.012 +0.03 -0.03 +0.012 -0.012 +0.15 -0.15 +0.006 -0.006 +0.05 -0.05 +0.002 -0.002 Rev. 02 Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane PCB Thermal Consideration for 64-Pin EPAD-TQFP Package M9999-012508 hbwhelp@micrel.com or (408) 955-1690 15 Micrel, Inc. SY87721L APPENDIX A Layout and General Suggestions 1. Establish controlled impedance stripline, microstrip, or co-planar construction techniques. 2. Signal paths should have, approximately, the same width as the device pads. 3. All differential paths are critical timing paths, where skew should be matched to within 10ps. 4. Signal trace impedance should not vary more than 5%. If in doubt, perform TDR analysis of all high-speed signal traces. 5. Maintain compact filter networks as close to filter pins as possible. Provide ground plane relief under filter path to reduce stray capacitance. Be careful of crosstalk coupling into the filter network. 6. Maintain low jitter on the REFCLK input. Isolate the XTAL oscillator from power supply noise by adequately decoupling. Keep XTAL oscillator close to device, and minimize capacitive coupling from adjacent signals. 7. Higher speed operation may require use of fundamental-tone (third-overtone typically have more jitter) crystal based oscillator for optimum performance. Evaluate and compare candidates by measuring TXCLK jitter. 8. Evaluate ASIC AND FPGA REFIN source clocks with suitable jitter analysis equipment, such as TDS11801 tektronix DSO oscilloscope, or Wavecrest DTS2077 Time Interval Analyzer. 9. All unused outputs require termination. NC, however, should be unconnected. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB USA http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated. M9999-012508 hbwhelp@micrel.com or (408) 955-1690 16