This is information on a product in full production.
March 2019 DS11546 Rev 5 1/197
L99DZ100G, L99DZ100GP
Automotive door module with LIN and HS-CAN (L99DZ100G) or
HS-CAN supporting selective wake up (L99DZ100GP)
Datasheet - production data
Features
AEC Q100 compliant qualified
1 half bridge for 7.5 A load (RON = 100 m)
1 half bridge for 7.5 A load (RON = 150 m)
2 half bridges for 0.5 A load (RON = 2000 m)
2 half bridges for 3 A load (RON = 300 m)
1 configurable high-side driver for up to 1.5 A
(RON = 500 m) or 0.35 A (RON = 1600 m)
load
1 configurable high-side driver for 0.8 A
(RON = 800 m) or 0.35 A (RON = 1600 m)
load
3 configurable high-side drivers for
0.15 A/0.35 A (RON =2 )
1 configurable high-side driver for 0.25 A/0.5 A
(RON = 2 ) to supply EC Glass MOSFET
4 configurable high-side drivers for
0.15 A/0.25 A (RON = 5 )
Internal 10bit PWM timer for each stand-alone
high-side driver
Buffered supply for voltage regulators and 2
high-side drivers (OUT15 & OUT_HS / both
P-channel) to supply e.g. external contacts
Programmable soft-start function to drive loads
with higher inrush currents as current limitation
value (for OUT1-6, OUT7, OUT8 and
OUT_HS) with thermal expiration feature
All the embedded outputs come with protection
and supervision features:
– Current Monitor (high-side only)
– Open-load
– Overcurrent
– Thermal warning
– Thermal shutdown
Fully protected driver for external MOSFETs in
H-bridge configuration or dual Half bridge
configuration
Fully protected driver for external high-side
MOSFET
Control block for electro-chromic element
Two 5 V voltage regulators for microcontroller
and peripheral supply
Programmable reset generator for power-on
and undervoltage
Configurable window watchdog
LIN 2.2a compliant (SAEJ2602 compatible)
transceiver
Advanced high speed CAN transceiver (ISO
11898-2:2003 /-5:2007 and SAE J2284
compliant) with local failure and bus failure
diagnosis and selective wake-up functionality
according to ISO 11898-6:2013
Separated (Isolated) fail-safe block with 2 LS
(RON = 1 ) to pull down the gates of the
external HS MOSFETs
Thermal clusters
A/D conversion of supply voltages and internal
temperature sensors
Embedded and programmable VS duty cycle
adjustment for LED driver outputs
Applications
Door zone applications.
www.st.com
L99DZ100G, L99DZ100GP
2/197 DS11546 Rev 5
Table 1. Device summary
Package Variant
Order codes
Tray Tape and reel
LQFP-64 epad High Speed CAN Transceiver with partial networking
(ISO 11898-6:2013) L99DZ100GP L99DZ100GPTR
LQFP-64 epad High Speed CAN Transceiver (ISO 11898-2:2003
and 11898-5:2007) L99DZ100G L99DZ100GTR
Product label
DS11546 Rev 5 3/197
L99DZ100G, L99DZ100GP Contents
7
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 Block diagram and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.1 LQFP64 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4.1 Supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4.3 Power-on reset (VSREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4.4 Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4.5 Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4.6 Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4.7 Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.4.8 Current monitor output (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.4.9 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.4.10 Outputs OUT1 - OUT15, OUT_HS, ECV, ECDR . . . . . . . . . . . . . . . . . . 38
3.4.11 Power outputs switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.4.12 Current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.4.13 Heater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.4.14 H-bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.4.15 Gate drivers for the external Power-MOS switching times . . . . . . . . . . 45
3.4.16 Drain source monitoring external H-bridge . . . . . . . . . . . . . . . . . . . . . . 48
3.4.17 Drain source monitoring external heater MOSFET . . . . . . . . . . . . . . . . 49
3.4.18 Open-load monitoring external H-bridge . . . . . . . . . . . . . . . . . . . . . . . . 49
3.4.19 Open-load monitoring external heater MOSFET . . . . . . . . . . . . . . . . . . 50
3.4.20 Electro-chrome mirror driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.4.21 Fail safe low-side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.4.22 Wake up input WU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.4.23 High speed CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.4.24 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Contents L99DZ100G, L99DZ100GP
4/197 DS11546 Rev 5
3.4.25 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.4.26 Inputs TxD_C and TxD_L for Flash mode . . . . . . . . . . . . . . . . . . . . . . . 63
3.4.27 Inputs DIRH, PWMH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.4.28 Debug input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.4.29 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.4.30 Temperature diode characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.4.31 Interrupt outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.4.32 Timer1 and Timer2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.4.33 SGND loss comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.1 Supply VS, VSREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.2 Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.2.1 Voltage regulator: V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.2.2 Voltage regulator: V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.2.3 Voltage regulator failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.2.4 Short to ground detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.2.5 Voltage regulator behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.3 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.3.1 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.3.2 Flash modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.3.3 SW-debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.3.4 V1_standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.3.5 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.3.6 CAN wake-up signalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.3.7 VBAT_standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.4 Wake-up from Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.4.1 Wake up input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.5 Functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.6 Configurable window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.6.1 Change watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.7 Fail-safe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.7.1 Temporary failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.7.2 Non-recoverable failures – forced Vbat_standby mode . . . . . . . . . . . . . 83
4.8 Reset output (NReset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.9 LIN Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
DS11546 Rev 5 5/197
L99DZ100G, L99DZ100GP Contents
7
4.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.9.2 Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.9.3 Wake up from Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.9.4 Receive-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.10 High-speed CAN bus transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.10.1 Features: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.10.2 CAN transceiver operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.10.3 Automatic voltage biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.10.4 Wake-up by CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.10.5 CAN looping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.10.6 Pretended networking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.10.7 CAN error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.11 Serial Peripheral Interface (ST SPI Standard) . . . . . . . . . . . . . . . . . . . . . 93
4.12 Power supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.12.1 VS supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.12.2 VSREG supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.13 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 97
4.14 Power outputs OUT1..15 and OUT_HS . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.15 Auto-recovery alert and thermal expiration . . . . . . . . . . . . . . . . . . . . . . . 99
4.16 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.17 Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.18 Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.19 Overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.20 Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.21 PWM mode of the power outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.22 Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.23 Programmable soft-start function to drive loads with higher inrush current .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.24 H-bridge control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.25 H-bridge driver slew-rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.26 Resistive low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.27 Short circuit detection / drain source monitoring . . . . . . . . . . . . . . . . . . 108
4.28 H-bridge monitoring in off-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.29 Programmable cross current protection . . . . . . . . . . . . . . . . . . . . . . . . . .111
Contents L99DZ100G, L99DZ100GP
6/197 DS11546 Rev 5
4.30 Power window H-bridge safety switch off block . . . . . . . . . . . . . . . . . . . .111
4.31 Heater MOSFET Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
4.32 Controller of electro-chromic glass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
4.33 Temperature warning and shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
4.34 Thermal clusters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
4.35 VS compensation (duty cycle adjustment) module . . . . . . . . . . . . . . . . . .117
4.36 Analog digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
5 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.1 ST SPI 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.1.1 Physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.2.1 Clock and Data Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.2.2 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.2.3 Address definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.2.4 Protocol failure detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
7.1 Global Status Byte GSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
7.2 Control register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.3 Status register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
7.4 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
7.4.1 Control Register CR1 (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
7.4.2 Control Register CR2 (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7.4.3 Control Register CR3 (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
7.4.4 Control Register CR4 (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
7.4.5 Control Register CR5 (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
7.4.6 Control Register CR6 (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
7.4.7 Control Register CR7 (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
7.4.8 Control Register CR8 (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
7.4.9 Control Register CR9 (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
7.4.10 Control Register CR10 (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
7.4.11 Control Register CR11 (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
7.4.12 Control Register CR12 (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
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L99DZ100G, L99DZ100GP Contents
7
7.4.13 Control Register CR13 (0x0D) to CR17 (0x11) . . . . . . . . . . . . . . . . . . 167
7.4.14 Control Register CR18 (0x12) to CR22 (0x16) . . . . . . . . . . . . . . . . . . 168
7.4.15 Control Register CR23 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
7.4.16 Control Register CR24 (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
7.4.17 Control Register CR25 (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
7.4.18 Control Register CR26 (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
7.4.19 Control Register CR27 (0x1B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
7.4.20 Control Register CR28 (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
7.4.21 Control Register CR29 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
7.4.22 Control Register CR34 (0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
7.4.23 Configuration Register (0x3F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
7.5 Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
7.5.1 Status Register SR1 (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
7.5.2 Status Register SR2 (0x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
7.5.3 Status Register SR3 (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
7.5.4 Status Register SR4 (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
7.5.5 Status Register SR5 (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
7.5.6 Status Register SR6 (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.5.7 Status Register SR7 (0x37) to SR9 (0x39) . . . . . . . . . . . . . . . . . . . . . 188
7.5.8 Status Register SR10 (0x3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
7.5.9 Status Register SR11 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
7.5.10 Status Register SR12 (0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
8.1 LQFP-64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
8.2 LQFP-64 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
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List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 4. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5. Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 6. Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7. Supply and supply monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8. Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9. Power-on reset (VSREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 10. Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 11. Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 12. Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 13. Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 14. Current monitor output (CM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 15. Charge pump electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 16. Outputs OUT1 - OUT15, OUT_HS, ECV, ECDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 17. Power outputs switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 18. Current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 19. Heater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 20. H-bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 21. Gate drivers for the external Power-MOS switching times . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 22. Drain source monitoring external H-bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 23. Drain source monitoring external heater MOSFET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 24. Open-load monitoring external H-bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 25. Open-load monitoring external heater MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 26. Electro-chrome mirror driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 27. Fail safe low-side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 28. Wake-up inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 29. CAN communication operating range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 30. CAN transmit data input: pin TxDC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 31. CAN receive data output: Pin RxDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 32. CAN transmitter dominant output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 33. CAN transmitter recessive output characteristics, CAN normal mode . . . . . . . . . . . . . . . . 54
Table 34. CAN transmitter recessive output characteristics, CAN low-power mode, biasing active . 54
Table 35. CAN transmitter recessive output characteristics, CAN low-power mode, biasing inactive 55
Table 36. CAN receiver input characteristics during CAN normal mode . . . . . . . . . . . . . . . . . . . . . . 55
Table 37. CAN receiver input characteristics during CAN low power mode, biasing active . . . . . . . . 55
Table 38. CAN Receiver input characteristics during CAN Low power mode, biasing inactive . . . . . 56
Table 39. CAN receiver input resistance biasing active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 40. CAN transceiver delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 41. Maximum leakage currents on CAN_H and CAN_L, unpowered . . . . . . . . . . . . . . . . . . . . 57
Table 42. Biasing control timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 43. LIN transmit data input: pin TxD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 44. LIN receive data output: pin RxD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 45. LIN transmitter and receiver: pin LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 46. LIN transceiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 47. Input: CSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 48. Inputs: CLK, DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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Table 49. DI, CLK and CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 50. Output: DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 51. DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 52. CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 53. Inputs: TxD_C and TxD_L for Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 54. Inputs DIRH, PWMH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 55. Debug input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 56. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 57. Temperature diode characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 58. Interrupt outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 59. Timer1 and Timer2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 60. SGND loss comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 61. CAN wake-up signalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 62. Wake-up events description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 63. Status of different functions/features vs operating modes . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 64. Temporary failures description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 65. Non-recoverable failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 66. Power output settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 67. H-bridge control truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 68. H-bridge monitoring in off-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 69. Heater MOSFET control truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 70. Thermal cluster definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 71. Operation codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 72. Global Status Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 73. Device application access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 74. Device information read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 75. RAM address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 76. ROM address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 77. Information Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 78. SPI Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 79. Burst Read Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 80. SPI Data Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 81. Data Consistency Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 82. WD Type/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 83. WD bit position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 84. Global Status Byte (GSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 85. GSB signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 86. Control register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 87. Status register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 88. Control Register CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 89. CR1 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 90. Wake-up input1 filter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 91. CAN transceiver mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 92. Voltage regulator V2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 93. Standby transition configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 94. Control Register CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 95. CR2 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 96. Configuration of Timer x on-time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 97. Control Register CR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 98. CR3 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 99. Control Register CR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 100. CR4 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
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Table 101. Control Register CR5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 102. CR5 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 103. OUTx Configuration bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 104. Control Register CR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 105. CR6 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 106. Control Register CR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 107. CR7 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 108. Half-bridge minimum ON time and related overcurrent recovery frequency. . . . . . . . . . . 160
Table 109. High-side minimum ON time and related overcurrent recovery frequency . . . . . . . . . . . . 160
Table 110. Control Register CR8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 111. CR8 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 112. Control Register CR9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 113. CR9 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 114. Control Register CR10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 115. CR10 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 116. Control Register CR11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 117. CR11 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 118. Control Register CR12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 119. CR12 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 120. Control Register CR13 to CR17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 121. CR13 to CR17 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 122. Control Register CR18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 123. CR18 to CR22 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 124. Control Register CR23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 125. CR23 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 126. Control Register CR24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 127. CR24 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 128. Control Register CR25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 129. CR25 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 130. Control Register CR26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 131. CR26 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 132. Control Register CR27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 133. CR27 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 134. Control Register CR28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 135. CR28 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 136. Control Register CR29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 137. CR29 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 138. Control Register CR34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 139. CR34 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 140. Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 141. CR signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 142. Status Register SR1 (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 143. SR1 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 144. Status Register SR2 (0x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 145. SR2 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 146. Status Register SR3 (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 147. SR3 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 148. Status Register SR4 (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 149. SR4 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 150. Status Register SR5 (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 151. SR5 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 152. Status Register SR6 (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
DS11546 Rev 5 11/197
L99DZ100G, L99DZ100GP List of tables
11
Table 153. SR6 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 154. Status Register SR7 (0x37) to SR9 (0x39) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 155. SR7 to SR9 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 156. Status Register SR10 (0x3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 157. SR10 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 158. Status Register SR11 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 159. SR11 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 160. Status Register SR12 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 161. SR12 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 162. LQFP-64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 163. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
List of figures L99DZ100G, L99DZ100GP
12/197 DS11546 Rev 5
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 3. Activation profile 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 4. Activation profile 1 (first cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 5. Activation profile 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 6. Activation profile 2 (first cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 7. LQFP64 package and PCB thermal configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 8. Voltage regulator V1 characteristics (quiescent current and accuracy) . . . . . . . . . . . . . . . 31
Figure 9. Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 10. Watchdog early, late and safe windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 11. H-driver delay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 12. IGHxr ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 13. IGHxf ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 14. LIN transmit, receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 15. SPI – transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 16. SPI input timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 17. SPI output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 18. SPI CSN - output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 19. SPI – CSN high to low transition and global status bit access . . . . . . . . . . . . . . . . . . . . . . 69
Figure 20. Voltage regulator behaviour and diagnosis during supply voltage . . . . . . . . . . . . . . . . . . . 72
Figure 21. Sequence to disable/enable the watchdog in CAN Flash mode . . . . . . . . . . . . . . . . . . . . . 73
Figure 22. NINT pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 23. Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 24. Watchdog in normal operating mode (no errors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 25. Watchdog with error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 26. Watchdog in Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 27. NReset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 28. RxDL pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 29. Wake-up behavior according to LIN 2.2a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 30. RxDC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 31. CAN transceiver state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 32. CAN wake up capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 33. Thermal shutdown protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 34. Example of long auto-recovery on OUT7. Temperature acquisition starts after tAR, thermal
expiration occurs after a T = 30° . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 35. Block diagram of physical realization of AR alert and thermal expiration . . . . . . . . . . . . . 101
Figure 36. Charge pump low filtering and start up implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 37. Software strategy for half bridges before applying auto-recovery mode. . . . . . . . . . . . . . 104
Figure 38. Overcurrent recovery mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 39. H-bridge GSHx slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 40. H-bridge diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 41. H-bridge open-load-detection (no open-load detected) . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 42. H-bridge open-load-detection (open-load detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 43. H-bridge open-load-detection (short to ground detected). . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 44. H-bridge open-load detection (short to VS detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 45. PWMH cross current protection time implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 46. LSx_FSO: low-side driver “passively” turned on, taking supply from output pin (if main supply
fails), can guarantee VLSx_FSO < VOUT_max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
DS11546 Rev 5 13/197
L99DZ100G, L99DZ100GP List of figures
13
Figure 47. Safety concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 48. Heater MOSFET open-load and short-circuit to GND detection . . . . . . . . . . . . . . . . . . . . 113
Figure 49. Electro-chrome control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 50. Thermal clusters identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 51. Block diagram VS compensation (duty cycle adjustment) module . . . . . . . . . . . . . . . . . . 118
Figure 52. Sequential ADC Read Out for VSREG, VS, WU and THCL1 ..THCL6 . . . . . . . . . . . . . . . . 119
Figure 53. SPI pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 54. SDO pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 55. SPI signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 56. SDI Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 57. SDO frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 58. Window watchdog operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 59. Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 60. Timer_x controlled by DIR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 61. Extended ID and extended ID mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 62. LQFP-64 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 63. LQFP-64 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 64. LQFP-64 marking information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Description L99DZ100G, L99DZ100GP
14/197 DS11546 Rev 5
1 Description
The L99DZ100G and L99DZ100GP are door zone systems IC providing electronic control
modules with enhanced power management power supply functionality, including various
standby modes, as well as LIN and HS CAN physical communication layers.
The two low-drop voltage regulators of the devices supply the system microcontroller and
external peripheral loads such as sensors and provide enhanced system standby
functionality with programmable local and remote wake-up capability. In addition 8 high-side
drivers to supply LEDs, 2 high-side drivers to supply bulbs increase the system integration
level.
Up to 5 DC motors and 4 external MOS transistors in H-bridge configuration can be driven.
An additional gate drive can control an external MOSFET in high-side configuration to
supply a resistive load connected to GND (e.g. mirror heater). An electro-chromic mirror
glass can be controlled using the integrated SPI-driven module in conjunction with an
external MOS transistor. All outputs are SC protected and implement an open-load
diagnosis.
The ST standard SPI interface (4.0) allows control and diagnosis of the device and enables
generic software development.
DS11546 Rev 5 15/197
L99DZ100G, L99DZ100GP Block diagram and pin descriptions
196
2 Block diagram and pin descriptions
Figure 1. Block diagram
Table 2. Pin definitions and functions
Pin Symbol Function
1 WU Wake-up Input: Input pin for static or cyclic monitoring of external contacts
2 CP2M Charge pump pin for capacitor 2, negative side
3 CP2P Charge pump pin for capacitor 2, positive side
4 CP Charge pump output
5 CP1P Charge pump pin for capacitor 1, positive side
6 CP1M Charge pump pin for capacitor 1, negative side
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Block diagram and pin descriptions L99DZ100G, L99DZ100GP
16/197 DS11546 Rev 5
7 GHheater Gate driver for external power N-Channel MOSFET in high-side
configuration to control the heater
8 SHheater Source of high-side MOSFET to control the heater
9 OUT14 High-side-driver output to drive LEDs
10 OUT13 High-side-driver output to drive LEDs
11 OUT12 High-side-driver output to drive LEDs
12 OUT9 High-side-driver output to drive LEDs
13 OUT10
High-side-driver-output; Important: Beside the bits OUT10_x (CR 5) this
output can be switched on setting the ECON bit for electro-chrome control
mode with higher priority.
14 OUT11 High-side-driver output to drive LEDs
15 LS1_FSO Fail Safe low-side switch (Active low)
16 LS2_FSO Fail Safe low-side switch (Active low)
17 VS
Power supply voltage for power stage outputs (external reverse battery
protection required), for this input a ceramic capacitor as close as
possible to GND is recommended. Important: For the capability of driving,
the full current at the outputs all pins of VS must be connected externally!
18 VS; 2nd pin Current capability (pin description see above)
19 OUT7 High-side-driver output to drive LEDs or a 10 Watt bulb (programmable
Rdson)
20 OUT6
Half-bridge outputs: the output is built by a high-side and a low-side switch
which are internally connected. The output stage of both switches is a
power DMOS transistor. Each driver has an internal parasitic reverse
diode (bulk-drain-diode: high-side driver from output to VS, low-side driver
from GND to output)
21 OUT1
Half-bridge outputs: the output is built by a high-side and a low-side switch
which are internally connected. The output stage of both switches is a
power DMOS transistor. Each driver has an internal parasitic reverse
diode (bulk-drain-diode: high-side driver from output to VS, low-side driver
from GND to output)
22 OUT2
Half-bridge outputs: the output is built by a high-side and a low-side switch
which are internally connected. The output stage of both switches is a
power DMOS transistor. Each driver has an internal parasitic reverse
diode (bulk-drain-diode: high-side driver from output to VS, low-side driver
from GND to output)
23 OUT5
Half-bridge outputs: the output is built by a high-side and a low-side switch
which are internally connected. The output stage of both switches is a
power DMOS transistor. Each driver has an internal parasitic reverse
diode (bulk-drain-diode: high-side driver from output to VS, low-side driver
from GND to output)
24 OUT5; 2nd pin Current capability (pin description see above)
Table 2. Pin definitions and functions (continued)
Pin Symbol Function
DS11546 Rev 5 17/197
L99DZ100G, L99DZ100GP Block diagram and pin descriptions
196
25 VSREG
Power supply voltage to supply the internal voltage regulators, OUT15
and the OUT_HS (external reverse battery protection required / Diode) for
this input a ceramic capacitor as close as possible to GND and an
electrolytic back up capacitor is recommended.
26 OUT_HS High-side-driver output to drive LEDs or to supply contacts
27 OUT4
Half-bridge outputs: the output is built by a high-side and a low-side switch
which are internally connected. The output stage of both switches is a
power DMOS transistor. Each driver has an internal parasitic reverse
diode (bulk-drain-diode: high-side driver from output to VS, low-side driver
from GND to output)
28 OUT4; 2nd pin Current capability (pin description see above)
29 OUT3
Half-bridge outputs: the output is built by a high-side and a low-side switch
which are internally connected. The output stage of both switches is a
power DMOS transistor. Each driver has an internal parasitic reverse
diode (bulk-drain-diode: high-side driver from output to VS, low-side driver
from GND to output)
30 VS; 3rd pin Current capability (for the pin description see above)
31 OUT15 High-side-driver output to drive LEDs
32 PGND Power GND
33 OUT8 High-side-driver output to drive LEDs or a 5 Watt bulb (programmable
Rdson)
34 ECDR ECDR: using the device in EC control mode this pin is used to control the
gate of an external N-Channel MOSFET
35 SGND Signal Ground
36 CM
Current monitor output: depending on the selected multiplexer bits
CM_SEL_x (CR 7) of the; Control Register this output sources an image
of the instant current; through the corresponding high-side driver with a
fixed ratio
37 ECV
ECV: using the device in EC control mode this pin is used as voltage
monitor input. For fast discharge an additional low-side-switch is
implemented
38 CLK SPI: serial clock input
39 DO SPI: serial data output (push pull output stage)
40 DI SPI: serial data input
41 CSN SPI: chip select not input
42 TxD_L LIN Transmit data input
43 RxD_L/NINT RxDL -> LIN receive data output; NINT -> indicates local/remote wake-up
events (push pull output stage)
44 TxD_C CAN transmit data input
45 RxD_C/NINT CAN receive data output NINT -> indicates local/remote wake-up events
(push pull output stage)
46 DIR1 Direct Drive Input 1
Table 2. Pin definitions and functions (continued)
Pin Symbol Function
Block diagram and pin descriptions L99DZ100G, L99DZ100GP
18/197 DS11546 Rev 5
47 PWMH PWMH input: this input signal can be used to control the H-bridge Gate
Drivers.
48 DIRH Direction Input: this input controls the H-bridge Drivers for the external
MOSFETs
49 DIR2 Direct Drive Input 2
50 NRESET
NReset output to micro controller; (reset state = LOW) (Low-side switch
with drain connected to the output pin and internal pull up resistance to
5V_1)
51 5V_1 Voltage regulator 1 output: 5 V supply e.g. micro controller, CAN
transceiver
52 CAN Supply CAN supply input; to allow external CAN supply from V1 or V2 regulator
53 NINT
Interrupt output (low active; push-pull output stage) to indicate VSREG
early warning (Active mode); indicates wake-up events from V1_standby
mode
54 CAN_L CAN low level voltage I/O
55 CAN_H CAN high level voltage I/O
56 Debug Debug input to deactivate the window watchdog (high active)
57 LIN LIN bus line
58 5V_2 Voltage regulator 2 output: 5 V supply for external loads (potentiometer,
sensors) or CAN Transceiver. V2 is protected against reverse supply
59 GL1 Gate driver for PowerMOS low-side switch in half-bridge 1
60 SH1 Source of high-side switch in half-bridge 1
61 GH1 Gate driver for PowerMOS high-side switch in half-bridge 1
62 GH2 Gate driver for PowerMOS high-side switch in half-bridge 2
63 SH2 Source of high-side switch in half-bridge 2
64 GL2 Gate driver for PowerMOS low-side switch in half-bridge 2
Table 2. Pin definitions and functions (continued)
Pin Symbol Function
DS11546 Rev 5 19/197
L99DZ100G, L99DZ100GP Block diagram and pin descriptions
196
Figure 2. Pin connection (top view)
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Electrical specifications L99DZ100G, L99DZ100GP
20/197 DS11546 Rev 5
3 Electrical specifications
3.1 Absolute maximum ratings
Stressing the device above the rating listed in Table 3 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability
Table 3. Absolute maximum ratings
Symbol Parameter / test condition Value [DC voltage] Unit
VS, VSREG
DC supply voltage / “jump start” -0.3 to +28 V
Load dump -0.3 to +40 V
5V_1 Stabilized supply voltage, logic supply -0.3 to 6.5
V1 < VSREG
V
5V_2(1) Stabilized supply voltage -0.3 to +28(2) V
VDI, VCLK VCSN VDO,
VRXDL/NINT, VRXDC,
VNRESET, VCM, VDIR,
VDIR2, VPWMH,
VDIRH, VINT
Logic input / output voltage range -0.3 to V1+0.3 V
VTXDC, VTXDL Multi Level Inputs -0.3 to 40 V
VDebug Debug input pin voltage range -0.3 to 40 V
VLS1_FSO, VLS2_FSO
Output voltage range of Fail-Safe Low-side
Switches -0.3 to 35 V
VWU
DC Wake up input voltage / “jump start” -0.3 to +28 V
Load dump -0.3 to +40 V
VLIN LIN bus I/O voltage range -20 to +40 V
IInput(3) Current injection into VS related input pins 20 mA
IOUT_INJ(3) Current injection into VS related outputs 20 mA
VCANSUP CAN supply -0.3 to +5.25 V
VCANH, VCANL CAN bus I/O voltage range -27 to +40 V
VCANH - VCANL Differential CAN-Bus Voltage -5 to +10 V
VOUTn, VECDR, VECV,
Vout_HS
Output voltage (n = 1 to 15) -0.3 to VS+0.3 V
VGH1, VGH2 (VGxy) High Voltage Signal Pins VSxy-0.3 to
VSxy+13; VCP+0.3 V
VGL1, VGL2, (VGxy) High Voltage Signal Pins
VSxy-0.3 to
VSxy+13; VCP-0.3V
to +12V; Vcp+0.3V
V
DS11546 Rev 5 21/197
L99DZ100G, L99DZ100GP Electrical specifications
196
VSH1, VSH2 (VSxy)
High Voltage Signal Pins -1 to 40 V
High Voltage Signal Pins; single pulse with
tmax = 200ns -5 to 40 V
VCP1P High Voltage Signal Pins VS-0.3 to VS+14 V
VCP2P High Voltage Signal Pins VS-0.6 to VS+14 V
VCP1M, VCP2M High Voltage Signal Pins -0.3 to VS+0.3 V
VCP
High Voltage Signal Pin VS 26 V VS-0.3 to VS+14 V
High Voltage Signal Pin VS > 26 V VS-0.3 to +40 V
VGH_heater
VSheater -0.3 to
VSheater+13;
VCP+0.3
V
VSH_heater
-0.3 to 40V
Or -0.3 to Vs+0.3 V
ISH_Heater +/-10 mA
IECV, IOUT2, IOUT3,
IOUT9, IOUT10, IOUT11,
IOUT12, IOUT13,
IOUT14, IOUT15,
IOUT_HS
Output current(2)
±1.25 A
IOUT8 ±2.5 A
IOUT7 ±5 A
IOUT1,6 ±5 A
IOUT4,5 ±10 A
IVScum
Maximum cumulated current at VS drawn by
OUT1 & OUT2(2) ±7.5 A
IVScum
Maximum cumulated current at VS drawn by
OUT3, OUT8 & OUT10(2) ±2.5 A
IVScum
Maximum cumulated current at VS drawn by
OUT4(2) ±10 A
IVScum
Maximum cumulated current at VS drawn by
OUT5(2) ±10 A
IVScum
Maximum cumulated current at VS drawn by
OUT6 & OUT7(2) ±7.5 A
IVScum
Maximum cumulated current at VS drawn by
OUT9, OUT11, OUT12, OUT13, OUT14,
OUT15 and CP
±2.5 A
IVSREG
Maximum current at VSREG pin (2) (5V_1. 5V_2
and OUT_HS) ±2.5 A
IPGNDcum
Maximum cumulated current at PGND drawn
by OUT1 & OUT6(2) ±7.5 A
Table 3. Absolute maximum ratings (continued)
Symbol Parameter / test condition Value [DC voltage] Unit
Electrical specifications L99DZ100G, L99DZ100GP
22/197 DS11546 Rev 5
Note: All maximum ratings are absolute ratings. Leaving the limitation of any of these values may
cause an irreversible damage of the integrated circuit!
Note: Loss of ground or ground shift with externally grounded loads: ESD structures are
configured for nominal currents only. If external loads are connected to different grounds,
the current load must be limited to this nominal current.
3.2 ESD protection
IPGNDcum
Maximum cumulated current at PGND drawn
by OUT2 & OUT5(2) ±12.5 A
IPGNDcum
Maximum cumulated current at PGND drawn
by OUT3, OUT4 & ECV(2) ±12.5 A
ISGND Maximum current at SGND(2) ±1.25 A
GND pins PGND versus SGND -0.3 to 0.3 V
1. 5V_2 is robust against SC to 28 V only in case VSREG is supplied.
2. Values for the absolute maximum DC current through the bond wires. This value does not consider
maximum power dissipation or other limits.
3. Guaranteed by design.
Table 3. Absolute maximum ratings (continued)
Symbol Parameter / test condition Value [DC voltage] Unit
Table 4. ESD protection
Parameter Value Unit
All pins(1)
1. HBM (human body model, 100 pF, 1.5 k) according to MIL 883C, Method 3015.7 or EIA/JESD22A114-A.
+/-2 kV
All power output pins (2): OUT1 – OUT15, OUT_HS, ECV +/-4 kV
LIN
+/-8(2)
+/-9(3) (4)
+/-6(5)
2. HBM with all none zapped pins grounded.
3. Indirect ESD Test according to IEC 61000-4-2 (150 pF, 330 ) and ‘Hardware Requirements for LIN, CAN
and Flexray Interfaces in Automotive Applications’ (version 1.3, 2012-05-04).
4. Value has been verified by an external test house; the result was equal or better than minimum
requirement.
5. Direct ESD Test according to IEC 61000-4-2 (150 pF, 330 ) and ‘Hardware Requirements for LIN, CAN
and Flexray Interfaces in Automotive Applications’ (version 1.3, 2012-05-04).
kV
CAN_H, CAN_L +/-8(2)
+/-6(5) (4) kV
All pins(6)
6. Charged device model.
+/-500 V
Corner pins(6) +/-750 V
All pins(7)
7. Machine model; C = 220 pF, R = 0 .
+/- 200 V
DS11546 Rev 5 23/197
L99DZ100G, L99DZ100GP Electrical specifications
196
3.3 Thermal data
All parameters are guaranteed in the junction temperature range -40 to 150°C (unless
otherwise specified); the device is still operative and functional at higher temperatures (up to
175°C).
Note: Parameters limits at higher junction temperatures than 150°C may change respect to what
is specified as per the standard temperature range.
Note: Device functionality at high junction temperature is guaranteed by characterization.
3.3.1 LQFP64 thermal data
Devices belonging to L99DZxxx family embed a multitude of junctions (i.e. Outputs based
on a PowerMOSFET stage) housed in a relatively small piece of silicon. The devices
contain, among all the described features, 6 Half-bridges (12 N-Channel PowerMOS), 10
high-sides and two voltage regulators; all the other derivatives, even if smaller than the
family super set device, still contain a significant number of junctions.
For this reason, using the Thermal Impedance of a single junction (i.e. voltage regulator or
major power dissipation contributor) does not allow to predict thermal behavior of the whole
device and therefore it is not possible to assess if a device is thermally suitable for a given
activation profile and loads characteristics.
Thermal information is provided as temperature reading by different clusters placed close to
the most dissipative junctions.
Some representative and realistic worst-case thermal profiles are described in the below
paragraph.
Following measurement methods can be easily implemented, by final user, for a specific
activation profile.
Table 5. Operating junction temperature
Symbol Parameter Value Unit
TjOperating junction temperature -40 to 175 °C
Table 6. Temperature warning and thermal shutdown
Symbol Parameter Min. Typ. Max. Unit
TWThermal overtemperature warning threshold Tj(1)
1. Non-overlapping.
140 150 160 °C
TSD1 Thermal shutdown junction temperature 1
Tj(1)
Cluster 1-4
Cluster 5-6
165
165
175
175
185
190
°C
TSD2 Thermal shutdown junction temperature 2
Tj(1) 175 185 195 °C
TSD12hys Hysteresis 5 °C
Tjtft Thermal warning / shutdown filter time 32 µs
Electrical specifications L99DZ100G, L99DZ100GP
24/197 DS11546 Rev 5
L99DZ100G and L99DZ100GP thermal profiles
Profile 1
Battery Voltage: 16V, Ambient temperature start: 85°C
DC activation
V1 charged with 70 mA (DC activation)
V2 charged with 30 mA (DC activation)
OUT7: 1 x10W bulb (DC activation)
OUT8: 1 x 5W bulb (DC activation)
OUT11: 300 resistor (DC activation)
OUT12: 300 resistor (DC activation)
OUT13: 300 resistor (DC activation)
OUT14: 300 resistor (DC activation)
Cyclic activation
OUT4 – OUT5: 3,3 resistor placed across those outputs
– 10 activations of Lock/Un-lock (250 ms ON Lock; 500 ms wait; 250 ms ON Un-
lock unlock; 500 ms wait)
OUT5 – OUT6: 10 resistor placed across those outputs
– (250 ms ON Safe Lock; 500 ms wait; 250 ms ON Safe unlock; 500 ms wait)
Test execution:
Once thermal equilibrium is reached with all DC load active, the “Cyclic Activation”
sequence is applied.
Temperature reading is logged just at the end of the whole sequence.
Figure 3. Activation profile 1
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