TS3000GB0A0NCG8 - IDT - Datasheet.Directory

1 of 25 November 4, 2014

 2014 Integrated Device Technology, Inc. DSC 7332/8

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Description

The TS3000GB0A0 digital temperature sensor with accuracy up to

±0.5°C was designed to target applications demanding highest level of

temperature readout. The sensor is fully compliant with JEDEC JC42.4

Component Specification.

The digital temperature sensor comes with several user-programmable

registers to provide maximum flexibility for temperature-sensing

applications. The registers allow specifying critical, upper, and lower

temperature limits as well as hysteresis settings. Both the limits and

hysteresis values are used for communicating temperature events from

the chip to the system. This communication is done using the Event pin,

which has an open-drain configuration. The user has the option of setting

the Event pin polarity as either an active-low or active-high comparator

output for thermostat operation, or as a temperature event interrupt

output for microprocessor-based systems.

The sensor uses an industry standard 2-wire, I2C/SMBus serial

interface, and allows up to eight devices to be controlled on the bus.

Typical Server or Laptop Applications

Total Number of

Sensors is Application

Dependent

Thermal

Controller

Board

management

Controller

Any other

I2C/SMBus

Master Device

MCH

Local

Temperature

Sensor

EVENT

Local

Temperature

Sensor

SMBus

EVENT

SMBus

Features

•Temperature Sensor

•Single Supply: 1.7V to 1.9V

•Accurate timeout support

- Meets strict SMBus spec of 25ms (min) 35ms (max)

•Timeout supported in all Modes

– Active mode

– Shutdown mode

•Schmitt trigger and noise filtering on bus inputs

•2-wire Serial Interface: 10-400 kHz I2C™ /SMBus™

•Available Package: TDFN-8

Temperature Sensor Features

•Temperature Converted to Digital Data

•Sampling Rate of 100ms (max)

•Selectable 0, 1.5°C, 3°C, 6°C Hysteresis

•Programmable Resolution from 0.0625°C to 0.5°C

•Accuracy:

– ±0.5°C/ ±1.0°C (typ/max)from +75°C to +95°C

– ±1.0°C/±2.0°C (typ/max) from +40°C to +125°C

– ±2.0°C/ ±3.0°C (typ/max) from -40°C to +125°C

Typical Applications

•SSD Boards

•Servers, Laptops, Ultra-portables, PC Boards

•High end audio / video equipment

•Portable devices

•Hard Disk Drives and Other PC Peripherals

TS3000GB0A0

Data Sheet

1.8V Local Temperature

Sensor

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Block Diagram: Temperature Sensor

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Maximum Ratings

Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress

ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not

implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings

DC and AC Parameters

This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC

and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables.

Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. DC

Characteristics

Operating Conditions

Symbol Parameter Min. Max. Units

TSTG Storage Temperature -65 150 C

VIO Input or output range, SA0 -0.50 10 V

Input or output range, other pins -0.50 4.3 V

VDD Supply Voltage -0.5 4.3 V

Symbol Parameter Min. Max. Units

VDD Supply Voltage 1.7 1.9 V

TAAmbient operating tem perat ure -40 +125 C

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AC Measurement Conditions

AC Measurement I/O Waveform

Input Parameters for the TS3000GB0A0

1.TA=25°C, f=400 kHz

2.Verified by design and characterization not necessarily tested on all devices

Symbol Parameter Min. Max. Units

CLLoad capacitance 100 pF

Input rise and fall times 50 ns

Input levels 0.2*VDD to 0.8*VDD V

Input and output timing referen ce levels 0.3*VDDto 0.7*VDD V

Symbol Parameter1,2 Test Condition Min. Max. Units

CIN Input capacitance (SDA) 8 pF

CIN Input rise and fall times 6 ns

ZEIL Ei (SA0,SA1,SA2) input impedance VIN< 0.3* VDD 30 k

ZEIH Ei (SA0,SA1,SA2) input impedance VIN> 0.7* VDD 800 k

tSP Pulse width ignored (input filter on

SCL and SDA) Single glitch, f < 100 KHz 100 ns

Single glitch, f> 100 KHz 50

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DC Characteristics

Parameter Symbol Conditions Min. Max. Units

Input Leakage Current ILI VIN = VSS or VDD ±1 A

Output Leakage Current ILO VOUT = VSS or VDD,

SDA in Hi-Z ±1 A

Supply Current, temp sensor active IDD VDDSPD = 1.8 V, fC = 100 kHz

(rise/fall time < 30 ns) 500 A

Standby(Shutdown) Supply Current IDD1 VIN = VSS or VDD,

VDD= 1.9 V 40 A

Input Low Voltage (SCL, SDA) VIL -0.5 0.3*VDD V

Input High Voltage (SCL, SDA) VIH 0.7* VDD VDD +1 V

SA0 High Voltage VHV VHV - VDD > 4.8 V 7 10 V

Output Low Voltage VOL IOL = 2.1 mA,

1.7V =< VDD =< 1.9 V 0.4 V

IOL = 0.7 mA,

VDD = 1.7 - 1.9V 0.2 V

Input hysteresis VHYST VDD> 2.2V 0.05*VDD __ V

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AC Characteristics

1. For a RESTART condition, or following a write cycle.

2. Guaranteed by design and characterization, not necessarily tested.

3. To avoid spurious START and STOP conditions, a minimum delay is placed between falling edge of SCL and the falling or

rising edge of SDA.

4. The TS3000GB0A0 does not initiate clock stretchin g which is an optional I2C bus feature

5. Devices participating in a transfer can abort the transfer in progress and release the bus when any single clock low interval

exceeds the value of tTIMEOUT,MIN. After the master in a transaction detect s this condi tio n, it must gen erate a stop condition

within or after the current data byte in the transfer process. Devices that have detected this condition must reset their

communication and be able to receive a new START condition no later than tTIMEOUT,MAX. Typical device examples include

the host controller and embedded controller and most devices that can master the SMBus. Some devices do not contain a clock

low drive circuit; this simple kind of device typically may reset its comm unications port after a start or stop cond ition. A

timeout conditio n can only be ensured if the device that is forcing the timeout holds SCL low for t TIMEOUT,MAX or longer.

6. The temperature sensor family of devices are not required to support the SMBus ALERT function.

Parameter3,6 Symbol

VDD > 1.7 V

UnitsMin. Max.

Clock Frequency fSCL 10 400 kHz

Clock Pulse Width High Time tHIGH 600 ns

Clock Pulse Width Low Time tLOW41300 ns

Detect clock low timeout, Capabilities

SDA Rise Time tR220 300 ns

SDA Fall Time tF220 300 ns

Data In Setup Time tSU:DAT 100 ns

Data In Hold Time tHD:DI 0ns

Data Out Hold Time tHD:DAT 200 900 ns

Start Condition Setup Tim e tSU:STA1600 ns

Start Condition Hold Time tHD:STA 600 ns

Stop Condition Setup Time tSU:STO 600 ns

Time Between Stop Condition and Next

Start Condition tBUF 1300 ns

Write Time tW4.5 ms

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Temperature-to-Digital Conversion Performance

1VDDSPDMIN < VDDSPD < VDDSPDMAX.

Temperature Conversion Time

Parameter Typ Max Unit Test Conditions1

Temperature Sensor Accuracy ±0.5 ±1.0 °C 75°C < TA < 95°C

±1.0 ±2.0 °C 40°C < TA < 125°C

±2.0 ±3.0 °C -40°C < TA < 125°C

Resolution ADC Setting tCONV (typ) tCONV (Max) Unit

0.5°C 9 bit 100 ms

0.25°C 10 bit 100 ms

0.125°C (POR default) 11 bit 100 ms

0.0625°C 12 bit 100 ms

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Pin Assignment

Pin Description

Pin Functional Descriptions

Serial Clock (SCL)

This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus

to a slower clock, the bus master must have an open drain output, and a pull-up resistor can be connected from Serial Clock (SCL) to VDD. (refer to

the Maximum RL Value vs. Bus Capacitance figure on how the value of the pull-up resistor can be calculated). In most applications, though, this

method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than

open drain) output.

Serial Data (SDA)

This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-ORed with other open drain or

open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to the most positive V DD in the I2C chain. (refer to the

Maximum RL Value vs. Bus Capacitance figure on how the value of the pull-up resistor can be calculated).

Pin # Pin Name Definition

1 SA0 Select Address 0

2 SA1 Select Address 1

3 SA2 Select Address 2

SS Ground

5SDASerial Data In

6 SCL Serial Clock In

7 EVENT Temperature Event Out

DD Supply Voltage

SA0

SA1

SA2

VSS

VDD

EVENT

SCL

SDA

8SA0

SA1

SA2

VSS

VDD

EVENT

SCL

SDA

8SA0

SA1

SA2

VSS

VDD

EVENT

SCL

SDA

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Maximum RL Value vs. Bus Capacitance (CBUS) for an I2C Bus

Select Address (SA0, SA1, SA2)

These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Slave Address. In the

end application, SA0, SA1 and SA2 must be directly (not through a pull-up or pull-down resistor) connected to VDD or VSS to establish the Slave

Address. When these inputs are not connected, an internal pull-down circuitry makes (SA0, SA1, SA2) = (0, 0, 0).

EVENT

The TS3000GB0A0 EVENT pin is an open drain output that requires a pull-up to VDD on the system motherboard or integrated into the master

controller. The TS3000GB0A0 EVENT pin has three operating modes, depending on configuration settings and any current out-of-limit conditions.

These modes are Interrupt, Comparator, or TCRIT Only.

In Interrupt Mode the EVENT pin will remain asserted until it is released by writing a '1' to the “Clear Event” bit in the Status Register. The value to

write is independent of the EVENT polarity bit.

In Comparator Mode the EVENT pin will clear itself when the error condition that caused the pin to be asserted is removed. When the temperature

is compared against the TCRIT limit, then this mode is always used.

Finally, in the TCRIT Only Mode the EVENT pin will only be asserted if the measured tempe rature exceeds the TCRIT Limit. Once the pin has been

asserted, it will remain asserted until the temperature drops below the TCRIT Limit minus the TCRIT hysteresis. The next figure illustrates the opera-

tion of the different modes over time and temperature.

Systems that use the active high mode for EVENT must be wired point to point between the TS3000GB0A0 and the sensing controller. Wire-OR

configurations should not be used with active high EVENT since any device pulling the EVENT signal low will mask the other devices on the bus. Also

note that the normal state of EVENT in active high mode is a 0 which will continually draw power through the pull-up resistor.

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EVENT Pin Mode Functionality

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Serial Communications

The TS3000GB0A0 temperature sensor circuitry continuously monitors the temperature and updates the temperature data minimum of eight times

per second. Temperature data is latched internally by the device and may be read by software from the bus host at any time.

Internal registers are used to configure both the TS performance and response to over-temperature conditions. The device contains programmable

high, low , and critical temperature limits. Finally, the device EVENT pin can be configured as active high or active low and can be configured to operate

as an interrupt or as a comparator output.

Device Diagram

SMBus/I2C Communications

The data registers in this device are selected by the Pointer Register. At power-up the Pointer Register is set to “00”, the location for the Capability

Register. The Pointer Register latches the last location it was set to. Each data register falls into one of three types of user accessibility:

1. Read only

2. Write only

3. Write/Read same address

A Write to this device will always include the address byte and the pointer byte. A write to any register, other than the pointer register, requires two

data bytes.

Reading this device can take place either of two ways:

If the location latched in the Pointer Register is correct (most of the time it is expected that the Pointer Register will point to one of the Read

Temperature Registers because that will be the data most frequently read), then the read can simply consist of an address byte, followed by retrieving

the two data bytes.

If the Pointer Register needs to be set, then an address byte, pointer byte, repeat start, and another address byte will accomplish a read.

The data byte has the most significant bit first. At the end of a read, this device can accept either Acknowledge (Ack) or No Acknowledge (No Ack)

from the Master (No Acknowledge is typically used as a signal for the slave that the Master has read its last byte).

SA0

SA1

SA2

VDD

VSS

EVENT

SCL SDA

SA0

SA1

SA2

VDD

VSS

EVENT

SCL SDA

TS3000GB0A0

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SMBus/I2C write to the pointer register

SMBus/I2C write to the pointer register followed by a write data word

SMBus/I2C word read from register with a preset pointer

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SMBus/I2C write to pointer register followed by a repeat start and an immediate data word read

SMBus/I2C write to the Configu rat io n Re gi st er to Enabl e Sh ut d own ((SHD N ) <0 00 0 00 01 00 00 00 00 >b

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SMBus/I2C Slave Sub-Address Decoding

The physical address for TS is different than that used by current SPD devices. The physical address for thermal sensor is “0 0 1 1 A2 A1 A0 RW”

in binary, where A2, A1, A0 are the three slave sub-address pins, and the least significant bit “RW” is the Read/Write flag.

Assuming the slave base address of the SPD+TS interface is fixed, for example at 0x30, then the pins set the sub-address bits of the slave

address, allowing the device to be located anywhere within 8 slave address locations, for example from 0x30 to 0x3E.

Slave Address Decoding

The meaning of the A0/A1/A2 pin states is as follows:; 0= Pull-down to Thermal Sensor Vss, 1=Pull-up to Thermal Sensor VDD

Slave Address A2 A1 A0

x0 0 0 0

x2 0 0 1

x4 0 1 0

x6 0 1 1

x8 1 0 0

xA 1 0 1

xC 1 1 0

xE 1 1 1

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SMBus/I2 AC Timing Consideration

In order for this device to be both SMBus and I2C compliant, the device complies with a subset of each specification. This requires a few minor

considerations to ensure interoperability. The time out requirements of SMBus are optional for this device. The minimum clock frequency of SMBus is

a required feature. Note that the minimum data hold time (THD:DAT) of 200 ns is smaller than the 300 ns of the SMBus specification. With these minor

considerations, this device is capable of co-existing with devices on either an SMBus or an I2C bus.

TS Register Set Definition

The register set address are shown in the Acknowledge When Writing Data or Defining Write Protection table. These values are used in the I2C

operations as the “REG_PTR” as shown in previous figures.

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Temperature Register Addresses

Capabilities Register

The Capabilities Register indicates the supported features of the temperature sensor.

Capabilities Register

Bits 15 - Bit 8 – RFU; Reserved for future use. These bits will always read '0' and writing to them will have no affect.

Bit 7- EVSD-EVENT with Shutdown action.

‘0’ - (default) The EVENT output freezes in its current state when entering shutdown. Upon exiting shutdown, the EVENT output remains in the

previous state until the next thermal sample is taken, or possibly sooner if EVENT is programmed for comparator mode.

‘1’ The EVENT output is deasserted (not driven) when entering shutdown and remains deasserted upon exit from shutdown until the next thermal

sample is taken, or possibly sooner if EVENT is programmed for comparator mode.

Bit 6 - TMOUT – Bus timeout period for thermal sensor access during normal operation. Note that the TS3000GB0A0 supports timeout in both

active and shutdown mode for temperature sensor and SPD (EEPROM) portions of the device.

‘0’ - Parameter tTIMEOUT is supported within the range of 10 to 60 ms.

‘1’ - (default) Parameter tTIMEOUT is supported within the range of 25 to 35 ms (SMBus compatible).

Bit 5 - X – May be 0 or 1; applications must accept either code. (Default =1)

Bits 4 - 3 – TRES[1:0]; Indicates the resolution of the temperature monitor as shown in the TRES Bit Decode table. (Default =01)

ADDR R/W Name Function Default

N/A W Address Pointer Address storage for subsequent operatio ns 00

00 R Capabilities Indicates the functions and capabilities of the

temperature sensor 0077

01 R/W Configuration Controls the operation of the temperature monitor 0000

02 R/W High Limit Temperature High Limit 0000

03 R/W Low Limit Temperature Low Li mit 0000

04 R/W TCRIT Limit Critical Temperature 0000

05 R Ambient Temperature Current Ambient temperature N/A

06 R Manufacturer ID PCI-SIG manufacturer ID 00B3

07 R Device/Revision Device ID and Revision number 2913

08 R/W R esolution Register Allows changing temperature sensor resolution 0010

ADDR R/W B15/B7 B14/B6 B13/B5 B12/B4 B11/B3 B10/B2 B9/B1 B8/B0 Default

00 R RFU RFU RFU RFU RFU RFU RFU RFU 0077

EVSD TMOUT X TRES[1:0] RANGE ACC EVENT

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TRES Bit Decode

Note: Refer to section Resolution Register on page 22.

Bit 2 - RANGE; Indicates the supported temperature range.

'0' - The temperature monitor clamps values lower than 0 °C.

'1' (default) - The temperature monitor can read temperatures below 0 °C and sets the sign bit appropriately.

Bit 1 - ACC; Indicates the supported temperature accuracy.

'0' - Not used.

'1' (default) The temperature monitor has ±1 °C accuracy over the active range (75°C to 95°C) and ±2°C accuracy over the monitoring range

(40°C to 125°C)

Bit 0 - EVENT; Indicates whether the temperature monitor supports interrupt capabilities

'0'.-The device does not support interrupt capabilities.

'1' (default); The device supports interrupt capabilities.

Configuration Register

The Configuration Register holds the control and status bits of the EVENT pin as well as general hysteresis on all limits.

Bits 15 - 11 – RFU; Reserved for future use. These bits will always read '0' and writing to them will have no affect. For future compatibility, all RFU

bits must be programmed as '0'.

Bits 10 - 9 – HYST[1:0]; Control the hysteresis that is applied to all limits as shown in the HYST Bit Decode table that follows. This hysteresis

applies to all limits when the temperature is dropping below the threshold so that once the temperature is above a given threshold, it must drop below

the threshold minus the hysteresis in order to be flagged as an interrupt event. Note that hysteresis is also applied to EV ENT pin functionality. When

either of the lock bits is set, these bits cannot be altered.

TRES[1:0] Temperature Resolution

0 0 0.5°C (9-bit)

0 1 0.25°C (10-bit)

1 0 0.125°C (11-bit) (default)

1 1 0.0625°C (12-bit)

ADDR R/W B15/B7 B14/B6 B13/B5 B12/B4 B11/B3 B10/B2 B9/B1 B8/B0 Default

01 R/W

RFU RFU RFU RFU RFU HYST[1:0] SHDN

0000

TCRIT_

LOCK EVENT_

LOCK CLEAR EVENT_

STS EVENT_

CTRL TCRIT_

ONLY EVENT_

POL EVENT_

MODE

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Hysteresis

TU= Value stored in Alarm Temperature Upper Boundary Trip Register

TL=Value stored in Alarm Temperature Lower Boundary Trip Register

Hyst= Absolute value of selected hysteresis

HYST Bit Decode

Bit 8 – SHDN-Shutdown. The thermal sensing device and A/D converters are disabled to save power, no events will be generated. When either of

the lock bits is set, this bit cannot be set until unlocked. However it can be cleared at any time. When in shutdown mode, the TS3000GB0A0 still

responds to commands normally, however bus timeout may or may not be supported in this mode.

'0' (default); The temperature monitor is active and converting

'1'; The temperature monitor is disabled and wi ll not generate interrupts or update the temperature data.

Bit 7 – TCRIT_LOCK; Locks the TCRIT Limit Register from being updated.

'0' (default; The TCRIT Limit Register can be updated normally.

'1'; The TCRIT Limit Register is locked and cannot be updated. Once this bit has been set, it cannot be cleared until an internal

power on reset.

HYST[1:0] Hysteresis

0 0 Disable hysteresis (default)

0 1 1.5°C

1 0 3°C

1 1 6°C

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Bit 6 – EVENT_LOCK; Locks the High and Low Limit Registers from being updated.

'0' (default); The High and Low Limit Registers can be upda t e d no rmally.

'1'; The High and Low Limit Registers are locked and cannot be updated. Once this bit has been set, it cannot be cleared until

an internal power on reset.

Bit 5 – CLEAR; Clears the EVENT pin when it has been asserted. This bit is write only and will always read '0'.

'0'; does nothing

'1'; The EVENT pin is released and will not be asserted until a new interrupt condition occurs. This bit is ignored if the device

is operating in Comparator Mode. This bit is self clearing.

Bit 4 – EVENT_STS; Indicates if the EVENT pin is asserted. This bit is read only.

‘0' (default); The EVENT pin is not asserted.

'1'; The EVENT pin is being asserted by the device.

Bit 3 – EVENT_CTRL; Masks the EVENT pin from generating an interrupt. If either of the lock bits are set (bit 7 and bit 6), then this bit cannot be

altered.

'0' (default); The EVENT pin is disabled and will not generate interrupts.

'1'; The EVENT pin is enabled.

Bit 2 – TCRIT_ONLY; Controls whether the EVE NT pin will be asserted from a high / low out-of-lim it condition. When the EVENT_LOCK bit is set,

this bit cannot be altered.

'0' (default); The EVENT pin will be asserted if the measured temperature is above the High Limit or below the Low Limit in

addition to if the temperature is above the TCRIT Limit.

'1'; The EVENT pin will only be asserted if the measured temperature is above the TCRIT Limit.

Bit 1 – EVENT_POL; Controls the “active” state of the EVENT pin. The EVENT pin is driven to this state when it is asserted.

'0' (default); The EVENT pin is active low. The “active” state of the pin will be logical '0'.

'1'; The EVENT pin is active high. The “active” state of the pin will be logical '1'.

Bit 0 – EVENT_MODE; Controls the behavior of the EVENT pin. The EVENT pin may function in either comparator or interrupt mode.

'0'; The EVENT pin will function in comparator mode.

'1'; The EVENT pin will functio n in int e rrupt m ode.

Temperature Register Value Definitions

Temperatures in the High Limit Register, Low Limit Register, TCRIT Register, and Temperature Data Register are expressed in two's complement

format. Bits B12 through B2 for each of these registers are defined for all device resolutions as defined in the TRES field of the Capabilities Register,

hence a 0.25°C minimum granularity is supported in all registers. Examples of valid settings and interpretation of temperature register bits:

Temperature Register Coding Examples

B15~B0 (binary) Value Units

xxx0 0000 0010 11xx +2.75 °C

xxx0 0000 0001 00xx +1.00 °C

xxx0 0000 0000 01xx +0.25 °C

xxx0 0000 0000 00xx 0 °C

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The TRES field of the Capabilities Register optionally defines higher resolution devices. For compatibility and simplicity, this additional resolution

affects only the Temperature Data Register but none of the Limit Registers. When higher resolution devices generate status or EVENT changes, only

bits B12 through B2 are used in the comparison; however, all 11 bits (TRES[1-0] = 10) or all 12 bits (TRES[1-0] = 11) are visible in reads from the

Temperature Data Register.

When a lower resolution device is indicated in the Capabilities Register (TRES[1-0] = 00), the finest resolution supported is 0.5°C. When this is

detected, bit 2 of all Limit Registers should be programmed to 0 to assure correct operation of the temperature comparators.

High Limit Register

The temperature limit registers (High, Low, and TCRIT) define the temperatures to be used by various on-chip comparators to determine device

temperature status and thermal EVENTs. For future compatibility, unused bits “-” must be programmed as 0.

High Limit Register

The High Limit Register holds the High Limit for the nominal operating window. When the temperature rises above the High Limit, or drops below or

equal to the High Limit, then the EVENT pin is asserted (if enabled). If the EVENT_LOCK bit is set as shown in the Configuration Register table), then

this register becomes read-only.

Low Limit Register

The Low Limit Register holds the lower limit for the nominal operating window . When the temperature drops below the Low Limit or rises up to meet

or exceed the Low Limit, then the EVENT pin is asserted (if enabled). If the EVENT_LOCK bit is set as shown in the Configuration Register, then this

xxx1 1111 1111 11x x -0.2 5 °C

xxx1 1111 1111 00xx -1.00 °C

xxx1 111 1 1101 01xx -2.75 °C

ADDR R/W B15/B7 B14/B6 B13/B5 B12/B4 B11/B3 B10/B2 B9/B1 B8/B0 Default

02 R/W – – – Sign 128 64 32 16 0000

8 4 2 1 0.5 0.25 – –

ADDR R/W B15/B7 B14/B6 B13/B5 B12/B4 B11/B3 B10/B2 B9/B1 B8/B0 Default

03 R/W – – – Sign 128 64 32 16 0000

8 4 2 1 0.5 0.25 – –

Temperature Register Coding Examples

B15~B0 (binary) Value Units

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TCRIT Limit Register

The TCRIT Limit Register holds the TCRIT Limit. If the temperature exceeds the limit, the EVENT pin will be asserted. It will remain asserted until

the temperature drops below or equal to the limit minus hysteresis. If the TCRIT_LOCK bit is set as shown in the Configuration Register table, then

this register becomes read-only.

Temperature Data Register

* Resolution defined based on value of TRES field of the Capabilities Register. Unused/unsupported bits will read as 0.

The Temperature Data Register holds the 10-bit + sign data for the internal temperature measurement as well as the status bits indicating which

error conditions, if any, are active. The encoding of bits B 12 through B0 is the same as for the temperature limit registers.

Bit 15 – TCRIT; When set, the temperature is above the TCRIT Limit. This bit will remain set so long as the temperature is above TCRIT and will

automatically clear once the temperature has dropped below the limit minus the hysteresis.

Bit 14 – HIGH; When set, the temperature is above the High Limit. This bit will remain set so long as the temperature is above the HIGH limit. Once

set, it will only be cleared when the temperature drops below or equal to the HIGH Limit minus the hysteresis.

Bit 13 – LOW; When set, the temperature is below the Low Limit. This bit will remain set so long as the temperature is below the Low Limit minus

the hysteresis. Once set, it will only be cleared when the temperature meets or exceeds the Low Limit.

Manufacturer ID Register

The Manufacturer ID Register holds the PCI SIG number assigned to the specific manufacturer.

Device ID/Revision Register

The upper byte of the Device ID / Revision Register stores a unique number indicating the TS3000GB0A0 from other devices.

The lower byte holds the revision value.

ADDR R/W B15/B7 B14/B6 B13/B5 B12/B4 B11/B3 B10/B2 B9/B1 B8/B0 Default

04 R/W – – – Sign 128 64 32 16 0000

8 4 2 1 0.5 0.25 – –

ADDR R/W B15/B7 B14/B6 B13/B5 B12/B4 B11/B3 B10/B2 B9/B1 B8/B0 Default

05 R TCRIT HIGH LOW Sign 128 64 32 16 N/A (0000)

8 4 2 1 0.5 0.25* 0.125* 0.0625*

ADDR R/W B15/B7 B14/B6 B13/B5 B12/B4 B11/B3 B10/B2 B9/B1 B8/B0 Default

06 R/W 00000 0 00

00B3

10110 0 11

ADDR R/W B15/B7 B14/B6 B13/B5 B12/B4 B11/B3 B10/B2 B9/B1 B8/B0 Default

07 R/W 00101 0 01

2913

00010 0 10

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Resolution Register

This register allows the user to change the resolution of the temperature sensor. The POR default resolution is 0.125°C. The resolution imple-

mented via this register is also reflected in the capability register.

Resolution Register

Legend:

Resolution bi ts 4 -3 TRES[4:3]

00 = LSB = 0.5°C (register value = 0007)

01 = LSB = 0.25°C (register value = 000F)

10 = LSB = 0.125°C (register value = 0017)

11 = LSB = 0.0625°C (register value = 001F)

Conversion times for each resolution are less than 100ms (worst case).

ADDR R/W B15/B7 B14/B6 B13/B5 B12/B4 B11/B3 B10/B2 B9/B1 B8/B0 Default

Value

08hR/W000000000010

0 0 0 TRES[1] TRES[0] 0 0 0

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IDT

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IDT

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for SALES:

800-345-7015 or 408-284-8200

fax: 408-284-2775

www.idt.com

for Tech Support:

email: memorymodule-help@idt.com

phone: 408-284-8208

Ordering Information

Example: TS3000GB0A0 NCG8

XXXXX XX

Rev.

Voltage Shipping

8Tape and Reel

Device Type

3000G Temperature Sensor

Temp

BTemperature Accuracy Grade

Carrier

Range

XXX

Package

NCG Green TDFN (2.0 x 3.0mm body, 0.75mm thick)

(1.7V to 1.9V)