Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPS7A33 SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 TPS7A33 -36-V, 1-A, Ultralow-Noise Negative Voltage Regulator 1 Features 3 Description * * The TPS7A33 series of linear regulators are negative voltage (-36 V), ultralow-noise (16-VRMS, 72-dB PSRR) linear regulators capable of sourcing a maximum load of 1 A. 1 * * * * * * * Input Voltage Range: -3 V to -36 V Noise: - 16 VRMS (10 Hz to 100 kHz) Power-Supply Ripple Rejection: - 72 dB (10 kHz) Adjustable Output: -1.18 V to -33 V Maximum Output Current: 1 A Stable With Ceramic Capacitors 10 F Built-In Current-Limit and Thermal Shutdown Protection Available in an External Heatsink-Capable, High Thermal Performance TO-220 Package Operating Temperature Range: -40C to 125C The TPS7A33 series include a complementary metal oxide semiconductor (CMOS) logic-level-compatible enable pin (EN) to allow for user-customizable power management schemes. Other features available include built-in current limit and thermal shutdown features to protect the device and system during fault conditions. The TPS7A33 family is designed using bipolar technology primarily for high-accuracy, high-precision instrumentation applications, where clean voltage rails are critical to maximize system performance. This feature makes it ideal to power operational amplifiers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other highperformance analog circuitry. 2 Applications * * * * * * * * Supply Rails for Operational Amplifiers, DACs, ADCs, and Other High-Precision Analog Circuitry Audio Post DC-DC Converter Regulation and Ripple Filtering Test and Measurement Medical Industrial Instrumentation Base Stations and Telecom Infrastructure 12-V and 24-V Industrial Buses In addition, the TPS7A33 family of linear regulators is suitable for post DC-DC converter regulation. By filtering out the output voltage ripple inherent to DCDC switching conversion, maximum system performance is ensured in sensitive instrumentation, medical, test and measurement, audio, and RF applications. For applications where positive and negative highperformance rails are required, consider the TPS7A4700 positive high-voltage, ultralow-noise, lowdropout linear regulator as well. Device Information(1) PART NUMBER TPS7A33 PACKAGE BODY SIZE (NOM) TO-220 (7) 10.17 mm x 8.38 mm VQFN (20) 5.00 mm x 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Schematic TPS7A47xx RF LDO Amplifier TPS7A33 Negative-Voltage Regulator 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS7A33 SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 5 6.1 6.2 6.3 6.4 6.5 6.6 5 5 5 5 6 7 Absolute Maximum Ratings ..................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 12 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 12 12 12 14 8 Application and Implementation ........................ 15 8.1 Application Information............................................ 15 8.2 Typical Application .................................................. 18 8.3 Do's and Don'ts....................................................... 20 9 Power Supply Recommendations...................... 21 10 Layout................................................................... 21 10.1 10.2 10.3 10.4 Layout Guidelines ................................................. 21 Layout Example .................................................... 21 Thermal Performance and Heat Sink Selection.... 24 Package Mounting ................................................ 25 11 Device and Documentation Support ................. 25 11.1 11.2 11.3 11.4 11.5 Device Support...................................................... Documentation Support ........................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 25 25 25 25 25 12 Mechanical, Packaging, and Orderable Information ........................................................... 26 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (February 2013) to Revision D Page * Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 * Corrected title of data sheet to show accurate maximum output current; changed "-1 A" to "1-A" ..................................... 1 * Changed front-page figures and deleted note stating that RGW package was product preview........................................... 1 * Changed Pin Configuration and Functions section; updated table format and deleted footnote about RGW productpreview status......................................................................................................................................................................... 4 * Deleted footnote from Pin Functions table indicating RGW product-preview status.............................................................. 4 * Deleted footnote (2) from Absolute Maximum Ratings table.................................................................................................. 5 * Deleted note from Thermal Information table stating that RGW package was product preview .......................................... 5 * Corrected condition values for Figure 23 ............................................................................................................................... 9 * Corrected condition values for Figure 24 ............................................................................................................................... 9 * Corrected condition values and trace indicators for Figure 25............................................................................................. 10 * Corrected condition values and trace indicators for Figure 26............................................................................................. 10 * Changed CSS value from 1 F to 10 nF in Figure 27 ........................................................................................................... 10 * Deleted Parametric Measurement Information section ....................................................................................................... 12 * Revised Functional Block Diagram....................................................................................................................................... 12 * Changed first paragraph of Adjustable Operation section stating the device output voltage range .................................... 15 * Changed Equation 2 for clarity ............................................................................................................................................ 15 * Changed last sentence of Capacitor Recommendations section ........................................................................................ 16 * Changed noise reduction capacitor value from 1 F to 10 nF in first paragraph of Power-Supply Rejection section. ........ 17 * Revised last paragraph of Power-Supply Rejection section................................................................................................. 17 * Changed noise reduction capacitor value from 1 F to 10 nF in second paragraph of Output Noise section. ................... 17 * Added footnote (1) to Figure 32 ........................................................................................................................................... 18 * Changed title for Figure 41 ................................................................................................................................................... 23 * Changed title for Figure 42 ................................................................................................................................................... 23 2 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 TPS7A33 www.ti.com SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 Revision History (continued) * Changed Power Dissipation section title to Layout Guidelines for Thermal Performance and Heat Sink Selection .......... 24 * Revised wording in Layout Guidelines for Thermal Performance section for clarification .................................................. 24 Changes from Revision B (March 2012) to Revision C Page * Changed product status from Mixed Status to Production Data ............................................................................................ 1 * Added last paragraph in Description section.......................................................................................................................... 1 * Changed typical application block diagram ............................................................................................................................ 1 * Updated Figure 31................................................................................................................................................................ 17 Changes from Revision A (December 2011) to Revision B Page * Changed product status from Production Data to Mixed Status ............................................................................................ 1 * Added RGW pinout drawing ................................................................................................................................................... 1 * Added RGW pinout drawing to Pin Configuration and Functions section .............................................................................. 4 * Added RGW and footnote 1 to Pin Functions table ............................................................................................................... 4 * Added RGW column to Thermal Information table................................................................................................................. 5 Changes from Original (December 2011) to Revision A * Page Changed product status from Product Preview to Production Data....................................................................................... 1 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 3 TPS7A33 SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 www.ti.com 5 Pin Configuration and Functions KC Package 7-Pin TO-220 Top View OUT 1 NC 2 OUT NC NC NC IN 20 19 18 17 16 RGW Package 20-Pin VQFN Top View Thermal Pad 15 IN 14 NR/SS 13 EN FB 3 NC 4 12 NC NC 5 11 NC 6 7 8 9 10 GND NC NC NC EN IN NC FB NR/SS GND OUT NC 1 2 3 4 5 6 7 Pin Functions PIN NAME I/O DESCRIPTION TO-220 VQFN EN 1 13 I This pin turns the regulator on or off. If VEN VEN(+HI) or VEN VEN(-HI), the regulator is enabled. If VEN(+LO) VEN VEN(-LO), the regulator is disabled. The EN pin can be connected to IN, if not used. |VEN| |VIN|. FB 7 3 I This pin is the input to the control-loop error amplifier. It is used to set the output voltage of the device. TI recommends connecting a 10-nF capacitor from FB to OUT (as close to the device as possible) to maximize AC performance. GND 4 7 -- Ground Input supply. A capacitor greater than or equal to 10 nF must be tied from this pin to ground to assure stability. It is recommended to connect a 10-F capacitor from IN to GND (as close to the device as possible) to reduce circuit sensitivity to printed-circuit-board (PCB) layout, especially when long input traces or high source impedances are encountered. IN 3 15, 16 I NC 5 2, 4-6, 812, 17-19 -- This pin can be left open or tied to any voltage between GND and IN. NR/SS 2 14 -- Noise reduction pin. A capacitor connected from this pin to GND controls the soft-start function and allows RMS noise to be reduced to very low levels. TI recommends connecting a 1-F capacitor from NR/SS to GND (as close to the device as possible) to filter the noise generated by the internal bandgap and maximize ac performance. OUT 6 1, 20 O Regulator output. A capacitor greater than or equal to 10 F must be tied from this pin to ground to assure stability. TI recommends connecting a 47-F ceramic capacitor from OUT to GND (as close to the device as possible) to maximize ac performance. Tab -- -- Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND. An external heatsink can be installed to provide additional thermal performance. Thermal Pad 4 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 TPS7A33 www.ti.com SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX -36 0.3 OUT pin to GND pin -33 0.3 OUT pin to IN pin -0.3 36 FB pin to GND pin -2 0.3 -0.3 36 EN pin to GND pin -36 10 NR/SS pin to IN pin -0.3 36 -2 0.3 IN pin to GND pin Voltage FB pin to IN pin NR/SS pin to GND pin Current Peak output Temperature (1) UNIT V Internally limited Operating virtual junction, TJ -40 150 Storage temperature, Tstg -65 150 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 1000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input supply voltage -35 -3 V VEN Enable supply voltage VIN 10 V VOUT Output voltage -33.2 VREF V IOUT Output current 0 1 A R2 (1) R2 is the lower feedback resistor 240 k CIN Input capacitor 10 47 F COUT Output capacitor 10 47 F CNR Noise reduction capacitor 1 F CFF Feed-forward capacitor TJ Operating junction temperature (1) 10 nF -40 125 C This condition helps ensure stability at no load. 6.4 Thermal Information TPS7A33 THERMAL METRIC (1) KC (TO-220) RGW (VQFN) 7 PINS 20 PINS 31.2 33.7 40 30.4 RJA Junction-to-ambient thermal resistance RJC(top) Junction-to-case(top) thermal resistance RJB Junction-to-board thermal resistance 17.4 12.5 JT Junction-to-top characterization parameter 6.4 0.4 JB Junction-to-board characterization parameter 17.2 12.5 RJC(bot) Junction-to-case(bottom) thermal resistance 0.8 2.4 (1) UNIT C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 5 TPS7A33 SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 www.ti.com 6.5 Electrical Characteristics At -40C TJ 125C, |VIN| = |VOUT(nom)| + 1 V or |VIN| = 3 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 10 F, COUT = 10 F, CNR/SS = 0 nF, and FB tied to OUT, unless otherwise noted. (1) PARAMETER TEST CONDITIONS VIN Input voltage VREF Internal reference VUVLO Undervoltage lockout threshold Output voltage range (2) VOUT Overall accuracy TJ = 25C, |VIN| = |VOUT(nom)| + 0.5 V Load regulation IGND Ground current |ISHDN| Shutdown supply current IFB Feedback current (3) Enable current V V VREF 1.5 V %VOUT %VOUT -2.5 2.5 0.14 %VOUT 1 mA IOUT 1 A 0.4 %VOUT VIN = 95% VOUT(nom), IOUT = 500 mA 290 VIN = 95% VOUT(nom), IOUT = 1 A 325 VOUT = 90% VOUT(nom) 800 1900 IOUT = 0 mA 210 5 VEN = +0.4 V 1 3 VEN = -0.4 V 1 3 14 100 0.48 1 VIN = VEN = -35 V 0.51 1 0.5 1 VEN(+LO) Positive enable low-level voltage VEN(-HI) Negative enable high-level voltage VEN(-LO) Negative enable low-level voltage -0.4 Vn Output noise voltage VIN = -3 V, VOUT(nom) = VREF, COUT = 22 F, CNR/SS = 10 nF, BW = 10 Hz to 100 kHz PSRR Power-supply rejection ratio VIN = -6.2 V, VOUT(nom) = -5 V, COUT = 22 F, CNR/SS = 10 nF, CFF (4) = 10 nF, f = 10 kHz Tsd Thermal shutdown temperature TJ Operating junction temperature A mA VEN = |VIN| = |VOUT(nom)| + 1 V Positive enable high-level voltage mV mA 350 IOUT = 500 mA VEN(+HI) 6 V -1.157 -1.5 VIN = -35 V, VEN = +10 V (1) (2) (3) (4) UNIT 1 |VOUT(nom)| + 1 V |VIN| 35 V 1 mA IOUT 1 A VOUT(IL) |IEN| -3 -1.175 -33.2 5 V |VIN| 35 V 1 mA IOUT 1 A |VOUT(nom)| + 1 V |VIN| 35 V Current limit -1.192 |VIN| |VOUT(nom)| + 1 V Line regulation ICL MAX -2 VOUT(VI) Dropout voltage TYP -35 TJ = 25C, VFB = VREF Nominal accuracy |VDO| MIN A nA A 2 10 V 0 0.4 V VIN -2 V 0 V 16 VRMS 72 dB Shutdown, temperature increasing 170 C Reset, temperature decreasing 150 -40 C 125 C At operating conditions, VIN 0 V, VOUT(nom) VREF 0 V. At regulation, VIN VOUT(nom) - |VDO|. IOUT > 0 flows from OUT to IN. To ensure stability at no load conditions, a current from the feedback resistive network equal to or greater than 5 A is required. IFB > 0 flows into the device. CFF refers to a feed-forward capacitor connected between the FB and OUT pins. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 TPS7A33 www.ti.com SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 6.6 Typical Characteristics At -40C TJ 125C, |VIN| = |VOUT(nom)| + 1 V or |VIN| = 3 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 22 F, COUT = 22 F, CNR/SS = 0 nF, and the FB pin tied to OUT, unless otherwise noted. -1.167 100 90 80 -1.172 IFB (nA) VFB (V) 70 -1.177 60 50 40 30 -1.182 - 40C + 0C + 25C -1.187 -40 -35 -30 -25 -20 -15 Input Voltage (V) 20 + 85C + 125C -10 -5 10 0 -40 -25 -10 0 Figure 1. Feedback Voltage vs Input Voltage 10 20 35 50 65 Temperature (C) 80 95 110 125 Figure 2. Feedback Current vs Temperature 10 5 A 10 mA 500 mA 1000 mA - 40C 0C + 25C + 85C + 125C 9 8 IGND (mA) 7 IGND (mA) 5 1 6 5 4 3 2 1 TJ = +25C 0.1 -30 -27 -24 -21 -18 -15 -12 Input Voltage (V) -9 -6 -3 Figure 3. Ground Current vs Input Voltage -27 -24 -21 -18 -15 -12 Input Voltage (V) -9 -6 -3 0 Figure 4. Ground Current vs Input Voltage 10 1000 - 40C 0C + 25C + 85C + 125C 800 600 400 IEN (nA) IGND (mA) IOUT = 500mA 0 -30 0 1 200 0 -200 - 40C 0C + 25C + 85C + 125C -400 -600 -800 0.1 0.01 0.1 1 10 Output Current (mA) 100 Figure 5. Ground Current vs Output Current 1000 -1000 -35 -30 -25 -20 -15 -10 -5 Input Voltage (V) 0 5 10 Figure 6. Enable Current vs Enable Voltage Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 7 TPS7A33 SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 www.ti.com Typical Characteristics (continued) At -40C TJ 125C, |VIN| = |VOUT(nom)| + 1 V or |VIN| = 3 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 22 F, COUT = 22 F, CNR/SS = 0 nF, and the FB pin tied to OUT, unless otherwise noted. 500 50 IOUT = 0A - 40C + 0C + 25C + 105C + 125C 40 35 300 ISHDN (A) IQ (A) 400 - 40C + 0C + 25C + 105C + 125C 45 200 30 25 20 15 100 10 5 0 -40 -35 -30 -25 -20 -15 Input Voltage (V) -10 -5 0 -40 0 Figure 7. Quiescent Current vs Input Voltage -25 -20 -15 Input Voltage (V) -10 -5 0 1000 - 40C 0C + 25C + 85C + 125C 900 800 700 800 700 600 500 400 600 500 400 300 300 200 200 100 100 0 100 200 50mA 200mA 400mA 800mA 1000mA 900 VDO (mV) VDO (mV) -30 Figure 8. Shutdown Current vs Input Voltage 1000 0 -35 300 400 500 600 700 Output Current (mA) 800 0 -40 -25 -10 900 1000 Figure 9. Dropout Voltage vs Output Current 5 20 35 50 65 Temperature (C) 80 95 110 125 Figure 10. Dropout Voltage vs Temperature 2.5 4 2 - 40C 0C + 25C 3 Enable Threshold Positive 1.5 + 85C + 125C 2 VOUT(NOM) (%) VEN (V) 1 0.5 0 OFF -0.5 1 0 -1 -1 -2 -1.5 -2 -2.5 -40 -25 -10 -3 Enable Threshold Negative 5 20 35 50 65 Temperature (C) 80 95 110 125 -4 -40 Figure 11. Enable Threshold Voltage vs Temperature 8 Submit Documentation Feedback -35 -30 -25 -20 -15 Input Voltage (V) -10 -5 0 Figure 12. Line Regulation Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 TPS7A33 www.ti.com SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 Typical Characteristics (continued) At -40C TJ 125C, |VIN| = |VOUT(nom)| + 1 V or |VIN| = 3 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 22 F, COUT = 22 F, CNR/SS = 0 nF, and the FB pin tied to OUT, unless otherwise noted. 4 100 - 40C + 0C + 25C 3 + 85C + 125C IOUT = 1A CNR = 10nF 90 80 2 PSRR (dB) VOUT(NOM) (%) 70 1 0 -1 60 50 40 30 COUT = 10F COUT = 22F COUT = 47F COUT = 100F -2 20 -3 -4 10 0 100 200 300 400 500 600 700 Output Current (mA) 800 0 900 1000 Figure 13. Load Regulation IOUT = 1A COUT = 22F 80 80 70 70 PSRR (dB) PSRR (dB) 10k 100k Frequency (Hz) 1M 10M 60 50 40 VOUT = -5V IOUT = 1A COUT = 22F CNR SS = 10nF 90 30 60 50 40 30 20 20 CNR CNR 10 10 100 = 0nF SS = 10nF SS 1k CFF = 0nF CFF = 10nF 10 10k 100k Frequency (Hz) 1M 0 10M Figure 15. Power-Supply Rejection Ratio vs CNR/SS 10 100 1k 10k 100k Frequency (Hz) 1M 10M Figure 16. Power-Supply Rejection Ratio vs CFF 110 100 100 90 90 80 80 IOUT = 1A COUT = 22F 70 70 PSRR (dB) PSRR (dB) 1k 100 90 60 50 40 30 10 10 100 1k 60 50 40 30 IOUT = 1mA IOUT = 200mA IOUT = 500mA IOUT = 1A 20 0 100 Figure 14. Power-Supply Rejection Ratio vs COUT 100 0 10 20 COUT = 22F CNR = 10nF 10k 100k Frequency (Hz) 1M 10M Figure 17. Power-Supply Rejection Ratio vs IOUT VOUT = -1.171V VOUT = -5V 10 0 10 100 1k 10k 100k Frequency (Hz) 1M 10M Figure 18. Power-Supply Rejection Ratio vs VOUT Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 9 TPS7A33 SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 www.ti.com Typical Characteristics (continued) At -40C TJ 125C, |VIN| = |VOUT(nom)| + 1 V or |VIN| = 3 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 22 F, COUT = 22 F, CNR/SS = 0 nF, and the FB pin tied to OUT, unless otherwise noted. 110 10 VDO = 1V VDO = 750mV VDO = 500mV 100 90 VDO = 350mV PSRR in Dropout IOUT = 1mA, VNOISE = 16.26VRMS IOUT = 1A, VNOISE = 16.48VRMS 80 Noise (V/ Hz) PSRR (dB) 70 60 50 40 30 10 10 100 1k 10k 100k Frequency (Hz) 1M COUT = 22F CNR SS = 10nF BWRMSNOISE [10Hz, 100kHz] 10M 0.01 G001 10 = 0nF, VNOISE = 78VRMS SS = 10nF, VNOISE = 16VRMS 100k 1M VOUT = -1.171V, VNOISE = 16.48VRMS VOUT = -5V, VNOISE = 37VRMS SS Noise (V/ Hz) 1 0.1 1 0.1 IOUT = 1A COUT = 22F CNR SS = 10nF BWRMSNOISE [10Hz, 100kHz] COUT = 22F BWRMSNOISE [10Hz, 100kHz] 1k 10k Frequency (Hz) 100k 1M VO (100 mV/div) IO (500 mA/div) IO = 1 mA to 500 mA VI = -16 V VO = -15 V 0.01 10 100 1k 10k Frequency (Hz) 100k 1M Figure 22. Output Spectral Noise Density vs VOUT(nom) VO (100 mV/div) 100 IO (500 mA/div) 10 Figure 21. Output Spectral Noise Density vs CNR/SS Time (100 ms/div) IO = 500 mA to 1 mA VI = -16 V VO = -15 V Time (100 ms/div) Figure 23. Load Transient 10 1k 10k Frequency (Hz) 10 CNR CNR 0.01 100 Figure 20. Output Spectral Noise Density vs Output Current Figure 19. Power-Supply Rejection Ratio vs VDO 10 Noise (V/ Hz) 0.1 IOUT = 1A CNR = 10nF COUT = 22F 20 0 1 Figure 24. Load Transient Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 TPS7A33 www.ti.com SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 Typical Characteristics (continued) VO (100 mV/div) VI = -16 V to -26 V VO = -15 V IO = 500 mA VI = -26 V to -16 V VO = -15 V IO = 500 mA VI (10 V/div) VI (10 V/div) VO (100 mV/div) At -40C TJ 125C, |VIN| = |VOUT(nom)| + 1 V or |VIN| = 3 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 22 F, COUT = 22 F, CNR/SS = 0 nF, and the FB pin tied to OUT, unless otherwise noted. Time (500 ms/div) Time (500 ms/div) Figure 25. Line Transient Figure 26. Line Transient VOUT (5 V/div) VIN (10 V/div) CSS = 10 nF Time (20 ms/div) Figure 27. Capacitor-Programmable Soft-Start Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 11 TPS7A33 SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 www.ti.com 7 Detailed Description 7.1 Overview The TPS7A33 belongs to a family of new-generation linear regulators that use an innovative bipolar process to achieve ultralow-noise and very high PSRR levels at a wide input voltage and current range. These features, combined with the external heatsink-capable, high thermal performance TO-220 package, make this device ideal for high-performance analog applications. 7.2 Functional Block Diagram GND Control Logic EN FB NR/SS Bandgap OUT Error Amp Pass Device Thermal Shutdown Current Limit IN 7.3 Feature Description 7.3.1 Internal Current Limit The fixed internal current limit of the TPS7A33xx family helps protect the regulator during fault conditions. The maximum amount of current the device can source is the current limit (1.9 A, typical), and it is largely independent of output voltage. For reliable operation, do not operate the device in current limit for extended periods of time. 12 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 TPS7A33 www.ti.com SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 Feature Description (continued) 7.3.2 Enable Pin Operation The TPS7A33 provides a dual-polarity enable pin (EN) that turns on the regulator when |VEN| > 2 V, whether the voltage is positive or negative, as shown in Figure 28. This functionality allows for different system power management topologies; for example: * Connecting the EN pin directly to a negative voltage, such as VIN, or * Connecting the EN pin directly to a positive voltage, such as the output of digital logic circuitry. VOUT VEN VIN Time (20ms/div) Figure 28. Enable Pin Positive and Negative Threshold 7.3.3 Programmable Soft-Start The NR capacitor also acts as a soft-start capacitor to slow down the rise time of the output. The output rise time, when using an NR capacitor, is governed by Equation 1. tSS (ms) = 1.2 CNR (nF) (1) In Equation 1, tSS is the soft-start time in milliseconds, and CNR/SS is the capacitance at the NR pin in nanofarads. Figure 29 shows the start-up voltage waveforms versus CNR/SS. 2 CNR/SS = 0nF CNR/SS = 10nF CNR/SS = 100nF 0 Output Voltage (V) -2 -4 -6 -8 -10 -12 -14 -16 0 20 40 60 80 100 Time (ms) 120 140 160 180 200 D001 D001 Figure 29. Start-Up vs CNR/SS 7.3.4 Thermal Protection Thermal protection disables the output when the junction temperature rises to approximately 170C, allowing the device to cool. When the junction temperature cools to approximately 150C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 13 TPS7A33 SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 www.ti.com Feature Description (continued) Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heat sink. For reliable operation, junction temperature should be limited to a maximum of 125C. To estimate the margin of safety in a complete design (including heat sink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 35C above the maximum expected ambient condition of your particular application. This configuration produces a worst-case junction temperature of 125C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS7A33 has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS7A33 into thermal shutdown degrades device reliability. 7.4 Device Functional Modes 7.4.1 Normal Operation The device regulates to the nominal output voltage under the following conditions: * The input voltage has previously exceeded the UVLO rising voltage and has not decreased below the UVLO falling threshold. * The input voltage is greater than the nominal output voltage added to the dropout voltage. * |VEN| > |V(HI)| * The output current is less than the current limit. * The device junction temperature is less than the maximum specified junction temperature. 7.4.2 Dropout Operation If the input voltage magnitude is lower than the nominal output voltage magnitude plus the specified dropout voltage magnitude, but all other conditions are met for normal operation, the device operates in dropout mode. In this condition, the output voltage magnitude is the same as the input voltage magnitude minus the dropout voltage magnitude. The transient performance of the device is significantly degraded because the pass device (as a bipolar junction transistor, or BJT) is in saturation and no longer controls the current through the LDO. Line or load transients in dropout can result in large output voltage deviations. 7.4.3 Disabled The device is disabled under the following conditions: * |VEN| < |V(HI)| * The device junction temperature is greater than the thermal shutdown temperature. Table 1 shows the conditions that lead to the different modes of operation. Table 1. Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VEN IOUT TJ Normal mode |VIN| > { |VOUT(nom)| + |VDO|, |VIN(min)| } |VEN| > |V(HI)| I OUT < ICL T J < 125C Dropout mode |VIN(min)| < |VIN| < |VOUT(nom)| + |VDO| |VEN| > |V(HI)| -- TJ < 125C Disabled mode (any true condition disables the device) -- |VEN| < |V(HI)| -- TJ > 165C 14 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 TPS7A33 www.ti.com SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Adjustable Operation The TPS7A3301 has an output voltage range of -VREF to -33 V. The nominal output voltage of the device is set by two external resistors, as shown in Figure 32. R1 and R2 can be calculated for any output voltage range using Equation 2. To ensure stability under no-load conditions at VOUT > VREF, this resistive network must provide a current equal to or greater than 5 A. |VREF(max)| VOUT > 5 mA R1 = R2 - 1 , where R2 VREF (2) If greater voltage accuracy is required, consider the output voltage offset contributions because of the feedback pin current and use 0.1%-tolerance resistors. Table 2 shows the resistor combinations to achieve a few of the most common rails using commercially available, 0.1%-tolerance resistors to maximize nominal voltage accuracy while adhering to the formula shown in Equation 2. Table 2. Suggested Resistors For Common Voltage Rails VOUT (V) R1 R2 (k) VOUT/(R1+R2) (A) NOMINAL ACCURACY -1.171 0 0 1.5% -1.8 76.8 k 143 8.18 (1.5% + 0.08%) -3.3 200 k 110 10.64 (1.5% + 0.13%) -5 332 k 102 11.48 (1.5% + 0.5%) -10 1.62 M 215 5.44 (1.5% + 0.23%) -12 1.5 M 162 7.22 (1.5% + 0.29%) -15 1.24 M 105 11.15 (1.5% + 0.18%) -18 3.09 M 215 5.44 (1.5% + 0.19%) -24 1.15 M 59 19.84 (1.5% + 0.21%) Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 15 TPS7A33 SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 www.ti.com 8.1.2 Capacitor Recommendations Low equivalent series resistance (ESR) capacitors should be used for the input, output, noise reduction, and bypass capacitors. Ceramic capacitors with X7R and X5R dielectrics are preferred. These dielectrics offer more stable characteristics. Ceramic X7R capacitors offer improved overtemperature performance, while ceramic X5R capacitors are the most cost-effective and are available in higher values. NOTE High-ESR capacitors may degrade PSRR and affect stability. 8.1.3 Input and Output Capacitor Requirements The TPS7A33 family of negative, high-voltage linear regulators achieve stability with a minimum input and output capacitance of 10 F; however, TI highly recommends using a 47-F capacitor to maximize AC performance. 8.1.4 Noise Reduction and Feed-Forward Capacitor Requirements Although the noise-reduction (CNR/SS) and feed-forward (CFF) capacitors are not needed to achieve stability, TI highly recommends using a 10-nF feed-forward capacitor and a 1-F noise-reduction capacitor to minimize noise and maximize AC performance. The feed-forward capacitor can also provide a soft-start effect, as detailed in the application note, Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator, SBVA042 (available for download from the TI website). Figure 30 shows device start-up with no CNR/SS, CFF = 10 nF, VIN = -16 V, and VOUT = -15 V. EN, 2V/div VOUT, 5V/div Time (1 ms/div) Figure 30. Start-up With a Feed-Forward Capacitor 8.1.5 Post DC-DC Converter Filtering Most of the time, the voltage rails available in a system do not match the voltage specifications demanded by one or more of its circuits; these rails must be stepped up or down, depending on specific voltage requirements. DC-DC converters are the preferred solution to stepping up or down a voltage rail when current consumption is not negligible. These devices offer high efficiency with minimum heat generation, but they have one primary disadvantage: they introduce a high-frequency component, and the associated harmonics, on top of the DC output signal. If not filtered properly, this high-frequency component degrades analog circuitry performance, and reduces overall system accuracy and precision. The TPS7A33 offers a wide-bandwidth, very-high power-supply rejection ratio (PSRR). This specification makes it ideal for post DC-DC converter filtering, as shown in Figure 31. TI highly recommends using the maximum performance schematic shown in Figure 32. Also, verify that the fundamental frequency (and its first harmonic, if possible) is within the bandwidth of the regulator PSRR, shown in Figure 16. 16 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 TPS7A33 www.ti.com SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 +18 V IN OUT +15 V TPS7A47 +LDO EN GND -18 V IN OUT TPS7A33 -LDO EN GND -15 V EVM Figure 31. Post DC-DC Converter Regulation to High-Performance Analog Circuitry 8.1.6 Audio Applications Audio applications are extremely sensitive to any distortion and noise in the audio band from 20 Hz to 20 kHz. This stringent requirement demands clean voltage rails to power critical high-performance audio systems. The very high power-supply rejection ratio (> 60 dB) and low noise at the audio band of the TPS7A33 maximize performance for audio applications; see Figure 16. 8.1.7 Maximum AC Performance To maximize noise and PSRR performance, TI recommends including 47-F or higher input and output capacitors, 100-nF noise-reduction capacitors, and 10-nF feed-forward capacitors, as shown in Figure 32. The solution shown delivers minimum noise levels of 16 VRMS and power-supply rejection levels above 55 dB from 10 Hz to 1 MHz; see Figure 19. 8.1.8 Power-Supply Rejection The 10-nF noise-reduction capacitor greatly improves TPS7A33 power-supply rejection, achieving up to 10 dB of additional power-supply rejection for frequencies between 140 Hz and 500 kHz. Additionally, AC performance can be maximized by adding a 10-nF feed-forward capacitor (CFF) from the FB pin to the OUT pin. This capacitor greatly improves power-supply rejection at lower frequencies, for the band from 100 Hz to 100 kHz; see Figure 15. The high power-supply rejection of the TPS7A33 makes it a good choice for powering high-performance analog circuitry. 8.1.9 Output Noise The TPS7A33 provides low output noise when a noise-reduction capacitor (CNR/SS) is used. The noise-reduction capacitor serves as a filter for the internal reference. By using a 10-nF noise reduction capacitor, the output noise is reduced by almost 80% (from 80 VRMS to 17 VRMS); see Figure 21. The TPS7A33 low output voltage noise makes it an ideal solution for powering noise-sensitive circuitry. 8.1.10 Transient Response As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude, but increases duration of the transient response. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 17 TPS7A33 SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 www.ti.com 8.1.11 Power for Precision Analog One of the primary TPS7A33 applications is to provide ultralow-noise voltage rails to high-performance analog circuitry in order to maximize system accuracy and precision. The TPS7A33 family of negative, high-voltage linear regulators provides ultralow noise, positive and negative voltage rails to high-performance analog circuitry such as operational amplifiers, ADCs, DACs, and audio amplifiers. Because of the ultralow noise levels at high voltages, analog circuitry with high-voltage input supplies can be used. This characteristic allows for high-performance analog solutions to optimize the voltage range, thus maximizing system accuracy. 8.2 Typical Application VIN EN CNR/SS 1 mF A. OUT IN CIN 10 mF TPS7A3301 NR/SS FB GND (1) CFF 10 nF VOUT = -15 V R1 1.24 MW R2 105 kW Where: COUT 47 mF VOUT 5 mA, and R1 + R2 R1 = R2 VOUT -1 VREF Refer to application report Pros and Cons of Using a Feed-forward Capacitor with a Low-Dropout Regulator, SBVA042. Figure 32. Adjustable Operation for Maximum AC Performance 8.2.1 Design Requirements The design goals for this example are VIN = -16 V, VOUT = -15 V, and IOUT = 1 A maximum. The design must optimize transient response, and the input supply comes from a supply on the same printed-circuit board (PCB). 8.2.2 Detailed Design Procedure The design space consists of CIN, COUT, CSS/NR, R1, R2, and the circuit shown in Figure 32. The first step when designing with a linear regulator is to examine the maximum load current along with the input and output voltage requirements to determine if the device thermal and dropout voltage requirements can be met. At 1 A, the input dropout voltage of the TPS7A33xx family is a maximum of 800 mV overtemperature; thus, the dropout headroom is sufficient for operation over both input and output voltage accuracy. Keep in mind that operating an LDO close to the dropout limit reduces AC performance, but has the benefit of reducing the power dissipation across the LDO. The maximum power dissipated in the linear regulator is the maximum voltage drop across the pass element from the input to the output multiplied by the maximum load current. In this example, the maximum voltage drop across in the pass element is (-16 V) - (-15 V), giving us a VDROP = 1 V. The power dissipated in the pass element is calculated by taking this voltage drop multiplied by the maximum load current. For this example, the maximum power dissipated in the linear regulator is approximately 1 W, and does not include the power consumed by the VBIAS rail. Once the power dissipated in the linear regulator is known, the corresponding junction temperature rise can be calculated. To calculate the junction temperature rise above ambient, the power dissipated must be multiplied by the junction-to-ambient thermal resistance. For thermal resistance information, refer to Thermal Information and Thermal Performance and Heat Sink Selection. For this example, using the RGW package, the maximum junction temperature rise is calculated to be 17.2C. The maximum junction temperature rise is calculated by adding junction temperature rise to the maximum ambient temperature, which is 85C. In this example, then, the maximum junction temperature is 102.2C. The maximum junction temperate must be less than 125C for reliable operation. Additional ground planes, added thermal vias, and air flow all combine to lower the maximum junction temperature. To ensure an accurate output voltage, R1 and R2 must also be found, and the current through these resistors must be greater than 5 A to ensure that the leakage into the device does not affect the accuracy. Using 1% resistors, and setting R1 to 1 M to minimize the current leakage while continuing to hold it above 5 A, then use Equation 3 to calculate the proper value for R2 and the divider current. 18 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 TPS7A33 www.ti.com SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 Typical Application (continued) R2 = VO (R1 * VREF) = 85 kW and IDIVIDER = = 13.8 mA R1 + R2 VO - VREF (3) For CIN, assume that the -16 V supply has some inductance, and is placed several inches away from the PCB. For this case, select a 10-F ceramic input capacitor to ensure that the input inductance is negligible to the regulator control loop while also keeping the physical size and cost of the capacitor low because it is a standardvalue capacitor. COUT is set at 20 F for AC performance, CFF is set at 10 nF, and CNR is set at 100 nF for optimal noise performance and to minimize the size of the external capacitor. 8.2.3 Application Curves Figure 33 and Figure 34 show typical application performance for PSRR and spectral noise density, respectively, versus CNR/SS with CFF. 80 2 CNR/SS = 1PF CNR/SS = 100nF 0.5 Noise (PV/(Hz)) 60 PSRR (dB) CNR/SS = 1PF, VNOISE = 17.6PVRMS CNR/SS = 100nF, VNOISE = 17.6PVRMS 1 40 20 0.3 0.2 0.1 0.05 0.03 0.02 0.01 0 1E+1 1E+2 1E+3 1E+4 1E+5 Frequency (Hz) 1E+6 1E+7 1E+2 1E+3 1E+4 1E+5 Frequency (Hz) 1E+6 1E+7 IO = 1 mA to 500 mA VI = -16 V VO = -15 V IO (500 mA/div) Figure 34. Output Spectral Noise Density vs CNR/SS With CFF IO (500 mA/div) Figure 33. Power-Supply Rejection Ratio vs CNR/SS With CFF VO (100 mV/div) VIN = -16 V, VOUT = -15 V, IOUT = 1 A, CFF = 10 nF, COUT = 2 x F VO (100 mV/div) VIN = -16 V, VOUT = -15 V, IOUT = 1 A, CFF = 10 nF, COUT = 2 x 10 F 0.005 1E+1 Time (100 ms/div) IO = 500 mA to 1 mA VI = -16 V VO = -15 V Time (100 ms/div) Figure 35. Load Transient Figure 36. Load Transient Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 19 TPS7A33 SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 www.ti.com VO (100 mV/div) VO (100 mV/div) Typical Application (continued) VI = -26 V to -16 V VO = -15 V IO = 500 mA VI (10 V/div) VI (10 V/div) VI = -16 V to -26 V VO = -15 V IO = 500 mA Time (500 ms/div) Time (500 ms/div) Figure 37. Line Transient Figure 38. Line Transient VOUT (5 V/div) VIN (10 V/div) CSS = 10 nF Time (20 ms/div) Figure 39. Capacitor-Programmable Soft-Start 8.3 Do's and Don'ts Place at least one low ESR 10-F capacitor as close as possible to both the IN and OUT terminals of the regulator to the GND pin. Provide adequate thermal paths away from the device. Do not place the input or output capacitor more than 10 mm away from the regulator. Do not exceed the absolute maximum ratings. Do not float the EN pin. Do not resistively or inductively load the NR/SS pin. 20 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 TPS7A33 www.ti.com SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 9 Power Supply Recommendations The input supply for the LDO must be within its recommended operating conditions, from -35 V to -3 V. The input voltage must provide adequate headroom for the device to have a regulated output. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance. 10 Layout Layout is a critical part of good power-supply design. Several signal paths that conduct fast-changing currents or voltages can interact with stray inductance or parasitic capacitance to generate noise or degrade the powersupply performance. To help eliminate these problems, the IN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with a X5R or X7R dielectric. 10.1 Layout Guidelines 10.1.1 Improve PSRR and Noise Performance To improve AC performance such as PSRR, output noise, and transient response, TI recommends designing the board with separate planes for IN, OUT, and GND. The IN and OUT planes should be isolated from each other by a GND plane section. In addition, the ground connection for the output capacitor should connect directly to the GND pin of the device. Equivalent series inductance (ESL) and equivalent series resistance (ESR) must be minimized in order to maximize performance and ensure stability. Every capacitor (CIN, COUT, CNR/SS, CFF) must be placed as close as possible to the device and on the same side of the PCB as the regulator itself. Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use of vias and long traces is strongly discouraged because they may impact system performance negatively and even cause instability. 10.2 Layout Example It may be possible to obtain acceptable performance with alternative PCB layouts; however, the layout shown in Figure 41 and the schematic shown in Figure 42 have been shown to produce good results and are meant as a guideline. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 21 TPS7A33 SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 www.ti.com R1 R2 Sense Line CFF NC SNS/ FB NC OUT 4 3 2 1 COUT 20 OUT 19 NC 18 NC 9 17 NC 10 16 IN NC NC Thermal Pad 11 12 13 14 15 IN 8 NR 7 NC EN GND NC Input GND Plane and Thermal Relief 5 6 NC NC NC Output Power Plane CNR Output GND Plane Input Power Plane CIN Scale is 8:1 This figure shows a 1x1 layout; expand to 3x3 or at least 2x2. Figure 40. TPS7A33 5-mm x 5-mm QFN-20 Layout Guideline 22 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 TPS7A33 www.ti.com SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 Figure 41. TPS7A33 TO-220 EVM PCB Layout Example: Top Layer Figure 42. TPS7A33 TO-220 EVM PCB Layout Example: Bottom Layer Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 23 TPS7A33 SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 www.ti.com Figure 43. Schematic for TPS7A33 TO-220 EVM PCB Layout Example 10.3 Thermal Performance and Heat Sink Selection The primary TPS7A33 application is to provide ultralow-noise voltage rails to high-performance analog circuitry in order to maximize system accuracy and precision. The high-current and high-voltage characteristics of this regulator means that, often enough, high power (heat) is dissipated from the device itself. This heat, if dissipated into the PCB (as is the case with SMT packages), creates a temperature gradient in the surrounding area that causes nearby components to react to this temperature change (drift). In high-performance systems, such drift may degrade overall system accuracy and precision. Compared to surface-mount packages, the TO-220 (KC) package allows for an external heat sink to be used to maximize thermal performance and keep heat from dissipating into the PCB. The heat generated by the device is a result of the power dissipation, which depends on input voltage and load conditions. Power dissipation (PD) can be approximated by calculating the product of the output current times the voltage drop across the output pass element, as shown in Equation 4: PD = (VIN - VOUT) IOUT (4) Heat flows from the device to the ambient air through many paths, each of which represents resistance to the heat flow; this effect is called thermal resistance. The total thermal resistance of a system is defined by: JA = (TJ - TA)/PD; where: JA is the thermal resistance (in C/W), TJ is the allowable juntion temperature of the device (in C), TA is the maximum temperature of the ambient cooling air (in C), and PD is the amount of power (heat) dissipated by the device (in W). Whenever a heat sink is installed, the total thermal resistance (JA) is the sum of all the individual resistances from the device, going through its case and heatsink to the ambient cooling air (JA = JC + CS + SA). Realistically, only two resistances can be controlled: CS and SA. Therefore, for a device with a known JC, CS and SA become the main design variables in selecting a heat sink. The thermal interface between the case and the heat sink (CS) is controlled by selecting the correct heatconducting material. Once the CS is selected, the required thermal resistance from the heat sink to ambient is calculated by the following equation: SA = [(TJ - TA)/PD] - [JC+ CS]. This information allows the most appropriate heat sink to be selected for any particular application. 24 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 TPS7A33 www.ti.com SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 10.4 Package Mounting The TO-220 (KC) 7-lead, straight-formed package lead spacing poses a challenge when creating a suitable PCB footprint without bending the leads. Component forming pliers can be used to manually bend the package leads into a 7-lead stagger pattern with increased lead spacing that can be more easily used. The TPS7A33 evaluation board layout can be used as a guideline on suitable PCB footprints, available at www.ti.com. Refer to the TPS7A3301EVM-061 user's guide for more information. 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 Evaluation Modules An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS7A33. The TPS7A3301EVM-061 evaluation module (and related user's guide) can be requested at the TI website through the product folders or purchased directly from the TI eStore. 11.1.1.2 Spice Models Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. A SPICE model for the TPS7A33 is available through the product folders under the Tools & Software tab. 11.1.2 Device Nomenclature Table 3. Device Nomenclature (1) PRODUCT TPS7A3301YYYZ (1) VOUT YYY is the package designator. Z is the tape and reel quantity (R = 3000, T = 250). For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following (available for download at www.ti.com): * Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator, SBVA042 * TPS7A3301EVM-061 Evaluation Module User's Guide, SLVU602 11.3 Trademarks All trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 25 TPS7A33 SBVS169D - DECEMBER 2011 - REVISED APRIL 2015 www.ti.com 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 26 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: TPS7A33 PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPS7A3301KC LIFEBUY TO-220 KC 7 50 Pb-Free (RoHS) CU SN Level-2-260C-1 YEAR -40 to 125 PPQQ TPS7A3301RGWR ACTIVE VQFN RGW 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PXQQ TPS7A3301RGWT ACTIVE VQFN RGW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PXQQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS7A3301RGWR VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2 TPS7A3301RGWT VQFN RGW 20 250 180.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS7A3301RGWR VQFN RGW 20 3000 367.0 367.0 35.0 TPS7A3301RGWT VQFN RGW 20 250 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA MSOT010 - OCTOBER 1994 KC (R-PSFM-T7) PLASTIC FLANGE-MOUNT PACKAGE 0.156 (3,96) 0.146 (3,71) 0.420 (10,67) 0.380 (9,65) DIA 0.113 (2,87) 0.103 (2,62) 0.185 (4,70) 0.175 (4,46) 0.055 (1,40) 0.045 (1,14) 0.147 (3,73) 0.137 (3,48) 0.335 (8,51) 0.325 (8,25) 1.020 (25,91) 1.000 (25,40) 1 7 0.125 (3,18) (see Note C) 0.030 (0,76) 0.026 (0,66) 0.010 (0,25) M 0.050 (1,27) 0.300 (7,62) 0.122 (3,10) 0.102 (2,59) 0.025 (0,64) 0.012 (0,30) 4040251 / B 01/95 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Lead dimensions are not controlled within this area. All lead dimensions apply before solder dip. The center lead is in electrical contact with the mounting tab. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI's published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. 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NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED "AS IS" AND WITH ALL FAULTS. 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Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers' own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. 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