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FEATURES
APPLICATIONS
DESCRIPTION
3 V–5.5 V
3 V–13 V
FAULT
typical application
NOTE: Terminal 14 is active-high on TPS2321.
VREG
IN1 ISET1 ISENSE1 GATE1 DISCH1
TIMER
DISCH2
GATE2
ISENSE2ISET2IN2
DGND
AGND
V2
V1
TPS2320
+VO1
VO2
+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GATE1
GATE2
DGND
TIMER
VREG
AGND
ISENSE2
ISENSE1
DISCH1
DISCH2
ENABLE
FAULT
ISET1
ISET2
IN2
IN1
D OR PW PACKAGE
(TOP VIEW)
ENABLE
TPS2320
TPS2321
SLVS276E – MARCH 2000 – REVISED NOVEMBER 2006
DUAL HOT SWAP POWER CONTROLLERSWITH INDEPENDENT CIRCUIT BREAKER
•Dual-Channel High-Side MOSFET Drivers•IN1: 3 V to 13 V; IN2: 3 V to 5.5 V•Output dV/dt Control Limits Inrush Current•Independent Circuit-Breaker WithProgrammable Overcurrent Threshold andTransient Timer•CMOS- and TTL-Compatible Enable Input•Low, 5- µA Standby Supply Current (Max)•Available in 16-Pin SOIC and TSSOP Package•–40 °C to 85 °C Ambient Temperature Range•Electrostatic Discharge Protection
•Hot-Swap/Plug/Dock Power Management•Hot-Plug PCI, Device Bay•Electronic Circuit Breaker
The TPS2320 and TPS2321 are dual-channelhot-swap controllers that use external N-channelMOSFETs as high-side switches in powerapplications. Features of these devices, such asovercurrent protection (OCP), inrush-current control,and the ability to discriminate between loadtransients and faults, are critical requirements forhot-swap applications.
A
The TPS2320/21 devices incorporate undervoltage lockout (UVLO) to ensure the device is off at startup. Eachinternal charge pump, capable of driving multiple MOSFETs, provides enough gate-drive voltage to fullyenhance the N-channel MOSFETs. The charge pumps control both the rise times and fall times (dv/dt) of theMOSFETs, reducing power transients during power up/down. The circuit-breaker functionality combines theability to sense overcurrent conditions with a timer function; this allows designs such as DSPs, that may havehigh peak currents during power-state transitions, to disregard transients for a programmable period.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000–2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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FUNCTIONAL BLOCK DIAGRAM
PREREG
UVLO and
Power Up
IN1 ISET1 ISENSE1 GATE1
Clamp
Charge
Pump
75 µA
Pulldown FET
Circuit Breaker
dv/dt Rate
Protection
DISCH1
Logic FAULT
TIMER
Second Channel
GATE2ISENSE2ISET2IN2 DISCH2
Circuit
Breaker
VREG
Deglitcher
AGND
DGND
ENABLE
50 µA
TPS2320
TPS2321
SLVS276E – MARCH 2000 – REVISED NOVEMBER 2006
AVAILABLE OPTIONS
PACKAGESPINT
A
HOT-SWAP CONTROLLER DESCRIPTION
COUNT
ENABLE ENABLE
Dual-channel with independent OCP and adjustable PG 20 TPS2300IPW TPS2301IPWDual-channel with interdependent OCP and adjustable PG 20 TPS2310IPW TPS2311IPWTPS2320ID TPS2321ID–40 °C to 85 °C
Dual-channel with independent OCP 16
TPS2320IPW TPS2321IPWTPS2330ID TPS2331IDSingle-channel with OCP and adjustable PG 14
TPS2330IPW TPS2331IPW
Table 1. Terminal Functions
TERMINAL
I/O DESCRIPTIONNAME NO.
AGND 6 I Analog ground, connects to DGND as close as possibleDGND 3 I Digital groundDISCH1 16 O Discharge transistor 1DISCH2 15 O Discharge transistor 2ENABLE/ENABLE 14 I Active low (TPS2320) or active high enable (TPS2321)FAULT 13 O Overcurrent fault, open-drain outputGATE1 1 O Connects to gate of channel 1 high-side MOSFETGATE2 2 O Connects to gate of channel 2 high-side MOSFETIN1 9 I Input voltage for channel 1IN2 10 I Input voltage for channel 2ISENSE1 8 I Current-sense input channel 1ISENSE2 7 I Current-sense input channel 2ISET1 12 I Adjusts circuit-breaker threshold with resistor connected to IN1
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TPS2320
TPS2321
SLVS276E – MARCH 2000 – REVISED NOVEMBER 2006
Table 1. Terminal Functions (continued)
TERMINAL
I/O DESCRIPTIONNAME NO.
ISET2 11 I Adjusts circuit-breaker threshold with resistor connected to IN2TIMER 4 O Adjusts circuit-breaker deglitch timeVREG 5 O Connects to bypass capacitor, for stable operation
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DETAILED DESCRIPTION
TPS2320
TPS2321
SLVS276E – MARCH 2000 – REVISED NOVEMBER 2006
DISCH1, DISCH2 – DISCH1 and DISCH2 should be connected to the sources of the external N-channelMOSFET transistors connected to GATE1 and GATE2, respectively. These pins discharge the loads when theMOSFET transistors are disabled. They also serve as reference-voltage connections for internal gatevoltage-clamp circuitry.
ENABLE or ENABLE – ENABLE for TPS2320 is active low. ENABLE for TPS2321 is active high. When thecontroller is enabled, both GATE1 and GATE2 voltages will power up to turn on the external MOSFETs. Whenthe ENABLE pin is pulled high for TPS2320 or the ENABLE pin is pulled low for TPS2321 for more than 50 µs,the gate of the MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled todischarge the output bulk capacitance. In addition, the device turns on the internal regulator PREREG (seeVREG) when enabled and shuts down PREREG when disabled so that total supply current is much less than5µA.
FAULT – FAULT is an open-drain overcurrent flag output. When an overcurrent condition in either channel issustained long enough to charge TIMER to 0.5 V, the overcurrent channel latches off and pulls FAULT low. Theother channel will run normally if not in overcurrent. In order to turn the channel back on, either the enable pinhas to be toggled or the input power has to be cycled.
GATE1, GATE2 – GATE1 and GATE2 connect to the gates of external N-channel MOSFET transistors. Whenthe device is enabled, internal charge-pump circuitry pulls these pins up by sourcing approximately 15 µA toeach. The turnon slew rates depend upon the capacitance present at the GATE1 and GATE2 terminals. Ifdesired, the turnon slew rates can be further reduced by connecting capacitors between these pins and ground.These capacitors also reduce inrush current and protect the device from false overcurrent triggering duringpower up. The charge-pump circuitry will generate gate-to-source voltages of 9 V-12 V across the externalMOSFET transistors.
IN1, IN2 – IN1 and IN2 should be connected to the power sources driving the external N-channel MOSFETtransistors connected to GATE1 and GATE2, respectively. The TPS2320/TPS2321 draws its operating currentfrom IN1, and both channels will remain disabled until the IN1 power supply has been established. The IN1channel has been constructed to support 3-V, 5-V, or 12-V operation, while the IN2 channel has beenconstructed to support 3-V or 5-V operation
ISENSE1, ISENSE2, ISET1, ISET2 – ISENSE1 and ISENSE2, in combination with ISET1 and ISET2, implementovercurrent sensing for GATE1 and GATE2. ISET1 and ISET2 set the magnitude of the current that generatesan overcurrent fault, through external resistors connected to ISET1 and ISET2. An internal current source draws50 µA from ISET1 and ISET2. With a sense resistor from IN1 to ISENSE1 or from IN2 to ISENSE2, which isalso connected to the drains of external MOSFETs, the voltage on the sense resistor reflects the load current.An overcurrent condition is assumed to exist if ISENSE1 is pulled below ISET1 or if ISENSE2 is pulled belowISET2.
TIMER – A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turningoff. When the overcurrent protection circuits sense an excessive current, a current source is enabled whichcharges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breakerlatch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled torestart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is stronglyrecommended from TIMER to ground, to prevent any false triggering.
VREG – VREG is the output of an internal low-dropout voltage regulator, where IN1 is the input. The regulator isused to generate a regulated voltage source, less than 5.5 V, for the device. A 0.1- µF ceramic capacitor shouldbe connected between VREG and ground to aid in noise rejection. In this configuration, upon disabling thedevice, the internal low-dropout regulator will also be disabled, which removes power from the internal circuitryand allows the device to be placed in low-quiescent-current mode. In applications where IN1 is less than5.5 V,VREG and IN1 may be connected together. However, under these conditions, disabling the device will not placethe device in low-quiescent-current mode, because the internal low-dropout voltage regulator is being bypassed,thereby keeping internal circuitry operational. If VREG and IN1 are connected together, a 0.1- µF ceramiccapacitor between VREG and ground is not needed if IN1 already has a bypass capacitor of 1 µF to 10 µF.
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE
RECOMMENDED OPERATING CONDITIONS
TPS2320
TPS2321
SLVS276E – MARCH 2000 – REVISED NOVEMBER 2006
over operating free-air temperature range (unless otherwise noted)
(1) (2)
VALUE UNIT
V
I(IN1)
, V
I(ISENSE1)
, V
I(ISET1)
, V
I(ENABLE)
–0.3 to 15 VInput voltage range
V
I(IN2)
, V
I(ISENSE2)
, V
I(ISET2)
, V
I(VREG)
–0.3 to 7 VV
O(GATE1)
–0.3 to 30 VOutput voltage range V
O(GATE2)
–0.3 to 22 VV
O(DISCH1)
, V
O( FAULT)
, V
O(DISCH2)
, V
O(TIMER)
–0.3 to 15 VI
(GATE1)
, I
(GATE2)
, I
(DISCH1)
, I
(DISCH2)
0 to 100 mASink current range
I
(TIMER)
, I
( FAULT)
0 to 10 mAOperating virtual junction temperature range, T
J
–40 to 100 °CStorage temperature range, T
stg
–55 to 150 °CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages are respect to DGND.
T
A
≤25 °C DERATING FACTOR T
A
= 70 °C T
A
= 85 °CPACKAGE
POWER RATING ABOVE T
A
= 25 °C POWER RATING POWER RATING
PW-16 823 mW 10.98 mW/ °C 329 mW 165 mWD-16 674 mW 8.98 mW/ °C 270 mW 135 mW
MIN NOM MAX UNIT
V
I(IN1)
, V
I(ISENSE1)
, V
I(ISET1)
3 13V
I
Input voltage VV
I(IN2)
, V
I(ISENSE2)
, V
I(ISET2)
, V
I(VREG)
3 5.5T
J
Operating virtual junction temperature 40 100 °C
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ELECTRICAL CHARACTERISTICS
TPS2320
TPS2321
SLVS276E – MARCH 2000 – REVISED NOVEMBER 2006
over recommended operating temperature range (–40 °C < T
A
< 85 °C), 3V ≤V
I(IN1)
≤13V, 3V ≤V
I(IN2)
≤5.5V (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GENERAL
I
I(IN1)
Input current, IN1 V
I(ENABLE)
= 5 V (TPS2321), 0.5 1 mAI
I(IN2)
Input current, IN2 V
I( ENABLE)
= 0 V (TPS2320) 75 200 µAStandby current (sum ofcurrents into IN1, IN2, V
I(ENABLE)
= 0 V (TPS2321),I
I(stby)
5 µAISENSE1, ISENSE2, V
I( ENABLE)
= 5 V (TPS2320)ISET1, and ISET2)
GATE1
V
G(GATE1_3V)
V
I(IN1)
= 3 V 9 11.5V
G(GATE1_4.5V)
Gate voltage I
I(GATE1)
= 500 nA, DISCH1 open V
I(IN1)
= 4.5 V 10.5 14.5 VV
G(GATE1_10.8V)
V
I(IN1)
= 10.8 V 16.8 21Clamping voltage, GATE1V
C(GATE1)
9 10 12 Vto DISCH1
3 V ≤V
I(IN1)
≤13.2 V, 3 V ≤V
O(VREG)
≤5.5 V,I
S(GATE1)
Source current, GATE1 10 14 20 µAV
I(GATE1)
= V
I(IN1)
+ 6 V3 V ≤V
I(IN1)
≤13.2 V, 3 V ≤V
O(VREG)
≤5.5 V,Sink current, GATE1 50 75 100 µAV
I(GATE1)
= V
I(IN1)
V
I(IN1)
= 3 V 0.5t
r(GATE1)
Rise time, GATE1 C
g
to GND = 1 nF
(1)
V
I(IN1)
= 4.5 V 0.6 msV
I(IN1)
= 10.8 V 1V
I(IN1)
= 3 V 0.1t
f(GATE1)
Fall time, GATE1 C
g
to GND = 1 nF
(1)
V
I(IN1)
= 4.5 V 0.12 msV
I(IN1)
= 10.8 V 0.2
GATE2
V
G(GATE2_3V)
V
I(IN2)
= 3 V 9 11.7Gate voltage I
I(GATE2)
= 500 nA, DISCH2 open VV
G(GATE2_4.5V)
V
I(IN2)
= 4.5 V 10.5 14.7Clamping voltage, GATE2V
C(GATE2)
9 10 12 Vto DISCH2
3 V ≤V
I(IN2)
≤5.5 V, 3 V ≤V
O(VREG)
≤5.5 V,I
S(GATE2)
Source current, GATE2 10 14 20 µAV
I(GATE2)
= V
I(IN2)
+ 6 V3 V ≤V
I(IN2)
≤5.5 V, 3 V ≤V
O(VREG)
≤5.5 V,Sink current, GATE2 50 75 100 µAV
I(GATE2)
= V
I(IN2)
V
I(IN2)
= 3 V 0.5t
r(GATE2)
Rise time, GATE2 C
g
to GND = 1 nF
(1)
msV
I(IN2)
= 4.5 V 0.6V
O(VREG)
= 3 VV
I(IN2)
= 3 V 0.1t
f(GATE2)
Fall time, GATE2 C
g
to GND = 1 nF
(1)
msV
I(IN2)
= 4.5 V 0.12
(1) Specified, but not production tested.
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(1) Test I
O
of ENABLE at V
I( ENABLE)
= 1 V and 0 V, then R
I( ENABLE)
=
1 V
IO_0V *IO_1V
ELECTRICAL CHARACTERISTICS (Continued)
TPS2320
TPS2321
SLVS276E – MARCH 2000 – REVISED NOVEMBER 2006
over recommended operating temperature range (–40 °C < T
A
< 85 °C), 3V ≤V
I(IN1)
≤13V, 3V ≤V
I(IN2)
≤5.5V (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TIMER
V
(TO_TIMER)
Threshold voltage, TIMER 0.4 0.5 0.6 VCharge current, TIMER V
I(TIMER)
= 0 V 35 50 65 µADischarge current, TIMER V
I(TIMER)
= 1 V 1 2.5 mA
CIRCUIT BREAKER
R
ISETx
= 1 k Ω40 50 60R
ISETx
= 400 Ω, T
A
= 25 °C 14 19 24V
IT(CB)
Threshold voltage, circuit breaker mVR
ISETx
= 1 k Ω, T
A
= 25 °C 44 50 53R
ISETx
= 1.5 k Ω, T
A
= 25 °C 68 73 78I
(IB_ISENSEx)
Input bias current, I
SENSEx
0.1 5 µAV
O(GATEx)
= 4 V 400 800Discharge current, GATEx mAV
O(GATEx)
= 1 V 25 150Propagation (delay) time, C
g
= 50 pF, 10 mV overdrive,t
pd(CB)
1.3 µscomparator inputs to gate output (50% to 10%), C
TIMER
= 50 pF
ENABLE, ACTIVE LOW (TPS2320)
V
IH( ENABLE)
High-level input voltage, ENABLE 2 VV
IL( ENABLE)
Low-level input voltage, ENABLE 0.8 VR
I( ENABLE)
Input pullup resistance, ENABLE See
(1)
100 200 300 k ΩV
I( ENABLE)
increasing above stop threshold;t
d(off_ ENABLE)
Turnoff delay time, ENABLE 60 µs100 ns rise time, 20 mV overdrive
(2)
V
I( ENABLE)
decreasing below start threshold;t
d(on_ ENABLE)
Turnon delay time, ENABLE 125 µs100 ns fall time, 20 mV overdrive
(2)
ENABLE, ACTIVE HIGH (TPS2321)
V
IH(ENABLE)
High-level input voltage, ENABLE 2 VV
IL(ENABLE)
Low-level input voltage, ENABLE 0.7 VR
I(ENABLE)
Input pulldown resistance, ENABLE 100 150 300 k ΩV
I(ENABLE)
increasing above start threshold;t
d(on_ENABLE)
Turnon delay time, ENABLE 85 µs100 ns rise time, 20 mV overdrive
(2)
V
I(ENABLE)
decreasing below stop threshold;t
d(off_ENABLE)
Turnoff delay time, ENABLE 100 µs100 ns fall time, 20 mV overdrive
(2)
PREREG
V
(VREG)
PREREG output voltage 4.5 ≤V
I(IN1)
≤13 V 3.5 4.1 5.5 VV
(drop_PREREG)
PREREG dropout voltage V
I(IN1)
= 3 V 0.1 V
(2) Specified, but not production tested.
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ELECTRICAL CHARACTERISTICS (Continued)
TPS2320
TPS2321
SLVS276E – MARCH 2000 – REVISED NOVEMBER 2006
over recommended operating temperature range (–40 °C < T
A
< 85 °C), 3V ≤V
I(IN1)
≤13V, 3V ≤V
I(IN2)
≤5.5V (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREG UVLO
V
(TO_UVLOstart)
Output threshold voltage, start 2.75 2.85 2.95 VV
(TO_UVLOstop)
Output threshold voltage, stop 2.65 2.78 VV
hys(UVLO)
Hysteresis 50 75 mVUVLO sink current, GATEx V
I(GATEx)
= 2 V 10 mA
FAULT OUTPUT
V
O(sat_ FAULT)
Output saturation voltage, FAULT I
O
= 2 mA 0.4 VI
lkg( FAULT)
Leakage current, FAULT V
O( FAULT)
= 13 V 1 µA
DISCH1 AND DISCH2
I
(DISCH)
Discharge current, DISCHx V
I(DISCHx)
= 1.5 V, V
I(VIN1)
= 5 V 5 10 mAV
IH(DISCH)
Discharge on high-level input 2 VvoltageV
IL(DISCH)
Discharge on low-level input voltage 1 V
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PARAMETER MEASUREMENT INFORMATION
V
5V/div
I( )ENABLE
V
10V/div
O(GATE1)
V
5V/div
O(DISCH1)
t – Time – 10ms/div
Load12 W
V
5V/div
I( )ENABLE
V
10V/div
O(GATE1)
V
5V/div
O(DISCH1)
t – Time – 10ms/div
Load12 W
V
5V/div
I( )ENABLE
V
10V/div
O(GATE2)
V
5V/div
O(DISCH2)
t – Time – 10ms/div
Load5 W
V
5V/div
I( )ENABLE
V
10V/div
O(GATE2)
V
5V/div
O(DISCH2)
t – Time – 10ms/div
Load5 W
TPS2320
TPS2321
SLVS276E – MARCH 2000 – REVISED NOVEMBER 2006
Figure 1. Turnon Voltage Transition of Channel 1 Figure 2. Turnoff Voltage Transition of Channel 1
Figure 3. Turnon Voltage Transition of Channel 2 Figure 4. Turnoff Voltage Transition of Channel 2
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V
5V/div
I( )ENABLE
V
10V/div
O( )FAULT
V
10V/div
O(GATE1)
I
2 A/div
O(OUT1)
t – Time – 5ms/div
NoCapacitoronTimer
V
5V/div
I( )ENABLE
V
10V/div
O( )FAULT
V
10V/div
O(GATE1)
I
2 A/div
O(OUT1)
t – Time – 1ms/div
NoCapacitoronTimer
V
5V/div
I( )ENABLE
V
10V/div
O( )FAULT
V
10V/div
O(GATE2)
I
2 A/div
O(OUT2)
t – Time – 2ms/div
NoCapacitoronTimer
V
5V/div
I( )ENABLE
V
10V/div
O( )FAULT
V
10V/div
O(GATE2)
I
2 A/div
O(OUT2)
t – Time – 0.5ms/div
NoCapacitoronTimer
TPS2320
TPS2321
SLVS276E – MARCH 2000 – REVISED NOVEMBER 2006
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 5. Channel 1 Overcurrent Response: Figure 6. Channel 1 Overcurrent Response: anEnabled Into Overcurrent Load OvercurrentLoad Plugged Into the Enabled Board
Figure 7. Channel 2 Overcurrent Response: Figure 8. Channel 2 Overcurrent Response: anEnabled Into Overcurrent Load Overcurrent Load Plugged Into the Enabled Board
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V
5V/div
I( )ENABLE
V
10V/div
O( )FAULT
V
10V/div
O(GATE1)
I
2 A/div
I(IN1)
t – Time – 1ms/div
NoCapacitoronTimer
V
5V/div
I( )ENABLE
V
10V/div
O( )FAULT
V
5V/div
O(GATE2)
I
2 A/div
I(IN2)
t – Time – 1ms/div
NoCapacitoronTimer
V
10V/div
I(IN1)
V
10V/div
O(OUT1)
V
10V/div
O(GATE1)
I
1 A/div
O(OUT1)
t – Time – 5ms/div
NoCapacitoronTimer
V
10V/div
I(IN1)
V
10V/div
O(OUT1)
V
10V/div
O(GATE1)
I
1 A/div
O(OUT1)
t – Time – 1ms/div
NoCapacitoronTimer
TPS2320
TPS2321
SLVS276E – MARCH 2000 – REVISED NOVEMBER 2006
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 9. Channel 1 – Enabled Into Short Circuit Figure 10. Channel 2 – Enabled Into Short Circuit
Figure 11. Channel 1 –Hot Plug Figure 12. Channel 1 –Hot Removal
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V
5V/div
I(IN2)
V
5V/div
O(OUT2)
V
10V/div
O(GATE2)
I
1 A/div
O(OUT2)
t – Time – 5ms/div
NoCapacitoronTimer
TPS2320
TPS2321
SLVS276E – MARCH 2000 – REVISED NOVEMBER 2006
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 13. Channel 2 - Hot Plug
Figure 14. Channel 2 - Hot Removal
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TYPICAL CHARACTERISTICS
49
46
45
43
4 5 6 7 8 9 10
–InputCurrent1 – Am
50
51
52
11 12 13 14
48
47
44
II1
VI1 – InputVoltage1 – V
IN2=5.5V
TA=85°C
TA=25°C
TA=0°C
TA= –40°C
–InputCurrent2 – AmII2
VI2 – InputVoltage2 – V
70
69.5
69
68
2.5 3 3.5 4 4.5 5 5.5
70.5
71
71.5
6
68.5
IN1=13V
TA=85°C
TA=25°C
TA=0°C
TA= –40°C
12
10
9
7
4 5 6 7 8 9 10
13
14
15
11 12 13 14
11
8
–InputCurrent1 – nAII1
VI1 – InputVoltage1 – V
TA=85°C
TA=25°C
TA=0°C
TA= –40°C
IN2=5.5V
17
13
7
5
2.5 3 3.5 4 4.5 5 5.5
19
21
23
6
15
9
11
–InputCurrent2 – nAII2
VI2 – InputVoltage2 – V
TA=85°C
TA=25°C
TA=0°C
TA= –40°C
IN1=13V
TPS2320
TPS2321
SLVS276E – MARCH 2000 – REVISED NOVEMBER 2006
INPUT CURRENT 1 (ENABLED) INPUT CURRENT 2 (ENABLED)vs vsINPUT VOLTAGE 1 INPUT VOLTAGE 2
Figure 15. Figure 16.
INPUT CURRENT 1 (DISABLED) INPUT CURRENT 2 (DISABLED)vs vsINPUT VOLTAGE 1 INPUT VOLTAGE 2
Figure 17. Figure 18.
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16
14
12
10
2 3 4 5 6 7 8
V– GA
OTE1OutputVoltage – V
18
20
22
9 10 11 12
V – InputVoltage1 – V
I1
TA=85°C
TA=25°C
TA=0°C
TA= –40°C
CL(GATE1) =1000pF
t– GATE1VoltageRiseTime – ms
r
C – GATE1LoadCapacitance – nF
L(GATE1)
3
0
0 3 6
6
9
12
15
18
9 12
IN1=12V
TA=25°C
V – GATE1Voltage – V
13.5
13
12
11
14 15 16 17 18 19 20
I– GA
OTE1OutputCurrent – A
m
14
14.5
15
21 22 23 24
12.5
11.5
TA=85°C
TA=25°C
TA=0°C
TA= –40°C
IN1=13V
1
0
0 3 6
–GATE1VoltageFallT
ime – ms
2
3
4
9 12
tf
CL(GATE1) – GATE1LoadCapacitance – nF
IN1=12V
TA=25°C
TPS2320
TPS2321
SLVS276E – MARCH 2000 – REVISED NOVEMBER 2006
TYPICAL CHARACTERISTICS (continued)
GATE1 OUTPUT VOLTAGE GATE1 VOLTAGE RISE TIMEvs vsINPUT VOLTAGE 1 GATE1 LOAD CAPACITANCE
Figure 19. Figure 20.
GATE1 VOLTAGE FALL TIME GATE1 OUTPUT CURRENTvs vsGATE1 LOAD CAPACITANCE GATE1 VOLTAGE
Figure 21. Figure 22.
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C – TIMERCapacitance – nF
TIMER
6
3
0
0 0.2 0.4 0.6
t – Circuit-BreakerResponseTime
(res) – sm
9
12
0.8 1
IN1=12V
TA=25°C
TA– Temperature – °C
2.8
2.78
2.74
2.7
–45–35–25–15 –5 5 15
–UVLOStartandStopThresholds –V
2.84
2.88
2.9
45 65 75 95
2.86
2.82
2.76
2.72
25 35 55 85
Vref
Start
Stop
TPS2320
TPS2321
SLVS276E – MARCH 2000 – REVISED NOVEMBER 2006
TYPICAL CHARACTERISTICS (continued)
CIRCUIT-BREAKER RESPONSE TIME LOAD VOLTAGE 1 DISCHARGE TIMEvs vsTIMER CAPACITANCE LOAD CAPACITANCE
Figure 23. Figure 24.
UVLO START AND STOP THRESHOLDS
vsTEMPERATURE
Figure 25.
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APPLICATION INFORMATION
VREG
0.1 µF
IN1 ISET1
RISET1
ISENSE1
RSENSE1
GATE1 DISCH1
+
FAULT
VO1 or VO2
FAULT
TIMER IN2 ISET2 ISENSE2 GATE2 DISCH2
ENABLE
DGND
AGND
RISET2
+
VO1
VO2
ENABLE
1 µF ∼ 10 µF
RSENSE2
1 µF ∼ 10 µF
3 V ∼ 13 V IN1
3 V ∼ 5.5 V IN2
TPS2321
System Board
INPUT CAPACITOR
OUTPUT CAPACITOR
EXTERNAL FET
TPS2320
TPS2321
SLVS276E – MARCH 2000 – REVISED NOVEMBER 2006
Figure 26 shows a typical dual hot-swap application. The pullup resistor at FAULT should be relatively large(e.g., 100 k Ω) to reduce power loss, unless it is required to drive a large load.
Figure 26. Typical Dual Hot-Swap Application
A 0.1- µF ceramic capacitor in parallel with a 1- µF ceramic capacitor should be placed on the input powerterminals near the connector on the hot-plug board to help stabilize the voltage rails on the cards. TheTPS2320/01 does not need to be mounted near the connector or to these input capacitors. For applications withmore severe power environments, a 2.2- µF, or higher, ceramic capacitor is recommended near the inputterminals of the hot-plug board. A bypass capacitor for IN1 and for IN2 should be placed close to the device.
A 0.1- µF ceramic capacitor is recommended per load on the TPS2320/21; these capacitors should be placedclose to the external FETs and to TPS2320/21. A larger bulk capacitor is also recommended on the load. Thevalue of the bulk capacitor should be selected based on the power requirements and the transients generated bythe application.
To deliver power from the input sources to the loads, each channel needs an external N-channel MOSFET. Afew widely used MOSFETs are shown in Table 2 . But many other MOSFETs on the market can also be usedwith TPS23xx in hot-swap systems.
Table 2. Some Available N-Channel MOSFETs
CURRENT RANGE
PART NUMBER DESCRIPTION MANUFACTURER(A)
IRF7601 N-channel, r
DS(on)
= 0.035 Ω, 4.6 A, Micro-8 International Rectifier0 to 2 MTSF3N03HDR2 N-channel, r
DS(on)
= 0.040 Ω, 4.6 A, Micro-8 ON SemiconductorMMSF5N02HDR2 Dual N-channel, r
DS(on)
= 0.04 Ω, 5 A, SO-8 ON Semiconductor
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TIMER
OUTPUT-VOLTAGE SLEW-RATE CONTROL
dVs
dt +15 mA
Cgd
(1)
VREG CAPACITOR
GATE-DRIVE CIRCUITRY
TPS2320
TPS2321
SLVS276E – MARCH 2000 – REVISED NOVEMBER 2006
APPLICATION INFORMATION (continued)Table 2. Some Available N-Channel MOSFETs (continued)
CURRENT RANGE
PART NUMBER DESCRIPTION MANUFACTURER(A)
IRF7401 N-channel, r
DS(on)
= 0.022 Ω, 7 A, SO-8 International RectifierMMSF5N02HDR2 N-channel, r
DS(on)
= 0.025 Ω, 5 A, SO-8 ON Semiconductor2 to 5
IRF7313 Dual N-channel, r
DS(on)
= 0.029 Ω, 5.2 A, SO-8 International RectifierSI4410 N-channel, r
DS(on)
= 0.020 Ω, 8 A, SO-8 Vishay DaleIRLR3103 N-channel, r
DS(on)
= 0.019 Ω, 29 A, d-Pak International Rectifier5 to 10
IRLR2703 N-channel, r
DS(on)
= 0.045 Ω, 14 A, d-Pak International Rectifier
For most applications, a minimum capacitance of 50 pF is recommended to prevent false triggering. A capacitorshould be connected between TIMER and ground. The presence of an overcurrent condition on either channelof the TPS2320/TPS2321 causes a 50- µA current source to begin charging this capacitor. If the over-currentcondition persists until the capacitor has been charged to approximately 0.5 V, the TPS2320/TPS2321 latchesoff the offending channels and pulls the FAULT pin low. The timer capacitor can be made as large as desired toprovide additional time delay before registering a fault condition. PWRGDx will not correctly report powerconditions when the device is disabled. The time delay is approximately:
dt(sec) = C
TIMER
(F) ×10,000( Ω).
When enabled, the TPS2320/TPS2321 controllers supply the gates of each external MOSFET transistor with acurrent of approximately 15 µA. The slew rate of the MOSFET source voltage is thus limited by the gate-to-draincapacitance C
gd
of the external MOSFET capacitor to a value approximating:
If a slower slew rate is desired, an additional capacitance can be connected between the gate of the externalMOSFET and ground.
The internal voltage regulator connected to VREG requires an external capacitor to ensure stability. A 0.1-µF or0.22-µF ceramic capacitor is recommended.
The TPS2320/TPS2321 includes four separate features associated with each gate-drive terminal:•A charging current of approximately 15 µA is applied to enable the external MOSFET transistor. This currentis generated by an internal charge pump that can develop a gate-to-source potential (referenced to DISCH1or DISCH2) of 9 V–12 V. DISCH1 and DISCH2 must be connected to the respective external MOSFETsource terminals to ensure proper operation of this circuitry.•A discharge current of approximately 75 µA is applied to disable the external MOSFET transistor. Once thetransistor gate voltage has dropped below approximately 1.5 V, this current is disabled and the UVLOdischarge driver is enabled instead. This feature allows the part to enter a low-current shutdown mode whileensuring that the gates of the external MOSFET transistors remain at a low voltage.•During a UVLO condition, the gates of both MOSFET transistors are pulled down by internal PMOStransistors. These transistors continue to operate even if IN1 and IN2 are both at 0 V. This circuitry alsohelps hold the external MOSFET transistors off when power is suddenly applied to the system.•During an overcurrent fault condition, the external MOSFET transistor that exhibited an overcurrent conditionwill be rapidly turned off by an internal pulldown circuit capable of pulling in excess of 400 mA (at 4 V) fromthe pin. Once the gate has been pulled below approximately 1.5 V, this driver is disengaged and the UVLOdriver is enabled instead. If one channel experiences an overcurrent condition and the other does not, then
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SETTING THE CURRENT-LIMIT CIRCUIT-BREAKER THRESHOLD
ILMT1 +RISET1 50 10–6
RISENSE1
(2)
UNDERVOLTAGE LOCKOUT (UVLO)
SINGLE-CHANNEL OPERATION
POWER-UP CONTROL
3-CHANNEL HOT-SWAP APPLICATION
TPS2320
TPS2321
SLVS276E – MARCH 2000 – REVISED NOVEMBER 2006
only the channel that is conducting excessive current will be turned off rapidly. The other channel willcontinue to operate normally.
Using channel 1 as an example, the current sensing resistor R
ISENSE1
and the current-limit-setting resistor R
ISET1determine the current limit of the channel, and can be calculated by the following equation:
Typically R
ISENSE1
is very small (0.001 Ωto 0.1 Ω). If the trace and solder-junction resistances between thejunction of R
ISENSE1
and ISENSE1 and the junction of R
ISENSE1
and R
ISET1
are greater than 10% of the R
ISENSE1value, then these resistance values should be added to the R
ISENSE1
value used in the calculation above.
The above information and calculation also apply to channel 2. Table 3 shows some of the current senseresistors available in the market.
Table 3. Some Current Sense Resistors
CURRENT RANGE (A) PART NUMBER DESCRIPTION MANUFACTURER
0 to 1 WSL-1206, 0.05 1% 0.05 Ω, 0.25 W, 1% resistor1 to 2 WSL-1206, 0.025 1% 0.025 Ω, 0.25 W, 1% resistor2 to 4 WSL-1206, 0.015 1% 0.015 Ω, 0.25 W, 1% resistor
Vishay Dale4 to 6 WSL-2010, 0.010 1% 0.010 Ω, 0.5 W, 1% resistor6 to 8 WSL-2010, 0.007 1% 0.007 Ω, 0.5 W, 1% resistor8 to 10 WSR-2, 0.005 1% 0.005 Ω, 0.5 W, 1% resistor
The TPS2320/TPS2321 includes an undervoltage lockout (UVLO) feature that monitors the voltage present onthe VREG pin. This feature will disable both external MOSFETs if the voltage on VREG drops below 2.78 V(nominal) and will re-enable normal operation when it rises above 2.85 V (nominal). Since VREG is fed from IN1through a low-dropout voltage regulator, the voltage on VREG will track the voltage on IN1 within 50 mV. Whilethe undervoltage lockout is engaged, both GATE1 and GATE2 are held low by internal PMOS pulldowntransistors, ensuring that the external MOSFET transistors remain off at all times, even if all power supplies havefallen to 0 V.
Some applications may require only a single external MOS transistor. Such applications should use GATE1 andthe associated circuitry (IN1, ISENSE1, ISET1, DISCH1). The IN2 pin should be grounded to disable thecircuitry associated with the GATE2 pin.
The TPS2320/TPS2321 includes a 500 µs (nominal) startup delay that ensures that internal circuitry hassufficient time to start before the device begins turning on the external MOSFETs. This delay is triggered onlyupon the rapid application of power to the circuit. If the power supply ramps up slowly, the undervoltage lockoutcircuitry will provide adequate protection against undervoltage operation.
Some applications require hot-swap control of up to three voltage rails, but may not explicitly require the sensingof the status of the output power on all three of the voltage rails. One such application is device bay, where dv/dtcontrol of 3.3 V, 5 V, and 12 V is required. By using Channel 2 to drive both the 3.3-V and 5-V power rails andChannel 1 to drive the 12-V power rail, as is shown below, TPS2320/01 can deliver three different voltages tothree loads while monitoring the status of two of the loads.
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VREG
0.1 µF
IN1 ISET1
RISET1
ISENSE1
RSENSE1
GATE1 DISCH1
+
FAULT
VO1 or VO2
FAULT
TIMER IN2 ISET2 ISENSE2 GATE2 DISCH2
ENABLE
DGND
AGND
RISET2 Rg1
+
VO1
VO2
ENABLE
1 µF ∼ 10 µF
RSENSE2
1 µF ∼ 10 µF
12 V IN1
3.3 V IN2
TPS2321
+VO3
1 µF ∼ 10 µF
5 V IN3
System Board
Rg2
t – Time – 2.5ms/div
V – OutputVoltage – 2V/div
O
VO1
VO3
VO2
TPS2320
TPS2321
SLVS276E – MARCH 2000 – REVISED NOVEMBER 2006
Figure 27. Three-Channel Application
Figure 28 shows ramp-up waveforms of the three output voltages.
Figure 28.
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PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS2320ID ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2320IDG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2320IDR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2320IDRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2320IPW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2320IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2320IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2320IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2321ID ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2321IDG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2321IPW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2321IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2321IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2321IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 2
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2320IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TPS2320IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TPS2321IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2320IDR SOIC D 16 2500 333.2 345.9 28.6
TPS2320IPWR TSSOP PW 16 2000 367.0 367.0 35.0
TPS2321IPWR TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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