TPS2320 TPS2321 www.ti.com SLVS276E - MARCH 2000 - REVISED NOVEMBER 2006 DUAL HOT SWAP POWER CONTROLLERS WITH INDEPENDENT CIRCUIT BREAKER FEATURES * * * * * * * * * Dual-Channel High-Side MOSFET Drivers IN1: 3 V to 13 V; IN2: 3 V to 5.5 V Output dV/dt Control Limits Inrush Current Independent Circuit-Breaker With Programmable Overcurrent Threshold and Transient Timer CMOS- and TTL-Compatible Enable Input Low, 5-A Standby Supply Current (Max) Available in 16-Pin SOIC and TSSOP Package -40C to 85C Ambient Temperature Range Electrostatic Discharge Protection D OR PW PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 GATE1 GATE2 DGND TIMER VREG AGND ISENSE2 ISENSE1 16 15 14 13 12 11 10 9 DISCH1 DISCH2 ENABLE FAULT ISET1 ISET2 IN2 IN1 NOTE: Terminal 14 is active-high on TPS2321. typical application APPLICATIONS * * * Hot-Swap/Plug/Dock Power Management Hot-Plug PCI, Device Bay Electronic Circuit Breaker DESCRIPTION The TPS2320 and TPS2321 are dual-channel hot-swap controllers that use external N-channel MOSFETs as high-side switches in power applications. Features of these devices, such as overcurrent protection (OCP), inrush-current control, and the ability to discriminate between load transients and faults, are critical requirements for hot-swap applications. VO1 + V1 3 V-13 V IN1 ISET1 ISENSE1 GATE1 DISCH1 VREG AGND TPS2320 DGND FAULT TIMER ENABLE IN2 ISET2 ISENSE2 GATE2 DISCH2 VO2 + V2 3 V-5.5 V A The TPS2320/21 devices incorporate undervoltage lockout (UVLO) to ensure the device is off at startup. Each internal charge pump, capable of driving multiple MOSFETs, provides enough gate-drive voltage to fully enhance the N-channel MOSFETs. The charge pumps control both the rise times and fall times (dv/dt) of the MOSFETs, reducing power transients during power up/down. The circuit-breaker functionality combines the ability to sense overcurrent conditions with a timer function; this allows designs such as DSPs, that may have high peak currents during power-state transitions, to disregard transients for a programmable period. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2000-2006, Texas Instruments Incorporated TPS2320 TPS2321 www.ti.com SLVS276E - MARCH 2000 - REVISED NOVEMBER 2006 AVAILABLE OPTIONS PACKAGES PIN COUNT ENABLE ENABLE Dual-channel with independent OCP and adjustable PG 20 TPS2300IPW TPS2301IPW Dual-channel with interdependent OCP and adjustable PG 20 TPS2310IPW TPS2311IPW 16 TPS2320ID TPS2320IPW TPS2321ID TPS2321IPW 14 TPS2330ID TPS2330IPW TPS2331ID TPS2331IPW TA HOT-SWAP CONTROLLER DESCRIPTION -40C to 85C Dual-channel with independent OCP Single-channel with OCP and adjustable PG FUNCTIONAL BLOCK DIAGRAM IN1 VREG ISET1 ISENSE1 GATE1 PREREG DISCH1 Clamp dv/dt Rate Protection 50 A Circuit Breaker Charge Pump Pulldown FET Circuit Breaker UVLO and Power Up AGND 75 A DGND ENABLE FAULT Logic Deglitcher TIMER Second Channel IN2 ISET2 ISENSE2 GATE2 DISCH2 Table 1. Terminal Functions TERMINAL NAME 2 NO. I/O DESCRIPTION AGND 6 I Analog ground, connects to DGND as close as possible DGND 3 I Digital ground DISCH1 16 O Discharge transistor 1 DISCH2 15 O Discharge transistor 2 ENABLE/ENABLE 14 I Active low (TPS2320) or active high enable (TPS2321) FAULT 13 O Overcurrent fault, open-drain output GATE1 1 O Connects to gate of channel 1 high-side MOSFET GATE2 2 O Connects to gate of channel 2 high-side MOSFET IN1 9 I Input voltage for channel 1 IN2 10 I Input voltage for channel 2 ISENSE1 8 I Current-sense input channel 1 ISENSE2 7 I Current-sense input channel 2 ISET1 12 I Adjusts circuit-breaker threshold with resistor connected to IN1 Submit Documentation Feedback TPS2320 TPS2321 www.ti.com SLVS276E - MARCH 2000 - REVISED NOVEMBER 2006 Table 1. Terminal Functions (continued) TERMINAL NAME NO. I/O DESCRIPTION ISET2 11 I Adjusts circuit-breaker threshold with resistor connected to IN2 TIMER 4 O Adjusts circuit-breaker deglitch time VREG 5 O Connects to bypass capacitor, for stable operation Submit Documentation Feedback 3 TPS2320 TPS2321 www.ti.com SLVS276E - MARCH 2000 - REVISED NOVEMBER 2006 DETAILED DESCRIPTION DISCH1, DISCH2 - DISCH1 and DISCH2 should be connected to the sources of the external N-channel MOSFET transistors connected to GATE1 and GATE2, respectively. These pins discharge the loads when the MOSFET transistors are disabled. They also serve as reference-voltage connections for internal gate voltage-clamp circuitry. ENABLE or ENABLE - ENABLE for TPS2320 is active low. ENABLE for TPS2321 is active high. When the controller is enabled, both GATE1 and GATE2 voltages will power up to turn on the external MOSFETs. When the ENABLE pin is pulled high for TPS2320 or the ENABLE pin is pulled low for TPS2321 for more than 50 s, the gate of the MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to discharge the output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see VREG) when enabled and shuts down PREREG when disabled so that total supply current is much less than 5A. FAULT - FAULT is an open-drain overcurrent flag output. When an overcurrent condition in either channel is sustained long enough to charge TIMER to 0.5 V, the overcurrent channel latches off and pulls FAULT low. The other channel will run normally if not in overcurrent. In order to turn the channel back on, either the enable pin has to be toggled or the input power has to be cycled. GATE1, GATE2 - GATE1 and GATE2 connect to the gates of external N-channel MOSFET transistors. When the device is enabled, internal charge-pump circuitry pulls these pins up by sourcing approximately 15A to each. The turnon slew rates depend upon the capacitance present at the GATE1 and GATE2 terminals. If desired, the turnon slew rates can be further reduced by connecting capacitors between these pins and ground. These capacitors also reduce inrush current and protect the device from false overcurrent triggering during power up. The charge-pump circuitry will generate gate-to-source voltages of 9 V-12 V across the external MOSFET transistors. IN1, IN2 - IN1 and IN2 should be connected to the power sources driving the external N-channel MOSFET transistors connected to GATE1 and GATE2, respectively. The TPS2320/TPS2321 draws its operating current from IN1, and both channels will remain disabled until the IN1 power supply has been established. The IN1 channel has been constructed to support 3-V, 5-V, or 12-V operation, while the IN2 channel has been constructed to support 3-V or 5-V operation ISENSE1, ISENSE2, ISET1, ISET2 - ISENSE1 and ISENSE2, in combination with ISET1 and ISET2, implement overcurrent sensing for GATE1 and GATE2. ISET1 and ISET2 set the magnitude of the current that generates an overcurrent fault, through external resistors connected to ISET1 and ISET2. An internal current source draws 50 A from ISET1 and ISET2. With a sense resistor from IN1 to ISENSE1 or from IN2 to ISENSE2, which is also connected to the drains of external MOSFETs, the voltage on the sense resistor reflects the load current. An overcurrent condition is assumed to exist if ISENSE1 is pulled below ISET1 or if ISENSE2 is pulled below ISET2. TIMER - A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breaker latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled to restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly recommended from TIMER to ground, to prevent any false triggering. VREG - VREG is the output of an internal low-dropout voltage regulator, where IN1 is the input. The regulator is used to generate a regulated voltage source, less than 5.5 V, for the device. A 0.1-F ceramic capacitor should be connected between VREG and ground to aid in noise rejection. In this configuration, upon disabling the device, the internal low-dropout regulator will also be disabled, which removes power from the internal circuitry and allows the device to be placed in low-quiescent-current mode. In applications where IN1 is less than5.5 V, VREG and IN1 may be connected together. However, under these conditions, disabling the device will not place the device in low-quiescent-current mode, because the internal low-dropout voltage regulator is being bypassed, thereby keeping internal circuitry operational. If VREG and IN1 are connected together, a 0.1-F ceramic capacitor between VREG and ground is not needed if IN1 already has a bypass capacitor of 1F to 10F. 4 Submit Documentation Feedback TPS2320 TPS2321 www.ti.com SLVS276E - MARCH 2000 - REVISED NOVEMBER 2006 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) VALUE UNIT VI(IN1), VI(ISENSE1), VI(ISET1), VI(ENABLE) -0.3 to 15 V VI(IN2), VI(ISENSE2), VI(ISET2), VI(VREG) -0.3 to 7 V VO(GATE1) -0.3 to 30 V VO(GATE2) -0.3 to 22 V VO(DISCH1), VO(FAULT), VO(DISCH2), VO(TIMER) -0.3 to 15 V I(GATE1), I(GATE2), I(DISCH1), I(DISCH2) 0 to 100 mA I(TIMER), I(FAULT) 0 to 10 mA Operating virtual junction temperature range, TJ -40 to 100 C Storage temperature range, Tstg -55 to 150 C 260 C Input voltage range Output voltage range Sink current range Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are respect to DGND. DISSIPATION RATING TABLE PACKAGE TA 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING TA = 85C POWER RATING PW-16 823 mW 10.98 mW/C 329 mW 165 mW D-16 674 mW 8.98 mW/C 270 mW 135 mW RECOMMENDED OPERATING CONDITIONS MIN NOM MAX VI(IN1), VI(ISENSE1), VI(ISET1) 3 13 VI(IN2), VI(ISENSE2), VI(ISET2), VI(VREG) 3 5.5 40 100 VI Input voltage TJ Operating virtual junction temperature Submit Documentation Feedback UNIT V C 5 TPS2320 TPS2321 www.ti.com SLVS276E - MARCH 2000 - REVISED NOVEMBER 2006 ELECTRICAL CHARACTERISTICS over recommended operating temperature range (-40C < TA < 85C), 3V VI(IN1) 13V, 3V VI(IN2) 5.5V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT GENERAL II(IN1) Input current, IN1 VI(ENABLE) = 5 V (TPS2321), 0.5 1 mA II(IN2) Input current, IN2 VI(ENABLE) = 0 V (TPS2320) 75 200 A II(stby) Standby current (sum of currents into IN1, IN2, ISENSE1, ISENSE2, ISET1, and ISET2) VI(ENABLE) = 0 V (TPS2321), VI(ENABLE) = 5 V (TPS2320) 5 A Gate voltage II(GATE1) = 500 nA, DISCH1 open GATE1 VG(GATE1_3V) VG(GATE1_4.5V) VI(IN1) = 3 V VG(GATE1_10.8V) 9 11.5 VI(IN1) = 4.5 V 10.5 14.5 VI(IN1) = 10.8 V 16.8 21 9 10 12 V V VC(GATE1) Clamping voltage, GATE1 to DISCH1 IS(GATE1) Source current, GATE1 3 V VI(IN1) 13.2 V, 3 V VO(VREG) 5.5 V, VI(GATE1) = VI(IN1) + 6 V 10 14 20 A Sink current, GATE1 3 V VI(IN1) 13.2 V, 3 V VO(VREG) 5.5 V, VI(GATE1) = VI(IN1) 50 75 100 A Rise time, GATE1 Cg to GND = 1 nF tr(GATE1) (1) VI(IN1) = 3 V 0.5 VI(IN1) = 4.5 V 0.6 VI(IN1) = 10.8 V VI(IN1) = 3 V tf(GATE1) Fall time, GATE1 Cg to GND = 1 nF (1) ms 1 0.1 VI(IN1) = 4.5 V 0.12 VI(IN1) = 10.8 V 0.2 ms GATE2 VG(GATE2_3V) VG(GATE2_4.5V) II(GATE2) = 500 nA, DISCH2 open VI(IN2) = 3 V VI(IN2) = 4.5 V 9 11.7 10.5 14.7 9 10 12 V V VC(GATE2) Clamping voltage, GATE2 to DISCH2 IS(GATE2) Source current, GATE2 3 V VI(IN2) 5.5 V, 3 V VO(VREG) 5.5 V, VI(GATE2) = VI(IN2) + 6 V 10 14 20 A Sink current, GATE2 3 V VI(IN2) 5.5 V, 3 V VO(VREG) 5.5 V, VI(GATE2) = VI(IN2) 50 75 100 A Rise time, GATE2 Cg to GND = 1 nF (1) tr(GATE2) tf(GATE2) (1) 6 Gate voltage Fall time, GATE2 Cg to GND = 1 nF (1) VI(IN2) = 3 V VI(IN2) = 4.5 V VI(IN2) = 3 V VI(IN2) = 4.5 V Specified, but not production tested. Submit Documentation Feedback 0.5 VO(VREG) = 3 V 0.6 0.1 0.12 ms ms TPS2320 TPS2321 www.ti.com SLVS276E - MARCH 2000 - REVISED NOVEMBER 2006 ELECTRICAL CHARACTERISTICS (Continued) over recommended operating temperature range (-40C < TA < 85C), 3V VI(IN1) 13V, 3V VI(IN2) 5.5V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TIMER V(TO_TIMER) Threshold voltage, TIMER 0.4 0.5 0.6 V Charge current, TIMER VI(TIMER) = 0 V 35 50 65 A Discharge current, TIMER VI(TIMER) = 1 V 1 2.5 RISETx = 1 k 40 50 60 RISETx = 400 , TA = 25C 14 19 24 RISETx = 1 k, TA = 25C 44 50 53 RISETx = 1.5 k, TA = 25C 68 73 78 0.1 5 VO(GATEx) = 4 V 400 800 VO(GATEx) = 1 V 25 150 mA CIRCUIT BREAKER VIT(CB) I(IB_ISENSEx) Threshold voltage, circuit breaker Input bias current, ISENSEx Discharge current, GATEx tpd(CB) Propagation (delay) time, comparator inputs to gate output Cg = 50 pF, (50% to 10%), 10 mV overdrive, CTIMER = 50 pF mV A mA 1.3 s ENABLE, ACTIVE LOW (TPS2320) VIH(ENABLE) High-level input voltage, ENABLE 2 VIL(ENABLE) Low-level input voltage, ENABLE RI(ENABLE) Input pullup resistance, ENABLE See td(off_ENABLE) Turnoff delay time, ENABLE VI(ENABLE) increasing above stop threshold; 100 ns rise time, 20 mV overdrive (2) 60 s td(on_ENABLE) Turnon delay time, ENABLE VI(ENABLE) decreasing below start threshold; 100 ns fall time, 20 mV overdrive (2) 125 s (1) 100 V 200 0.8 V 300 k ENABLE, ACTIVE HIGH (TPS2321) VIH(ENABLE) High-level input voltage, ENABLE VIL(ENABLE) Low-level input voltage, ENABLE 2 RI(ENABLE) Input pulldown resistance, ENABLE td(on_ENABLE) Turnon delay time, ENABLE VI(ENABLE) increasing above start threshold; 100 ns rise time, 20 mV overdrive (2) 85 s td(off_ENABLE) Turnoff delay time, ENABLE VI(ENABLE) decreasing below stop threshold; 100 ns fall time, 20 mV overdrive (2) 100 s V(VREG) PREREG output voltage 4.5 VI(IN1) 13 V V(drop_PREREG) PREREG dropout voltage VI(IN1) = 3 V 100 V 150 0.7 V 300 k PREREG (1) (2) 3.5 4.1 5.5 V 0.1 V 1V Test IO of ENABLE at VI(ENABLE) = 1 V and 0 V, then RI(ENABLE) = I 0V * I 1V O_ O_ Specified, but not production tested. Submit Documentation Feedback 7 TPS2320 TPS2321 www.ti.com SLVS276E - MARCH 2000 - REVISED NOVEMBER 2006 ELECTRICAL CHARACTERISTICS (Continued) over recommended operating temperature range (-40C < TA < 85C), 3V VI(IN1) 13V, 3V VI(IN2) 5.5V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(TO_UVLOstart) Output threshold voltage, start 2.75 2.85 2.95 V V(TO_UVLOstop) Output threshold voltage, stop 2.65 2.78 50 75 VREG UVLO Vhys(UVLO) Hysteresis UVLO sink current, GATEx VI(GATEx) = 2 V V mV 10 mA FAULT OUTPUT VO(sat_FAULT) Output saturation voltage, FAULT IO = 2 mA Ilkg(FAULT) Leakage current, FAULT VO(FAULT) = 13 V 0.4 V 1 A DISCH1 AND DISCH2 8 I(DISCH) Discharge current, DISCHx VIH(DISCH) Discharge on high-level input voltage VIL(DISCH) Discharge on low-level input voltage VI(DISCHx) = 1.5 V, VI(VIN1) = 5 V 5 10 mA 2 V 1 Submit Documentation Feedback V TPS2320 TPS2321 www.ti.com SLVS276E - MARCH 2000 - REVISED NOVEMBER 2006 PARAMETER MEASUREMENT INFORMATION Load 12 W VI(ENABLE) 5 V/div Load 12 W VI(ENABLE) 5 V/div VO(GATE1) 10 V/div VO(DISCH1) 5 V/div VO(GATE1) 10 V/div VO(DISCH1) 5 V/div t - Time - 10 ms/div t - Time - 10 ms/div Figure 1. Turnon Voltage Transition of Channel 1 Figure 2. Turnoff Voltage Transition of Channel 1 Load 5 W VI(ENABLE) 5 V/div Load 5 W VI(ENABLE) 5 V/div VO(GATE2) 10 V/div VO(GATE2) 10 V/div VO(DISCH2) 5 V/div VO(DISCH2) 5 V/div t - Time - 10 ms/div t - Time - 10 ms/div Figure 3. Turnon Voltage Transition of Channel 2 Figure 4. Turnoff Voltage Transition of Channel 2 Submit Documentation Feedback 9 TPS2320 TPS2321 www.ti.com SLVS276E - MARCH 2000 - REVISED NOVEMBER 2006 PARAMETER MEASUREMENT INFORMATION (continued) No Capacitor on Timer VI(ENABLE) 5 V/div VI(ENABLE) 5 V/div VO(GATE1) 10 V/div No Capacitor on Timer VO(GATE1) 10 V/div VO(FAULT) 10 V/div VO(FAULT) 10 V/div IO(OUT1) 2 A/div IO(OUT1) 2 A/div t - Time - 5 ms/div t - Time - 1 ms/div Figure 5. Channel 1 Overcurrent Response: Enabled Into Overcurrent Load VI(ENABLE) 5 V/div Figure 6. Channel 1 Overcurrent Response: an Overcurrent Load Plugged Into the Enabled Board No Capacitor on Timer No Capacitor on Timer VI(ENABLE) 5 V/div VO(GATE2) 10 V/div VO(GATE2) 10 V/div VO(FAULT) 10 V/div VO(FAULT) 10 V/div IO(OUT2) 2 A/div IO(OUT2) 2 A/div t - Time - 0.5 ms/div t - Time - 2 ms/div Figure 7. Channel 2 Overcurrent Response: Enabled Into Overcurrent Load 10 Figure 8. Channel 2 Overcurrent Response: an Overcurrent Load Plugged Into the Enabled Board Submit Documentation Feedback TPS2320 TPS2321 www.ti.com SLVS276E - MARCH 2000 - REVISED NOVEMBER 2006 PARAMETER MEASUREMENT INFORMATION (continued) VI(ENABLE) 5 V/div No Capacitor on Timer VI(ENABLE) 5 V/div VO(GATE1) 10 V/div VO(GATE2) 5 V/div VO(FAULT) 10 V/div VO(FAULT) 10 V/div II(IN1) 2 A/div II(IN2) 2 A/div No Capacitor on Timer t - Time - 1 ms/div t - Time - 1 ms/div Figure 9. Channel 1 - Enabled Into Short Circuit No Capacitor on Timer Figure 10. Channel 2 - Enabled Into Short Circuit VI(IN1) 10 V/div No Capacitor on Timer VO(GATE1) 10 V/div VI(IN1) 10 V/div VO(GATE1) 10 V/div VO(OUT1) 10 V/div IO(OUT1) 1 A/div VO(OUT1) 10 V/div IO(OUT1) 1 A/div t - Time - 1 ms/div t - Time - 5 ms/div Figure 11. Channel 1 -Hot Plug Submit Documentation Feedback Figure 12. Channel 1 -Hot Removal 11 TPS2320 TPS2321 www.ti.com SLVS276E - MARCH 2000 - REVISED NOVEMBER 2006 PARAMETER MEASUREMENT INFORMATION (continued) No Capacitor on Timer VI(IN2) 5 V/div VO(GATE2) 10 V/div VO(OUT2) 5 V/div IO(OUT2) 1 A/div t - Time - 5 ms/div Figure 13. Channel 2 - Hot Plug VI(IN2) 5 V/div No Capacitor on Timer VO(GATE2) 10 V/div VO(OUT2) 5 V/div IO(OUT2) 1 A/div t - Time - 1 ms/div Figure 14. Channel 2 - Hot Removal 12 Submit Documentation Feedback TPS2320 TPS2321 www.ti.com SLVS276E - MARCH 2000 - REVISED NOVEMBER 2006 TYPICAL CHARACTERISTICS INPUT CURRENT 1 (ENABLED) vs INPUT VOLTAGE 1 INPUT CURRENT 2 (ENABLED) vs INPUT VOLTAGE 2 71.5 52 IN1 = 13 V IN2 = 5.5 V TA = 85C 50 TA = 25C 49 48 47 TA = 0C 46 TA = 0C 71 I I2 - Input Current 2 - mA I I1 - Input Current 1 - mA 51 TA = -40C TA = -40C 70.5 TA = 25C 70 TA = 85C 69.5 69 45 68.5 44 68 2.5 43 4 5 6 7 8 9 10 11 12 13 14 3 VI1 - Input Voltage 1 - V 3.5 4.5 5 5.5 Figure 15. Figure 16. INPUT CURRENT 1 (DISABLED) vs INPUT VOLTAGE 1 INPUT CURRENT 2 (DISABLED) vs INPUT VOLTAGE 2 6 23 15 TA = 85C IN2 = 5.5 V IN1 = 13 V 21 14 TA = 25C TA = 85C 19 13 I I2 - Input Current 2 - nA I I1 - Input Current 1 - nA 4 VI2 - Input Voltage 2 - V TA = -40C 12 TA = 0C 11 10 9 TA = -40C 17 15 13 11 TA = 0C 9 8 TA = 25C 7 7 4 5 6 7 8 9 10 11 12 13 14 5 2.5 VI1 - Input Voltage 1 - V 3 3.5 4 4.5 5 5.5 6 VI2 - Input Voltage 2 - V Figure 17. Figure 18. Submit Documentation Feedback 13 TPS2320 TPS2321 www.ti.com SLVS276E - MARCH 2000 - REVISED NOVEMBER 2006 TYPICAL CHARACTERISTICS (continued) GATE1 OUTPUT VOLTAGE vs INPUT VOLTAGE 1 GATE1 VOLTAGE RISE TIME vs GATE1 LOAD CAPACITANCE 18 22 CL(GATE1) = 1000 pF TA = 25C TA = 0C 18 TA = -40C 16 14 12 tr - GATE1 Voltage Rise Time - ms VO - GATE1 Output Voltage - V 20 IN1 = 12 V TA = 25C TA = 85C 15 12 9 6 3 0 10 2 3 4 5 6 7 8 9 10 11 0 12 Figure 20. GATE1 VOLTAGE FALL TIME vs GATE1 LOAD CAPACITANCE GATE1 OUTPUT CURRENT vs GATE1 VOLTAGE 12 15 IN1 = 12 V TA = 25C 14.5 IO - GATE1 Output Current - mA t f - GATE1 Voltage Fall Time - ms 9 6 Figure 19. 4 3 2 1 14 TA = -40C 0 TA = 85C 13.5 TA = 25C TA = 0C 13 12.5 12 IN1 = 13 V 11.5 11 0 3 6 9 12 14 15 CL(GATE1) - GATE1 Load Capacitance - nF Figure 21. 14 3 CL(GATE1) - GATE1 Load Capacitance - nF VI1 - Input Voltage 1 - V 16 17 18 19 20 Figure 22. Submit Documentation Feedback 21 V - GATE1 Voltage - V 22 23 24 TPS2320 TPS2321 www.ti.com SLVS276E - MARCH 2000 - REVISED NOVEMBER 2006 TYPICAL CHARACTERISTICS (continued) CIRCUIT-BREAKER RESPONSE TIME vs TIMER CAPACITANCE LOAD VOLTAGE 1 DISCHARGE TIME vs LOAD CAPACITANCE 320 t - Load Voltage 1 Discharge Time - ms IN1 = 12 V TA = 25C 9 6 3 0 IN1 = 12 V IO1 = 0 A TA = 25C 280 240 200 160 120 80 40 0 0 0.2 0.4 0.6 0.8 CTIMER - TIMER Capacitance - nF 0 1 400 100 200 300 CL - Load Capacitance - mF Figure 23. 500 Figure 24. UVLO START AND STOP THRESHOLDS vs TEMPERATURE 2.9 V ref - UVLO Start and Stop Thresholds - V t(res) - Circuit-Breaker Response Time - ms 12 2.88 2.86 Start 2.84 2.82 2.8 2.78 Stop 2.76 2.74 2.72 2.7 -45-35-25-15 -5 5 15 25 35 45 55 65 75 85 95 TA - Temperature - C Figure 25. Submit Documentation Feedback 15 TPS2320 TPS2321 www.ti.com SLVS276E - MARCH 2000 - REVISED NOVEMBER 2006 APPLICATION INFORMATION Figure 26 shows a typical dual hot-swap application. The pullup resistor at FAULT should be relatively large (e.g., 100 k) to reduce power loss, unless it is required to drive a large load. System Board RSENSE1 3 V 13 V IN1 1 F 10 F VO1 + RISET1 0.1 F VREG IN1 ISET1 ISENSE1 GATE1 ENABLE ENABLE DGND AGND TIMER IN2 DISCH1 FAULT ISET2 ISENSE2 GATE2 DISCH2 RISET2 3 V 5.5 V IN2 1 F 10 F FAULT TPS2321 VO1 or VO2 VO2 RSENSE2 + Figure 26. Typical Dual Hot-Swap Application INPUT CAPACITOR A 0.1-F ceramic capacitor in parallel with a 1-F ceramic capacitor should be placed on the input power terminals near the connector on the hot-plug board to help stabilize the voltage rails on the cards. The TPS2320/01 does not need to be mounted near the connector or to these input capacitors. For applications with more severe power environments, a 2.2-F, or higher, ceramic capacitor is recommended near the input terminals of the hot-plug board. A bypass capacitor for IN1 and for IN2 should be placed close to the device. OUTPUT CAPACITOR A 0.1-F ceramic capacitor is recommended per load on the TPS2320/21; these capacitors should be placed close to the external FETs and to TPS2320/21. A larger bulk capacitor is also recommended on the load. The value of the bulk capacitor should be selected based on the power requirements and the transients generated by the application. EXTERNAL FET To deliver power from the input sources to the loads, each channel needs an external N-channel MOSFET. A few widely used MOSFETs are shown in Table 2. But many other MOSFETs on the market can also be used with TPS23xx in hot-swap systems. Table 2. Some Available N-Channel MOSFETs CURRENT RANGE (A) 0 to 2 16 PART NUMBER DESCRIPTION MANUFACTURER IRF7601 N-channel, rDS(on) = 0.035 , 4.6 A, Micro-8 International Rectifier MTSF3N03HDR2 N-channel, rDS(on) = 0.040 , 4.6 A, Micro-8 ON Semiconductor MMSF5N02HDR2 Dual N-channel, rDS(on) = 0.04 , 5 A, SO-8 ON Semiconductor Submit Documentation Feedback TPS2320 TPS2321 www.ti.com SLVS276E - MARCH 2000 - REVISED NOVEMBER 2006 APPLICATION INFORMATION (continued) Table 2. Some Available N-Channel MOSFETs (continued) CURRENT RANGE (A) 2 to 5 5 to 10 PART NUMBER DESCRIPTION MANUFACTURER IRF7401 N-channel, rDS(on) = 0.022 , 7 A, SO-8 International Rectifier MMSF5N02HDR2 N-channel, rDS(on) = 0.025 , 5 A, SO-8 ON Semiconductor IRF7313 Dual N-channel, rDS(on) = 0.029 , 5.2 A, SO-8 International Rectifier SI4410 N-channel, rDS(on) = 0.020 , 8 A, SO-8 Vishay Dale IRLR3103 N-channel, rDS(on) = 0.019 , 29 A, d-Pak International Rectifier IRLR2703 N-channel, rDS(on) = 0.045 , 14 A, d-Pak International Rectifier TIMER For most applications, a minimum capacitance of 50 pF is recommended to prevent false triggering. A capacitor should be connected between TIMER and ground. The presence of an overcurrent condition on either channel of the TPS2320/TPS2321 causes a 50-A current source to begin charging this capacitor. If the over-current condition persists until the capacitor has been charged to approximately 0.5 V, the TPS2320/TPS2321 latches off the offending channels and pulls the FAULT pin low. The timer capacitor can be made as large as desired to provide additional time delay before registering a fault condition. PWRGDx will not correctly report power conditions when the device is disabled. The time delay is approximately: dt(sec) = CTIMER(F) x 10,000(). OUTPUT-VOLTAGE SLEW-RATE CONTROL When enabled, the TPS2320/TPS2321 controllers supply the gates of each external MOSFET transistor with a current of approximately 15 A. The slew rate of the MOSFET source voltage is thus limited by the gate-to-drain capacitance Cgd of the external MOSFET capacitor to a value approximating: dV s 15 mA + dt C gd (1) If a slower slew rate is desired, an additional capacitance can be connected between the gate of the external MOSFET and ground. VREG CAPACITOR The internal voltage regulator connected to VREG requires an external capacitor to ensure stability. A 0.1-F or 0.22-F ceramic capacitor is recommended. GATE-DRIVE CIRCUITRY The TPS2320/TPS2321 includes four separate features associated with each gate-drive terminal: * A charging current of approximately 15 A is applied to enable the external MOSFET transistor. This current is generated by an internal charge pump that can develop a gate-to-source potential (referenced to DISCH1 or DISCH2) of 9 V-12 V. DISCH1 and DISCH2 must be connected to the respective external MOSFET source terminals to ensure proper operation of this circuitry. * A discharge current of approximately 75 A is applied to disable the external MOSFET transistor. Once the transistor gate voltage has dropped below approximately 1.5 V, this current is disabled and the UVLO discharge driver is enabled instead. This feature allows the part to enter a low-current shutdown mode while ensuring that the gates of the external MOSFET transistors remain at a low voltage. * During a UVLO condition, the gates of both MOSFET transistors are pulled down by internal PMOS transistors. These transistors continue to operate even if IN1 and IN2 are both at 0 V. This circuitry also helps hold the external MOSFET transistors off when power is suddenly applied to the system. * During an overcurrent fault condition, the external MOSFET transistor that exhibited an overcurrent condition will be rapidly turned off by an internal pulldown circuit capable of pulling in excess of 400 mA (at 4 V) from the pin. Once the gate has been pulled below approximately 1.5 V, this driver is disengaged and the UVLO driver is enabled instead. If one channel experiences an overcurrent condition and the other does not, then Submit Documentation Feedback 17 TPS2320 TPS2321 www.ti.com SLVS276E - MARCH 2000 - REVISED NOVEMBER 2006 only the channel that is conducting excessive current will be turned off rapidly. The other channel will continue to operate normally. SETTING THE CURRENT-LIMIT CIRCUIT-BREAKER THRESHOLD Using channel 1 as an example, the current sensing resistor RISENSE1 and the current-limit-setting resistor RISET1 determine the current limit of the channel, and can be calculated by the following equation: R 50 10 -6 I LMT1 + ISET1 R ISENSE1 (2) Typically RISENSE1 is very small (0.001 to 0.1 ). If the trace and solder-junction resistances between the junction of RISENSE1 and ISENSE1 and the junction of RISENSE1 and RISET1 are greater than 10% of the RISENSE1 value, then these resistance values should be added to the RISENSE1 value used in the calculation above. The above information and calculation also apply to channel 2. Table 3 shows some of the current sense resistors available in the market. Table 3. Some Current Sense Resistors CURRENT RANGE (A) PART NUMBER DESCRIPTION 0 to 1 WSL-1206, 0.05 1% 0.05 , 0.25 W, 1% resistor 1 to 2 WSL-1206, 0.025 1% 0.025 , 0.25 W, 1% resistor 2 to 4 WSL-1206, 0.015 1% 0.015 , 0.25 W, 1% resistor 4 to 6 WSL-2010, 0.010 1% 0.010 , 0.5 W, 1% resistor 6 to 8 WSL-2010, 0.007 1% 0.007 , 0.5 W, 1% resistor 8 to 10 WSR-2, 0.005 1% 0.005 , 0.5 W, 1% resistor MANUFACTURER Vishay Dale UNDERVOLTAGE LOCKOUT (UVLO) The TPS2320/TPS2321 includes an undervoltage lockout (UVLO) feature that monitors the voltage present on the VREG pin. This feature will disable both external MOSFETs if the voltage on VREG drops below 2.78 V (nominal) and will re-enable normal operation when it rises above 2.85 V (nominal). Since VREG is fed from IN1 through a low-dropout voltage regulator, the voltage on VREG will track the voltage on IN1 within 50 mV. While the undervoltage lockout is engaged, both GATE1 and GATE2 are held low by internal PMOS pulldown transistors, ensuring that the external MOSFET transistors remain off at all times, even if all power supplies have fallen to 0 V. SINGLE-CHANNEL OPERATION Some applications may require only a single external MOS transistor. Such applications should use GATE1 and the associated circuitry (IN1, ISENSE1, ISET1, DISCH1). The IN2 pin should be grounded to disable the circuitry associated with the GATE2 pin. POWER-UP CONTROL The TPS2320/TPS2321 includes a 500 s (nominal) startup delay that ensures that internal circuitry has sufficient time to start before the device begins turning on the external MOSFETs. This delay is triggered only upon the rapid application of power to the circuit. If the power supply ramps up slowly, the undervoltage lockout circuitry will provide adequate protection against undervoltage operation. 3-CHANNEL HOT-SWAP APPLICATION Some applications require hot-swap control of up to three voltage rails, but may not explicitly require the sensing of the status of the output power on all three of the voltage rails. One such application is device bay, where dv/dt control of 3.3 V, 5 V, and 12 V is required. By using Channel 2 to drive both the 3.3-V and 5-V power rails and Channel 1 to drive the 12-V power rail, as is shown below, TPS2320/01 can deliver three different voltages to three loads while monitoring the status of two of the loads. 18 Submit Documentation Feedback TPS2320 TPS2321 www.ti.com SLVS276E - MARCH 2000 - REVISED NOVEMBER 2006 System Board RSENSE1 12 V IN1 1 F 10 F + VO1 RISET1 0.1 F VREG ENABLE IN1 ISET1 ISENSE1 ENABLE DGND AGND TIMER 1 F 10 F DISCH1 FAULT FAULT TPS2321 IN2 ISET2 ISENSE2 RISET2 3.3 V IN2 GATE1 GATE2 DISCH2 VO1 or VO2 Rg1 VO2 + RSENSE2 Rg2 5 V IN3 VO3 1 F 10 F + Figure 27. Three-Channel Application Figure 28 shows ramp-up waveforms of the three output voltages. VO - Output Voltage - 2 V/div VO1 VO3 VO2 t - Time - 2.5 ms/div Figure 28. Submit Documentation Feedback 19 PACKAGE OPTION ADDENDUM www.ti.com 30-Jul-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TPS2320ID ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2320IDG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2320IDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2320IDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2320IPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2320IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2320IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2320IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2321ID ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2321IDG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2321IPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2321IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2321IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2321IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 30-Jul-2011 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS2320IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TPS2320IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TPS2321IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2320IDR SOIC D 16 2500 333.2 345.9 28.6 TPS2320IPWR TSSOP PW 16 2000 367.0 367.0 35.0 TPS2321IPWR TSSOP PW 16 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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