High Speed Super Low Power SRAM 128K-Word By 16 Bit CS16LV20493 Revision History Rev. No. History Issue Date 1.0 Initial issue Jan.17, 2005 1.1 Add 48 CSP-6x8mm Sep. 16, 2005 1.2 Revise DC characteristics Apr. 11, 2008 1.3 Remove 48 Mini BGA 6*8 mm package type Add 48 Mini BGA 6*7 mm package type 1 Remark Jul. 05, 2010 Rev. 1.3 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV20493 128K-Word By 16 Bit GENERAL DESCRIPTION The CS16LV20493 is a high performance; high speed and super low power CMOS Static Random Access Memory organized as 131,072 words by 16bits and operates from a wide range of 2.7 to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed, super low power features and maximum access time of 55/70ns in 3.0V operation. Easy memory expansion is provided by an active LOW chip enable inputs (/CE1, CE2) and active LOW output enable (/OE). The CS16LV20493 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The CS16LV20493 is available in JEDEC standard 44-pin TSOP 2 and 48-ball mini_BGA-6x7mm packages. FEATURES Wide operation voltage : 2.7 ~ 3.6V Ultra low power consumption : 3mA 1MHz (Max.) , Vcc=3.0V. 0.5 uA (Typ.) CMOS standby current High speed access time : 55/70ns. Automatic power down when chip is deselected. Three state outputs and TTL compatible. Data retention supply voltage as low as 1.5V. Easy expansion with (/CE1, CE2) and /OE options. Product Family Part No. Operating Temp Vcc. Range Speed (ns) o 0~70 C CS16LV20493 55/ 70 Standby (Typ.) 0.5uA (Vcc = 3.0V) 2.7~3.6 o -40~85 C 55/ 70 2 0.8uA (Vcc= 3.0V) Package Type 44 TSOP 2 48 Mini BGA 6*7mm Dice 44 TSOP 2 48 Mini BGA 6*7mm Dice Rev. 1.3 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 128K-Word By 16 Bit CS16LV20493 PIN CONFIGURATION FUNCTIONAL BLOCK DIAGRAM 3 Rev. 1.3 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV20493 128K-Word By 16 Bit PIN DESCRIPTIONS Name Type A0 A16 Input Function Address inputs for selecting one of the 131,072 x 16 bit words in the RAM /CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when /CE1, CE2 Input data read from or write to the device. If either chip enable is not active, the device is deselected and in a standby power down mode. The DQ pins will be in high impedance state when the device is deselected. The Write enable input is active LOW. It controls read and write operations. With the /WE Input chip selected, when /WE is HIGH and /OE is LOW, output data will be present on the DQ pins, when /WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is /OE Input selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when /OE is inactive. /LB, /UB Input DQ0~DQ15 I/O Vcc Power Power Supply Gnd Power Ground Lower byte and upper byte data input/output control pins. These 16 bi-directional ports are used to read data from or write data into the RAM. TRUTH TABLE MODE Standby Output Disabled Read Write /CE1 CE2 /WE /OE /LB /UB X L X X X X H X X X X X L H H H X X X X H H L L L H H H L L X 4 DQ0~7 DQ8~15 Vcc Current High Z High Z ICCSB, ICCSB1 High Z High Z ICC L DOUT DOUT ICC H L High Z DOUT ICC L H DOUT High Z ICC L L DIN DIN ICC H L X DIN ICC L H DIN X ICC Rev. 1.3 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV20493 128K-Word By 16 Bit ABSOLUTE MAXIMUM RATINGS (1) Symbol VTERM Parameter Rating Terminal Voltage with Respect to GND -0.5 to Vcc+0.5 Temperature Under Bias TBIAS Unit V -40 to +125 O -60 to +150 O C TSTG Storage Temperature PT Power Dissipation 1.0 W IOUT DC Output Current 25 mA C 1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Range Ambient Temperature Vcc o Commercial 0~70 C 2.7V ~3.6V Industrial -40~85oC 2.7V ~ 3.6V 1. Overshoot : Vcc +2.0V in case of pulse width 2. Undershoot : - 2.0V in case of pulse width 20ns. 20ns. 3. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE (1) (TA = 25oC, f =1.0 MHz) Symbol Parameter Conditions MAX. Unit CIN Input Capacitance VIN=0V 6 pF CDQ Input/Output Capacitance VI/O=0V 8 pF 1. This parameter is guaranteed, and not 100% tested. 5 Rev. 1.3 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV20493 128K-Word By 16 Bit DC ELECTRICAL CHARACTERISTICS Name Parameter o Test Condition VIL Guaranteed Input Low Voltage VIH Guaranteed Input High Voltage IIL Input Leakage Current (2) (2) o (TA = 0 ~70 C, Vcc = 3.0V ) MIN TYP(1) MAX Unit Vcc=3.0V -0.5 0.8 V Vcc=3.0V 2.0 Vcc+0.2 V VCC=MAX, VIN=0 to VCC -1 1 uA -1 1 uA 0.4 V VCC=MAX, /CE1=VIh, or Output Leakage Current IOL /OE=VIh ,or /WE= VIL VIO=0V to VCC VOL Output Low Voltage VCC=MAX, IOL =2.0mA VOH Output High Voltage VCC=MIN, IOH = -1.0mA ICC Operating Power Supply Current ICCSB TTL Standby Supply ICCSB1 CMOS Standby Current 2.4 V /CE1=VIL, IDQ=0mA, F=FMAX =1/ tRC 25 mA 1 mA 4 uA /CE1=V IH, IDQ=0mA, /CE1 VCC-0.2V, V IN VCC-0.2V or VIN 0.5 0.2V, o 1. Typical characteristics are at TA = 25 C. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC. DATA RETENTION CHARACTERISTICS (TA = 0o ~70oC) Name VDR ICCDR TCDR tR Parameter Test Condition VCC for Data Retention /CE1 VCC-0.2V, V IN VCC-0.2V Data Retention Current /CE1 VCC-0.2V, V CC =1.5V VIN VCC-0.2V or V IN Operation Recovery o 0.2V TYP(1) MAX 1.5 Unit V 0.3 2 uA 0 ns tRC (2) ns Refer to Retention Waveform Time 1.TA = 25 C, or VIN 0.2V Chip Deselect to Data Retention Time MIN 2. tRC= Read Cycle Time 6 Rev. 1.3 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV20493 128K-Word By 16 Bit AC TEST CONDITIONS Input Pulse Levels Vcc/0V Input Rise and Fall Times Input and Output Timing Reference Level Output Load KEY TO SWITCHING WAVEFORMS WAVEFORMS 5ns INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY 0.5Vcc See FIGURE 1A MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H DONT CARE ANY CHANGE PERMITTED CHANGE STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE OFF STATE and 1B LOW Vcc DATA RETENTION WAVEFORM(1) ( /CE1 Controlled ) LOW Vcc DATA RETENTION WAVEFORM(2) ( CE2 Controlled ) 7 Rev. 1.3 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV20493 128K-Word By 16 Bit AC TEST LOADS AND WAVEFORMS OUTPUT TERMINAL EQUIVALENT 667 ALL INPUT PULSES VCC GND FIGURE 1A 90% 10% 5ns 5ns AC ELECTRICAL CHARACTERISTICS (TA = 0o ~70oC < READ CYCLE > JEDEC Parameter Name Name 90% 10% FIGURE 2 FIGURE 1B 1.73V Description Vcc=3.0V ) -55 MIN -70 MAX 55 MIN MAX tAVAX tRC Read Cycle Time tAVQV tAA Address Access Time 55 70 ns tELQV tCO Chip Select Access Time (/CE1) 55 70 ns tBA tBA Data Byte Control Access Time (/LB, /UB) 25 35 ns tGLQV tOE Output Enable to Output Valid 25 35 ns tELQX tLZ iChip Select to Output Low Z (/CE1) 10 10 ns tBE tBLZ Data Byte Control to Output Low Z (/LB, /UB) 5 5 ns tGLQX tOLZ Output Enable to Output in Low Z 5 5 ns tEHQZ tHZ Chip Deselect to Output in High Z (/CE1) 0 20 0 25 ns tBDO tBHZ Data Byte Control to Output High Z (/LB, /UB) 0 20 0 25 ns tGHQZ tOHZ Output Disable to Output in High Z 0 20 0 25 ns tAXOX tOH Out Disable to Address Change 10 8 70 Unit ns 10 ns Rev. 1.3 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 128K-Word By 16 Bit CS16LV20493 SWITCHING WAVEFORMS (READ CYCLE) NOTES: 1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 9 Rev. 1.3 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV20493 128K-Word By 16 Bit AC ELECTRICAL CHARACTERISTICS (TA = 0o ~70oC < WRITE CYCLE > JEDEC Name Symbol Description Vcc=3.0V -55 MIN MAX ) -70 MIN MAX Unit tAVAX tWC Write Cycle Time 55 70 ns tE1LWH tCW Chip Select to End of Write 45 60 ns tAVWL tAS Address Setup Time 0 0 ns tAVWH tAW Address Valid to End of Write 45 60 ns tBW tBW /UB, /LB valid to end of write 45 60 ns tWLWH tWP Write Pulse Width 40 50 ns tWHAX tWR Write Recovery Time 0 0 ns tWLQZ tWHZ Write to Output in High Z tDVWH tDW Data to Write Time Overlap 25 30 ns tWHDX tDH Data Hold for Write End 0 0 ns tGHQZ tOHZ Output Disable to Output in High Z 0 tWHOX tOW End of Write to Output Active 5 25 30 30 0 ns 30 ns 5 ns SWITCHING WAVEFORMS (WRITE CYCLE) 10 Rev. 1.3 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 128K-Word By 16 Bit CS16LV20493 11 Rev. 1.3 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 128K-Word By 16 Bit CS16LV20493 NOTES: 1. A write occurs during the overlap(t WP) of low /CE1, high CE2 and low /WE. A write begins when /CE1 goes low and /WE goes low with asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CE1 goes high, CE2 goes low and /WE goes high. The t WP is measured from the beginning of the write to the end of write. 2. tCW is measured from the /CE1 going low or CE2 going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. T WR applied in case a write ends as /CE1 or /WE going high or CE2 going low. ORDER INFORMATION Note: Package material code P & R meets RoHS 12 Rev. 1.3 Chiplus reserves the right to change product or specification without notice.