FLAT PACK CRYSTAL CLOCK OSCILLATORS -5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.12Hz to 200MHz Q-TECH CORPORATION Description Q-Tech's flat pack crystal oscillators consist of a source clock square wave generator, logic output buffers and/or logic divider stages, and a round AT highprecision quartz crystal built in an all metal flat package. Features * Made in the USA * ECCN: 3A001.b.10 * DFARS 252-225-7014 Compliant: Electronic Component Exemption * USML Registration # M17677 * Wide frequency range from 0.12Hz to 200MHz * Available as QPL MIL-PRF-55310/21 (TTL) QT24 only * Choice of flat packs and pin outs * Choice of supply voltages * Choice of output logic options * AT-Cut crystal * All metal hermetically sealed package * Tight or custom symmetry available * Capacitive load drive capability (Z output) * Low height * External tuning capacitor option * Fundamental and third overtone designs * Tristate function option D * Three-point crystal mounts * Custom design available tailors to meet customer's needs * Q-Tech does not use pure lead or pure tin in its products * RoHS compliant Applications * Designed to meet today's requirements for all voltage applications * Wide military clock applications * Industrial controls * Microcontroller driver Ordering Information Sample part number QT24ACD10M-20.000MHz QT 24 AC D 10 M - 20.000MHz T = Standard S = Solder Dip (*) Output frequency Model # (See page 3) C AC HC T L N R E EH EF PE LP Z = = = = = = = = = = = = = CMOS +5V to +15V (**) ACMOS +5V HCMOS +5V TTL +5V LVHCMOS +3.3V LVHCMOS +2.5V LVHCMOS +1.8V 10K ECL -5.2V 10KH ECL -5.2V 100K/300K ECL -4.5V PECL +5V PECL +3.3V Z output Tristate Option D (Left blank if no Tristate) Screened to MIL-PRF-55310,level B (Left blank if no screening) 1= 4= 5= 6= 9= 10 = 11 = 12 = 100ppm at 0C to +70C 50ppm at 0C to +70C 25ppm at -20C to +70C 50ppm at -55C to +105C 50ppm at -55C to +125C 100ppm at -55C to +125C 50ppm at -40C to +85C 100ppm at -40C to +85C (*) Hot Solder Dip Sn60 per MIL-PRF 55310 is optional for an additional cost (**) Please specify supply voltage when ordering CMOS For frequency stability vs. temperature options not listed herein, request a custom part number. For Non-Standard requirements, contact Q-Tech Corporation at Sales@Q-Tech.com Packaging Options * Standard packaging in a locked anti-static cardboard Other Options Available For An Additional Charge * Lead forming available on all packages. Please contact for details. * P. I. N. D. test (MIL-STD 883, Method 2020) * Lead trimming All Flat Pack packages are available in surface mount form. Specifications subject to change without prior notice. Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com Flat Pack (Revision E, June 2010) (ECO# 9856) 1 FLAT PACK CRYSTAL CLOCK OSCILLATORS -5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.12Hz to 200MHz Q-TECH CORPORATION Electrical Characteristics Parameters Output freq. range QT21, 24, 25 (Fo) QT22, 26, 28 Supply voltage (Vdd) Maximum Applied Voltage (Vdd max.) C AC HC T L (*) ECL / PECL (**) 500Hz -- 15MHz 500Hz -- 125MHz 0.12Hz -- 125MHz 0.12Hz -- 125MHz 0.12Hz -- 160MHz 1MHz -- 200MHz 500Hz -- 15MHz 500Hz -- 85MHz 500Hz -- 85MHz 500Hz -- 85MHz 500Hz -- 85MHz 5V ~ 15Vdc 10% 5.0Vdc 10% 3.3Vdc 10% -0.5 to +18Vdc -0.5 to +7.0Vdc -0.5 to +5.0Vdc Freq. stability (F/T) See Option codes Operating temp. (Topr) See Option codes Storage temp. (Tsto) Operating supply current (Idd) (No Load) Symmetry (50% of ouput waveform or 1.4Vdc for TTL) 0 to -8.0Vdc (10K / 10KHECL) 0 to +8.0Vdc (PECL) 0 to +5.0Vdc (LVPECL) -62C to + 125C F and Vdd dependent 3 mA max. at 5V up to 5MHz 25 mA max. at 15V up to 15MHz 20 mA max. 25 mA max. 35 mA max. 45 mA max. 60 mA max. - 0.12Hz ~ 16MHz ~ 40MHz ~ 60MHz ~ 85MHz ~ < < < < 3 mA max. - 0.12Hz ~ < 500kHz 6 mA max. - 500kHz ~ < 16MHz 10 mA max. - 16MHz ~ < 32MHz 20 mA max. - 32MHz ~ < 60MHz 30 mA max. - 60MHz ~ < 100MHz 40 mA max. - 100MHz ~ < 130MHz 50 mA max. - 130MHz ~ 160MHz 16MHz 40MHz 60MHz 85MHz 125MHz 45/55% max. Fo < 4MHz 40/60% max. Fo 4MHz 45/55% max. Fo < 12MHz 40/60% max. Fo 12MHz 30ns max. 15ns max. Fo < 15kHz 6ns max. Fo 15kHz ~ 39.999MHz 3ns max. Fo 40MHz ~ 160 MHz (Measured from 10% to 90% CMOS or from 0.8V to 2.0V TTL) Rise and Fall times (with typical load) (Measured from 10% to 90%) Output Load 45 mA max. - 8MHz ~ < 125MHz 75 mA max. - 125MHz ~ 200MHz 45/55% max. Fo < 12MHz 40/60% max. Fo 12MHz 3.5ns max. Fo < 125MHz 3ns max. Fo 125MHz ~ 200MHz (Measured from 20% to 80%) 15pF // 10k 10TTL Fo < 20MHz 6TTL Fo 20MHz 0.9 x Vdd min.; 0.1 x Vdd max. 2.4V min.; 0.4V max. 0.9 x Vdd min.; 0.1 x Vdd max. -1.6mA / TTL +40A / TTL 4mA . -50mA VIH 0.7 x Vdd Oscillation; VIL 0.3 x Vdd High Impedance Call for details 15ps typ. - < 40MHz 8ps typ. - 40MHz Integrated phase jitter 12kHz - 20MHz 1ps typ. Start-up time (Tstup) 15pF // 10k 50 to -2V (10K / 10KH) 50 to Vcc -2V (P & LP) 10ms max. Output voltage (Voh/Vol) Output Current (Ioh/Iol) 8MHz -- 85MHz -5.2Vdc 5% (10K / 10KHECL) 5Vdc 5% (PECL) 3.3Vdc 5% (LVPECL) 1mA typ. at 5V 6.8mA typ. at 15V Enable/Disable Tristate function 8 mA 24mA VIH 2.2V Oscillation; VIL 0.8V High Impedance Call for details 8ps typ. - < 40MHz 5ps typ. - 40MHz Jitter RMS 1 (at 25C) -1.15V min; -1.54V max. (E) 4V min.; 3.37V max. (PE) 2.27V min.; 1.68V max. (LP) 5ppm max. first year / 2ppm typ. per year thereafter Aging (at 70C) (*) Available in 2.5Vdc (N) or 1.8Vdc (R) (**) Please contact Q-Tech for details on 100KECL logic (EF) Z Output logic can drive up to 200 pF load with typical 6ns rise & fall times (tr, tf) Q-TECH Corporation - Flat Pack (Revision E, June 2010) (ECO# 9856) 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech .co m 2 FLAT PACK CRYSTAL CLOCK OSCILLATORS -5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.12Hz to 200MHz Q-TECH CORPORATION Package Configuration Versus Pin Connections A B C D QT21 QT22 QT24 QT25 .120 .140 (3.05) (3.56) .085/.070 .010 (2.16/1.78) (.254) .625 .050 (15.88) Q-TECH P/N FREQ. D/C S/N Q-TECH P/N FREQ. D/C S/N Q-TECH P/N FREQ. D/C S/N .120 MAX. (3.05) .060/.035 .010 (1.52/.889) (.254) .050 (1.27) 10 8 11 .010 (.254) .625 SQ. (15.88) 11 .350 (8.89) 1 1 .500 (.381) .015 .500 MIN. 10 .450 .450 (11.43) (12.70) 1 20 20 .015 .500 (.381) MIN. .500 (.381) MIN. (12.70) (12.70) E F QT26 QT28 QT # Conf Vcc GND Case Q-TECH P/N Q-TECH P/N FREQ. D/C S/N FREQ. D/C S/N .120 MAX. (3.05) (4.06) .05 MIN. (1.27) .010 (1.78) 11 (11.43) .015 (12.70) .070 SQ. 16 .015 20 .160 (15.88) .050 (1.27) 10 9 .450 (.381) .060/.045 (1.52/1.14) .500 (12.70) (11.43) 1 .010 (.254) (1.27) (1.27) MAX. (3.81) .060/.045 .050 (9.53) .150 MAX. (1.52/1.14) .625 .375 SQ. Q-TECH P/N FREQ. D/C S/N .05 MIN. (1.27) (.254) Output (*) E/D or N/C Equivalent MIL-PRF-55310 Configuration QT21 A 13 10 10 11 12 N/A QT22 B 8 9 9 10 11 N/A QT24 C 13 10 10 11 12 /21 = QT24T QT25 D 13 10 10 11 12 N/A QT26 E 14 7 7 8 6 N/A QT28 F 8 9 9 10 11 N/A MAX. .010 (.254) .590 .375 .100 (14.99) .050 (*) ECL / PECL complimentary output available on pin 12 (9.53) (1.27) (2.54) 7 8 8 9 .790 .600 .350 (8.89) (20.07) 1 (15.24) .015 (.381) 1 14 .015 (.381) .500 MIN. (12.70) Dimensions are in inches (mm) 16 .15 (3.81) .500 (12.70) (except QT22, 26, & 28) with a Q-Tech custom part number Package Information * Package material (Header and Leads): Kovar * Lead finish: Gold Plated - 50 ~ 80 inches Nickel Underplate - 100 ~ 250 inches * Cover: Kovar, Gold Plated - 50 ~ 100 inches Nickel Underplate - 70 ~ 90 inches * Package to lid attachment: Seam weld * Weight: 2.0g typ., 4.0g max. Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com Flat Pack (Revision E, June 2010) (ECO# 9856) 3 MIN. FLAT PACK CRYSTAL CLOCK OSCILLATORS -5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.12Hz to 200MHz Q-TECH CORPORATION Output Waveform (Typical) Test Circuit TH SYMMETRY = x 100% T Typical test circuit for ECL logic. Tr mA GND Tf Vdd VOH OUT OUT + 0.9xVdd Vee POWER SUPPLY + 0.1F or 0.01F Vdc - 50 - 0.5xVdd -2Vdc 0.1xVdd -4.5V or -5.2V VOL GND TH T Startup Time Vdd Typical test circuit for TTL logic. TYPICAL SET-UP FOR START-UP TIME RL + - mA Vdd OUT OUT E/D GND + + POWER SUPPLY - 0.1F or 0.01F Vdc - LOAD 6 TTL CL(*) 12pF RL 430 RS 10k 10 TTL 20pF 270 6k Variable Ramp Oscilloscope 54616B Agilent CL DUT Rs Ts Start-up box (*) CL inclides the loading effect of the oscilloscope probe. Supply Current Typical test circuit for CMOS logic TYPICAL SUPPLY CURRENT ICC (mA) AT 3.3Vdc & 5.0Vdc CMOS Logic NO LOAD Vdd Out Output 0.1F or E/D GND 0.01F + Vdc - 40 35 30 15pF (*) 10k Icc (mA) + mA + Power supply - 45 Ground 25 20 15 10 5 Tristate Function 0 0.5 2 (*) CL includes probe and jig capacitance 8 16 24 27 32 36 40 48 50 55 65 70 75 85 100 125 133 150 160 Freq(MHz) The Tristate function on pin 1 has a built-in pull-up resistor typical 50k, so it can be left floating or tied to Vdd without deteriorating the electrical performance. Icc 3.3V Icc 5V Frequency vs. Temperature Curve 50 FREQUENCY STABILITY VERSUS TEMPERATURE QT24T- 48.000MHz 40 Frequency Stability (PPM) 30 20 10 0 -10 -20 -30 -40 -50 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 Temperature (C) 2_5 3_5 4_5 5_5 Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com Flat Pack (Revision E, June 2010) (ECO# 9856) 4 FLAT PACK CRYSTAL CLOCK OSCILLATORS -5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.12Hz to 200MHz Q-TECH CORPORATION Thermal Characteristics The heat transfer model in a hybrid package is described in figure 1. D/A epoxy Die D/A epoxy 45 Heat spreading occurs when heat flows into a material layer of increased cross-sectional area. It is adequate to assume that spreading occurs at a 45 angle. The total thermal resistance is calculated by summing the thermal resistances of each material in the thermal path between the device and hybrid case. 45 Heat Hybrid Case R1 R2 Die D/A epoxy R3 Substrate R4 D/A epoxy R5 Hybrid Case (Figure 1) RT = R1 + R2 + R3 + R4 + R5 The total thermal resistance RT (see figure 2) between the heat source (die) to the hybrid case is the Theta Junction to Case (Theta JC) inC/W. T A CA * Theta junction to case (Theta JC) for this product is 30C/W. * Theta case to ambient (Theta CA) for this part is 100C/W. * Theta Junction to ambient (Theta JA) is 130C/W. T C T J Die JC Maximum power dissipation PD for this package at 25C is: * PD(max) = (TJ (max) - TA)/Theta JA * With TJ = 175C (Maximum junction temperature of die) * PD(max) = (175 - 25)/130 = 1.15W Substrate JA JC CA (Figure 2) Environmental Specifications Q-Tech Standard Screening/QCI (MIL-PRF55310) is available for all of our Flat Packs. Q-Tech can also customize screening and test procedures to meet your specific requirements. The Flat Packs are designed and processed to exceed the following test conditions: Environmental Test Temperature cycling Constant acceleration Seal: Fine and Gross Leak Burn-in Aging Vibration sinusoidal Shock, non operating Thermal shock, non operating Ambient pressure, non operating Resistance to solder heat Moisture resistance Terminal strength Resistance to solvents Solderability ESD Classification Moisture Sensitivity Level Test Conditions MIL-STD-883, Method 1010, Cond. B MIL-STD-883, Method 2001, Cond. A, Y1 MIL-STD-883, Method 1014, Cond. A and C 160 hours, 125C with load 30 days, 70C, 1.5ppm max MIL-STD-202, Method 204, Cond. D MIL-STD-202, Method 213, Cond. I MIL-STD-202, Method 107, Cond. B MIL-STD-202, 105, Cond. C, 5 minutes dwell time minimum MIL-STD-202, Method 210, Cond. C MIL-STD-202, Method 106 MIL-STD-202, Method 211, Cond. C MIL-STD-202, Method 215 MIL-STD-202, Method 208 MIL-STD-883, Method 3015, Class 1HBM 0 to 1,999V J-STD-020, MSL=1 Please contact Q-Tech for higher shock requirements Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com Flat Pack (Revision E, June 2010) (ECO# 9856) 5 FLAT PACK CRYSTAL CLOCK OSCILLATORS -5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.12Hz to 200MHz Q-TECH CORPORATION Period Jitter As data rates increase, effects of jitter become critical with its budgets tighter. Jitter is the deviation of a timing event of a signal from its ideal position. Jitter is complex and is composed of both random and deterministic jitter components. Random jitter (RJ) is theoretically unbounded and Gaussian in distribution. Deterministic jitter (DJ) is bounded and does not follow any predictable distribution. DJ is also referred to as systematic jitter. A technique to measure period jitter (RMS) one standard deviation (1) and peak-to-peak jitter in time domain is to use a high sampling rate (>8G samples/s) digitizing oscilloscope. Figure shows an example of peak-to-peak jitter and RMS jitter (1) of a QT24L-20MHz, at 3.3Vdc. Phase Noise and Phase Jitter Integration RMS jitter (1): 5.75ps Peak-to-peak jitter: 60ps Phase noise is measured in the frequency domain, and is expressed as a ratio of signal power to noise power measured in a 1Hz bandwidth at an offset frequency from the carrier, e.g. 10Hz, 100Hz, 1kHz, 10kHz, 100kHz, etc. Phase noise measurement is made with an Agilent E5052A Signal Source Analyzer (SSA) with built-in outstanding low-noise DC power supply source. The DC source is floated from the ground and isolated from external noise to ensure accuracy and repeatability. In order to determine the total noise power over a certain frequency range (bandwidth), the time domain must be analyzed in the frequency domain, and then reconstructed in the time domain into an rms value with the unwanted frequencies excluded. This may be done by converting L(f) back to S(f) over the bandwidth of interest, integrating and performing some calculations. Symbol Definition L(f) Integrated single side band phase noise (dBc) S (f)=(180/)x2 L(f)df Spectral density of phase modulation, also known as RMS phase error (in degrees) RMS jitter = S (f)/(fosc.360) Jitter(in seconds) due to phase noise. Note S (f) in degrees. The value of RMS jitter over the bandwidth of interest, e.g. 10kHz to 20MHz, 10Hz to 20MHz, represents 1 standard deviation of phase jitter contributed by the noise in that defined bandwidth. Figure below shows a typical Phase Noise/Phase jitter of a QT24HC, 5.0Vdc, 24MHz and QT24L, 3.3Vdc, 24MHz clock at offset frequencies 10Hz to 5MHz, and phase jitter integrated over the bandwidth of 12kHz to 1MHz. QT24HC, 5.0Vdc, 24MHz QT24L, 3.3Vdc, 24 MHz Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com Flat Pack (Revision E, June 2010) (ECO# 9856) 6