This is information on a product in full production.
April 2019 DS12117 Rev 7 1/356
STM32H753xI
32-bit Arm
®
Cortex
®
-M7 480MHz MCUs, 2MB Flash,
1MB RAM, 46 com. and analog interfaces, crypto
Datasheet - production data
Features
Core
•32-bit Arm® Cortex®-M7 core with double-
precision FPU and L1 cache: 16 Kbytes of data
and 16 Kbytes of instruction cache; frequency
up to 480 MHz, MPU, 1027 DMIPS/
2.14 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
Memories
•2 Mbytes of Flash memory with read-while-
write support
•1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc.
64 Kbytes of ITCM RAM + 128 Kbytes of
DTCM RAM for time critical routines),
864 Kbytes of user SRAM, and 4 Kbytes of
SRAM in Backup domain
•Dual mode Quad-SPI memory interface
running up to 133 MHz
•Flexible external memory controller with up to
32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, NOR/NAND Flash
memory clocked up to 100 MHz in
Synchronous mode
•CRC calculation unit
Security
•ROP, PC-ROP, active tamper, secure firmware
upgrade support, Secure access mode
General-purpose input/outputs
•Up to 168 I/O ports with interrupt capability
Reset and power management
•3 separate power domains which can be
independently clock-gated or switched off:
– D1: high-performance capabilities
– D2: communication peripherals and timers
– D3: reset/clock control/power management
•1.62 to 3.6 V application supply and I/Os
•POR, PDR, PVD and BOR
•Dedicated USB power embedding a 3.3 V
internal regulator to supply the internal PHYs
•Embedded regulator (LDO) with configurable
scalable output to supply the digital circuitry
•Voltage scaling in Run and Stop mode (6
configurable ranges)
•Backup regulator (~0.9 V)
•Voltage reference for analog peripheral/VREF+
•Low-power modes: Sleep, Stop, Standby and
VBAT supporting battery charging
Low-power consumption
•VBAT battery operating mode with charging
capability
•CPU and domain power state monitoring pins
•2.95 µA in Standby mode (Backup SRAM OFF,
RTC/LSE ON)
Clock management
•Internal oscillators: 64 MHz HSI, 48 MHz
HSI48, 4 MHz CSI, 32 kHz LSI
•External oscillators: 4-48 MHz HSE,
32.768 kHz LSE
•3× PLLs (1 for the system clock, 2 for kernel
clocks) with Fractional mode
FBGA
LQFP100
(14 x 14 mm)
LQFP144
(20 x 20 mm)
LQFP176
(24 x 24 mm)
LQFP208
(28 x 28 mm)
UFBGA169
(7 x 7 mm)
UFBGA176+25
(10 x 10 mm)
FBGA
TFBGA100
(8 x 8 mm)(1)
TFBGA240+25
(14 x 14 mm)
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STM32H753xI
2/356 DS12117 Rev 7
Interconnect matrix
•3 bus matrices (1 AXI and 2 AHB)
•Bridges (5× AHB2-APB, 2× AXI2-AHB)
4 DMA controllers to unload the CPU
•1× high-speed master direct memory access
controller (MDMA) with linked list support
•2× dual-port DMAs with FIFO
•1× basic DMA with request router capabilities
Up to 35 communication peripherals
•4× I2Cs FM+ interfaces (SMBus/PMBus)
•4× USARTs/4x UARTs (ISO7816 interface,
LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART
•6× SPIs, 3 with muxed duplex I2S audio class
accuracy via internal audio PLL or external
clock, 1x I2S in LP domain (up to 150 MHz)
•4x SAIs (serial audio interface)
•SPDIFRX interface
•SWPMI single-wire protocol master I/F
•MDIO Slave interface
•2× SD/SDIO/MMC interfaces (up to 125 MHz)
•2× CAN controllers: 2 with CAN FD, 1 with
time-triggered CAN (TT-CAN)
•2× USB OTG interfaces (1FS, 1HS/FS) crystal-
less solution with LPM and BCD
•Ethernet MAC interface with DMA controller
•HDMI-CEC
•8- to 14-bit camera interface (up to 80 MHz)
11 analog peripherals
•3× ADCs with 16-bit max. resolution (up to 36
channels, up to 3.6 MSPS)
•1× temperature sensor
•2× 12-bit D/A converters (1 MHz)
•2× ultra-low-power comparators
•2× operational amplifiers (7.3 MHz bandwidth)
•1× digital filters for sigma delta modulator
(DFSDM) with 8 channels/4 filters
Graphics
•LCD-TFT controller up to XGA resolution
•Chrom-ART graphical hardware Accelerator™
(DMA2D) to reduce CPU load
•Hardware JPEG Codec
Up to 22 timers and watchdogs
•1× high-resolution timer (2.1 ns max
resolution)
•2× 32-bit timers with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input (up to 240 MHz)
•2× 16-bit advanced motor control timers (up to
240 MHz)
•10× 16-bit general-purpose timers (up to
240 MHz)
•5× 16-bit low-power timers (up to 240 MHz)
•2× watchdogs (independent and window)
•1× SysTick timer
•RTC with sub-second accuracy and hardware
calendar
Cryptographic acceleration
•AES 128, 192, 256, TDES,
•HASH (MD5, SHA-1, SHA-2), HMAC
•True random number generators
Debug mode
•SWD & JTAG interfaces
•4-Kbyte Embedded Trace Buffer
96-bit unique ID
All packages are ECOPACK®2 compliant
Table 1. Device summary
Reference Part number
STM32H753xI
STM32H753VI, STM32H753ZI,
STM32H753II, STM32H753BI,
STM32H753XI, STM32H753AI
DS12117 Rev 7 3/356
STM32H753xI Contents
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Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1 Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.1 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.2 Secure access mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.3 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.6 Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.7 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.7.1 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.7.2 System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.9 Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.10 DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.11 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 33
3.13 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 33
3.14 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 33
3.15 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.16 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.17 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.18 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.19 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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3.20 Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.21 Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.22 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.23 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 37
3.24 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.25 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.26 JPEG Codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.27 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.28 Cryptographic acceleration (CRYP and HASH) . . . . . . . . . . . . . . . . . . . . 40
3.29 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.29.1 High-resolution timer (HRTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.29.2 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.29.3 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.29.4 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.29.5 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 44
3.29.6 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.29.7 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.29.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.30 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 45
3.31 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.32 Universal synchronous/asynchronous receiver transmitter (USART) . . . 46
3.33 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 47
3.34 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 48
3.35 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.36 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.37 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 49
3.38 Management Data Input/Output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . 50
3.39 SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . 50
3.40 Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 50
3.41 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 51
3.42 Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 51
3.43 High-definition multimedia interface (HDMI)
- consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.44 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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STM32H753xI Contents
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4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6 Electrical characteristics (rev Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.2 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.3.3 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 108
6.3.4 Embedded reset and power control block characteristics . . . . . . . . . . 109
6.3.5 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3.11 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.3.13 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 136
6.3.14 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.3.17 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
6.3.18 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
6.3.19 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
6.3.20 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
6.3.21 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.3.22 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 177
Contents STM32H753xI
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6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.3.24 Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.3.25 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.3.26 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.3.27 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.3.28 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 185
6.3.29 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 188
6.3.30 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 189
6.3.31 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
6.3.32 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.3.33 JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 206
7 Electrical characteristics (rev V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
7.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 211
7.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
7.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
7.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
7.3.2 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
7.3.3 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 216
7.3.4 Embedded reset and power control block characteristics . . . . . . . . . . 217
7.3.5 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
7.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
7.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 231
7.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 232
7.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 236
7.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
7.3.11 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
7.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
7.3.13 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 244
7.3.14 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
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7.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
7.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
7.3.17 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
7.3.18 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
7.3.19 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
7.3.20 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
7.3.21 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
7.3.22 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 290
7.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
7.3.24 Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
7.3.25 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
7.3.26 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
7.3.27 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 294
7.3.28 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 296
7.3.29 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 299
7.3.30 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 300
7.3.31 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
7.3.32 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
8.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
8.2 TFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
8.3 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
8.4 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
8.5 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
8.6 LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
8.7 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
8.8 TFBGA240+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
8.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
8.9.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
List of tables STM32H753xI
8/356 DS12117 Rev 7
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. STM32H753xI features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3. System vs domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 4. DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 5. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 6. USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 7. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 8. Pin/ball definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 9. Port A alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 10. Port B alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 11. Port C alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 12. Port D alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 13. Port E alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 14. Port F alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 15. Port G alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 16. Port H alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 17. Port I alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 18. Port J alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 19. Port K alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 20. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 21. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 22. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 23. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 24. VCAP operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 25. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 108
Table 26. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 27. Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 28. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 29. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 30. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 31. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache OFF, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 32. Typical consumption in Run mode and corresponding performance
versus code position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 33. Typical current consumption batch acquisition mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 34. Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 114
Table 35. Typical and maximum current consumption in Stop mode, regulator ON. . . . . . . . . . . . . 115
Table 36. Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 115
Table 37. Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 116
Table 38. Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 39. Peripheral current consumption in Stop, Standby and VBAT mode . . . . . . . . . . . . . . . . . 123
Table 40. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 41. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 42. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 43. 4-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 44. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
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STM32H753xI List of tables
12
Table 45. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 46. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 47. CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 48. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 49. PLL characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 50. PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 51. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 52. Flash memory programming (single bank configuration nDBANK=1) . . . . . . . . . . . . . . . 134
Table 53. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 54. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 55. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 56. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 57. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 58. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 59. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 60. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . 140
Table 61. Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . 141
Table 62. Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 63. Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 64. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 65. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 148
Table 66. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 148
Table 67. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 149
Table 68. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 150
Table 69. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 70. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 151
Table 71. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 72. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 153
Table 73. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 74. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 75. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 76. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 77. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 78. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 79. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 80. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 81. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 82. LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 83. QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 84. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 85. Dynamics characteristics: Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 86. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 87. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 88. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 89. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 90. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 91. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 92. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 93. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 94. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 95. Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 96. Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
List of tables STM32H753xI
10/356 DS12117 Rev 7
Table 97. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 98. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 99. DFSDM measured timing 1.62-3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 100. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 101. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 102. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 103. Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 104. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 105. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 106. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 107. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 108. MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 109. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 200
Table 110. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 201
Table 111. USB OTG_FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 112. Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 113. Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 114. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 115. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 116. Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 117. Dynamics SWD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 118. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 119. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 120. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 121. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 122. Supply voltage and maximum frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 123. VCAP operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 124. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 216
Table 125. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 126. Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 127. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 128. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 129. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 130. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache OFF,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 131. Typical and maximum current consumption batch acquisition mode,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 132. Typical and maximum current consumption in Stop, LDO regulator ON . . . . . . . . . . . . . 222
Table 133. Typical and maximum current consumption in Sleep mode, LDO regulator. . . . . . . . . . . 223
Table 134. Typical and maximum current consumption in Standby . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 135. Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 224
Table 136. Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 137. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 138. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 139. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 140. 4-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 141. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 142. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
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Table 143. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Table 144. CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Table 145. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 146. PLL characteristics (wide VCO frequency range). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Table 147. PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Table 148. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 149. Flash memory programming (single bank configuration nDBANK=1) . . . . . . . . . . . . . . . 241
Table 150. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 151. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 152. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 153. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 154. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 155. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Table 156. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Table 157. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . 248
Table 158. Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . 249
Table 159. Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 160. Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 161. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Table 162. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 255
Table 163. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 255
Table 164. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 257
Table 165. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 257
Table 166. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Table 167. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 259
Table 168. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 169. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 260
Table 170. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Table 171. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Table 172. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 266
Table 173. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Table 174. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table 175. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table 176. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Table 177. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Table 178. SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Table 179. LPSDR SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 180. QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 181. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Table 182. Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 183. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 184. Minimum sampling time vs RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Table 185. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Table 186. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Table 187. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Table 188. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Table 189. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Table 190. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Table 191. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 192. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 193. Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 194. Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
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Table 195. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Table 196. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Table 197. DFSDM measured timing 1.62-3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Table 198. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Table 199. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Table 200. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Table 201. Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Table 202. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Table 203. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Table 204. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Table 205. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Table 206. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Table 207. MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Table 208. Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V . . . . . . . . . . . . . 314
Table 209. Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 315
Table 210. Dynamics characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Table 211. Dynamics characteristics: Ethernet MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . 318
Table 212. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 319
Table 213. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 319
Table 214. Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Table 215. Dynamics SWD characteristics: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Table 216. LQPF100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Table 217. TFBGA100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Table 218. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 327
Table 219. LQFP144 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Table 220. UFBGA169 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Table 221. LQFP176 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Table 222. LQFP208 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Table 223. UFBGA176+25 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Table 224. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 344
Table 225. TFBG240+25 ball package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Table 226. TFBGA240+25 recommended PCB design rules (0.8 mm pitch) . . . . . . . . . . . . . . . . . . . 348
Table 227. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Table 228. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
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List of figures
Figure 1. STM32H753xI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 2. Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 3. STM32H753xI bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 4. LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 5. TFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 6. LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 7. UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 8. LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 9. UFBGA176+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 10. LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 11. TFBGA240+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 12. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 13. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 14. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 15. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 16. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 17. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 18. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 19. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 20. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 21. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 22. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 23. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 147
Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 149
Figure 25. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 26. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 27. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 28. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 29. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 30. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 31. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 32. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 33. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 161
Figure 34. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 162
Figure 35. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 36. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 37. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 38. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 39. ADC accuracy characteristics (12-bit resolution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 40. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 41. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 173
Figure 42. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 173
Figure 43. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 44. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 45. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 46. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 47. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 48. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
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14/356 DS12117 Rev 7
Figure 49. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 50. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 51. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 52. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 53. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 54. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 55. MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 56. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 57. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 58. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 59. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 60. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 61. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 62. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 63. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 64. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 65. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 66. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 67. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 68. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 69. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 70. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 71. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 72. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 73. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 74. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Figure 75. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 254
Figure 77. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 256
Figure 78. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 79. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Figure 80. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Figure 81. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 265
Figure 82. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Figure 83. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Figure 84. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Figure 85. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 270
Figure 86. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 271
Figure 87. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Figure 88. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 89. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Figure 90. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Figure 91. ADC accuracy characteristics (12-bit resolution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 92. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 93. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 285
Figure 94. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 285
Figure 95. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Figure 96. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Figure 97. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Figure 98. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Figure 99. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Figure 100. USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
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STM32H753xI List of figures
15
Figure 101. USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Figure 102. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Figure 103. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Figure 104. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Figure 105. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Figure 106. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Figure 107. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Figure 108. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Figure 109. MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Figure 110. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Figure 111. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Figure 112. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Figure 113. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Figure 114. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Figure 115. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Figure 116. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Figure 117. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Figure 118. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Figure 119. LQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Figure 120. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Figure 121. LQFP100 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Figure 122. TFBGA100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Figure 123. TFBGA100 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Figure 124. TFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Figure 125. LQFP144 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Figure 126. LQFP144 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Figure 127. LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Figure 128. UFBGA169 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Figure 129. UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Figure 130. LQFP176 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Figure 131. LQFP176 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Figure 132. LQFP176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Figure 133. LQFP208 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Figure 134. LQFP208 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Figure 135. LQFP208 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Figure 136. UFBGA176+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Figure 137. UFBGA176+25 package recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Figure 138. UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Figure 139. TFBGA240+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Figure 140. TFBGA240+25 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Figure 141. TFBGA240+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Introduction STM32H753xI
16/356 DS12117 Rev 7
1 Introduction
This document provides information on STM32H53xI microcontrollers, such as description,
functional overview, pin assignment and definition, electrical characteristics, packaging, and
ordering information.
This document should be read in conjunction with the STM32H53xI reference manual
(RM0433), available from the STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-M7 core, please refer to the Cortex®-M7 Technical
Reference Manual, available from the http://www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS12117 Rev 7 17/356
STM32H753xI Description
53
2 Description
STM32H753xI devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC
core operating at up to 480 MHz. The Cortex® -M7 core features a floating point unit (FPU)
which supports Arm® double-precision (IEEE 754 compliant) and single-precision data-
processing instructions and data types. STM32H753xI devices support a full set of DSP
instructions and a memory protection unit (MPU) to enhance application security.
STM32H753xI devices incorporate high-speed embedded memories with a dual-bank Flash
memory of 2 Mbytes, up to 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, up to
864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of
enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB
bus matrix and a multi layer AXI interconnect supporting internal and external memory
access.
All the devices offer three ADCs, two DACs, two ultra-low power comparators, a low-power
RTC, a high-resolution timer, 12 general-purpose 16-bit timers, two PWM timers for motor
control, five low-power timers, a true random number generator (RNG), and a cryptographic
acceleration cell. The devices support four digital filters for external sigma-delta modulators
(DFSDM). They also feature standard and advanced communication interfaces.
•Standard peripherals
–Four I
2Cs
– Four USARTs, four UARTs and one LPUART
– Six SPIs, three I2Ss in Half-duplex mode. To achieve audio class accuracy, the I2S
peripherals can be clocked by a dedicated internal audio PLL or by an external
clock to allow synchronization.
– Four SAI serial audio interfaces
– One SPDIFRX interface
– One SWPMI (Single Wire Protocol Master Interface)
– Management Data Input/Output (MDIO) slaves
– Two SDMMC interfaces
– A USB OTG full-speed and a USB OTG high-speed interface with full-speed
capability (with the ULPI)
– One FDCAN plus one TT-FDCAN interface
– An Ethernet interface
– Chrom-ART Accelerator™
– HDMI-CEC
•Advanced peripherals including
– A flexible memory control (FMC) interface
– A Quad-SPI Flash memory interface
– A camera interface for CMOS sensors
– An LCD-TFT display controller
– A JPEG hardware compressor/decompressor
Refer to Table 2: STM32H753xI features and peripheral counts for the list of peripherals
available on each part number.
Description STM32H753xI
18/356 DS12117 Rev 7
STM32H753xI devices operate in the –40 to +85 °C temperature range from a 1.62 to 3.6 V
power supply. The supply voltage can drop down to 1.62 V by using an external power
supervisor (see Section 3.5.2: Power supply supervisor) and connecting the PDR_ON pin to
VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power
voltage detector enabled.
Dedicated supply inputs for USB (OTG_FS and OTG_HS) are available on all packages
except LQFP100 to allow a greater power supply choice.
A comprehensive set of power-saving modes allows the design of low-power applications.
STM32H753xI devices are offered in 8 packages ranging from 100 pins to 240 pins/balls.
The set of included peripherals changes with the device chosen.
These features make STM32H753xI microcontrollers suitable for a wide range of
applications:
•Motor drive and application control
•Medical equipment
•Industrial applications: PLC, inverters, circuit breakers
•Printers, and scanners
•Alarm systems, video intercom, and HVAC
•Home audio appliances
•Mobile applications, Internet of Things
•Wearable devices: smart watches.
Figure 1 shows the device block diagram.
DS12117 Rev 7 19/356
STM32H753xI Description
53
Table 2. STM32H753xI features and peripheral counts
Peripherals STM32H753
VI
STM32H753
ZI
STM32H753
AI
STM32H753
II
STM32H753
BI
STM32H753
XI
Flash memory in Kbytes 2 x 1 Mbyte
SRAM in Kbytes
SRAM mapped
onto AXI bus 512
SRAM1 (D2
domain) 128
SRAM2 (D2
domain) 128
SRAM3 (D2
domain) 32
SRAM4 (D3
domain) 64
TCM RAM in Kbytes
ITCM RAM
(instruction) 64
DTCM RAM
(data) 128
Backup SRAM (Kbytes) 4
FMC Yes
GPIOs 82 114 131 140 168
Quad-SPI Yes
Ethernet Yes
Timers
High-resolution 1
General-
purpose 10
Advanced-
control (PWM) 2
Basic 2
Low-power 5
Random number generator Yes
Cryptographic accelerator Yes
Description STM32H753xI
20/356 DS12117 Rev 7
Communication
interfaces
SPI / I2S6/3
(1)
I2C4
USART/UART/
LPUART
4/4
/1
SAI 4
SPDIFRX 4 inputs
SWPMI Yes
MDIO Yes
SDMMC 2
FDCAN/TT-
FDCAN 1/1
USB OTG_FS Yes
USB OTG_HS Yes
Ethernet and camera interface Yes
LCD-TFT Yes
JPEG Codec Yes
Chrom-ART Accelerator™ (DMA2D) Yes
16-bit ADCs
Number of channels
3
Up to 36
12-bit DAC
Number of channels
Yes
2
Comparators 2
Operational amplifiers 2
DFSDM Yes
Maximum CPU frequency 480MHz(2)(3)/400 MHz
Operating voltage 1.71 to
3.6 V(4) 1.62 to 3.6 V(5)
Operating temperatures
Ambient temperatures: –40 up to +85 °C(6)
Junction temperature: –40 to + 125 °C
Package LQFP100
TFBGA100(7) LQFP144 UFBGA169
(7)
LQFP176
UFBGA176+
25
LQFP208 TFBGA240+
25
1. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio
mode.
2. The maximum CPU frequency of 480 MHz can be obtained on devices revision V.
3. The product junction temperature must be kept within the –40 to +105 °C temperature range.
4. Since the LQFP100 package does not feature the PDR_ON pin (tied internally to VDD), the minimum VDD value for this
package is 1.71 V.
Table 2. STM32H753xI features and peripheral counts (continued)
Peripherals STM32H753
VI
STM32H753
ZI
STM32H753
AI
STM32H753
II
STM32H753
BI
STM32H753
XI
DS12117 Rev 7 21/356
STM32H753xI Description
53
5. VDD/VDDA can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2: Power supply supervisor) and
connecting PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage
detector enabled.
6. The product junction temperature must be kept within the –40 to +125 °C temperature range.
7. This package is under development. Please contact STMicroelectronics for details.
Description STM32H753xI
22/356 DS12117 Rev 7
Figure 1. STM32H753xI block diagram
MSv40887V15
TT-FDCAN1
FDCAN2
I2C1/SMBUS
I2C2/SMBUS
I2C3/SMBUS
AXI/AHB12 (200MHz)
4 compl. chan. (TIM1_CH1[1:4]N),
4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF
APB1 30MHz
TX, RX
SCL, SDA, SMBAL as AF
APB1 100 MHz (max)
MDMA
PK[7:0]
4 compl. chan.(TIM8_CH1[1:4]N),
4 chan. (TIM8_CH1[1:4], ETR, BKIN as
AF
RX, TX, SCK, CTS, RTS as AF
SCL, SDA, SMBAL as AF
SCL, SDA, SMBAL as AF
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
TX, RX
RX, TX as AF
RX, TX as AF
RX, TX, SCK
CTS, RTS as AF
RX, TX, SCK, CTS,
RTS as AF
1 channel as AF
smcard
irDA
1 channel as AF
2 channels as AF
4 channels
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
RX, TX as AF
FIFO
LCD-TFT
FIFO
CHROM-ART
(DMA2D)
SD, SCK, FS, MCLK, D/CK[4:1] as
AF
FIFO
LCD_R[7:0], LCD_G[7:0],
LCD_B[7:0], LCD_HSYNC,
LCD_VSYNC, LCD_DE, LCD_CLK
CLK, CS,D[7:0]
64-bit AXI BUS-MATRIX
CEC as AF
IN[1:4] as AF
MDC, MDIO
AXIM
AXIM
Arm CPU
Cortex-M7
400 MHz
AHBP
AHBS
TRACECK
TRACED[3:0]
JTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
JTAG/SW
ETM
I-Cache
16KB
D-Cache
16KB
I-TCM
64KB
D-TCM
64KB
16 Streams
FIFO
SDMMC1
SDMMC_D[7:0],SDMMC_D[7:3,1]Dir
SDMMC_D0dir, SDMMC_D2dir
CMD, CMDdir, CK, Ckin,
CKio as AF
FIFO
DMA1
FIFOs
8 Stream
DMA2
FIFOs
ETHER
MAC
FIFO
SDMMC2
FIFO
OTG_HS
FIFO
OTG_FS
FIFO
SRAM1
128 KB
8 Stream
FMC_signals
DMA/ DMA/ DMA/
PHY PHY
MII / RMII
MDIO
as AF
DP, DM, STP,
NXT,ULPI:CK
, D[7:0], DIR,
ID, VBUS
AHB1 (200MHz)
ADC1
DAC_OUT1, DAC_OUT2 as AF
16b
AXI/AHB34 (200MHz)
JPEGWWDG
AHB2 (200MHz)
AHB2 (200MHz)
PA..J[15:0]
HSYNC, VSYNC, PIXCLK, D[13:0]
SAI3
MOSI, MISO, SCK, NSS as AF
MOSI, MISO, SCK, NSS as AF
smcard
irDA 32-bit AHB BUS-MATRIX
AHB4 (200MHz)
BDMA
DMA
Mux2
Up to 20 analog inputs
common to ADC1 & 2
HSEM
AHB4 (200MHz)
AHB3
AHB4
AHB4
AHB4
AHB4
AHB4
VDDA, VSSA
NRESET
WKUP[5:0]
@VDD
RCC
Reset &
control
OSC32_IN
OSC32_OUT
VBAT = 1.8 to 3.6 V
AWU
VDD12 BBgen + POWER MNGT
LS LS
OSC_IN
OSC_OUT
RTC_TS
RTC_TAMP[1:3]
RTC_OUT
RTC_REFIN
VDDMMC33 = 1.8 to 3.6V
VDDUSB33 = 3.0 to 3.6 V
VDD = 1.8 to 3.6 V
VSS
VCAP
@VDD
@VDD33
@VSW
PWRCTRL
AHB4 (200MHz)
SUPPLY SUPERVISION
Int
POR
reset
@VDD
WDG_LS_D1
LPTIM1_IN1, LPTIM1_IN2,
LPTIM1_OUT as AF
OPAMPx_VINM
OPAMPx_VINP
OPAMPx_VOUT as AF
HRTIM1_CH[A..E]x
HRTIM1_FLT[5:1],
HRTIM1_FLT[5:1]_in, SYSFLT
DFSDM1_CKOUT,
DFSDM1_DATAIN[0:7],
DFSDM1_CKIN[0:7]
2 compl. chan.(TIM15_CH1[1:2]N),
2 chan. (TIM_CH15[1:2], BKIN as AF
1 compl. chan.(TIM16_CH1N),
1 chan. (TIM16_CH1, BKIN as AF
1 compl. chan.(TIM17_CH1N),
1 chan. (TIM17_CH1, BKIN as AF
SDMMC_
D[7:0],
CMD, CK as AF
Up to 17 analog inputs
common to ADC1 and 2
SD, SCK, FS, MCLK,
D[3;1], CK[2:1] as AF
SCL, SDA, SMBAL as AF
COMPx_INP, COMPx_INM,
COMPx_OUT as AF
LPTIM5_OUT as AF
D-TCM
64KB
AHB/APB
Quad-SPI
1 MB FLASH
1 MB FLASH
512 KB AXI
SRAM
FMC
Delay block
DCMI AHB/APB
HRTIM1
DFSDM1
SD, SCK, FS, MCLK, CK[2:1] as AF
FIFO
SAI2
SD, SCK, FS, MCLK, D[3:1],
CK[2:1] as AF
FIFO
SAI1
SPI5
TIM17
TIM16
TIM15
SPI4
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF SPI1/I2S1
USART6
RX, TX, SCK, CTS, RTS as AF irDA USART1
TIM1/PWM 16b
TIM8/PWM 16b
APB2 100 MHz (max)
ADC3
GPIO PORTA.. J
GPIO PORTK
SAI4
COMP1&2
LPTIM5
LPTIM4_OUT as AF LPTIM4
LPTIM3_OUT as AF LPTIM3
I2C4
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF SPI6/I2S6
RX, TX, CK, CTS, RTS as AF LPUART1
LPTIM2
VREF
SYSCFG
EXTI WKUP
CRC
DAP
RNG
DMA
Mux1
To APB1-2
peripherals
SRAM2
128 KB
SRAM3
32 KB
ADC2
AHB/APB
TIM6 16b
TIM7 16b
SWPMI
TIM2
32b
TIM3
16b
TIM4
16b
TIM5
32b
TIM12
16b
TIM13
16b
TIM14
16b
USART2
smcard
irDA
USART3
UART4
UART5
UART7
RX, TX as AF
UART8
SPI2/I2S2
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
SPI3/I2S3
Digital filter
MDIOs
FIFO
10 KB SRAM
RAM
I/F
USBCR
SPDIFRX1
HDMI-CEC
DAC
LPTIM1
OPAMP1&2
AHB/APB
XTAL 32 kHz
RTC
Backup registers
XTAL OSC
4- 48 MHz
HS RC
LS RC
PLL1+PLL2+PLL3
POR/PDR/BOR
PVD
smcard
Voltage
regulator
3.3 to 1.2V
LSI
HSI
CSI
HSI48
LPTIM2_IN1, LPTIM2_IN2 and
LPTIM2_OUT
AHB1 (200MHz)
DP, DM, ID,
VBUS
64 KB SRAM 4 KB BKP
RAM
AHB4
32-bit AHB BUS-MATRIX
APB4 100 MHz (max)
APB4 100 MHz (max)
APB4 100 MHz (max)
IWDG
Temperature
sensor
HASH
3DES/AES
DS12117 Rev 7 23/356
STM32H753xI Functional overview
53
3 Functional overview
3.1 Arm® Cortex®-M7 with FPU
The Arm® Cortex®-M7 with double-precision FPU processor is the latest generation of Arm
processors for embedded systems. It was developed to provide a low-cost platform that
meets the needs of MCU implementation, with a reduced pin count and optimized power
consumption, while delivering outstanding computational performance and low interrupt
latency.
The Cortex®-M7 processor is a highly efficient high-performance featuring:
•Six-stage dual-issue pipeline
•Dynamic branch prediction
•Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache)
•64-bit AXI interface
•64-bit ITCM interface
•2x32-bit DTCM interfaces
The following memory interfaces are supported:
•Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency
•Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM
accesses
•AXI Bus interface to optimize Burst transfers
•Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
It also supports single and double precision FPU (floating point unit) speeds up software
development by using metalanguage development tools, while avoiding saturation.
Figure 1 shows the general block diagram of the STM32H753xI family.
Note: Cortex®-M7 with FPU core is binary compatible with the Cortex®-M4 core.
3.2 Memory protection unit (MPU)
The memory protection unit (MPU) manages the CPU access rights and the attributes of the
system resources. It has to be programmed and enabled before use. Its main purposes are
to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by
a privileged task, but also to protect data processes or read-protect memory regions.
The MPU defines access rules for privileged accesses and user program accesses. It
allows defining up to 16 protected regions that can in turn be divided into up to 8
independent subregions, where region address, size, and attributes can be configured. The
protection area ranges from 32 bytes to 4 Gbytes of addressable memory.
When an unauthorized access is performed, a memory management exception is
generated.
Functional overview STM32H753xI
24/356 DS12117 Rev 7
3.3 Memories
3.3.1 Embedded Flash memory
The STM32H753xI devices embed 2 Mbytes of Flash memory that can be used for storing
programs and data.
The Flash memory is organized as 266-bit Flash words memory that can be used for storing
both code and data constants. Each word consists of:
•One Flash word (8 words, 32 bytes or 256 bits)
•10 ECC bits.
The Flash memory is divided into two independent banks. Each bank is organized as
follows:
•1 Mbyte of user Flash memory block containing eight user sectors of 128 Kbytes
(4 K Flash memory words)
•128 Kbytes of System Flash memory from which the device can boot
•2 Kbytes (64 Flash words) of user option bytes for user configuration
3.3.2 Secure access mode
In addition to other typical memory protection mechanism (RDP, PCROP), STM32H753xI
devices introduce the Secure access mode, a new enhanced security feature. This mode
allows developing user-defined secure services by ensuring, on the one hand code and
data protection and on the other hand code safe execution.
Two types of secure services are available:
•STMicroelectronics Root Secure Services:
These services are embedded in System memory. They provide a secure solution for
firmware and third-party modules installation. These services rely on cryptographic
algorithms based on a device unique private key.
•User-defined secure services:
These services are embedded in user Flash memory. Examples of user secure
services are proprietary user firmware update solution, secure Flash integrity check or
any other sensitive applications that require a high level of protection.
The secure firmware is embedded in specific user Flash memory areas configured
through option bytes.
Secure services are executed just after a reset and preempt all other applications to
guarantee protected and safe execution. Once executed, the corresponding code and data
are no more accessible.
The above secure services are available only for Cortex®-M7 core operating in Secure
access mode. The other masters cannot access the option bytes involved in Secure access
mode settings or the Flash secured areas.
DS12117 Rev 7 25/356
STM32H753xI Functional overview
53
3.3.3 Embedded SRAM
All devices feature:
•512 Kbytes of AXI-SRAM mapped onto AXI bus on D1 domain.
•SRAM1 mapped on D2 domain: 128 Kbytes
•SRAM2 mapped on D2 domain: 128 Kbytes
•SRAM3 mapped on D2 domain: 32 Kbytes
•SRAM4 mapped on D3 domain: 64 Kbytes
•4 Kbytes of backup SRAM
The content of this area is protected against possible unwanted write accesses,
and is retained in Standby or VBAT mode.
•RAM mapped to TCM interface (ITCM and DTCM):
Both ITCM and DTCM RAMs are 0 wait state memories. either They can be accessed
either from the CPU or the MDMA (even in Sleep mode) through a specific AHB slave
of the CPU(AHBP):
– 64 Kbytes of ITCM-RAM (instruction RAM)
This RAM is connected to ITCM 64-bit interface designed for execution of critical
real-times routines by the CPU.
– 128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports)
The DTCM-RAM could be used for critical real-time data, such as interrupt service
routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for
load/store operations) thanks to the Cortex®-M7 dual issue capability.
The MDMA can be used to load code or data in ITCM or DTCM RAMs.
Error code correction (ECC)
Over the product lifetime, and/or due to external events such as radiations, invalid bits in
memories may occur. They can be detected and corrected by ECC. This is an expected
behavior that has to be managed at final-application software level in order to ensure data
integrity through ECC algorithms implementation.
SRAM data are protected by ECC:
•7 ECC bits are added per 32-bit word.
•8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.
The ECC mechanism is based on the SECDED algorithm. It supports single-error correction
and double-error detection.
3.4 Boot modes
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
•All Flash address space
•All RAM address space: ITCM, DTCM RAMs and SRAMs
•The System memory bootloader
Functional overview STM32H753xI
26/356 DS12117 Rev 7
The boot loader is located in non-user System memory. It is used to reprogram the Flash
memory through a serial interface (USART, I2C, SPI, USB-DFU). Refer to STM32
microcontroller System memory Boot mode application note (AN2606) for details.
3.5 Power supply management
3.5.1 Power supply scheme
STM32H53xI power supply voltages are the following:
•VDD = 1.62 to 3.6 V: external power supply for I/Os, provided externally through VDD
pins.
•VDDLDO = 1.62 to 3.6 V: supply voltage for the internal regulator supplying VCORE
•VDDA = 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and
OPAMP.
•VDD33USB and VDD50USB:
VDD50USB can be supplied through the USB cable to generate the VDD33USB via the
USB internal regulator. This allows supporting a VDD supply different from 3.3 V.
The USB regulator can be bypassed to supply directly VDD33USB if VDD = 3.3 V.
•VBAT = 1.2 to 3.6 V: power supply for the VSW domain when VDD is not present.
•VCAP: VCORE supply voltage, which values depend on voltage scaling (1.0 V, 1.1 V,
1.2 V or 1.35 V). They are configured through VOS bits in PWR_D3CR register and
ODEN bit in the SYSCFG_PWRCR register. The VCORE domain is split into the
following power domains that can be independently switch off.
– D1 domain containing some peripherals and the Cortex®-M7 core.
– D2 domain containing a large part of the peripherals.
– D3 domain containing some peripherals and the system control.
During power-up and power-down phases, the following power sequence requirements
must be respected (see Figure 2):
•When VDD is below 1 V, other power supplies (VDDA, VDD33USB, VDD50USB) must
remain below VDD + 300 mV.
•When VDD is above 1 V, all power supplies are independent.
During the power-down phase, VDD can temporarily become lower than other supplies only
if the energy provided to the microcontroller remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the power-down
transient phase.