(Preliminary) PL123E-05 Low Skew Zero Delay Buffer FEATURES DESCRIPTION The PL123E-05 (-05H for High Drive) is a high performance, low skew, low jitter zero delay buffer d esigned to distribute high speed clocks. It has five low-skew outputs that are synchronized with the input. The sy nchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than 100ps, the device acts as a zero delay buffer. The input output propagation delay can be advanced or delayed by adjusting the load on the CLKOUT pin. Frequency Range 10MHz to 220MHz Zero input - output delay. Low output-to-output skew. Optional Drive Strength: Standard (8mA) PL123E-05 High (12mA) PL123E-05H 2.5V or 3.3V, 10% operation. Available in 8-pin SOP packaging. These parts are not intended for 5V input-tolerant applications. PIN CONFIGURATION REF 1 8 CLKOUT CLK2 2 7 CLK4 CLK1 3 6 VDD GND 4 5 CLK3 SOP-8L BLOCK DIAGRAM REF PLL CLKOUT CLK1 CLK2 CLK3 CLK4 Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1(408) 944 -0800 * fax +1(408) 474-1000 * www.micrel.com Rev 12/13/11 Page 1 (Preliminary) PL123E-05 Low Skew Zero Delay Buffer PIN DESCRIPTION Name Package Type SOP-8L Type Description REF [1 ] 1 I Input reference frequency. CLK2 [2 ] 2 O Buffered clock output. CLK1 3 O Buffered clock output. GND 4 P Ground connection. CLK3 [2 ] 5 O Buffered clock output. VDD 6 P VDD connection. CLK4 [2 ] 7 O Buffered clock output. CLKOUT [2 ,3 ] 8 O Buffered clock output. Internal feed back on this pin. [2 ] Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. 3. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output. INPUT / OUTPUT SKEW CONTROL The PL123E-05 will achieve Zero Delay from input to output when all the outputs are loaded equally. Adjus tments to the input/output delay can be made by adjusting the loading on the CLKOUT pin. Please contact Micrel for more information. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1(408) 944 -0800 * fax +1(408) 474-1000 * www.micrel.com Rev 12/13/11 Page 2 (Preliminary) PL123E-05 Low Skew Zero Delay Buffer LAYOUT RECOMMENDATIONS The following guidelines are to assist y ou with a performance optimized PCB design: Signal Integrity and Termination Considerations Decoupling and Power Supply Considerations - Keep traces short! - Place decoupling capacitors as close as possible to the VDD pin(s) to limit noise from the power supply - Trace = Inductor. With a capacitive load this equals ringing! - Long trace = Transmission Line. Without proper termination this will cause reflections ( looks like ringing ). - Design long traces as "striplines" or "microstrips" with defined impedance. - Addition of a ferrite bead in series with VDD can help prevent noise from other board sources - Value of decoupling capacitor is frequency dependant. Typical values to use are 0.1F for designs using frequencies < 50MHz and 0.01F for designs using frequencies > 50MHz. - Match trace at one side to avoid reflections bouncing back and forth. Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer To CMOS Input ( Typical buffer impedance 20 50 line Connect a 33 series resistor at each of the output clocks to enhance the stability of the output signal Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1(408) 944 -0800 * fax +1(408) 474-1000 * www.micrel.com Rev 12/13/11 Page 3 (Preliminary) PL123E-05 Low Skew Zero Delay Buffer Absolute Maximum Conditions Supply Voltage to Ground Potential ...... -0.5V to 4.6V DC Input Voltage............................. V SS - 0.5V to 4.6V Storage Temperature ......................... -65C to 150C Junction Temperature ....................................... 150C Static Discharge Voltage (per MIL-STD-883, Method 3015)..................> 2000V Operating Condition Description Parameter Min Max Unit Supply Voltage V DD 2.25 3.63 V Load Capacitance, <100 MHz, 3.3V CL [4 ] - 30 pF Load Capacitance, <100 MHz, 2.5V with High Drive - 30 pF Load Capacitance, <133.3 MHz, 3.3V - 22 pF Load Capacitance, <133.3 MHz, 2.5V with High Drive - 22 pF Load Capacitance, <133.3 MHz, 2.5V with Standard Drive - 15 pF Load Capacitance, >133.3 MHz, 3.3V - 15 pF Load Capacitance, >133.3 MHz, 2.5V with High Drive - 15 pF - 5 pF Input Capacitance [5] C IN Closed-loop bandwidth (typical), 3.3V BW 1 MHz 0.5 MHz 23 Output Impedance (typical), 3.3V Standard Drive 33 Output Impedance (typical), 2.5V High Drive 26 Output Impedance (typical), 2.5V Standard Drive 39 Closed-loop bandwidth (typical), 2.5V Output Impedance (typical), 3.3V Hi gh Drive Power-up time for all V DD's to reach minimum specified voltage (power ramps must be monotonic) ROUT t PU 0.01 250 ms Notes: 4. Applies to Test Circuit #1. 5. Applies to both REF Clock and internal feedback path on CLKOUT. 6. Theta Ja, EIA JEDEC 51 test board conditions, 2S2P; Theta Jc Mil -Spec 883E Method 1012.1. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1(408) 944 -0800 * fax +1(408) 474-1000 * www.micrel.com Rev 12/13/11 Page 4 (Preliminary) PL123E-05 Low Skew Zero Delay Buffer 3.3V DC Electrical Specifications Description Supply Voltage Parameter V DD Test Conditions Min 2.97 Max 3.63 Unit V Input LOW Voltage V IL - 0.8 V Input HIGH Voltage V IH 2.5 V DD + 0.3 V Input Leakage Current I IL 0 < V IN < V IL - 10 A Input HIGH Current I IH V IN = V DD - 100 A Output LOW Voltage V OL Output HIGH Voltage V OH - - 2.4 2.4 0.4 0.4 - - V V V V Supply Current I DD - 45 mA Min Max Unit I OL = 8 mA (Standard Drive) I OL = 12 mA (High Drive) I OH = -8 mA (Standard Drive) I OH = -12 mA (High Drive) Unloaded outputs, 66-MHz REF 2.5V DC Electrical Specifications Description Parameter Test Conditions Supply Voltage V DD 2.25 2.75 V Input LOW Voltage V IL - 0.7 V Input HIGH Voltage V IH 1.7 V DD + 0.3 V Input Leakage Current I IL 0<V IN < V DD - 10 A Input HIGH Current I IH V IN = V DD - 100 A Output LOW Voltage V OL I OL = 8 mA (Standard Drive) I OL = 12 mA (High Drive) - - 0.5 0.5 V Output HIGH Voltage V OH I OH = -8 mA (Standard Drive) I OH = -12 mA (High Drive) V DD - 0.6 V DD - 0.6 - - V Supply Current I DD Unloaded outputs, 66-MHz REF - 30 mA Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1(408) 944 -0800 * fax +1(408) 474-1000 * www.micrel.com Rev 12/13/11 Page 5 (Preliminary) PL123E-05 Low Skew Zero Delay Buffer 3.3V and 2.5V AC Electrical Specifications Description Parameter Test Conditions Maximum Frequency [7] (Input/Output) 1/t 1 Input Duty Cycle (PLL Mode only) T IDC Output Duty Cycle [8 ] t2 / t1 Rise, Fall Time (3.3V) [8 ] Rise, Fall Time (2.5V) [8 ] Output to Output Skew [8 ] Delay, REF Rising Edge to CLKOUT Rising Edge [8 ] Part to Part Skew [8] PLL Lock Time [8 ] Cycle-to-Cycle Jitter, Peak [8 ,9 ] t 3 ,t 4 t3 , t4 t5 t6 t7 t LOCK T JCC Min Typ Max Unit 3.3V High Drive 10 - 220 MHz 3.3V Standard Drive 10 - 167 MHz 2.5V High Drive 10 - 200 MHz 2.5V Standard Drive 10 - 134 MHz <133.3 MHz 25 - 75 % >133.3 MHz 40 - 60 % <133.3 MHz 47 - 53 % >133.3 MHz 45 - 55 % Standard Drive, CL = 30pF, <100 MHz - 1.6 - ns Standard Drive, CL = 22pF, <133.3 MHz - 1.6 - ns Standard Drive, CL = 15pF, <167 MHz - 0.6 - ns High Drive, CL = 30pF, <100 MHz - 1.2 - ns High Drive, CL = 22pF, <133.3 MHz - 1.2 - ns High Drive, CL = 15pF, >133.3 MHz - 0.5 - ns Standard Drive, CL = 15pF, <133.33 MHz - 1.5 - ns High Drive, CL = 30pF, <100 MHz - 2.1 - ns High Drive, CL = 22pF, <133.3 MHz - 1.3 - ns High Drive, CL = 15pF, >133.3 MHz - 1.2 - ns All outputs equally loaded - - 100 ps PLL enabled @ 3.3V -100 - 100 ps PLL enabled @2.5V -200 - 200 ps Measured at V DD/2. Any output to any output, 3.3V supply - - 150 ps Measured at V DD/2. Any output to any output, 2.5V supply - - 300 ps Stable power supply, valid clocks presented on REF and CLKOUT pins - - 1.0 ms 3.3V, >66 MHz, <15pF - - 55 ps 3.3V, >66 MHz, <30pF, Standard. Drive - - 125 ps 3.3V, >66 MHz, <30pF, High Drive - - 100 ps 2.5V, >66 MHz, <15pF, Standard. Drive - - 100 ps 2.5V, >66 MHz, <15pF, High Drive - - 80 ps 2.5V, >66 MHz, <30pF, High Drive - - 125 ps Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1(408) 944 -0800 * fax +1(408) 474-1000 * www.micrel.com Rev 12/13/11 Page 6 (Preliminary) PL123E-05 Low Skew Zero Delay Buffer 3.3V and 2.5V AC Electrical Specifications (continued) Description Period Jitter, Peak [8 ,9 ] Parameter T PER Test Conditions 3.3V, 66-100 MHz, <15 pF Min - Typ - Max 60 Unit ps 3.3V, >100 MHz, <15 pF - - 35 ps 3.3V, >66 MHz, <30 pF, Standard Drive - - 75 ps 3.3V, >66 MHz, <30 pF, High Drive - - 70 ps 2.5V, >66 MHz, <15 pF, Standard. Drive - - 60 ps 2.5V, 66-100 MHz, <15 pF, High Drive - - 60 ps 2.5V, >100 MHz, <15 pF, High Drive - - 45 ps Notes: 7. For the given maximum loading conditions. See C L in Operating Conditions Tab le. 8. Parameter is guaranteed by design and characterization. Not 100% tested in production. 9. Typical jitter is measured at 3.3V or 2.5V, 29C, with all outputs driven into the maximum spec ified load. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1(408) 944 -0800 * fax +1(408) 474-1000 * www.micrel.com Rev 12/13/11 Page 7 (Preliminary) PL123E-05 Low Skew Zero Delay Buffer SWITCHING WAVEFORMS Duty Cycle Timing t1 t2 VDD/2 VDD/2 All Outputs Rise/Fall Time OUTPUT 2.0V(1.8V) 2.0V(1.8V) 0.8V(0.6V) 0.8V(0.6V) t3 3.3V (2.5V) 0V t4 Output-Output Skew OUTPUT VDD/2 OUTPUT VDD/2 t5 Input-Output Propagation Delay INPUT VDD/2 CLKOUT VDD/2 t6 Device-Device Skew Any Output, Part 1 or 2 1 Any Output, Part 1 or 2 1 VDD/2 VDD/2 t7 Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1(408) 944 -0800 * fax +1(408) 474-1000 * www.micrel.com Rev 12/13/11 Page 8 (Preliminary) PL123E-05 Low Skew Zero Delay Buffer TEST CIRCUITS Test Circuit #1 VDD 0.1 F OUTPUTS CL OAD VDD GND 0.1 F CLK GND PACKAGE DRAWINGS (GREEN PACKAGE COM PLIANT) Recommended Land Pattern (MM) SOP-8L 3.80 REF Dimension (MM) Symbol Min Max A 1.35 1.75 A1 0.10 0.25 A2 1.25 1.50 b 0.33 0.53 C 0.19 0.27 D 4.80 5.00 E 3.80 4.00 H 5.80 6.20 L e 0.40 0.89 1.27 BSC E H 6.985 0.050 DDD 2.31 0.05 4.65 REF C L 2.40 REF A2 A1 A 1.27 Nom e b 0.53 0.05 Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1(408) 944 -0800 * fax +1(408) 474-1000 * www.micrel.com Rev 12/13/11 Page 9 (Preliminary) PL123E-05 Low Skew Zero Delay Buffer ORDERING INFORM ATION (GREEN PACKAGE COM PLIANT) For part ordering, please contact our Sales Department: 2180 Fortune Drive, San Jose, CA 95131, USA Tel: (408) 944-0800 Fax: (408) 474-1000 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range PL123E-05(H) S X - X Part Number H=High Drive None = Standard Drive None=Tubes R=Tape & Reel Temperature Range C=Commercial (0C to 70C) I=Industrial (-40C to 85C) Package Type S=SOP Part/Order Number PL123E-05SC PL123E-05SC-R PL123E-05HSC PL123E-05HSC-R PL123E-05SI PL123E-05SI-R PL123E-05HSI PL123E-05HSI-R *Note: Marking* P123E05 SC LLLLL P123E05H SC LLLLL P123E05 SI LLLLL P123E05H SI LLLLL Package Option 8-Pin SOP Tube 8-Pin SOP (Tape and Reel) 8-Pin SOP Tube 8-Pin SOP (Tape and Reel) 8-Pin SOP Tube 8-Pin SOP (Tape and Reel) 8-Pin SOP Tube 8-Pin SOP (Tape and Reel) LLLLL designates lot number Micrel Inc., reserves the right to make changes in its products or specif ications, or both at any time without notice. The information furnished by Micrel is believed to be accurate and reliable. However, Micrel makes no guarantee or warranty concerning the accuracy of said info rmation and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: Micrel's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Micrel Inc. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1(408) 944 -0800 * fax +1(408) 474-1000 * www.micrel.com Rev 12/13/11 Page 10