Datasheet Cover S3A7 Microcontroller Group Datasheet Renesas SynergyTM Platform Synergy Microcontrollers S3 Series All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com). www.renesas.com Rev.1.40 Oct 2018 Features S3A7 Microcontroller Group Datasheet High efficiency 48-MHz Arm(R) Cortex(R)-M4 microcontroller, up to 1-MB code flash memory, 192-KB SRAM, Segment LCD Controller, Capacitive Touch Sensing Unit, USB 2.0 Full-Speed Module, 14-bit A/D Converter, 12-bit D/A Converter, security and safety features Features Arm Cortex-M4 Core with Floating Point Unit (FPU) Armv7E-M architecture with DSP instruction set Maximum operating frequency: 48 MHz Support for 4-GB address space Arm Memory Protection Unit (Arm MPU) with 8 regions Debug and Trace: ITM, DWT, FPB, TPIU, ETB CoreSightTM Debug Port: JTAG-DP and SW-DP Memory Up to 1-MB code flash memory 16-KB data flash memory (100,000 program/erase (P/E) cycles) Up to 192-KB SRAM Flash Cache (FCACHE) Memory Protection Unit (MPU) Memory Mirror Function (MMF) 128-bit unique ID Connectivity USB 2.0 Full-Speed Module (USBFS) - On-chip transceiver with voltage regulator - Compliant with USB Battery Charging Specification 1.2 Serial Communications Interface (SCI) x 6 - UART - Simple IIC - Simple SPI Serial Peripheral Interface (SPI) x 2 I2C bus interface (IIC) x 3 Controller Area Network (CAN) module Serial Sound Interface (SSI) x 2 SD/MMC Host Interface (SDHI) Quad Serial Peripheral Interface (QSPI) IrDA interface External address space - 8- or 16-bit bus space selectable per area Analog 14-Bit A/D Converter (ADC14) 12-Bit D/A Converter (DAC12) x 2 High-Speed Analog Comparator (ACMPHS) x 2 Low-Power Analog Comparator (ACMPLP) x 2 Operational Amplifier (OPAMP) x 4 Temperature Sensor (TSN) Timers General PWM Timer 32-bit (GPT32) x 10 Asynchronous General-Purpose Timer (AGT) x 2 - VBATT support Watchdog Timer (WDT) Safety Error Correction Code (ECC) in SRAM SRAM parity error check Flash area protection ADC self-diagnosis function Clock Frequency Accuracy Measurement Circuit (CAC) Cyclic Redundancy Check (CRC) calculator Data Operation Circuit (DOC) Port Output Enable for GPT (POEG) Independent Watchdog Timer (IWDT) GPIO readback level detection Register write protection Main oscillator stop detection Illegal memory access R01DS0263EU0140 Rev.1.40 Oct 29, 2018 System and Power Management Low power modes Realtime Clock (RTC) with calendar and Battery Backup support Event Link Controller (ELC) DMA Controller (DMAC) x 4 Data Transfer Controller (DTC) Key Interrupt Function (KINT) Power-on reset Low Voltage Detection (LVD) with voltage settings Security and Encryption AES128/256 GHASH True Random Number Generator (TRNG) Human Machine Interface (HMI) Segment LCD Controller (SLCDC) - Up to 52 segments x 4 commons - Up to 48 segments x 8 commons Capacitive Touch Sensing Unit (CTSU) Multiple Clock Sources Main clock oscillator (MOSC) (1 to 20 MHz when VCC = 2.4 to 5.5 V) (1 to 8 MHz when VCC = 1.8 to 2.4 V) (1 to 4 MHz when VCC = 1.6 to 1.8 V) Sub-clock oscillator (SOSC) (32.768 kHz) High-speed on-chip oscillator (HOCO) (24, 32, 48, 64 MHz when VCC = 2.4 to 5.5 V) (24, 32, 48 MHz when VCC = 1.8 to 5.5 V) (24, 32 MHz when VCC = 1.6 to 5.5 V) Middle-speed on-chip oscillator (MOCO) (8 MHz) Low-speed on-chip oscillator (LOCO) (32.768 kHz) IWDT-dedicated on-chip oscillator (15 kHz) Clock trim function for HOCO/MOCO/LOCO Clock out support General Purpose I/O Ports Up to 124 input/output pins - Up to 3 CMOS input - Up to 121 CMOS input/output - Up to 10 input/output 5-V tolerant - Up to 2 high current (20 mA) Operating Voltage VCC: 1.6 to 5.5 V Operating Temperature and Packages Ta = -40C to +85C - 145-pin LGA(7 mm x 7 mm, 0.5 mm pitch) - 121-pin BGA (8 mm x 8 mm, 0.65 mm pitch) - 100-pin LGA (7 mm x 7 mm, 0.65 mm pitch) Ta = -40C to +105C - 144-pin LQFP (20 mm x 20 mm, 0.5 mm pitch) - 100-pin LQFP (14 mm x 14 mm, 0.5 mm pitch) - 64-pin LQFP (10 mm x 10 mm, 0.5 mm pitch) - 64-pin QFN (8 mm x 8 mm, 0.4 mm pitch) Page 2 of 137 S3A7 Datasheet 1. 1. Overview Overview The MCU integrates multiple series of software- and pin-compatible Arm(R)-based 32-bit MCUs that share a common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development. The MCU provides an optimal combination of low power, high performance Arm Cortex(R)-M4 core running up to 48 MHz with the following features: Up to 1-MB code flash memory 192-KB SRAM Segment LCD Controller (SLCDC) Capacitive Touch Sensing Unit (CTSU) USB 2.0 Full-Speed Module (USBFS) 14-bit A/D Converter (ADC14) 12-bit D/A Converter (DAC12) Security features. 1.1 Function Outline Table 1.1 Arm core Feature Functional description Arm Cortex-M4 Maximum operating frequency: up to 48 MHz Arm Cortex-M4 - Revision: r0p1-01rel0 - Armv7E-M architecture profile - Single precision floating-point unit compliant with the ANSI/IEEE Std 754-2008. Arm Memory Protection Unit (Arm MPU) - Armv7 Protected Memory System Architecture - 8 protected regions. SysTick timer - Driven by SYSTICCLK (LOCO) or ICLK. Table 1.2 Memory Feature Functional description Code flash memory Maximum 1-MB code flash memory. See section 48, Flash Memory in User's Manual. Data flash memory 16-KB data flash memory. See section 48, Flash Memory in User's Manual. Option-setting memory The option-setting memory determines the state of the MCU after a reset. See section 7, Option-Setting Memory in User's Manual. Memory Mirror Function (MMF) The Memory Mirror Function (MMF) can be configured to mirror the desired application image load address in code flash memory to the application image link address in the 23-bit unused memory space (memory mirror space addresses). Your application code is developed and linked to run from this MMF destination address. The application code does not need to know the load location where it is stored in code flash memory. See section 5, Memory Mirror Function (MMF) in User's Manual. SRAM On-chip high-speed SRAM with either parity-bit or Error Correction Code (ECC). An area in SRAM0 provides error correction capability using ECC. See section 47, SRAM in User's Manual. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 3 of 137 S3A7 Datasheet Table 1.3 1. Overview System (1 of 2) Feature Functional description Operating modes Two operating modes: Single-chip mode SCI/USB boot mode. See section 3, Operating Modes in User's Manual. Resets 14 resets: RES pin reset Power-on reset VBATT-selected voltage power-on reset Independent watchdog timer reset Watchdog timer reset Voltage monitor 0 reset Voltage monitor 1 reset Voltage monitor 2 reset SRAM parity error reset SRAM ECC error reset Bus master MPU error reset Bus slave MPU error reset CPU stack pointer error reset Software reset. See section 6, Resets in User's Manual. Low Voltage Detection (LVD) The Low Voltage Detection (LVD) function monitors the voltage level input to the VCC pin, and the detection level can be selected using a software program. See section 8, Low Voltage Detection (LVD) in User's Manual. Clocks Main clock oscillator (MOSC) Sub-clock oscillator (SOSC) High-speed on-chip oscillator (HOCO) Middle-speed on-chip oscillator (MOCO) Low-speed on-chip oscillator (LOCO) PLL frequency synthesizer IWDT-dedicated on-chip oscillator Clock out support. See section 9, Clock Generation Circuit in User's Manual. Clock Frequency Accuracy Measurement Circuit (CAC) The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be measured (measurement target clock) within the time generated by the clock to be used as a measurement reference (measurement reference clock), and determines the accuracy depending on whether the number of pulses is within the allowable range. When measurement is complete or the number of pulses within the time generated by the measurement reference clock is not within the allowable range, an interrupt request is generated. See section 10, Clock Frequency Accuracy Measurement Circuit (CAC) in User's Manual. Interrupt Controller Unit (ICU) The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC module and DMAC module. The ICU also controls NMI interrupts. See section 14, Interrupt Controller Unit (ICU) in User's Manual. Key Interrupt Function (KINT) A key interrupt can be generated by setting the Key Return Mode Register (KRM) and inputting a rising or falling edge to the key interrupt input pins. See section 21, Key Interrupt Function (KINT) in User's Manual. Low power modes Power consumption can be reduced in multiple ways, such as by setting clock dividers, controlling EBCLK output, stopping modules, selecting power control mode in normal operation, and transitioning to low power modes. See section 11, Low Power Modes in User's Manual. Battery backup function A battery backup function is provided for partial powering by a battery. The battery-powered area includes RTC, AGT, SOSC, LOCO, Wakeup Control, Backup Memory, VBATT_R Low Voltage Detection, and switches between VCC and VBATT. During normal operation, the battery powered area is powered by the main power supply, the VCC pin. When a VCC voltage drop is detected, the power source is switched to the dedicated battery backup power pin, the VBATT pin. When the voltage rises again, the power source is switched from the VBATT pin to the VCC pin. See section 12, Battery Backup Function in User's Manual. Register write protection The register write protection function protects important registers from being overwritten due to software errors. See section 13, Register Write Protection in User's Manual. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 4 of 137 S3A7 Datasheet Table 1.3 1. Overview System (2 of 2) Feature Functional description Memory Protection Unit (MPU) Four MPUs and a CPU stack pointer monitor function are provided for memory protection. See section 16, Memory Protection Unit (MPU) in User's Manual. Watchdog Timer (WDT) The WDT is a 14-bit down-counter. It can be used to reset the MCU when the counter underflows because the system has run out of control and is unable to refresh the WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. A refresh-permitted period can be set to refresh the counter and be used as the condition for detecting when the system runs out of control. See section 26, Watchdog Timer (WDT) in User's Manual. Independent Watchdog Timer (IWDT) The IWDT consists of a 14-bit down-counter that must be serviced periodically to prevent counter underflow. The IWDT provides functionality to reset the MCU or to generate a nonmaskable interrupt/interrupt for a timer underflow. Because the timer operates with an independent, dedicated clock source, it is particularly useful in returning the MCU to a known state as a fail safe mechanism when the system runs out of control. The IWDT can be triggered automatically on a reset, underflow, or refresh error, or by a refresh of the count value in the registers. See section 27, Independent Watchdog Timer (IWDT) in User's Manual. Table 1.4 Event link Feature Functional description Event Link Controller (ELC) The ELC uses the interrupt requests generated by various peripheral modules as event signals to connect them to different modules, enabling direct interaction between the modules without CPU intervention. See section 19, Event Link Controller (ELC) in User's Manual. Table 1.5 Direct memory access Feature Functional description Data Transfer Controller (DTC) A DTC module is provided for transferring data when activated by an interrupt request. See section 18, Data Transfer Controller (DTC) in User's Manual. DMA Controller (DMAC) A 4-channel DMAC module is provided for transferring data without the CPU. When a DMA transfer request is generated, the DMAC transfers data stored at the transfer source address to the transfer destination address. See section 17, DMA Controller (DMAC) in User's Manual. Table 1.6 External bus interface Feature Functional description External bus CS area: Connected to the external devices (external memory interface) QSPI area: Connected to the QSPI (external device interface). R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 5 of 137 S3A7 Datasheet Table 1.7 1. Overview Timers Feature Functional description General PWM Timer (GPT) The GPT is a 32-bit timer with 10 channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or the up- and down-counter. In addition, PWM waveforms can be generated for controlling brushless DC motors. The GPT can also be used as a generalpurpose timer. See section 23, General PWM Timer (GPT) in User's Manual. Port Output Enable for GPT (POEG) Use the POEG function to place the General PWM Timer (GPT) output pins in the output disable state. See section 22, Port Output Enable for GPT (POEG) in User's Manual. Asynchronous General Purpose Timer (AGT) The AGT is a 16-bit timer that can be used for pulse output, external pulse width or period measurement, and counting of external events. This 16-bit timer consists of a reload register and a down-counter. The reload register and the down-counter are allocated to the same address, and they can be accessed with the AGT register. See section 24, Asynchronous General Purpose Timer (AGT) in User's Manual. Realtime Clock (RTC) The RTC has two counting modes, calendar count mode and binary count mode, that are controlled by the register settings. For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and automatically adjusts dates for leap years. For binary count mode, the RTC counts seconds and retains the information as a serial value. Binary count mode can be used for calendars other than the Gregorian (Western) calendar. See section 25, Realtime Clock (RTC) in User's Manual. Table 1.8 Communication interfaces (1 of 2) Feature Functional description Serial Communications Interface (SCI) The SCI is configurable to five asynchronous and synchronous serial interfaces: Asynchronous interfaces (UART and asynchronous communications interface adapter (ACIA)) 8-bit clock synchronous interface Simple IIC (master-only) Simple SPI Smart card interface. The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and transmission protocol. Each SCI has FIFO buffers to enable continuous and full-duplex communication, and the data transfer speed can be configured individually using an on-chip baud rate generator. See section 29, Serial Communications Interface (SCI) in User's Manual. IrDA Interface (IrDA) The IrDA interface sends and receives IrDA data communication waveforms in cooperation with the SCI1 based on the IrDA (Infrared Data Association) standard 1.0. See section 30, IrDA Interface in User's Manual. I2C Bus Interface (IIC) The 3-channel IIC module conforms with and provides a subset of the NXP I2C bus (InterIntegrated Circuit bus) interface functions. See section 31, I2C Bus Interface (IIC) in User's Manual. Serial Peripheral Interface (SPI) Two independent SPI channels are capable of high-speed, full-duplex synchronous serial communications with multiple processors and peripheral devices. See section 33, Serial Peripheral Interface (SPI) in User's Manual. Serial Sound Interface (SSI) The SSI peripheral provides functionality to interface with digital audio devices for transmitting PCM audio data over a serial bus with the MCU. The SSI supports an audio clock frequency of up to 50 MHz, and can be operated as a slave or master receiver, transmitter, or transceiver to suit various applications. The SSI includes 8-stage FIFO buffers in the receiver and transmitter, and supports interrupts and DMA-driven data reception and transmission. See section 36, Serial Sound Interface (SSI) in User's Manual. Quad Serial Peripheral Interface (QSPI) The QSPI is a memory controller for connecting a serial ROM (nonvolatile memory such as a serial flash memory, serial EEPROM, or serial FeRAM) that has an SPI-compatible interface. See section 34, Quad Serial Peripheral Interface (QSPI) in User's Manual. Controller Area Network (CAN) Module The CAN module provides functionality to receive and transmit data using a message-based protocol between multiple slaves and masters in electromagnetically noisy applications. The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are supported. See section 32, Controller Area Network (CAN) Module in User's Manual. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 6 of 137 S3A7 Datasheet Table 1.8 1. Overview Communication interfaces (2 of 2) Feature Functional description USB 2.0 Full-Speed Module (USBFS) The full-speed USB controller can operate as a host controller or device controller. The module supports full-speed and low-speed (host controller only) transfer as defined in the Universal Serial Bus Specification 2.0. The module has an internal USB transceiver and supports all of the transfer types defined in the Universal Serial Bus Specification 2.0. The USB has buffer memory for data transfer, providing a maximum of 10 pipes. Pipes 1 to 9 can be assigned any endpoint number based on the peripheral devices used for communication or based on the user system. The MCU supports revision 1.2 of the battery charging specification. Because the MCU can be powered at 5 V, the USB LDO regulator provides the internal USB transceiver power supply 3.3 V. See section 28, USB 2.0 Full-Speed Module (USBFS) in User's Manual. SD/MMC Host Interface (SDHI) The SDHI provides the functionality needed to connect a variety of external memory cards to the MCU. The SDHI supports both 1-bit and 4-bit buses for connecting memory cards that support SD, SDHC, and SDXC formats. When developing host devices that are compliant with the SD specifications, you must comply with the SD Host/Ancillary Product License Agreement (SD HALA). The MMC interface supports 1-bit, 4-bit, and 8-bit MMC buses that provide eMMC 4.51 (JEDEC Standard JESD 84-B451) device access. This interface also provides backward compatibility and supports high-speed SDR transfer modes. See section 37, SD/MMC Host Interface (SDHI) in User's Manual. Table 1.9 Analog Feature Functional description 14-bit A/D Converter (ADC14) A 14-bit successive approximation A/D converter is provided. Up to 28 analog input channels are selectable. Temperature sensor output and internal reference voltage are selectable for conversion. The A/D conversion accuracy is selectable from 12-bit and 14-bit conversion making it possible to optimize the tradeoff between speed and resolution in generating a digital value. See section 39, 14-Bit A/D Converter (ADC14) in User's Manual. 12-bit D/A Converter (DAC12) The 12-bit D/A converts data and includes an output amplifier. See section 40, 12-Bit D/A Converter (DAC12) in User's Manual. Temperature Sensor (TSN) The on-chip temperature sensor determines and monitors the die temperature for reliable operation of the device. The sensor outputs a voltage directly proportional to the die temperature, and the relationship between the die temperature and the output voltage is linear. The output voltage is provided to the ADC14 for conversion and can be further used by the end application. See section 41, Temperature Sensor (TSN) in User's Manual. High-Speed Analog Comparator (ACMPHS) ACMPHS compares the test voltage with a reference voltage and to provide a digital output based on the result of conversion. Both the test and reference voltages can be provided to the comparator from internal sources such as the DAC12 output and internal reference voltage, and an external source. Such flexibility is useful in applications that require go/no-go comparisons to be performed between analog signals without necessarily requiring A/D conversion. See section 43, HighSpeed Analog Comparator (ACMPHS) in User's Manual. Low-Power Analog Comparator (ACMPLP) ACMPLP compares a reference input voltage and analog input voltage. The comparison result can be read by software and also be output externally. The reference input voltage can be selected from either an input to the CMPREFi (i = 0, 1) pin or from the internal reference voltage (Vref) generated internally in the MCU. The ACMPLP response speed can be set before starting an operation. Setting the high-speed mode decreases the response delay time, but increases current consumption. Setting the lowspeed mode increases the response delay time, but decreases current consumption. See section 44, Low Power Analog Comparator (ACMPLP) in User's Manual. Operational Amplifier (OPAMP) OPAMP amplifies small analog input voltages and outputs the amplified voltages. A total of four differential operational amplifier units with two input pins and one output pin are provided. See section 42, Operational Amplifier (OPAMP) in User's Manual. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 7 of 137 S3A7 Datasheet Table 1.10 1. Overview Human machine interfaces Feature Functional description Segment LCD Controller (SLCDC) The SLCDC provides the following functions: Waveform A or B selectable The LCD driver voltage generator can switch between an internal voltage boosting method, a capacitor split method, and an external resistance division method Automatic output of segment and common signals based on automatic display data register read The reference voltage generated when operating the voltage boost circuit can be selected in 16 steps (contrast adjustment) The LCD can be made to blink. See section 49, Segment LCD Controller/Driver (SLCDC) in User's Manual. Capacitive Touch Sensing Unit (CTSU) The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the touch sensor. Changes in the electrostatic capacitance are determined by software, which enables the CTSU to detect whether a finger is in contact with the touch sensor. The electrode surface of the touch sensor is usually enclosed with an electrical insulator so that a finger does not come into direct contact with the electrodes. See section 45, Capacitive Touch Sensing Unit (CTSU) in User's Manual. Table 1.11 Data processing Feature Functional description Cyclic Redundancy Check (CRC) Calculator The CRC calculator generates CRC codes to detect errors in the data. The bit order of CRC calculation results can be switched for LSB-first or MSB-first communication. Additionally, various CRC generation polynomials are available. The snoop function allows monitoring reads from and writes to specific addresses. This function is useful in applications that require CRC code to be generated automatically in certain events, such as monitoring writes to the serial transmit buffer and reads from the serial receive buffer. See section 35, Cyclic Redundancy Check (CRC) Calculator in User's Manual. Data Operation Circuit (DOC) The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. See section 46, Data Operation Circuit (DOC) in User's Manual. Table 1.12 Security Feature Functional description Secure Crypto Engine 5 (SCE5) Security algorithm: - Symmetric algorithm: AES. Other support features: - TRNG (True Random Number Generator) - Hash-value generation: GHASH. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 8 of 137 S3A7 Datasheet 1.2 1. Overview Block Diagram Figure 1.1 shows the block diagram of the MCU superset. Some individual devices within the group have a subset of the features. Memories Bus 1 MB Code Flash External 16 KB Data Flash CSC Arm Cortex-M4 DSP System FPU POR/LVD MOSC/SOSC MPU 192 KB SRAM Clocks Reset (H/M/L) OCO MPU NVIC Mode Control PLL System Timer Power Control CAC Test and DBG Interface ICU Battery Backup DMA DTC DMAC x 4 KINT Timers Communication Interfaces GPT32 x 10 SCI x 6 IrDA x 1 QSPI AGT x 2 IIC x 3 SDHI x1 RTC SPI x 2 CAN x 1 WDT/IWDT SSI x 2 USBFS with BC1.2 Event Link Register Write Protection Human Machine Interfaces CTSU Data Processing SLCDC Analogs ELC CRC ADC14 TSN Security DOC DAC12 ACMPHS x 2 ACMPLP x 2 OPAMP x 4 SCE5 Figure 1.1 Block diagram R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 9 of 137 S3A7 Datasheet 1.3 1. Overview Part Numbering Figure 1.2 shows the product part number information, including memory capacity, and package type. Table 1.13 shows a product list. R 7 F S 3 A 7 7C 2 A 0 1 C L K # A C 1 Product identification code Packing, terminal material (Pb-free) #AA: Tray/Sn (Tin) only #AC: Tray/others Package type BJ: BGA 121 pins FB: LQFP 144 pins FP: LQFP 100 pins FM: LQFP 64 pins LK: LGA 145 pins LJ: LGA 100 pins NB: QFN 64 pins Quality ID Software ID Operating temperature 2: -40 C to 85 C 3: -40 C to 105 C Code flash memory size C: 1 MB Feature set 7: Superset Group name A7: S3A7 Group, Arm Cortex-M4, 48 MHz Series name 3: High efficiency Renesas SynergyTM family Flash memory Renesas microcontroller Renesas Figure 1.2 Table 1.13 Part numbering scheme Product list Part number Ordering part number Package Code flash Data flash SRAM Operating temperature R7FS3A77C2A01CLK R7FS3A77C2A01CLK#AC1 PTLG0145KA-A 1 MB 16 KB 192 KB -40 to +85C R7FS3A77C3A01CFB R7FS3A77C3A01CFB#AA1 PLQP0144KA-B 1 MB 16 KB 192 KB -40 to +105C R7FS3A77C2A01CBJ R7FS3A77C2A01CBJ#AC1 PLBG0121JA-A 1 MB 16 KB 192 KB -40 to +85C R7FS3A77C3A01CFP R7FS3A77C3A01CFP#AA1 PLQP0100KB-B 1 MB 16 KB 192 KB -40 to +105C R7FS3A77C2A01CLJ R7FS3A77C2A01CLJ#AC1 PTLG0100JA-A 1 MB 16 KB 192 KB -40 to +85C R7FS3A77C3A01CFM R7FS3A77C3A01CFM#AA1 PLQP0064KB-C 1 MB 16 KB 192 KB -40 to +105C R7FS3A77C3A01CNB R7FS3A77C3A01CNB#AC1 PWQN0064LA-A 1 MB 16 KB 192 KB -40 to +105C R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 10 of 137 S3A7 Datasheet 1.4 1. Overview Function Comparison Table 1.14 Function comparison Parts number R7FS3A77C2A01CLK R7FS3A77C3A01CFB R7FS3A77C2A01CBJ R7FS3A77C3A01CFP R7FS3A77C2A01CLJ R7FS3A77C3A01CFM R7FS3A77C3A01CNB Pin count 145 144 121 100 100 64 Package LGA LQFP BGA LQFP LGA LQFP/QFN Code flash memory 1 MB Data flash memory 16 KB 192 KB SRAM 176 KB Parity 16 KB ECC System 48 MHz CPU clock 512 bytes Backup registers Yes ICU Event control DMA KINT 8 ELC Yes DTC Yes 4 DMAC BUS External bus Timers GPT32 AGT Communication 16-bit bus 8-bit bus 10 10 10 10 9 2 2 2 2 2 2 RTC Yes WDT/IWDT Yes 6 SCI 3 IIC 2 2 SPI SSI 2 1 QSPI 1 No SDHI 1 Yes USBFS 28 ADC14 26 DAC12 2 ACMPHS 2 OPAMP 4 4 25 18 4 4 3 4 com x 26 seg or 8 com x 22 seg 4 com x 26 seg or 8 com x 22 seg No 4 Yes TSN SLCDC CTSU Data processing 25 2 ACMPLP HMI No 1 CAN Analog No 10 CRC DOC Security R01DS0263EU0140 Rev.1.40 Oct 29, 2018 4 com x 52 seg or 8 com x 48 seg 4 com x 38 seg or 8 com x 34 seg 31 26 14 Yes Yes SCE5 Page 11 of 137 S3A7 Datasheet 1.5 1. Overview Pin Functions Function Signal I/O Description Power supply VCC Input Power supply pin. Connect to the system power supply. Connect this pin to VSS through a 0.1-F capacitor. Place the capacitor close to the pin. VCL Input Connect this pin to the VSS pin through the smoothing capacitor used to stabilize the internal power supply. Place the capacitor close to the pin. Clock VSS Input Ground pin. Connect it to the system power supply (0 V). VBATT Input Backup power supply pin XTAL Output EXTAL Input Pins for a crystal resonator. An external clock signal can be input through the EXTAL pin. XCIN Input XCOUT Output Input/output pins for the sub-clock oscillator. Connect a crystal resonator between XCOUT and XCIN. EBCLK Output Outputs the external bus clock for external devices CLKOUT Output Clock output pin Operating mode control MD Input Pin for setting the operating mode. The signal level on this pin must not be changed during operation mode transition on release from the reset state. System control RES Input Reset signal input pin. The MCU enters the reset state when this signal goes low. CAC CACREF Input Measurement reference clock input pin Interrupt NMI Input Non-maskable interrupt request pin IRQ0 to IRQ15 Input Maskable interrupt request pins KINT KR00 to KR07 Input A key interrupt (KINT) can be generated by inputting a falling edge to the key interrupt input pins On-chip debug TMS I/O On-chip emulator or boundary scan pins TDI Input TCK Input External bus interface Battery Backup TDO Output SWDIO I/O Serial wire debug data Input/output pin SWCLK Input Serial wire clock pin SWO Output Serial wire trace output pin RD Output Strobe signal indicating that reading from the external bus interface space is in progress, active-low WR Output Strobe signal indicating that writing to the external bus interface space is in progress, in 1-write strobe mode, active-low WR0, WR1 Output Strobe signals indicating that either group of data bus pins (D07 to D00, D15 to D08) is valid in writing to the external bus interface space, in byte strobe mode, active-low BC0, BC1 Output Strobe signals indicating that either group of data bus pins (D07 to D00, D15 to D08) is valid in access to the external bus interface space, in 1-write strobe mode, active-low WAIT Input Input pin for wait request signals in access to the external space, active-low CS0 to CS3 Output Select signals for CS areas, active-low A00 to A16 Output Address bus D00 to D15 I/O Data bus VBATWIO0 to VBATWIO2 I/O Output wakeup signal for the VBATT wakeup control function. External event input for the VBATT wakeup control function. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 12 of 137 S3A7 Datasheet 1. Overview Function Signal I/O Description GPT GTETRGA, GTETRGB, GTETRGC, GTETRGD Input External trigger input pins GTIOC0A to GTIOC9A, GTIOC0B to GTIOC9B I/O Input capture, output capture, or PWM output pins GTIU Input Hall sensor input pin U GTIV Input Hall sensor input pin V GTIW Input Hall sensor input pin W GTOUUP Output 3-phase PWM output for BLDC motor control (positive U phase) GTOULO Output 3-phase PWM output for BLDC motor control (negative U phase) GTOVUP Output 3-phase PWM output for BLDC motor control (positive V phase) GTOVLO Output 3-phase PWM output for BLDC motor control (negative V phase) GTOWUP Output 3-phase PWM output for BLDC motor control (positive W phase) GTOWLO Output 3-phase PWM output for BLDC motor control (negative W phase) AGTEE0, AGTEE1 Input External event input enable signals AGTIO0, AGTIO1 I/O External event input and pulse output pins AGTO0, AGTO1 Output Pulse output pins AGTOA0, AGTOA1 Output Output compare match A output pins AGTOB0, AGTOB1 Output Output compare match B output pins RTC RTCOUT Output Output pin for 1-Hz/64-Hz clock RTCIC0 to RTCIC2 Input Time capture event input pins SCI SCK0 to SCK4, SCK9 I/O Input/output pins for the clock (clock synchronous mode) RXD0 to RXD4, RXD9 Input Input pins for received data (asynchronous mode/clock synchronous mode) TXD0 to TXD4, TXD9 Output Output pins for transmitted data (asynchronous mode/clock synchronous mode) CTS0_RTS0 to CTS4_RTS4, CTS9_RTS9 I/O Input/output pins for controlling the start of transmission and reception (asynchronous mode/clock synchronous mode), active-low SCL0 to SCL4, SCL9 I/O Input/output pins for the I2C clock (simple IIC) SDA0 to SDA4, SDA9 I/O Input/output pins for the I2C data (simple IIC) SCK0 to SCK4, SCK9 I/O Input/output pins for the clock (simple SPI) MISO0 to MISO4, MISO9 I/O Input/output pins for slave transmission of data (simple SPI) MOSI0 to MOSI4, MOSI9 I/O Input/output pins for master transmission of data (simple SPI) Chip-select input pins (simple SPI), active-low AGT IIC SSI SS0 to SS4, SS9 Input SCL0 to SCL2 I/O Input/output pins for the clock SDA0 to SDA2 I/O Input/output pins for the data SSISCK0 I/O SSI serial bit clock pins I/O Word select pins SSITXD0 Output Serial data output pin SSIRXD0 Input Serial data input pin SSIDATA1 I/O Serial data input/output pin AUDIO_CLK Input External clock pin for audio (input oversampling clock) SSISCK1 SSIWS0 SSIWS1 R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 13 of 137 S3A7 Datasheet 1. Overview Function Signal I/O Description SPI RSPCKA, RSPCKB I/O Clock input/output pin MOSIA, MOSIB I/O Input or output pins for data output from the master MISOA, MISOB I/O Input or output pins for data output from the slave SSLA0, SSLB0 I/O Input or output pins for slave selection SSLA1, SSLA2, SSLA3, SSLB1, SSLB2, SSLB3 Output Output pins for slave selection QSPCLK Output QSPI clock output pin QSSL Output QSPI slave output pin QSPI CAN USBFS SDHI Analog power supply ADC14 QIO0 I/O Master transmit data/Data 0 QIO1 I/O Master input data/Data 1 Data 2, Data 3 QIO2, QIO3 I/O CRX0 Input Receive data CTX0 Output Transmit data VSS_USB Input Ground pins VCC_USB_LDO Input Power supply pin for USB LDO regulator VCC_USB I/O Input: Power supply pin for USB transceiver. Output: USB LDO regulator output pin. This pin should be connected to an external capacitor. USB_DP I/O D+ I/O pin of the USB on-chip transceiver. Connect this pin to the D+ pin of the USB bus. USB_DM I/O D- I/O pin of the USB on-chip transceiver. Connect this pin to the D- pin of the USB bus. USB_VBUS Input USB cable connection monitor pin. Connect this pin to VBUS of the USB bus. The VBUS pin status (connected or disconnected) can be detected when the USB module is operating as a device controller. USB_EXICEN Output Low power control signal for external power supply (OTG) chip USB_VBUSEN Output VBUS (5 V) supply enable signal for external power supply chip USB_OVRCURA, USB_OVRCURB Input Connect the external overcurrent detection signals to these pins. Connect the VBUS comparator signals to these pins when the OTG power supply chip is connected. USB_ID Input Connect the MicroAB connector ID input signal to this pin during operation in OTG mode SD0CLK Output SD clock output pin SD0CMD I/O Command output pin and response input signal pin SD0DAT0 to SD0DAT7 I/O SD and MMC data bus pins SD0WP Input SD write-protect signal AVCC0 Input Analog voltage supply pin AVSS0 Input Analog voltage supply ground pin VREFH0 Input Analog reference voltage supply pin VREFL0 Input Reference power supply ground pin VREFH Input Analog reference voltage supply pin for DAC12 VREFL Input Analog reference ground pin for DAC12 AN000 to AN027 Input Input pins for the analog signals to be processed by the ADC14 ADTRG0 Input Input pins for the external trigger signals that start the A/D conversion, active-low DAC12 DA0, DA1 Output Output pins for the analog signals to be processed by the D/A converter Comparator output VCOUT Output Comparator output pin ACMPHS IVREF0 to IVREF5 Input Reference voltage input pin IVCMP0 to IVCMP5 Input Analog voltage input pins ACMPLP CMPREF0, CMPREF1 Input Reference voltage input pins CMPIN0, CMPIN1 Input Analog voltage input pins OPAMP AMP0+ to AMP3+ Input Analog voltage input pins AMP0- to AMP3- Input Analog voltage input pins AMP0O to AMP3O Output Analog voltage output pins R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 14 of 137 S3A7 Datasheet 1. Overview Function Signal I/O Description CTSU TS00, TS01, TS03 to TS22, TS26 to TS27, TS29 to TS35 Input Capacitive touch detection pins (touch pins) TSCAP - Secondary power supply pin for the touch driver I/O ports SLCDC P000 to P015 I/O General-purpose input/output pins P100 to P115 I/O General-purpose input/output pins P200 Input General-purpose input pin P201 to P206, P212, P213 I/O General-purpose input/output pins P214, P215 Input General-purpose input pins P300 to P315 I/O General-purpose input/output pins P400 to P415 I/O General-purpose input/output pins P500 to P507, P511, P512 I/O General-purpose input/output pins P600 to P606, P608 to P614 I/O General-purpose input/output pins P700 to P705, P708 to P713 I/O General-purpose input/output pins P800 to P809 I/O General-purpose input/output pins P900 to P902 I/O General-purpose input/output pins VL1, VL2, VL3, VL4 I/O Voltage pin for driving the LCD CAPH, CAPL I/O Capacitor connection pin for the LCD controller/driver COM0 to COM7 Output Common signal output pins for the LCD controller/driver SEG00 to SEG51 Output Segment signal output pins for the LCD controller/driver R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 15 of 137 S3A7 Datasheet 1.6 1. Overview Pin Assignments Figure 1.3 to Figure 1.9 show the pin assignments. R7FS3A77C2A01CLK 13 A B C D E F G H J K L P407 P409 P412 P708 P711 VCC P212 /EXTAL P215 /XCIN VCL P702 P405 P402 P400 13 P410 P414 P710 VSS P213 /XTAL P214 /XCOUT VBATT P701 P404 P511 VCC 12 12 USB_DM USB_DP M N 11 VCC_ USB VSS_ USB VCC_ USB_LDO P411 P415 P712 P705 P704 P703 P403 P401 P512 VSS 11 10 P205 P206 P204 P408 P413 P709 P713 P700 P406 P003 P000 P002 P001 10 9 P203 P313 P202 P314 P004 P006 P009 P008 9 8 P900 P901 P200 P315 P005 AVSS0 P010 P011 /VREFL0 /VREFH0 8 7 VSS P902 RES P310 P007 AVCC0 P013 /VREFL P012 /VREFH 7 6 VCC P201/MD P312 P305 P505 P506 P015 P014 6 5 P309 P311 P308 P303 NC P503 P504 VSS VCC 5 4 P307 P306 P304 P109/TDO /SWO P114 P608 P604 P600 P105 P500 P502 P501 P507 4 3 P808 P809 P301 P112 P115 P610 P614 P603 P107 P106 P104 P803 P802 3 2 P302 P300/TCK /SWCLK P111 P806 P609 P612 VSS P605 P601 P805 P800 P101 P801 2 P108/TMS P110/TDI /SWDIO P113 P807 P611 P613 VCC P606 P602 P804 P103 P102 P100 1 C D E F G H J K L 1 A Figure 1.3 B M N Pin assignment for 145-pin LGA (top view) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 16 of 137 P602 P603 P604 P605 P606 VSS VCC P614 P613 P612 P611 P610 P609 P608 P807 P806 P115 P114 P113 P112 P111 P110/TDI P109/TDO/SWO P108/TMS/SWDIO 96 95 94 92 91 90 89 88 87 85 84 83 81 79 77 76 75 74 73 P601 97 78 P805 P600 99 80 P804 100 82 P107 101 86 P106 102 93 P104 P105 104 98 P102 P103 103 P101 106 105 P100 107 1. Overview 108 S3A7 Datasheet P800 109 72 P300/TCK/SWCLK P801 110 71 P301 P802 111 70 P302 P803 112 69 P303 P500 113 68 P501 114 67 P809 P808 P502 P503 115 66 P304 116 65 P305 P504 117 64 P306 P505 118 63 P307 P506 119 62 P308 P507 120 61 P309 VCC 121 60 VSS 122 59 P310 P311 P015 123 58 P312 P014 124 57 P013/VREFL P012/VREFH 125 56 P200 P201/MD 55 RES AVCC0 127 54 VCC AVSS0 128 53 VSS P011/VREFL0 129 52 P902 P010VREFH0 130 51 P901 P009 P008 131 50 P900 132 49 P315 P007 133 48 P006 134 47 P314 P313 P005 135 46 P004 136 45 P202 P203 P003 137 44 P204 P002 138 43 P205 P001 P000 139 42 P206 140 41 VCC_USB_LDO VSS VCC P512 141 40 VCC_USB 142 39 143 38 USB_DP USB_DM P511 144 37 VSS_USB Figure 1.4 12 13 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 P704 P705 VBATT VCL P215/XCIN P214/XCOUT VSS P213/XTAL P212/EXTAL VCC P713 P712 P711 P710 P709 P708 P415 P414 P413 P412 P411 P410 P409 P408 P407 14 11 10 9 P701 P702 5 P404 P405 8 4 P403 7 3 P402 P406 P700 2 6 1 P400 P401 P703 R7FS3A77C3A01CFB 126 Pin assignment for 144-pin LQFP (top view) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 17 of 137 S3A7 Datasheet 1. Overview R7FS3A77C2A01CBJ 11 A B C D E F G H J K L P407 P408 P411 P414 P212/ EXTAL P215/ XCIN VCL P406 P403 P401 P400 11 P410 P415 P213/ XTAL P214/ XCOUT VBATT P405 P402 P511 P512 10 10 USB_DM USB_DP Figure 1.5 9 VCC_ USB VSS_ USB P409 P412 P708 VCC VSS P404 P002 P001 P000 9 8 P205 VCC_ USB_ LDO P206 P204 P413 P710 P702 P006 P004 P003 P005 8 7 P203 P202 P313 P314 P315 P709 P701 P007 AVSS0 P011/ P010/ 7 VREFL0 VREFH0 6 VSS VCC RES P201/MD P200 NC P700 P008 AVCC0 P013/ VREFL P012/ VREFH 6 5 P308 P309 P307 P302 P304 P612 P601 P506 P505 P015 P014 5 4 P305 P306 P808 P114 P611 P603 P600 P504 P503 VSS VCC 4 3 P809 P303 P110/TDI P111 P609 P604 P106 P104 P502 P500 P501 3 2 P301 P108/ TMS/ SWDIO P113 P608 P613 P605 P602 P105 P102 P801 P800 2 1 P300/ TCK/ SWCLK P109/ TDO/ SWO P112 P115 P610 VCC VSS P107 P103 P101 P100 1 A B C D E F G H J K L Pin assignment for 121-pin BGA (top view) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 18 of 137 Figure 1.6 P100 P101 P102 P103 P104 P105 P106 P107 P600 P601 P602 P603 VSS VCC P610 P609 P608 P115 P114 P113 P112 P111 P110/TDI P109/TDO/SWO P108/TMS/SWDIO 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1. Overview 75 S3A7 Datasheet P500 76 50 P501 77 49 P300/TCK/SWCLK P301 P502 78 48 P302 P503 79 47 P303 P504 80 46 P809 P505 81 45 P808 VCC 82 44 P304 VSS 83 43 P305 P015 84 42 P306 P014 85 41 P307 P013/VREFL 86 40 P200 P012/VREFH 87 39 P201/MD AVCC0 88 38 RES AVSS0 89 37 VCC P011/VREFL0 90 36 VSS P010/VREFH0 91 35 P202 P008 92 34 P203 P007 93 33 P204 P006 94 32 P205 P005 95 31 P206 P004 96 30 VCC_USB_LDO P003 97 29 VCC_USB P002 98 28 USB_DP P001 99 27 USB_DM P000 100 26 VSS_USB 14 15 16 17 18 19 20 21 22 23 24 25 P212/EXTAL VCC P708 P415 P414 P413 P412 P411 P410 P409 P408 P407 9 VCL 13 8 VBATT P213/XTAL 7 P406 12 6 P405 VSS 5 P404 11 4 P403 P214/XCOUT 3 P402 10 2 P215/XCIN 1 P400 P401 R7FS3A77C3A01CFP Pin assignment for 100-pin LQFP (top view) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 19 of 137 S3A7 Datasheet 1. Overview R7FS3A77C2A01CLJ 10 A B C D E F G H J K P407 P409 P412 VCC P212/ EXTAL P215/ XCIN VCL P403 P400 P000 10 P413 VSS P213/ XTAL P214/ XCOUT VBATT P405 P401 P001 9 9 USB_DM USB_DP Figure 1.7 8 VCC_ USB VSS_ USB VCC_US B_LDO P411 P415 P708 P404 P003 P004 P002 8 7 P205 P204 P206 P408 P414 P406 P006 P007 P008 P005 7 6 VSS VCC P202 P203 P410 P402 P505 AVSS0 P011/ P010/ 6 VREFL0 VREFH0 5 P200 P201/MD P307 RES P113 P600 P504 AVCC0 P013/ VREFL P012/ VREFH 5 4 P305 P304 P808 P306 P115 P601 P503 P100 P015 P014 4 3 P809 P303 P110/TDI P111 P609 P602 P107 P103 VSS VCC 3 2 P300/ TCK/ SWCLK P302 P301 P114 P610 P603 P106 P101 P501 P502 2 1 P108/ TMS/ SWDIO P109/ TDO/ SWO P112 P608 VCC VSS P105 P104 P102 P500 1 A B C D E F G H J K Pin assignment for 100-pin LGA (top view) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 20 of 137 Figure 1.8 P100 P101 P102 P103 P104 P105 P106 P107 VSS VCC P113 P112 P111 P110/TDI P109/TDO/SWO P108/TMS/SWDIO 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1. Overview 48 S3A7 Datasheet P500 49 32 P300/TCK/SWCLK P501 50 31 P301 P502 51 30 P302 P015 52 29 P303 P014 53 28 P304 P013/VREFL 54 27 P200 P012/VREFH 55 26 P201/MD AVCC0 56 25 RES AVSS0 57 24 P204 P011/VREFL0 58 23 P205 P010/VREFH0 59 22 P206 P004 60 21 VCC_USB_LDO P003 61 20 VCC_USB P002 62 19 USB_DP P001 63 18 USB_DM P000 64 17 VSS_USB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P400 P401 P402 VBATT VCL P215/XCIN P214/XCOUT VSS P213/XTAL P212/EXTAL VCC P411 P410 P409 P408 P407 R7FS3A77C3A01CFM Pin assignment for 64-pin LQFP (top view) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 21 of 137 33 34 35 36 37 38 39 40 41 42 43 44 P102 P103 P104 P105 P106 P107 VSS VCC P113 P112 P111 P110/TDI P109/TDO/SWO P108/TMS/SWDIO 45 46 47 P100 P101 1. Overview 48 S3A7 Datasheet P500 P501 P502 P015 P014 P013/VREFL P012/VREFH AVCC0 AVSS0 P011/VREFL0 P010/VREFH0 P004 P003 P002 P001 49 32 50 31 58 23 59 22 60 21 61 20 62 19 63 18 P300/TCK/SWCLK P301 P302 P303 P304 P200 P201/MD RES P204 P205 P206 VCC_USB_LDO VCC_USB USB_DP USB_DM 51 30 52 29 53 28 54 27 55 26 P000 64 17 VSS_USB 24 16 15 14 13 12 11 10 9 8 7 6 5 4 25 P400 P401 P402 VBATT VCL P215/XCIN P214/XCOUT VSS P213/XTAL P212/EXTAL VCC P411 P410 P409 P408 P407 3 R7FS3A77C3A01CNB 1 57 2 56 Figure 1.9 Pin assignment for 64-pin QFN (top view) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 22 of 137 S3A7 Datasheet Pin Lists N13 1 L11 1 J10 1 1 IRQ0 P400 GTIOC 6A_A SCK4_ SCL0_ B A L11 2 K11 2 J9 2 2 IRQ5 P401 GTET GTIOC RGA_ 6B_A B CTX0_ CTS4_ SDA0_ B RTS4_ A B/ SS4_B M13 3 J10 3 F6 3 3 IRQ4 P402 AGTIO 0_B/ AGTIO 1_B K11 4 J11 4 H10 VBAT WIO1 P403 AGTIO 0_C/ AGTIO 1_C L12 5 H9 5 G8 VBAT WIO2 L13 6 H10 6 H9 J10 7 H11 7 F7 H10 8 G6 K12 9 G7 K13 10 G8 J11 11 H11 12 P704 G11 13 J12 14 VBAT WIO0 AUDIO _CLK CTSU SLCDC ACMPHS, ACMPLP HMI DAC12, OPAMP ADC14 SDHI Analogs SSI SPI/QSPI IIC SCI USBFS,CAN RTC GPT Communication interfaces GPT_OPS, POEG AGT External bus I/O ports Timers Interrupt QFN64 LQFP64 LGA100 LQFP100 BGA121 LGA145 LQFP144 Pin number Power, System, Clock, Debug, CAC, VBATT 1.7 1. Overview TS20 TS19 RTCIC CRX0_ 0 B TS18 GTIOC RTCIC 3A_B 1 SSISC K0_A TS17 P404 GTIOC RTCIC 3B_B 2 SSIWS 0_A TS16 P405 GTIOC 1A_B SSITX D0_A TS15 P406 GTIOC 1B_B SSIRX D0_A TS14 P700 GTIOC 5A_B TS32 P701 GTIOC 5B_B TS33 P702 GTIOC 6A_B TS34 P703 GTIOC 6B_B P705 G10 8 G9 4 4 VBATT J13 15 G11 9 G10 5 5 VCL H13 16 F11 10 F10 6 6 XCIN P215 H12 17 F10 11 F9 7 7 XCOU T P214 F12 18 G9 12 D9 8 8 VSS G12 19 E10 13 E9 9 9 XTAL IRQ2 P213 GTET RGC_ A TXD1_ A/ MOSI1 _A/ SDA1_ A G13 20 E11 14 E10 10 10 EXTAL IRQ3 P212 AGTE GTET E1 RGD_ A RXD1_ A/ MISO1 _A/ SCL1_ A F13 21 F9 15 D10 11 11 VCC G10 22 P713 GTIOC 2A_B F11 23 P712 GTIOC 2B_B E13 24 P711 CTS1_ RTS1_ B/ SS1_B E12 25 F8 P710 SCK1_ B TS35 F10 26 F7 IRQ10 P709 TXD1_ B/ MOSI1 _B/ SDA1_ B TS13 D13 27 E9 16 F8 CACR IRQ11 P708 EF_B RXD1_ B/ MISO1 _B/ SCL1_ B E11 28 D10 17 E8 P415 D12 29 D11 18 E7 P414 SSLA1 _B SD0W P TS10 E10 30 E8 19 C9 P413 GTOU UP_B CTS0_ RTS0_ B/ SS0_B SSLA0 _B SD0CL K TS09 C13 31 D9 20 C10 P412 GTOU LO_B SCK0_ B RSPC KA_B SD0C MD TS08 R01DS0263EU0140 Rev.1.40 Oct 29, 2018 SSLA3 _B TS12 SSLA2 _B TS11 Page 23 of 137 1. Overview CTSU SLCDC ACMPHS, ACMPLP HMI DAC12, OPAMP ADC14 SDHI Analogs SSI SPI/QSPI IIC SCI USBFS,CAN RTC GPT Communication interfaces GPT_OPS, POEG AGT External bus I/O ports Timers Interrupt QFN64 LQFP64 LGA100 LQFP100 BGA121 LGA145 LQFP144 Pin number Power, System, Clock, Debug, CAC, VBATT S3A7 Datasheet D11 32 C11 21 D8 12 12 IRQ4 P411 AGTO GTOV GTIOC A1 UP_B 9A_A TXD0_ B/ MOSI0 _B/ SDA0_ B/ CTS3_ RTS3_ A/ SS3_A MOSIA _B SD0D AT0 TS07 C12 33 C10 22 E6 13 13 IRQ5 P410 AGTO GTOV GTIOC B1 LO_B 9B_A RXD0_ B/ MISO0 _B/ SCL0_ B/ SCK3_ A MISOA _B SD0D AT1 TS06 B13 34 C9 23 B10 14 14 IRQ6 P409 GTOW UP_B USB_E TXD3_ XICEN A/ _A MOSI3 _A/ SDA3_ A TS05 D10 35 B11 24 D7 15 15 IRQ7 P408 GTOW LO_B USB_I RXD3_ D_A A/ MISO3 _A/ SCL3_ A TS04 A13 36 A11 25 A10 16 16 B11 37 B9 26 B8 17 17 A12 38 A10 27 A9 18 18 B12 39 B10 28 B9 19 19 A11 40 A9 29 A8 20 20 VCC_ USB C11 41 B8 30 C8 21 21 VCC_ USB_L DO B10 42 C8 31 C7 22 22 A10 43 A8 32 A7 23 23 CLKO UT_A C10 44 D8 33 B7 24 24 CACR EF_A A9 45 A7 34 D6 C9 46 B7 35 C6 RTCO USB_V CTS4_ SDA0_ SSLB3 _A UT BUS RTS4_ B A/ SS4_A P407 ADTR G0_B TS03 VSS_U SB USB_ DM USB_ DP GTIU_ A USB_V RXD4_ SDA1_ SSLB1 SSIDA SD0D A _A TA1_A AT2 BUSE A/ N_A MISO4 _A/ SCL4_ A TS01 AGTO GTIV_ GTIOC 1 A 4A_B USB_ TXD4_ SCL1_ SSLB0 SSIWS SD0D A _A 1_A AT3 OVRC A/ URA MOSI4 _A/ SDA4_ A/ CTS9_ RTS9_ A/ SS9_A TSCA P_A P204 AGTIO GTIW_ GTIOC 1_A A 4B_B USB_ SCK4_ SCL0_ RSPC SSISC SD0D B KB_A K1_A AT4 OVRC A/ URB SCK9_ A SEG23 TS00 IRQ2 P203 GTIOC 5A_A CTX0_ CTS2_ A RTS2_ A/ SS2_A / TXD9_ A/ MOSI9 _A/ SDA9_ A MOSIB _A SD0D AT5 SEG22 TSCA P_B IRQ3 P202 GTIOC 5B_A CRX0_ SCK2_ A A/ RXD9_ A/ MISO9 _A/ SCL9_ A MISOB _A SD0D AT6 SEG21 SD0D AT7 SEG20 IRQ0 P206 WAIT IRQ1 P205 A16 WR1/ BC1 B9 47 C7 P313 D9 48 D7 P314 SEG4 D8 49 E7 P315 SEG5 A8 50 P900 SEG6 B8 51 P901 SEG7 B7 52 P902 SEG8 A7 53 A6 A6 54 B6 C7 55 C6 38 D5 25 25 RES B6 56 D6 39 B5 26 26 MD C8 57 E6 40 A5 27 27 C6 58 36 37 A6 VSS B6 VCC R01DS0263EU0140 Rev.1.40 Oct 29, 2018 P201 NMI P200 P312 CS3 SEG9 Page 24 of 137 1. Overview B5 59 P311 CS2 SEG10 D7 60 P310 A15 SEG11 A5 61 B5 P309 A14 SEG12 C5 62 A5 P308 A13 SEG13 A4 63 C5 41 C5 P307 A12 SEG14 B4 64 B4 42 D4 P306 A11 SEG15 D6 65 A4 43 A4 IRQ8 P305 A10 C4 66 E5 44 B4 IRQ9 P304 A09 A3 67 C4 45 C4 P808 B3 68 A3 46 A3 P809 D5 69 B3 47 B3 29 29 A2 70 D5 48 B2 30 30 C3 71 A2 49 C2 31 31 B2 72 A1 50 A2 32 32 TCK/ SWCL K P300 GTIOC 0A_A A1 73 B2 51 A1 33 33 TMS/ SWDI O P108 GTIOC 0B_A CTS9_ RTS9_ B/ SS9_B SSLB0 _B D4 74 B1 52 B1 34 34 TDO/ SWO/ CLKO UT_B P109 GTOV GTIOC UP_A 1A_A TXD9_ B/ MOSI9 _B/ SDA9_ B MOSIB _B B1 75 C3 53 C3 35 35 TDI IRQ3 P110 GTOV GTIOC LO_A 1B_A CTS2_ RTS2_ B/ SS2_B / RXD9_ B/ MISO9 _B/ SCL9_ B MISOB _B C2 76 D3 54 D3 36 36 IRQ4 P111 A05 GTIOC 3A_A SCK2_ B/ SCK9_ B RSPC KB_B D3 77 C1 55 C1 37 37 P112 A04 GTIOC 3B_A TXD2_ B/ MOSI2 _B/ SDA2_ B SSISC K0_B CAPL C1 78 C2 56 E5 38 38 P113 A03 RXD2_ B/ MISO2 _B/ SCL2_ B SSIWS 0_B SEG0/ COM4 E4 79 D4 57 D2 P114 A02 SSIRX D0_B SEG24 E3 80 D1 58 E4 P115 A01 SSITX D0_B SEG25 D2 81 P806 D1 82 P807 F4 83 D2 59 D1 P608 A00/ BC0 SEG28 E2 84 E3 60 E3 P609 CS1 SEG29 F3 85 E1 61 E2 P610 CS0 SEG30 E1 86 E4 P611 F2 87 F5 P612 D08 SEG32 F1 88 E2 P613 D09 SEG33 G3 89 P614 D10 SEG34 G1 90 F1 62 E1 39 39 VCC G2 91 G1 63 F1 40 40 VSS H1 92 H2 93 F2 P605 D11 SEG36 G4 94 F3 P604 D12 SEG37 H3 95 F4 64 F2 P603 D13 SEG38 J1 96 G2 65 F3 P602 EBCLK SEG39 J2 97 G5 66 F4 P601 WR/ WR0 SEG40 H4 98 G4 67 F5 P600 RD SEG41 K2 99 P805 SEG42 K1 100 P804 SEG43 28 28 SEG16 GTIOC 7A_A SEG17 SEG18 SEG19 P303 A08 GTIOC 7B_A IRQ5 P302 A07 GTOU GTIOC UP_A 4A_A TXD2_ A/ MOSI2 _A/ SDA2_ A SSLB3 _B SEG2/ COM6 IRQ6 P301 A06 GTOU GTIOC LO_A 4B_A RXD2_ A/ MISO2 _A/ SCL2_ A SSLB2 _B SEG1/ COM5 SEG3/ COM7 SSLB1 _B VCOU T CAPH SEG26 SEG27 SEG31 P606 R01DS0263EU0140 Rev.1.40 Oct 29, 2018 CTSU SLCDC ACMPHS, ACMPLP HMI DAC12, OPAMP ADC14 SDHI Analogs SSI SPI/QSPI IIC SCI USBFS,CAN RTC GPT Communication interfaces GPT_OPS, POEG AGT I/O ports External bus Timers Interrupt QFN64 LQFP64 LGA100 LQFP100 BGA121 LGA145 LQFP144 Pin number Power, System, Clock, Debug, CAC, VBATT S3A7 Datasheet SEG35 Page 25 of 137 1. Overview J3 101 H1 68 G3 41 41 KR07 P107 D07 GTIOC 8A_A K3 102 G3 69 G2 42 42 KR06 P106 D06 GTIOC 8B_A J4 103 H2 70 G1 43 43 KR05/ P105 IRQ0 D05 L3 104 H3 71 H1 44 44 KR04/ P104 IRQ1 L1 105 J1 72 H3 45 45 KR03 M1 106 J2 73 J1 46 46 KR02 M2 107 K1 74 H2 47 N1 108 L1 75 H4 48 COM3 SSLA3 _A COM2 GTET RGA_ C SSLA2 _A COM1 D04 GTET RGB_ B SSLA1 _A COM0 P103 D03 GTOW GTIOC UP_A 2A_A CTS0_ RTS0_ A/ SS0_A SSLA0 _A AN024 CMPR VL4 EF1 P102 D02 AGTO GTOW GTIOC 0 LO_A 2B_A SCK0_ A RSPC KA_A AN025 / ADTR G0_A CMPIN VL3 1 47 KR01/ P101 IRQ1 D01 AGTE GTET E0 RGB_ A TXD0_ SDA1_ MOSIA B _A A/ MOSI0 _A/ SDA0_ A/ CTS1_ RTS1_ A/ SS1_A AN026 CMPR VL2 EF0 48 KR00/ P100 IRQ2 D00 AGTIO GTET 0_A RGA_ A RXD0_ SCL1_ MISOA B _A A/ MISO0 _A/ SCL0_ A/ SCK1_ A AN027 CMPIN VL1 0 L2 109 L2 P800 D14 SEG44 N2 110 K2 P801 D15 SEG45 N3 111 P802 M3 112 P803 K4 113 K3 76 K1 49 49 P500 AGTO GTIU_ A0 B USB_V BUSE N_B QSPC LK AN016 SEG48 M4 114 L3 77 J2 50 50 IRQ11 P501 AGTO GTIV_ B0 B USB_ OVRC URA QSSL AN017 SEG49 L4 115 J3 78 K2 51 51 IRQ12 P502 GTIW_ B USB_ OVRC URB QIO0 AN018 SEG50 K5 116 J4 79 G4 P503 GTET RGC_ B USB_E XICEN _B QIO1 AN019 SEG51 L5 117 H4 80 G5 P504 GTET RGD_ B USB_I D_B QIO2 AN020 81 G6 K6 118 J5 L6 119 H5 IRQ14 P505 CTSU SLCDC ACMPHS, ACMPLP HMI DAC12, OPAMP ADC14 SDHI Analogs SSI SPI/QSPI IIC SCI USBFS,CAN RTC GPT Communication interfaces GPT_OPS, POEG AGT External bus I/O ports Timers Interrupt QFN64 LQFP64 LGA100 LQFP100 BGA121 LGA145 LQFP144 Pin number Power, System, Clock, Debug, CAC, VBATT S3A7 Datasheet SEG46 SEG47 QIO3 AN021 IRQ15 P506 AN022 P507 AN023 N4 120 N5 121 L4 82 K3 M5 122 K4 83 J3 M6 123 K5 84 J4 52 52 IRQ13 P015 AN015 DA1 IVCMP 5/ IVCMP 2 N6 124 L5 85 K4 53 53 P014 AN014 DA0 IVREF 5/ IVREF 2 VCC VSS M7 125 K6 86 J5 54 54 VREFL P013 AN013 AMP1+ N7 126 L6 87 K5 55 55 VREF H P012 AN012 AMP1- L7 127 J6 88 H5 56 56 AVCC0 L8 128 J7 89 H6 57 57 AVSS0 M8 129 K7 90 J6 58 58 VREFL IRQ15 P011 0 AN011 AMP2+ TS31 N8 130 L7 91 K6 59 59 VREF H0 IRQ14 P010 AN010 AMP2- TS30 M9 131 IRQ13 P009 AN009 N9 132 H6 92 J7 IRQ12 P008 AN008 K7 133 H7 93 H7 P007 AN007 AMP3 IVCMP O 4/ IVCMP 1 L9 134 H8 94 G7 IRQ11 P006 AN006 AMP3- IVREF 4/ IVREF 1 TS27 K8 135 L8 95 K7 IRQ10 P005 AN005 AMP3+ IVREF 0 TS26 K9 136 J8 96 J8 IRQ9 AN004 AMP2 IVCMP O 0 60 60 R01DS0263EU0140 Rev.1.40 Oct 29, 2018 P004 TS29 Page 26 of 137 1. Overview K10 137 K8 97 H8 61 61 M10 138 J9 98 K8 62 62 N10 139 K9 99 K9 63 L10 140 L9 100 K10 64 N11 141 N12 142 M11 143 L10 IRQ14 P512 GTIOC 0A_B TXD4_ SCL2 B/ MOSI4 _B/ SDA4_ B M12 144 K10 IRQ15 P511 GTIOC 0B_B RXD4_ SDA2 B/ MISO4 _B/ SCL4_ B E5 Note: CTSU SLCDC ACMPHS, ACMPLP HMI DAC12, OPAMP ADC14 SDHI Analogs SSI SPI/QSPI IIC SCI USBFS,CAN RTC GPT Communication interfaces GPT_OPS, POEG AGT External bus I/O ports Timers Interrupt QFN64 LQFP64 LGA100 LQFP100 BGA121 LGA145 LQFP144 Pin number Power, System, Clock, Debug, CAC, VBATT S3A7 Datasheet P003 AN003 AMP1 IVREF O 3/ IVCMP 3 IRQ8 P002 AN002 AMP0 IVREF O 2/ IVCMP 2 63 IRQ7 P001 AN001 AMP0- IVREF 1/ IVCMP 1 TS22 64 IRQ6 P000 AN000 AMP0+ IVREF 0/ IVCMP 0 TS21 VSS VCC F6 NC Some pin names have the added suffix of _A, _B, and _C. The suffix can be ignored when assigning functionality. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 27 of 137 S3A7 Datasheet 2. 2. Electrical Characteristics Electrical Characteristics Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions: VCC*1 = AVCC0 = VCC_USB*2 = VCC_USB_LDO*2 = 1.6 to 5.5V, VREFH = VREFH0 = 1.6 to AVCC0, VBATT = 1.6 to 3.6V, VSS = AVSS0 = VREFL = VREFL0 = VSS_USB = 0V, Ta = Topr Note 1. The typical condition is set to VCC = 3.3V. Note 2. When USBFS is not used. Figure 2.1 shows the timing conditions. For example P100 C VOH = VCC x 0.7, VOL = VCC x 0.3 VIH = VCC x 0.7, VIL = VCC x 0.3 Load capacitance C = 30pF Figure 2.1 Input or output timing measurement conditions The measurement conditions of timing specification in each peripherals are recommended for the best peripheral operation. However, make sure to adjust driving abilities of each pin to meet your conditions. Each function pin used for the same function must select the same drive ability. If the I/O drive ability of each function pin is mixed, the AC specification of each function is not guaranteed. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 28 of 137 S3A7 Datasheet 2.1 2. Electrical Characteristics Absolute Maximum Ratings Table 2.1 Absolute maximum ratings Parameter Power supply voltage Input voltage ports*1 Symbol Value Unit VCC -0.5 to +6.5 V Vin -0.3 to +6.5 V P000 to P015 Vin -0.3 to AVCC0 + 0.3 V Others Vin -0.3 to VCC + 0.3 V VREFH0 -0.3 to +6.5 V 5V-tolerant Reference power supply voltage VREFH V VBATT power supply voltage VBATT -0.5 to +6.5 V Analog power supply voltage AVCC0 -0.5 to +6.5 V USB power supply voltage VCC_USB -0.5 to +6.5 V VCC_USB_LDO -0.5 to +6.5 V VAN -0.3 to AVCC0 + 0.3 V -0.3 to VCC + 0.3 V Analog input voltage When AN000 to AN015 are used When AN016 to AN027 are used LCD voltage VL1 voltage VL1 -0.3 to +2.8 V VL2 voltage VL2 -0.3 to +6.5 V VL3 voltage VL3 -0.3 to +6.5 V VL4 voltage VL4 -0.3 to +6.5 V Topr -40 to +85 C -40 to +105 C -55 to +125 C Operating temperature*2 *3 *4 Storage temperature Tstg Note 1. Note 2. Note 3. Ports P205, P206, P400 to P404, P407, P511, P512 are 5V-tolerant. See section 2.2.1, Tj/Ta Definition. Contact Renesas Electronics sales office for information on derating operation under Ta = +85C to +105C. Derating is the systematic reduction of load for improved reliability. Note 4. The upper limit of operating temperature is 85C or 105C, depending on the product. For details, refer to section 1.3, Part Numbering. Caution: Permanent damage to the MCU may result if absolute maximum ratings are exceeded. To preclude any malfunctions due to noise interference, insert capacitors of high frequency characteristics between the VCC and VSS pins, between the AVCC0 and AVSS0 pins, between the VCC_USB and VSS_USB pins, between the VREFH0 and VREFL0 pins, and between the VREFH and VREFL pins. Place capacitors of about 0.1 F as close as possible to every power supply pin and use the shortest and heaviest possible traces. Also, connect capacitors as stabilization capacitance. Connect the VCL pin to a VSS pin by a 4.7 F capacitor. The capacitor must be placed close to the pin. Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up might cause malfunction and the abnormal current that passes in the device at this time might cause degradation of internal elements. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 29 of 137 S3A7 Datasheet Table 2.2 2. Electrical Characteristics Recommended operating conditions Parameter Symbol Value Min Typ Max Unit Power supply voltages VCC*1, *2 When USBFS is not used 1.6 - 5.5 V When USBFS is used USB Regulator Disable VCC_USB - 3.6 V When USBFS is used USB Regulator Enable VCC_USB _LDO - 5.5 V - 0 - V When USBFS is not used - VCC - V When USBFS is used USB Regulator Disable (Input) 3.0 3.3 3.6 V When USBFS is not used - VCC - V When USBFS is used USB Regulator Disable - VCC - V When USBFS is used USB Regulator Enable 3.8 - 5.5 V - 0 - V When the battery backup function is not used - VCC - V When the battery backup function is used 1.6 - 3.6 V AVCC0*1, *2 1.6 - 5.5 V AVSS0 - 0 - V VSS USB power supply voltages VCC_USB VCC_USB_LDO VSS_USB VBATT power supply voltage Analog power supply voltages VBATT VREFH0 VREFL0 VREFH VREFL Note 1. Note 2. When used as ADC14 Reference When used as DAC12 Reference 1.6 - AVCC0 V - 0 - V 1.6 - AVCC0 V - 0 - V Use AVCC0 and VCC under the following conditions: AVCC0 and VCC can be set individually within the operating range when VCC 2.2 V and AVCC0 2.2 V AVCC0 = VCC when VCC < 2.2 V or AVCC0 < 2.2 V When powering on the VCC and AVCC0 pins, power them on at the same time or the VCC pin first and then the AVCC0 pin. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 30 of 137 S3A7 Datasheet 2.2 2. Electrical Characteristics DC Characteristics 2.2.1 Tj/Ta Definition Table 2.3 DC Characteristics Conditions: Products with operating temperature (Ta) -40 to +105C Parameter Symbol Typ Max Unit Test conditions Permissible junction temperature Tj - 125 C High-speed mode Middle-speed mode Low-voltage mode Low-speed mode Subosc-speed mode 105*1 Note: Make sure that Tj = Ta + ja x total power consumption (W), where total power consumption = (VCC - VOH) x IOH + VOL x IOL + ICCmax x VCC. Note 1. The upper limit of operating temperature is 85C or 105C, depending on the product. For details, see section 1.3, Part Numbering. If the part number shows the operation temperature as 85C, then Tj max is 105C, otherwise it is 125C. 2.2.2 I/O VIH, VIL Table 2.4 I/O VIH, VIL (1) Conditions: VCC = 2.7 to 5.5 V, AVCC0 = 2.7 to 5.5 V, VBATT = 1.6 to 3.6 V, VSS = AVSS0 = 0 V Parameter Schmitt trigger input voltage Input voltage (except for Schmitt trigger input pin) When VBATT power supply is selected Note 1. Note 2. Note 3. Symbol Min Typ Max Unit Test conditions VIH VCC x 0.7 - 5.8 V - VIL - - VCC x 0.3 VT VCC x 0.05 - - RES, NMI Other peripheral input pins excluding IIC VIH VCC x 0.8 - - VIL - - VCC x 0.2 VT VCC x 0.1 - - IIC (SMBus)*2 VIH 2.2 - - VCC = 3.6 to 5.5 V VIH 2.0 - - VCC = 2.7 to 3.6 V - IIC*1 (except for SMBus) VIL - - 0.8 5V-tolerant ports*3 VIH VCC x 0.8 - 5.8 VIL - - VCC x 0.2 P000 to P015 VIH AVCC0 x 0.8 - - VIL - - AVCC0 x 0.2 EXTAL D00 to D15 Input ports pins except for P000 to P015 VIH VCC x 0.8 - - VIL - - VCC x 0.2 P402, P403, P404 VIH VBATT x 0.8 - VBATT + 0.3 VIL - - VBATT x 0.2 VT VBATT x 0.05 - - SCL0_A, SDA0_A, SCL1_A, SDA1_A, SCL2, SDA2, SDA0_B (total 7 pins). SCL0_A, SDA0_A, SCL0_B, SDA0_B, SCL1_A, SDA1_A, SCL1_B, SDA1_B, SCL2, SDA2 (total 10 pins). P205, P206, P400 to P404, P407, P511, P512 (total 10 pins). R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 31 of 137 S3A7 Datasheet Table 2.5 2. Electrical Characteristics I/O VIH, VIL (2) Conditions: VCC = 1.6 to 2.7 V, AVCC0 = 1.6 to 2.7 V, VBATT = 1.6 to 3.6 V, VSS = AVSS0 = 0 V Parameter Symbol Min Typ Max Unit Test conditions V - Schmitt trigger input voltage RES, NMI Peripheral input pins Input voltage (except for Schmitt trigger input pin) 5V-tolerant ports*1 VIL - - VCC x 0.2 P000 to P015 VIH AVCC0 x 0.8 - - When VBATT power supply is selected Note 1. VIH VCC x 0.8 - - VIL - - VCC x 0.2 VT VCC x 0.01 - - VIH VCC x 0.8 - 5.8 VIL - - AVCC0 x 0.2 EXTAL D0 to D15 Input ports pins except for P000 to P015 VIH VCC x 0.8 - - VIL - - VCC x 0.2 P402, P403, P404 VIH VBATT x 0.8 - VBATT + 0.3 VIL - - VBATT x 0.2 VT VBATT x 0.01 - - P205, P206, P400 to P404, P407, P511, P512 (total 10 pins) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 32 of 137 S3A7 Datasheet 2.2.3 2. Electrical Characteristics I/O IOH, IOL Table 2.6 I/O IOH, IOL Conditions: VCC = AVCC0 = 1.6 to 5.5 V Parameter Permissible output current (average value per pin) Ports P000 to P015, Ports P212, P213 - Ports P408, P409 Low drive*1 Middle drive*2 VCC = 2.7 to 3.0 V Middle drive*2 VCC = 3.0 to 5.5 V Ports P100 to P115, P201 to P204, P300 to P315, P500 to P503, P600 to P606, P608 to P614, P800 to P809, P900 to P902 (total 67 pins) Low drive*1 Other output pin*3 Low drive*1 Middle drive*2 Middle drive*2 Permissible output current (Max value per pin) Ports P000 to P015, Ports P212, P213 - Ports P408, P409 Low drive*1 Middle drive*2 VCC = 2.7 to 3.0 V Middle drive*2 VCC = 3.0 to 5.5 V Ports P100 to P115, P201 to P204, P300 to P315, P500 to P503, P600 to P606, P608 to P614, P800 to P809, P900 to P902 (total 67 pins) Other output pin*3 Low drive*1 Middle Low drive*1 Middle Permissible output current (max value total pins) Total of ports P000 to P015 Total of all output pin Caution: Note 1. Note 2. Note 3. drive*2 drive*2 Symbol Min Typ Max Unit IOH - - -4.0 mA IOL - - 4.0 mA IOH - - -4.0 mA IOL - - 4.0 mA IOH - - -8.0 mA IOL - - 8.0 mA IOH - - -20.0 mA IOL - - 20.0 mA IOH - - -4.0 mA IOL - - 4.0 mA IOH - - -4.0 mA IOL - - 8.0 mA IOH - - -4.0 mA IOL - - 4.0 mA IOH - - -8.0 mA IOL - - 8.0 mA IOH - - -4.0 mA IOL - - 4.0 mA IOH - - -4.0 mA IOL - - 4.0 mA IOH - - -8.0 mA IOL - - 8.0 mA IOH - - -20.0 mA IOL - - 20.0 mA IOH - - -4.0 mA IOL - - 4.0 mA IOH - - -4.0 mA IOL - - 8.0 mA IOH - - -4.0 mA IOL - - 4.0 mA IOH - - -8.0 mA IOL - - 8.0 mA IOH (max) - - -30 mA IOL (max) - - 30 mA IOH (max) - - -60 mA IOL (max) - - 60 mA To protect the reliability of the MCU, the output current values should not exceed the values in this table. The average output current indicates the average value of current measured during 100 s. This is the value when low driving ability is selected with the Port Drive Capability bit in PmnPFS register. This is the value when middle driving ability is selected with the Port Drive Capability bit in PmnPFS register. Except for ports P200, P214, P215, which are input ports. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 33 of 137 S3A7 Datasheet 2.2.4 2. Electrical Characteristics I/O VOH, VOL, and Other Characteristics Table 2.7 I/O VOH, VOL (1) Conditions: VCC = AVCC0 = 4.0 to 5.5 V Parameter Output voltage IIC*1, *2 Ports P408, P409*2, *3 Ports P000 to P015 Low drive Middle drive Other output pins*4 Low drive Middle drive*5 Note 1. Note 2. Note 3. Note 4. Note 5. Symbol Min Typ Max Unit Test conditions VOL - - 0.4 V IOL = 3.0 mA VOL - - 0.6 IOL = 6.0 mA VOH VCC - 1.0 - - IOH = -20 mA VOL - - 1.0 IOL = 20 mA VOH AVCC0 - 0.8 - - IOH = -2.0 mA VOL - - 0.8 IOL = 2.0 mA VOH AVCC0 - 0.8 - - IOH = -4.0 mA VOL - - 0.8 IOL = 4.0 mA VOH VCC - 0.8 - - IOH = -2.0 mA VOL - - 0.8 IOL = 2.0 mA VOH VCC - 0.8 - - IOH = -4.0 mA VOL - - 0.8 IOL = 4.0 mA SCL0_A, SDA0_A, SCL0_B, SDA0_B, SCL1_A, SDA1_A, SCL1_B, SDA1_B, SCL2, SDA2 (total 10 pins). This is the value when middle driving ability is selected with the Port Drive Capability bit in PmnPFS register. Based on characterization data, not tested in production. Except for ports P200, P214, P215, which are input ports. Except for P212, P213. Table 2.8 I/O VOH, VOL (2) Conditions: VCC = AVCC0 = 2.7 to 4.0 V Parameter Output voltage IIC*1, *2 Ports P408, P409*2, *3 Ports P000 to P015 Low drive Middle drive Other output pins*4 Low drive Middle drive*5 Note 1. Note 2. Note 3. Note 4. Note 5. Symbol Min Typ Max Unit Test conditions VOL - - 0.4 V IOL = 3.0 mA VOL - - 0.6 IOL = 6.0 mA VOH VCC - 1.0 - - IOH = -20 mA VCC = 3.3 V VOL - - 1.0 IOL = 20 mA VCC = 3.3 V VOH AVCC0 - 0.5 - - IOH = -1.0 mA VOL - - 0.5 IOL = 1.0 mA VOH AVCC0 - 0.5 - - IOH = -2.0 mA VOL - - 0.5 IOL = 2.0 mA VOH VCC - 0.5 - - IOH = -1.0 mA VOL - - 0.5 IOL = 1.0 mA VOH VCC - 0.5 - - IOH = -2.0 mA VOL - - 0.5 IOL = 2.0 mA SCL0_A, SDA0_A, SCL0_B, SDA0_B, SCL1_A, SDA1_A, SCL1_B, SDA1_B, SCL2, SDA2 (total 10 pins). This is the value when middle driving ability is selected with the Port Drive Capability bit in PmnPFS register. Based on characterization data, not tested in production. Except for ports P200, P214, P215, which are input ports. Except for P212, P213. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 34 of 137 S3A7 Datasheet Table 2.9 2. Electrical Characteristics I/O VOH, VOL (3) Conditions: VCC = AVCC0 = 1.6 to 2.7 V Parameter Output voltage Ports P000 to P015 Other output pins*1 Symbol Min Typ Max Unit Test conditions Low drive VOH AVCC0 - 0.3 - - V IOH = -0.5 mA VOL - - 0.3 IOL = 0.5 mA Middle drive VOH AVCC0 - 0.3 - - IOH = -1.0 mA VOL - - 0.3 IOL = 1.0 mA VOH VCC - 0.3 - - IOH = -0.5 mA VOL - - 0.3 IOL = 0.5 mA VOH VCC - 0.3 - - IOH = -1.0 mA VOL - - 0.3 IOL = 1.0 mA Low drive Middle drive*2 Note 1. Except for ports P200, P214, P215, which are input ports. Note 2. Except for P212, P213. Table 2.10 I/O Other Characteristics Conditions: VCC = AVCC0 = 1.6 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions Input leakage current RES, P200, P214, P215 | Iin | - - 1.0 A Vin = 0 V Vin = VCC Three-state leakage current (off state) 5V-tolerant ports | ITSI | - - 1.0 A Vin = 0 V Vin = 5.8 V - - 1.0 Other ports (except for ports P200, P214, P215 and 5 V tolerant) Vin = 0 V Vin = VCC Input pull-up resistor All Ports (except for ports P200, P214, P215) RU 10 20 50 k Vin = 0 V Input capacitance USB_DP, USB_DM, P100 to P103, P111, P112, P200 Cin - - 30 pF Vin = 0 V f = 1 MHz Ta = 25C - - 15 Other input pins R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 35 of 137 S3A7 Datasheet 2.2.5 2. Electrical Characteristics I/O Pin Output Characteristics of Low Drive Capacity IOH/IOL vs VOH/VOL 60 50 VCC = 5.5 V 40 30 VCC = 3.3 V IOH/IOL [mA] 20 VCC = 2.7 V 10 VCC = 1.6 V 0 VCC = 1.6 V -10 VCC = 2.7 V -20 VCC = 3.3 V -30 -40 -50 VCC = 5.5 V -60 0 1 2 3 4 5 6 VOH/VOL [V] Figure 2.2 VOH/VOL and IOH/IOL voltage characteristics at Ta = 25C when low drive output is selected (reference data) IOH/IOL vs VOH/VOL 3 Ta = -40C Ta = 25C Ta = 105C 2 IOH/IOL [mA] 1 0 -1 Ta = 105C Ta = 25C -2 Ta = -40C -3 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH/VOL [V] Figure 2.3 VOH/VOL and IOH/IOL temperature characteristics at VCC = 1.6 V when low drive output is selected (reference data) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 36 of 137 S3A7 Datasheet 2. Electrical Characteristics IOH/IOL vs VOH/VOL 20 15 Ta = -40C Ta = 25C Ta = 105C IOH/IOL [mA] 10 5 0 -5 Ta = 105C Ta = 25C -10 Ta = -40C -15 -20 0 0.5 1 1.5 2 2.5 3 VOH/VOL [V] Figure 2.4 VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when low drive output is selected (reference data) IOH/IOL vs VOH/VOL 30 Ta = -40C Ta = 25C Ta = 105C 20 IOH/IOL [mA] 10 0 -10 Ta = 105C Ta = 25C -20 Ta = -40C -30 0 0.5 1 1.5 2 2.5 3 3.5 VOH/VOL [V] Figure 2.5 VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when low drive output is selected (reference data) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 37 of 137 S3A7 Datasheet 2. Electrical Characteristics IOH/IOL vs VOH/VOL 60 Ta = -40C Ta = 25C Ta = 105C 40 IOH/IOL [mA] 20 0 -20 Ta = 105C -40 Ta = 25C Ta = -40C -60 0 1 2 3 4 5 6 VOH/VOL [V] Figure 2.6 2.2.6 VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when low drive output is selected (reference data) I/O Pin Output Characteristics of Middle Drive Capacity IOH/IOL [mA] IOH/IOL vs VOH/VOL 140 120 100 80 60 40 20 VCC = 5.5 V VCC = 3.3 V VCC = 2.7 V VCC = 1.6 V 0 -20 -40 -60 -80 -100 -120 -140 VCC = 1.6 V VCC = 2.7 V VCC = 3.3 V VCC = 5.5 V 0 1 2 3 4 5 6 VOH/VOL [V] Figure 2.7 VOH/VOL and IOH/IOL voltage characteristics at Ta = 25C when middle drive output is selected (reference data) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 38 of 137 S3A7 Datasheet 2. Electrical Characteristics IOH/IOL vs VOH/VOL 6 Ta = -40C Ta = 25C Ta = 105C 4 IOH/IOL [mA] 2 0 -2 Ta = 105C -4 Ta = 25C Ta = -40C -6 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH/VOL [V] Figure 2.8 VOH/VOL and IOH/IOL temperature characteristics at VCC = 1.6 V when middle drive output is selected (reference data) IOH/IOL vs VOH/VOL 40 Ta = -40C Ta = 25C Ta = 105C 30 IOH/IOL [mA] 20 10 0 -10 -20 Ta = 105C Ta = 25C -30 Ta = -40C -40 0 0.5 1 1.5 2 2.5 3 VOH/VOL [V] Figure 2.9 VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when middle drive output is selected (reference data) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 39 of 137 S3A7 Datasheet 2. Electrical Characteristics IOH/IOL vs VOH/VOL 60 Ta = -40C Ta = 25C 40 Ta = 105C IOH/IOL [mA] 20 0 -20 Ta = 105C -40 Ta = 25C Ta = -40C -60 0 0.5 1 1.5 2 2.5 3 3.5 VOH/VOL [V] Figure 2.10 VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when middle drive output is selected (reference data) IOH/IOL [mA] IOH/IOL vs VOH/VOL 140 120 100 80 60 40 20 0 -20 -40 -60 -80 -100 -120 -140 Ta = -40C Ta = 25C Ta = 105C Ta = 105C Ta = 25C Ta = -40C 0 1 2 3 4 5 6 VOH/VOL [V] Figure 2.11 VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when middle drive output is selected (reference data) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 40 of 137 S3A7 Datasheet 2.2.7 2. Electrical Characteristics P408, P409 I/O Pin Output Characteristics of Middle Drive Capacity IOH/IOL [mA] IOH/IOL vs VOH/VOL 200 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 VCC = 5.5 V VCC = 3.3 V VCC = 2.7 V VCC = 2.7 V VCC = 3.3 V VCC = 5.5 V 0 1 2 3 4 5 6 VOH/VOL [V] Figure 2.12 VOH/VOL and IOH/IOL voltage characteristics at Ta = 25C when middle drive output is selected (reference data) IOH/IOL vs VOH/VOL 60 Ta = -40C Ta = 25C Ta = 105C 40 IOH/IOL [mA] 20 0 -20 Ta = 105C -40 Ta = 25C Ta = -40C -60 0 0.5 1 1.5 2 2.5 3 VOH/VOL [V] Figure 2.13 VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when middle drive output is selected (reference data) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 41 of 137 S3A7 Datasheet 2. Electrical Characteristics IOH/IOL vs VOH/VOL 100 Ta = -40C Ta = 25C Ta = 105C 80 60 40 IOH/IOL [mA] 20 0 -20 -40 Ta = 105C -60 Ta = 25C -80 Ta = -40C -100 0 0.5 1 1.5 2 2.5 3 3.5 VOH/VOL [V] Figure 2.14 VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when middle drive output is selected (reference data) IOH/IOL vs VOH/VOL 220 Ta = -40C Ta = 25C Ta = 105C 180 140 IOH/IOL [mA] 100 60 20 -20 -60 -100 -140 Ta = 105C Ta = 25C -180 Ta = -40C -220 0 1 2 3 4 5 6 VOH/VOL [V] Figure 2.15 VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when middle drive output is selected (reference data) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 42 of 137 S3A7 Datasheet 2.2.8 2. Electrical Characteristics IIC I/O Pin Output Characteristics IOL vs VOL 120 110 VCC = 5.5 V (Middle drive) 100 90 IOL [mA] 80 70 60 50 VCC = 3.3V (Middle drive) VCC = 5.5V (Low drive) 40 VCC = 2.7V (Middle drive) 30 VCC = 3.3V (Low drive) 20 10 VCC = 2.7V (Low drive) 0 0 1 2 3 4 5 6 VOL [V] Figure 2.16 VOH/VOL and IOH/IOL voltage characteristics at Ta = 25C R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 43 of 137 S3A7 Datasheet 2.2.9 Table 2.11 2. Electrical Characteristics Operating and Standby Current Operating and standby current (1) (1 of 2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Parameter Supply current*1 High-speed mode*2 Normal mode All peripheral clock disabled, while (1) code executing from flash*5 All peripheral clock disabled, CoreMark code executing from flash*5 Typ*10 ICC *7 - 8.6 - ICLK = 16 MHz 5.1 - ICLK = 8 MHz 3.4 - ICLK = 48 MHz 18.6 - 12.7 - ICLK = 8 MHz 4.5 - ICLK = 48 MHz 30.1 - *9 ICLK = 32 MHz 23.2 - *8 ICLK = 16 MHz 12.6 - ICLK = 8 MHz 7.3 - All peripheral clock enabled, code executing from SRAM*5 ICLK = 48 MHz - 75.0 *9 All peripheral clock disabled*5 ICLK = 48 MHz 6.4 - *7 ICLK = 32 MHz 4.7 - ICLK = 16 MHz 3.2 - ICLK = 8 MHz 2.4 - ICLK = 48 MHz 24.7 - *9 ICLK = 32 MHz 19.2 - *8 ICLK = 16 MHz 10.7 - ICLK = 8 MHz 6.4 - 2.5 - 3.6 - ICLK = 8 MHz 3.0 - ICLK = 1 MHz 1.4 - ICLK = 12 MHz 5.2 - ICLK = 8 MHz 4.0 - ICLK = 1 MHz 1.6 - ICLK = 12 MHz 9.4 - ICLK = 8 MHz 6.9 - All peripheral clock disabled, while (1) code executing from flash*5 All peripheral clock enabled, while (1) code executing from flash*5 ICLK = 12 MHz ICC ICLK = 1 MHz 2.2 - All peripheral clock enabled, code executing from SRAM*5 ICLK = 12 MHz - 30.0 All peripheral clock disabled*5 ICLK = 12 MHz 2.2 - ICLK = 8 MHz 2.0 - ICLK = 1 MHz 1.3 - ICLK = 12 MHz 7.9 - ICLK = 8 MHz 5.9 - All peripheral clock enabled*5 ICLK = 1 MHz Increase during BGO operation*6 R01DS0263EU0140 Rev.1.40 Oct 29, 2018 mA 11.8 7.2 All peripheral clock disabled, CoreMark code executing from flash*5 Sleep mode Test conditions ICLK = 32 MHz Increase during BGO operation*6 Normal mode Unit ICLK = 16 MHz All peripheral clock enabled*5 Middle-speed mode*2 Max ICLK = 32 MHz All peripheral clock enabled, while (1) code executing from flash*5 Sleep mode ICLK = 48 MHz Symbol 2.1 - 2.5 - mA *7 *8 *7 *8 - Page 44 of 137 S3A7 Datasheet Table 2.11 2. Electrical Characteristics Operating and standby current (1) (2 of 2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Parameter Supply current*1 Low-speed mode*3 Normal mode Sleep mode Low-voltage mode*3 Normal mode Sleep mode Suboscspeed mode*4 Normal mode Sleep mode Symbol Typ*10 Max Unit Test conditions ICC 0.5 - mA *7 All peripheral clock disabled, while (1) code executing from flash*5 ICLK = 1 MHz All peripheral clock disabled, CoreMark code executing from flash*5 ICLK = 1 MHz 0.7 - All peripheral clock enabled, while (1) code executing from flash*5 ICLK = 1 MHz 1.5 - All peripheral clock enabled, code executing from SRAM*5 ICLK = 1 MHz - 3.2 All peripheral clock disabled*5 ICLK = 1 MHz 0.4 - *7 All peripheral clock enabled*5 ICLK = 1 MHz 1.3 - *8 All peripheral clock disabled, while (1) code executing from flash*5 ICLK = 4 MHz 2.5 - All peripheral clock disabled, CoreMark code executing from flash*5 ICLK = 4 MHz 3.0 - All peripheral clock enabled, while (1) code executing from flash*5 ICLK = 4 MHz 4.5 - All peripheral clock enabled, code executing from SRAM*5 ICLK = 4 MHz - 11.2 All peripheral clock disabled*5 ICLK = 4 MHz 2.0 - *7 All peripheral clock enabled*5 ICLK = 4 MHz 4.0 - *8 All peripheral clock disabled, while (1) code executing from flash*5 ICLK = 32.768 kHz 13.5 - All peripheral clock enabled, while (1) code executing from flash*5 ICLK = 32.768 kHz 25.0 - All peripheral clock enabled, code executing from SRAM*5 ICLK = 32.768 kHz - 214.1 All peripheral clock disabled*5 ICLK = 32.768 kHz 9.5 - All peripheral clock enabled*5 ICLK = 32.768 kHz 21.0 - ICC ICC *8 mA *7 *8 A *8 Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up MOSs are in the off state. Note 2. The clock source is HOCO. Note 3. The clock source is MOCO. Note 4. The clock source is the sub-clock oscillator. Note 5. This does not include BGO operation. Note 6. This is the increase for programming or erasure of the flash memory for data storage during program execution. Note 7. FCLK, BCLK, PCLKA, PCLKB, PCLKC and PCLKD are set to divided by 64. Note 8. FCLK, BCLK, PCLKA, PCLKB, PCLKC and PCLKD are the same frequency as that of ICLK. Note 9. FCLK, BCLK, and PCLKB are set to divided by 2 and PCLKA, PCLKC and PCLKD are the same frequency as that of ICLK. Note 10. VCC = 3.3 V. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 45 of 137 S3A7 Datasheet 2. Electrical Characteristics 70 60 Ta = 105, ICLK = 48MHz*2 ICC (mA) 50 Ta = 105, ICLK = 32MHz*2 40 Ta = 25, ICLK = 48MHz*1 30 Ta = 25, ICLK = 32MHz*1 Ta = 105, ICLK = 16MHz*2 20 Ta = 25, ICLK = 16MHz*1 Ta = 105, ICLK = 8MHz*2 Ta = 25, ICLK = 8MHz*1 Ta = 105, ICLK = 4MHz*2 Ta = 25, ICLK = 4MHz*1 10 0 VCC (V) Ta = 25, ICLK = 48MHz *1 Ta = 25, ICLK = 32MHz *1 Ta = 25, ICLK = 16MHz *1 Ta = 25, ICLK = 8MHz *1 Ta = 25, ICLK = 4MHz *1 Ta = 105, ICLK = 48MHz *2 Ta = 105, ICLK = 32MHz *2 Ta = 105, ICLK = 16MHz *2 Ta = 105, ICLK = 8MHz *2 Ta = 105, ICLK = 4MHz *2 Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the actual measurements of the sample cores during product evaluation. Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the actual measurements for the upper-limit samples during product evaluation. Figure 2.17 Voltage dependency in High-speed operating mode (reference data) 20 ICC (mA) Ta = 105, ICLK = 12MHz*2 Ta = 105, ICLK = 8MHz*2 10 Ta = 25, ICLK = 12MHz*1 Ta = 25, ICLK = 8MHz*1 Ta = 105, ICLK = 4MHz*2 Ta = 25, ICLK = 4MHz*1 Ta = 105, ICLK = 1MHz*2 Ta = 25, ICLK = 1MHz*1 0 VCC (V) Ta = 25, ICLK = 12MHz *1 Ta = 25, ICLK = 8MHz *1 Ta = 25, ICLK = 4MHz *1 Ta = 25, ICLK = 1MHz *1 Ta = 105, ICLK = 12MHz *2 Ta = 105, ICLK = 8MHz *2 Ta = 105, ICLK = 4MHz *2 Ta = 105, ICLK = 1MHz *2 Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the actual measurements of the sample cores during product evaluation. Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the actual measurements for the upper-limit samples during product evaluation. Figure 2.18 Voltage dependency in Middle-speed mode (reference data) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 46 of 137 S3A7 Datasheet 2. Electrical Characteristics 3.0 2.5 Ta = 105, ICLK = 1MHz*2 ICC(A) 2.0 1.5 Ta = 25, ICLK = 1MHz*1 1.0 0.5 0.0 VCC (V) Ta = 25, ICLK = 1MHz *1 Ta = 105, ICLK = 1MHz *2 Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the actual measurements of the sample cores during product evaluation. Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the actual measurements for the upper-limit samples during product evaluation. Figure 2.19 Voltage dependency in Low-speed mode (reference data) 8 Ta = 105, ICLK = 4MHz*2 7 ICC (mA) 6 5 Ta = 25, ICLK = 4MHz*1 4 Ta = 105, ICLK = 1MHz*2 3 Ta = 25, ICLK = 1MHz*1 2 1 0 VCC (V) Ta = 25, ICLK = 4MHz *1 Ta = 25, ICLK = 1MHz *1 Ta = 105, ICLK = 4MHz *2 Ta = 105, ICLK = 1MHz *2 Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the actual measurements of the sample cores during product evaluation. Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the actual measurements for the upper-limit samples during product evaluation. Figure 2.20 Voltage dependency in Low-voltage mode (reference data) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 47 of 137 S3A7 Datasheet 2. Electrical Characteristics 160.0 Ta = 105, ICLK = 32kHz*2 140.0 120.0 ICC (A) 100.0 80.0 60.0 40.0 Ta = 25, ICLK = 32kHz*1 20.0 0.0 VCC (V) Ta = 25, ICLK = 32kHz *1 Ta = 105, ICLK = 32kHz *2 Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the actual measurements of the sample cores during product evaluation. Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the actual measurements for the upper-limit samples during product evaluation. Figure 2.21 Table 2.12 Voltage dependency in Subosc-speed mode (reference data) Operating and standby current (2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Parameter Supply current*1 Note 1. Note 2. Note 3. Note 4. Software Standby mode*2 Ta = 25C Symbol Typ*4 Max Unit Test conditions ICC A PSMCR.PSMC[1:0] = 01b (48 KB SRAM on) 0.9 6.0 Ta = 55C 1.6 12.2 Ta = 85C 4.8 27.1 Ta = 105C 12.2 66.7 Ta = 25C 1.1 7.5 Ta = 55C 2.2 17.0 Ta = 85C 7.5 43.3 Ta = 105C 19.6 105.9 Increment for RTC operation with low-speed on-chip oscillator*3 0.5 - - Increment for RTC operation with sub-clock oscillator*3 0.5 - SOMCR.SODRV[1:0] are 11b (Low power mode 3) 1.6 - SOMCR.SODRV[1:0] are 00b (Normal mode) PSMCR.PSMC[1:0] = 00b (All SRAM on) Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up MOSs are in the off state. The IWDT and LVD are not operating. Includes the current of sub-oscillation circuit or low-speed on-chip oscillator. VCC = 3.3 V. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 48 of 137 S3A7 Datasheet 2. Electrical Characteristics Figure 2.22 Temperature dependency in Software Standby mode 48 KB SRAM on (reference data) Figure 2.23 Temperature dependency in Software Standby mode all SRAM on (reference data) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 49 of 137 S3A7 Datasheet Table 2.13 2. Electrical Characteristics Operating and standby current (3) Conditions: VCC = AVCC0 = 0V, VBATT = 1.6 to 3.6 V, VSS = AVSS0 = 0V Parameter Supply current*1 Note 1. RTC operation when VCC is off Ta = 25C Ta = 55C Symbol Typ Max Unit Test conditions ICC 1.1 - A 1.2 - VBATT = 2.0 V SOMCR.SORDRV[1:0] = 11b (Low power mode 3) Ta = 85C 1.4 - Ta = 105C 1.6 - Ta = 25C 1.2 - Ta = 55C 1.3 - Ta = 85C 1.5 - Ta = 105C 1.7 - Ta = 25C 1.8 - Ta = 55C 2.1 - Ta = 85C 2.4 - Ta = 105C 2.7 - Ta = 25C 1.9 - Ta = 55C 2.2 - Ta = 85C 2.5 - Ta = 105C 2.8 - VBATT = 3.3 V SOMCR.SORDRV[1:0] = 11b (Low power mode 3) VBATT = 2.0 V SOMCR.SORDRV[1:0] = 00b (Normal mode) VBATT = 3.3 V SOMCR.SORDRV[1:0] = 00b (Normal mode) Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up MOSs are in the off state. Note 1. Figure 2.24 Average value of the tested middle sample during product evaluation. Temperature dependency of RTC operation with VCC off (reference data) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 50 of 137 S3A7 Datasheet Table 2.14 2. Electrical Characteristics Operating and standby current (4) Conditions: VCC = AVCC0 = 1.6 to 5.5 V, VREFH0 = 2.7 V to AVCC0 Symbol Min Typ Max Unit Test conditions IAVCC - - 3.0 mA - During A/D conversion (at low power conversion) - - 1.0 mA - During D/A conversion (per channel)*1 - 0.4 0.8 mA - Waiting for A/D and D/A conversion (all units)*6 - - 1.0 A - Parameter Analog power supply current Reference power supply current During A/D conversion (at high-speed conversion) During A/D conversion IREFH0 Waiting for A/D conversion (all units) During D/A conversion IREFH Waiting for D/A conversion (all units) Temperature sensor ITNS Low power Analog Comparator operating current ICMPLP Window mode - nA - - 50 100 A - - - 100 A - - 75 - A - 15 - A - 10 - A - Comparator Low-speed mode - 2 - A - - 70 100 A AVCC0 2.7 V IAMP Low power mode 1 unit operating - 2.5 4.0 A - 2 units operating - 4.5 8.0 A - 3 units operating - 6.5 11.0 A - 4 units operating - 8.5 14.0 A - 1 unit operating - 140 220 A - 2 units operating - 280 410 A - 3 units operating - 420 600 A - 4 units operating - 560 780 A - External resistance division method fLCD = fSUB = 128 Hz, 1/3 bias, and 4-time slice ILCD1 *5 - 0.34 - A - Internal voltage boosting method fLCD = fSUB = 128 Hz, 1/3 bias, and 4-time slice ILCD2*5 - 0.92 - A - Capacitor split method fLCD = fSUB = 128 Hz, 1/3 bias, and 4-time slice ILCD3*5 - 0.19 - A - During USB communication operation under the following settings and conditions: Host controller operation is set to Full-speed mode Bulk OUT transfer (64 bytes) x 1, bulk IN transfer (64 bytes) x 1 Connect peripheral devices via a 1-meter USB cable from the USB port. IUSBH*2 - 4.3 (VCC) 0.9 (VCC_USB)*4 - mA - During USB communication operation under the following settings and conditions: Function controller operation is set to Full-speed mode Bulk OUT transfer (64 bytes) x 1, bulk IN transfer (64 bytes) x 1 Connect the host device via a 1-meter USB cable from the USB port. IUSBF*2 - 3.6 (VCC) 1.1 (VCC_USB)*4 - mA - During suspended state under the following setting and conditions: Function controller operation is set to Full-speed mode (pull up the USB_DP pin) Software standby mode Connect the host device via a 1-meter USB cable from the USB port. ISUSP*3 - 0.35 (VCC) 170 (VCC_USB)*4 - A - High-speed mode Note 4. Note 5. Note 6. A 60 - Operational Amplifier operating current Note 1. Note 2. Note 3. 150 - - ICMPHS USB operating current - - Comparator High-speed mode High-Speed Analog Comparator operating current LCD operating current - Includes the reference power supply current in the power supply current value for D/A conversion. Includes current consumed by the USBFS only. Includes current supplied from the pull-up resistor of the USB_DP pin to the pull-down resistor of the host device, in addition to the current consumed by the MCU during the suspended state. When VCC = VCC_USB = 3.3 V. Includes current flowing to the LCD controller only. Does not include current flowing through the LCD panel. When the MSTPCRD.MSTPD16 (14-Bit A/D Converter Module Stop bit) is in the module-stop state. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 51 of 137 S3A7 Datasheet 2.2.10 2. Electrical Characteristics VCC Rise and Fall Gradient and Ripple Frequency Table 2.15 Rise and fall gradient characteristics Conditions: VCC = AVCC0 = 0 to 5.5 V Parameter Power-on VCC rising gradient Voltage monitor 0 reset disabled at startup Min Typ Max Unit Test conditions SrVCC 0.02 - 2 ms/V - 0.02 - - 0.02 - 2 Voltage monitor 0 reset enabled at startup*1 SCI/USB Boot Note 1. Note 2. Symbol mode*2 When OFS1.LVDAS = 0. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of the OFS1.LVDAS bit. Table 2.16 Rising and falling gradient and ripple frequency characteristics Conditions: VCC = AVCC0 = VCC_USB = 1.6 to 5.5 V The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (5.5 V) and lower limit (1.6 V). When VCC change exceeds VCC 10%, the allowable voltage change rising/falling gradient dt/dVCC must be met. Parameter Symbol Min Typ Max Unit Test conditions Allowable ripple frequency fr (VCC) - - 10 kHz Figure 2.25 Vr (VCC) VCC x 0.2 - - 1 MHz Figure 2.25 Vr (VCC) VCC x 0.08 - - 10 MHz Figure 2.25 Vr (VCC) VCC x 0.06 1.0 - - ms/V When VCC change exceeds VCC 10% Allowable voltage change rising and falling gradient dt/dVCC 1/fr(VCC) VCC Figure 2.25 Vr(VCC) Ripple waveform R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 52 of 137 S3A7 Datasheet 2.3 2. Electrical Characteristics AC Characteristics 2.3.1 Frequency Table 2.17 Operation frequency value in High-speed operating mode Conditions: VCC = AVCC0 = 2.4 to 5.5 V Symbol Min Typ Max*5 Unit f 0.032768 - 48 MHz 2.4 to 2.7 V 0.032768 - 16 2.7 to 5.5 V 0.032768 - 32 2.4 to 2.7 V 0.032768 - 16 2.7 to 5.5 V - - 48 2.4 to 2.7 V - - 16 2.7 to 5.5 V - - 32 2.4 to 2.7 V - - 16 2.7 to 5.5 V - - 64 2.4 to 2.7 V - - 16 2.7 to 5.5 V - - 64 2.4 to 2.7 V - - 16 2.7 to 5.5 V - - 24 2.4 to 2.7 V - - 16 2.7 to 5.5 V - - 12 2.4 to 2.7 V - - 8 Parameter Operation frequency System clock (ICLK)*4 FlashIF clock (FCLK)*1, *2, *4 Peripheral module clock Peripheral module clock Peripheral module clock Peripheral module clock External bus clock EBCLK pin output Note 1. Note 2. Note 3. Note 4. Note 5. 2.7 to 5.5 V (PCLKA)*4 (PCLKB)*4 (PCLKC)*3, *4 (PCLKD)*4 (BCLK)*4 The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. When using FCLK for programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. The frequency accuracy of FCLK must be 3.5% while programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. The lower-limit frequency of PCLKC is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D converter is in use. See section 9, Clock Generation Circuit in User's Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB, PCLKC, PCLKD, FCLK, and BCLK. The maximum value of operation frequency does not include errors of the internal oscillator. The operation can be guaranteed with the errors of the internal oscillator. For details, on the range for the guaranteed operation, see Table 2.22, Clock timing. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 53 of 137 S3A7 Datasheet Table 2.18 2. Electrical Characteristics Operation frequency value in Middle-speed mode Conditions: VCC = AVCC0 = 1.8 to 5.5 V Parameter Operation frequency Symbol System clock (ICLK)*4 2.7 to 5.5 V FlashIF clock (FCLK)*1, *2, *4 Peripheral module clock (PCLKA)*4 Peripheral module clock (PCLKB)*4 Peripheral module clock Peripheral module clock (PCLKC)*3, *4 (PCLKD)*4 External bus clock (BCLK)*4 EBCLK pin output Note 1. Note 2. Note 3. Note 4. Note 5. f Min Typ Max*5 Unit MHz 0.032768 - 12 2.4 to 2.7 V 0.032768 - 12 1.8 to 2.4 V 0.032768 - 8 2.7 to 5.5 V 0.032768 - 12 2.4 to 2.7 V 0.032768 - 12 1.8 to 2.4 V 0.032768 - 8 2.7 to 5.5 V - - 12 2.4 to 2.7 V - - 12 1.8 to 2.4 V - - 8 2.7 to 5.5 V - - 12 2.4 to 2.7 V - - 12 1.8 to 2.4 V - - 8 2.7 to 5.5 V - - 12 2.4 to 2.7 V - - 12 1.8 to 2.4 V - - 8 2.7 to 5.5 V - - 12 2.4 to 2.7 V - - 12 1.8 to 2.4 V - - 8 2.7 to 5.5 V - - 12 2.4 to 2.7 V - - 12 1.8 to 2.4 V - - 8 2.7 to 3.6 V - - 12 2.4 to 2.7 V - - 8 1.8 to 2.4 V - - 8 The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. When using FCLK for programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. The frequency accuracy of FCLK must be 3.5% while programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. The lower-limit frequency of PCLKC is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D converter is in use. See section 9, Clock Generation Circuit in User's Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB, PCLKC, PCLKD, FCLK, and BCLK. The maximum value of operation frequency does not include errors of the internal oscillator. The operation can be guaranteed with the errors of the internal oscillator. For details on the range for the guaranteed operation, see Table 2.22, Clock timing. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 54 of 137 S3A7 Datasheet Table 2.19 2. Electrical Characteristics Operation frequency value in Low-speed mode Conditions: VCC = AVCC0 = 1.8 to 5.5 V Parameter Operation frequency System clock (ICLK)*3 Max*4 Unit f MHz 0.032768 - 1 0.032768 - 1 Peripheral module clock (PCLKA)*3 1.8 to 5.5 V - - 1 Peripheral module clock (PCLKB)*3 1.8 to 5.5 V - - 1 1.8 to 5.5 V - - 1 1.8 to 5.5 V - - 1 External bus clock (PCLKC)*2, *3 (BCLK)*3 EBCLK pin output Note 4. Typ 1.8 to 5.5 V Peripheral module clock (PCLKD)*3 Note 1. Note 2. Note 3. Min FlashIF clock (FCLK)*1, *3 Peripheral module clock 1.8 to 5.5 V Symbol 1.8 to 5.5 V - - 1 1.8 to 5.5 V - - 1 The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. The lower-limit frequency of PCLKC is 1 MHz when the A/D converter is in use. See section 9, Clock Generation Circuit in User's Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB, PCLKC, PCLKD, FCLK, and BCLK. The maximum value of operation frequency does not include errors of the internal oscillator. The operation can be guaranteed with the errors of the internal oscillator. For details on the range for the guaranteed operation, Table 2.22, Clock timing. Table 2.20 Operation frequency value in Low-voltage mode Conditions: VCC = AVCC0 = 1.6 to 5.5 V Parameter Operation frequency System clock (ICLK)*4 Note 4. Note 5. Unit f MHz - 4 0.032768 - 4 Peripheral module clock (PCLKA)*4 1.6 to 5.5 V - - 4 Peripheral module clock (PCLKB)*4 1.6 to 5.5 V - - 4 1.6 to 5.5 V - - 4 1.6 to 5.5 V - - 4 EBCLK pin output Note 3. Max*5 0.032768 External bus clock Note 2. Typ 1.6 to 5.5 V (PCLKC)*3, *4 Peripheral module clock (PCLKD)*4 Note 1. Min FlashIF clock (FCLK)*1, *2, *4 Peripheral module clock 1.6 to 5.5 V Symbol (BCLK)*4 1.6 to 5.5 V - - 4 1.8 to 5.5 V - - 4 1.6 to 1.8 V - - 2 The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. When using FCLK for programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. The frequency accuracy of FCLK must be 3.5% while programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. The lower-limit frequency of PCLKC is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-Bit A/D converter is in use. See section 9, Clock Generation Circuit in User's Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB, PCLKC, PCLKD, FCLK, and BCLK. The maximum value of operation frequency does not include errors of the internal oscillator. The operation can be guaranteed with the errors of the internal oscillator. For details on the range for guaranteed operation, see Table 2.22, Clock timing. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 55 of 137 S3A7 Datasheet Table 2.21 2. Electrical Characteristics Operation frequency value in Subosc-speed mode Conditions: VCC = AVCC0 = 1.8 to 5.5 V Parameter Operation frequency Symbol System clock (ICLK)*3 Unit kHz 27.8528 32.768 37.6832 27.8528 32.768 37.6832 Peripheral module clock (PCLKA)*3 1.8 to 5.5 V - - 37.6832 Peripheral module clock (PCLKB)*3 1.8 to 5.5 V - - 37.6832 1.8 to 5.5 V - - 37.6832 1.8 to 5.5 V - - 37.6832 Peripheral module clock (PCLKD)*3 External bus clock (BCLK)*3 EBCLK pin output Note 1. Note 2. Note 3. Max 1.8 to 5.5 V (PCLKC)*2, *3 f Typ FlashIF clock (FCLK)*1, *3 Peripheral module clock 1.8 to 5.5 V Min 1.8 to 5.5 V - - 37.6832 1.8 to 5.5 V - - 37.6832 Programming and erasing the flash memory is not possible. The 14-bit A/D converter cannot be used. See section 9, Clock Generation Circuit in User's Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB, PCLKC, PCLKD, FCLK, and BCLK. 2.3.2 Table 2.22 Clock Timing Clock timing (1 of 2) Parameter EBCLK pin output cycle time VCC = 2.7 V or above Symbol Min Typ Max Unit Test conditions tBcyc 83.3 - - ns Figure 2.26 125 - - VCC = 1.8 V or above VCC = 1.6 V or above EBCLK pin output high pulse width VCC = 2.7 V or above EBCLK pin output low pulse width tCH - 30 - - VCC = 1.6 V or above 150 - - 20 - - 30 - - VCC = 2.7 V or above tCL VCC = 1.6 V or above 150 - - - - 15 VCC = 2.4 V or above - - 25 VCC = 1.8 V or above - - 30 VCC = 2.7 V or above tCr VCC = 1.6 V or above EBCLK pin output fall time - VCC = 1.8 V or above VCC = 1.8 V or above EBCLK pin output rise time 500 20 - - 50 - - 15 VCC = 2.4 V or above - - 25 VCC = 1.8 V or above - - 30 VCC = 2.7 V or above tCf VCC = 1.6 V or above ns ns ns ns - - 50 tXcyc 50 - - ns EXTAL external clock input high pulse width tXH 20 - - ns EXTAL external clock input low pulse width tXL 20 - - ns EXTAL external clock rising time tXr - - 5 ns EXTAL external clock falling time tXf - - 5 ns tEXWT 0.3 - - s - fEXTAL - - 20 MHz 2.4 VCC 5.5 - - 8 1.8 VCC < 2.4 - - 1 1.6 VCC < 1.8 1 - 20 1 - 8 EXTAL external clock input cycle time EXTAL external clock input wait time*1 EXTAL external clock input frequency Main clock oscillator oscillation frequency LOCO clock oscillation frequency R01DS0263EU0140 Rev.1.40 Oct 29, 2018 fMAIN fLOCO 1 - 4 27.8528 32.768 37.6832 MHz Figure 2.27 2.4 VCC 5.5 1.8 VCC < 2.4 1.6 VCC < 1.8 kHz - Page 56 of 137 S3A7 Datasheet Table 2.22 2. Electrical Characteristics Clock timing (2 of 2) Parameter Symbol Min Typ Max Unit Test conditions LOCO clock oscillation stabilization time tLOCO - - 100 s Figure 2.28 IWDT-dedicated clock oscillation frequency fILOCO 12.75 15 17.25 kHz - MOCO clock oscillation frequency fMOCO 6.8 8 9.2 MHz - MOCO clock oscillation stabilization time tMOCO - - 1 s - HOCO clock oscillation frequency fHOCO24 23.64 24 24.36 MHz Ta = -40 to -20C 1.8 VCC 5.5 22.68 24 25.32 Ta = -40 to 85C 1.6 VCC < 1.8 23.76 24 24.24 Ta = -20 to 85C 1.8 VCC 5.5 23.52 24 24.48 Ta = 85 to 105C 2.4 VCC 5.5 31.52 32 32.48 Ta = -40 to -20C 1.8 VCC 5.5 30.24 32 33.76 Ta = -40 to 85C 1.6 VCC < 1.8 31.68 32 32.32 Ta = -20 to 85C 1.8 VCC 5.5 31.36 32 32.64 Ta = 85 to 105C 2.4 VCC 5.5 47.28 48 48.72 Ta = -40 to -20C 1.8 VCC 5.5 47.52 48 48.48 Ta = -20 to 85C 1.8 VCC 5.5 47.04 48 48.96 Ta = 85C to 105C 2.4 VCC 5.5 63.04 64 64.96 Ta = -40 to -20C 2.4 VCC 5.5 63.36 64 64.64 Ta = -20 to 85C 2.4 VCC 5.5 62.72 64 65.28 Ta = 85 to 105C 2.4 VCC 5.5 tHOCO24 tHOCO32 - - 37.1 tHOCO48 - - 43.3 fHOCO32 fHOCO48*4 fHOCO64*5 HOCO clock oscillation stabilization time*6, *7 Except Low-Voltage mode Low-Voltage mode PLL input frequency*2 frequency*2 s Figure 2.29 tHOCO64 - - 80.6 tHOCO24 tHOCO32 tHOCO48 tHOCO64 - - 100.9 fPLLIN 4 - 12.5 MHz - fPLL 24 - 64 MHz - PLL clock oscillation stabilization time*8 tPLL - - 55.5 s Figure 2.31 PLL free-running oscillation frequency fPLLFR - 8 - MHz - Sub-clock oscillator oscillation frequency fSUB - 32.768 - kHz - Sub-clock oscillation stabilization time*3 tSUBOSC - 0.5 - s Figure 2.32 PLL circuit oscillation Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7. Note 8. Time until the clock can be used after the main clock oscillator stop bit (MOSCCR.MOSTP) is set to 0 (operating) when the external clock is stable. The VCC range that the PLL can be used is 2.4 to 5.5 V. After changing the setting of the SOSCCR.SOSTP bit to start sub-clock oscillator operation, only start using the sub-clock oscillator after the sub-clock oscillation stabilization wait time elapsed. Use the oscillator wait time value recommended by the oscillator manufacturer. The 48-MHz HOCO can be used within a VCC range of 1.8 V to 5.5 V. The 64-MHz HOCO can be used within a VCC range of 2.4 V to 5.5 V. This is a characteristic when HOCOCR.HCSTP bit is set to 0 (oscillation) in MOCO stop state. When HOCOCR.HCSTP bit is set to 0 (oscillation) during MOCO oscillation, this specification is shortened by 1 s. Whether stabilization time has elapsed can be confirmed by OSCSF.HOCOSF. This is a characteristic when PLLCR.PLLSTP bit is set to 0 (operation) in MOCO stop state. When PLLCR.PLLSTP bit is set to 0 (operation) during MOCO oscillation, this specification is shortened by 1 s. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 57 of 137 S3A7 Datasheet 2. Electrical Characteristics tBcyc tCH tCf EBCLK pin output tCr tCL Test conditions: VOH = VCC x 0.7, VOL = VCC x 0.3, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF Figure 2.26 EBCLK pin output timing tXcyc tXL tXH EXTAL external clock input VCC x 0.5 tXr Figure 2.27 tXf EXTAL external clock input timing LOCOCR.LCSTP tLOCO LOCO clock oscillator output Figure 2.28 LOCO clock oscillation start timing HOCOCR.HCSTP tHOCOx*1 HOCO clock Note 1. Figure 2.29 x = 24, 32, 48, 64 HOCO clock oscillation start timing (started by setting HOCOCR.HCSTP bit) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 58 of 137 S3A7 Datasheet 2. Electrical Characteristics MOSCCR.MOSTP Main clock oscillator output tMAINOSCWT Main clock Figure 2.30 Main clock oscillation start timing PLLCR.PLLSTP tPLL PLL clock Figure 2.31 PLL clock oscillation start timing (PLL is operated after main clock oscillation has settled) SOSCCR.SOSTP tSUBOSC Sub-clock oscillator output Figure 2.32 Sub-clock oscillation start timing R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 59 of 137 S3A7 Datasheet 2.3.3 2. Electrical Characteristics Reset Timing Table 2.23 Reset timing Symbol Min Typ Max Unit Test conditions At power-on tRESWP 3 - - ms Figure 2.33 Other than above tRESW 30 - - s Figure 2.34 tRESWT - 0.7 - ms Figure 2.33 - 0.3 - - 0.5 - ms Figure 2.34 - 0.05 - - 0.6 - - 0.15 - Parameter RES pulse width Wait time after RES cancellation (at power-on) LVD0: enable*1 LVD0: disable*2 Wait time after RES cancellation (during powered-on state) LVD0: enable*1 Wait time after internal reset cancellation (Watchdog timer reset, SRAM parity error reset, SRAM ECC error reset, bus master MPU error reset, bus slave MPU error reset, stack pointer error reset, software reset) LVD0: enable*1 Note 1. Note 2. LVD0: tRESWT2 disable*2 tRESWT3 LVD0: disable*2 ms When OFS1.LVDAS = 0. When OFS1.LVDAS = 1. VCC RES tRESWP Internal reset tRESWT Figure 2.33 Reset input timing at power-on tRESW RES Internal reset tRESWT2 Figure 2.34 Reset input timing (1) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 60 of 137 S3A7 Datasheet 2.3.4 2. Electrical Characteristics Wakeup Time Table 2.24 Timing of recovery from Low power modes (1) Symbol Min Typ Max Unit Test conditions System clock source is main clock oscillator (20 MHz)*2 tSBYMC - 2 3 ms Figure 2.35 System clock source is PLL (48 MHz) with Main clock oscillator*2 tSBYPC - 2 3 ms System clock source is main clock oscillator (20 MHz)*3 tSBYEX - 14 25 s System clock source is PLL (48 MHz) with Main clock oscillator*3 tSBYPE - 53 76 s System clock source is HOCO*4 (HOCO clock is 32 MHz) tSBYHO - 43 52 s System clock source is HOCO*4 (HOCO clock is 48 MHz) tSBYHO - 44 52 s System clock source is HOCO*5 (HOCO clock is 64 MHz) tSBYHO - 82 110 s System clock source is MOCO tSBYMO - 16 25 s Parameter Recovery time from Software Standby mode*1 High-speed mode Crystal resonator connected to main clock oscillator External clock input to main clock oscillator Note 1. Note 2. Note 3. Note 4. Note 5. The division ratio of ICK, BCK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time is determined by the system clock source. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h. The HOCO Clock Wait Control Register (HOCOWTCR) is set to 05h. The HOCO Clock Wait Control Register (HOCOWTCR) is set to 06h. Table 2.25 Timing of Recovery from Low power modes (2) Symbol Min Typ Max Unit Test conditions System clock source is main clock oscillator (12 MHz)*2 tSBYMC - 2 3 ms Figure 2.35 System clock source is PLL (24 MHz) with Main clock oscillator*2 tSBYPC - 2 3 ms System clock source is main clock oscillator (12 MHz)*3 tSBYEX - 2.9 10 s System clock source is PLL (24 MHz) with Main clock oscillator*3 tSBYPE - 49 76 s System clock source is HOCO*4 tSBYHO - 38 50 s System clock source is MOCO tSBYMO - 3.5 5.5 s Parameter Recovery time from Software Standby mode*1 Middle-speed mode Crystal resonator connected to main clock oscillator External clock input to main clock oscillator Note 1. Note 2. Note 3. Note 4. The division ratio of ICK, BCK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time is determined by the system clock source. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h. The system clock is 12 MHz. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 61 of 137 S3A7 Datasheet Table 2.26 2. Electrical Characteristics Timing of recovery from Low power modes (3) Parameter Recovery time from Software Standby mode*1 Low-speed mode Note 2. Note 3. Unit Test conditions Figure 2.35 tSBYMC - 2 3 ms External clock input to main clock oscillator System clock source is main clock oscillator (1 MHz)*3 tSBYEX - 28 50 s tSBYMO - 25 35 s Timing of recovery from Low power modes (4) Recovery time from Software Standby mode*1 Low-voltage mode Crystal resonator connected to main clock oscillator External clock input to main clock oscillator System clock source is main clock oscillator Symbol Min Typ Max Unit Test conditions tSBYMC - 2 3 ms Figure 2.35 tSBYEX - 108 130 s tSBYHO - 108 130 s (4 MHz)*2 System clock source is main clock oscillator (4 MHz)*3 System clock source is HOCO The division ratio of ICK, BCK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time is determined by the system clock source. When multiple oscillators are active, the recovery time can be determined by the following expression. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h. Table 2.28 Timing of recovery from Low power modes (5) Symbol Min Typ Max Unit Test conditions System clock source is sub-clock oscillator (32.768 kHz) tSBYSC - 0.85 1 ms Figure 2.35 System clock source is LOCO (32.768 kHz) tSBYLO - 0.85 1.2 ms Parameter Recovery time from Software Standby mode*1 Note 1. Max System clock source is main clock oscillator (1 MHz)*2 Parameter Note 2. Note 3. Typ The division ratio of ICK, BCK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time is determined by the system clock source. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h. Table 2.27 Note 1. Min Crystal resonator connected to main clock oscillator System clock source is MOCO Note 1. Symbol Subosc-speed mode The sub-clock oscillator or LOCO itself continues to oscillate in Software Standby mode during Subosc-speed mode. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 62 of 137 S3A7 Datasheet 2. Electrical Characteristics Oscillator ICLK IRQ Software Standby mode tSBYMC, tSBYPC, tSBYEX, tSBYPE, tSBYMO, tSBYHO Oscillator ICLK IRQ Software Standby mode tSBYSC, tSBYLO Figure 2.35 Software Standby mode cancellation timing Table 2.29 Timing of recovery from Low power modes (6) Parameter Recovery time from Software Standby mode to Snooze mode Symbol Min Typ Max Unit Test conditions High-speed mode System clock source is HOCO tSNZ - 36 45 s Figure 2.36 Middle-speed mode System clock source is MOCO tSNZ - 1.3 3.6 s Low-speed mode System clock source is MOCO tSNZ - 10 13 s Low-voltage mode System clock source is HOCO tSNZ - 87 110 s Oscillator ICLK (except DTC, SRAM) ICLK (to DTC, SRAM)*1 PCLK IRQ Software Standby mode Snooze mode tSNZ Note1: When SNZCR.SNZDTCEN is set to 1, ICLK is supplied to DTC and SRAM. Figure 2.36 Recovery timing from Software Standby mode to Snooze mode R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 63 of 137 S3A7 Datasheet 2.3.5 2. Electrical Characteristics NMI and IRQ Noise Filter Table 2.30 NMI and IRQ noise filter Parameter Symbol Min Typ Max Unit Test conditions NMI pulse width tNMIW 200 - - ns NMI digital filter disabled tPcyc x 2 200 ns - - 200 - - NMI digital filter enabled tNMICK x 3 200 ns tNMICK x 3.5*2 - - 200 - - tPcyc x 2*1 - - 200 - - - - tPcyc x IRQ pulse width tIRQW 2*1 tIRQCK x Note: Note 1. Note 2. Note 3. 3.5*3 tPcyc x 2 > 200 ns tNMICK x 3 > 200 ns ns IRQ digital filter disabled tPcyc x 2 200 ns tPcyc x 2 > 200 ns IRQ digital filter enabled tIRQCK x 3 200 ns tIRQCK x 3 > 200 ns 200 ns minimum in Software Standby mode. tPcyc indicates the cycle of PCLKB. tNMICK indicates the cycle of the NMI digital filter sampling clock. tIRQCK indicates the cycle of the IRQi digital filter sampling clock (i = 0 to 15). NMI tNMIW Figure 2.37 NMI interrupt input timing IRQ tIRQW Figure 2.38 IRQ interrupt input timing R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 64 of 137 S3A7 Datasheet 2.3.6 Table 2.31 2. Electrical Characteristics Bus Timing Bus timing (1) Conditions: Low drive output is selected in the Port Drive Capability bit in PmnPFS register VCC = AVCC0 = 2.7 to 5.5 V Output load conditions: VOH = VCC x 0.5, VOL = VCC x 0.5, C = 30 pF Parameter Symbol Min Max Unit Test conditions Address delay tAD - 55 ns Byte control delay tBCD - 55 ns Figure 2.39 to Figure 2.42 CS delay tCSD - 55 ns RD delay tRSD - 55 ns Read data setup time tRDS 37 - ns Read data hold time tRDH 0 - ns WR delay tWRD - 55 ns Write data delay tWDD - 55 ns Write data hold time tWDH 0 - ns WAIT setup time tWTS 37 - ns WAIT hold time tWTH 0 - ns Table 2.32 Figure 2.43 Bus timing (2) Conditions: Low drive output is selected in the Port Drive Capability bit in the PmnPFS register VCC = AVCC0 = 2.4 to 2.7 V Output load conditions: VOH = VCC x 0.5, VOL = VCC x 0.5, C = 30 pF Parameter Symbol Min Max Unit Test conditions Address delay tAD - 55 ns Byte control delay tBCD - 55 ns Figure 2.39 to Figure 2.42 CS delay tCSD - 55 ns RD delay tRSD - 55 ns Read data setup time tRDS 45 - ns Read data hold time tRDH 0 - ns WR delay tWRD - 55 ns Write data delay tWDD - 55 ns Write data hold time tWDH 0 - ns WAIT setup time tWTS 45 - ns WAIT hold time tWTH 0 - ns Table 2.33 Figure 2.43 Bus timing (3) (1 of 2) Conditions: Low drive output is selected in the Port Drive Capability bit in the PmnPFS register VCC = AVCC0 = 1.8 to 2.4 V Output load conditions: VOH = VCC x 0.5, VOL = VCC x 0.5, C = 30 pF Parameter Symbol Min Max Unit Test conditions Address delay tAD - 90 ns Byte control delay tBCD - 90 ns Figure 2.39 to Figure 2.42 CS delay tCSD - 90 ns RD delay tRSD - 90 ns Read data setup time tRDS 70 - ns Read data hold time tRDH 0 - ns WR delay tWRD - 90 ns Write data delay tWDD - 90 ns Write data hold time tWDH 0 - ns R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 65 of 137 S3A7 Datasheet Table 2.33 2. Electrical Characteristics Bus timing (3) (2 of 2) Conditions: Low drive output is selected in the Port Drive Capability bit in the PmnPFS register VCC = AVCC0 = 1.8 to 2.4 V Output load conditions: VOH = VCC x 0.5, VOL = VCC x 0.5, C = 30 pF Parameter Symbol Min Max Unit Test conditions WAIT setup time tWTS 70 - ns Figure 2.43 WAIT hold time tWTH 0 - ns Table 2.34 Bus timing (4) Conditions: Low drive output is selected in the Port Drive Capability bit in the PmnPFS register VCC = AVCC0 = 1.6 to 1.8 V Output load conditions: VOH = VCC x 0.5, VOL = VCC x 0.5, C = 30 pF Parameter Symbol Min Max Unit Test conditions Address delay tAD - 120 ns Byte control delay tBCD - 120 ns Figure 2.39 to Figure 2.42 CS delay tCSD - 120 ns RD delay tRSD - 120 ns Read data setup time tRDS 90 - ns Read data hold time tRDH 0 - ns WR delay tWRD - 120 ns Write data delay tWDD - 120 ns Write data hold time tWDH 0 - ns WAIT setup time tWTS 90 - ns WAIT hold time tWTH 0 - ns R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Figure 2.43 Page 66 of 137 S3A7 Datasheet 2. Electrical Characteristics CSRWAIT: 2 RDON:1 CSROFF: 2 CSON: 0 TW1 TW2 Tend Tn1 Tn2 EBCLK Byte strobe mode tAD tAD tAD tAD A16 to A00 1-write strobe mode A16 to A01 tBCD tBCD tCSD tCSD BC1, BC0 Common to both byte strobe mode and 1-write strobe mode CS3 to CS0 tRSD tRSD RD (Read) tRDS tRDH D15 to D00 (Read) Figure 2.39 External bus timing/normal read cycle (bus clock synchronized) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 67 of 137 S3A7 Datasheet 2. Electrical Characteristics CSWWAIT: 2 WRON: 1 WDON: 1*1 CSWOFF: 2 WDOFF: 1*1 CSON:0 TW1 TW2 Tend Tn1 Tn2 EBCLK Byte strobe mode tAD tAD tAD tAD A16 to A00 1-write strobe mode A16 to A01 tBCD tBCD tCSD tCSD BC1 to BC0 Common to both byte strobe mode and 1-write strobe mode CS3 to CS0 tWRD tWRD WR1, WR0, WR (Write) tWDD tWDH D15 to D00 (Write) Note 1. Figure 2.40 Be sure to specify WDON and WDOFF as at least one cycle of EBCLK. External bus timing/normal write cycle (bus clock synchronized) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 68 of 137 S3A7 Datasheet 2. Electrical Characteristics CSRWAIT:2 CSON:0 CSPRWAIT:2 CSPRWAIT:2 RDON:1 RDON:1 TW1 TW2 Tend CSPRWAIT:2 RDON:1 Tpw1 Tpw2 Tend CSROFF:2 RDON:1 Tpw1 Tpw2 Tend Tpw1 Tpw2 Tend Tn1 Tn2 EBCLK Byte strobe mode tAD tAD tAD tAD tAD tAD tAD tAD tAD tAD A16 to A00 1-write strobe mode A16 to A01 tBCD tBCD tCSD tCSD BC1, BC0 Common to both byte strobe mode and 1-write strobe mode CS3 to CS0 tRSD tRSD tRSD tRSD tRSD tRSD tRSD tRSD RD (Read) tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH D15 to D00 (Read) Figure 2.41 External bus timing/page read cycle (bus clock synchronized) CSPWWAIT:2 CSWWAIT:2 WRON:1 WDON:1*1 WDOFF:1*1 CSON:0 TW1 TW2 Tend Tdw1 WRON:1 WDON:1*1 Tpw1 CSPWWAIT:2 WDOFF:1*1 Tpw2 Tend Tdw1 WRON:1 WDON:1*1 Tpw1 CSWOFF:2 WDOFF:1*1 Tpw2 Tend Tn1 Tn2 EBCLK Byte strobe mode tAD tAD tAD tAD tAD tAD tAD tAD A16 to A00 1-write strobe mode A16 to A01 tBCD tBCD tCSD tCSD BC1, BC0 Common to both byte strobe mode and 1-write strobe mode CS3 to CS0 tWRD tWRD tWRD tWRD tWRD tWRD WR1, WR0, WR (Write) tWDD tWDH tWDD tWDH tWDD tWDH D15 to D00 (Write) Note 1. Figure 2.42 Be sure to specify WDON and WDOFF as at least one cycle of EBCLK. External bus timing/page write cycle (bus clock synchronized) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 69 of 137 S3A7 Datasheet 2. Electrical Characteristics CSRWAIT:3 CSWWAIT:3 TW1 TW2 TW3 (Tend) Tend Tn1 Tn2 EBCLK A16 to A00 CS3 to CS0 RD (Read) WR (Write) External wait tWTS tWTH tWTS tWTH WAIT Figure 2.43 External bus timing/external wait control R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 70 of 137 S3A7 Datasheet 2.3.7 2. Electrical Characteristics I/O Ports, POEG, GPT, AGT, KINT, and ADC14 Trigger Timing Table 2.35 I/O Ports, POEG, GPT, AGT, KINT, and ADC14 trigger timing Symbol Min Max Unit Test conditions Input data pulse width tPRW 1.5 - tPcyc Figure 2.44 Input/Output data cycle (P002, P003, P004, P007) tPOcyc 10 - s POEG POEG input trigger pulse width tPOEW 3 - tPcyc Figure 2.45 GPT Input capture pulse width tGTICW 1.5 - tPDcyc Figure 2.46 2.5 - 250 - ns Figure 2.47 2.4 V VCC < 2.7 V 500 - ns 1.8 V VCC < 2.4 V 1000 - ns 1.6 V VCC < 1.8 V 2000 - ns 100 - ns 200 - ns 400 - ns Parameter I/O Ports Single edge Dual edge AGT AGTIO, AGTEE input cycle AGTIO, AGTEE input high level width, low-level width 2.7 V VCC 5.5 V 2.7 V VCC 5.5 V 2.4 V VCC < 2.7 V tACYC*1 tACKWH, tACKWL 1.8 V VCC < 2.4 V 1.6 V VCC < 1.8 V AGTIO, AGTO, AGTOA, AGTOB output cycle 800 - ns 62.5 - ns 2.4 V VCC < 2.7 V 125 - ns 1.8 V VCC < 2.4 V 250 - ns 1.6 V VCC < 1.8 V 500 - ns 2.7 V VCC 5.5 V tACYC2 Figure 2.47 ADC14 14-bit A/D converter trigger input pulse width tTRGW 1.5 - tPcyc Figure 2.48 KINT KRn (n = 00 to 07) pulse width tKR 250 - ns Figure 2.49 Note: Note 1. tPcyc: PCLKB cycle, tPDcyc: PCLKD cycle Constraints on AGTIO input: tPcyc x 2 (tPcyc: PCLKB cycle) < tACYC Port tPRW Figure 2.44 I/O ports input timing POEG input trigger tPOEW Figure 2.45 POEG input trigger timing Input capture tGTICW Figure 2.46 GPT input capture timing R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 71 of 137 S3A7 Datasheet 2. Electrical Characteristics tACYC tACKWL tACKWH AGTIO, AGTEE (input) tACYC2 AGTIO, AGTO, AGTOA, AGTOB (output) Figure 2.47 AGT I/O timing ADTRG0 tTRGW Figure 2.48 ADC14 trigger input timing KR00 to KR07 tKR Figure 2.49 2.3.8 Key interrupt input timing CAC Timing Table 2.36 CAC timing Parameter CAC CACREF input pulse width tPBcyc tcac*2 tPBcyc > Note 1. Note 2. tcac*2 Symbol Min Typ Max Unit Test conditions tCACREF 4.5 x tcac + 3 x tPBcyc - - ns - 5 x tcac + 6.5 x tPBcyc - - ns tPBcyc: PCLKB cycle. tcac: CAC count clock source cycle. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 72 of 137 S3A7 Datasheet 2.3.9 2. Electrical Characteristics SCI Timing Table 2.37 SCI timing (1) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Parameter SCI Symbol Input clock cycle Asynchronous tScyc Clock synchronous Unit*1 Test conditions 4 - tPcyc Figure 2.50 6 - Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr - 20 ns tSCKf - 20 ns tScyc 6 - tPcyc 4 - 0.4 0.6 tScyc ns Input clock fall time Output clock cycle Asynchronous Clock synchronous Output clock pulse width Output clock rise time tSCKW 1.8 V or above tSCKr 1.6 V or above Output clock fall time 1.8 V or above tSCKf 1.6 V or above tTXD - 20 - 30 - 20 - 30 - 40 Transmit data delay (master) Clock synchronous 1.8 V or above 1.6 V or above - 45 Transmit data delay (slave) Clock synchronous 2.7 V or above - 55 2.4 V or above - 60 1.8 V or above - 100 - 125 45 - 2.4 V or above 55 - 1.8 V or above 90 - 1.6 V or above 105 - 2.7 V or above 40 - 1.6 V or above Receive data setup time (master) Note 1. Max Min Clock synchronous 2.7 V or above tRXS ns ns ns ns Receive data setup time (slave) Clock synchronous 45 - Receive data hold time (master) Clock synchronous tRXH 5 - ns Receive data hold time (slave) Clock synchronous tRXH 40 - ns 1.6 V or above Figure 2.51 ns tPcyc: PCLKA cycle. tSCKW tSCKr tSCKf SCKn (n = 0 to 4, 9) tScyc Figure 2.50 SCK clock input timing R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 73 of 137 S3A7 Datasheet 2. Electrical Characteristics SCKn tTXD TXDn tRXS tRXH RXDn n = 0 to 4, 9 Figure 2.51 SCI input/output timing in clock synchronous mode R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 74 of 137 S3A7 Datasheet Table 2.38 2. Electrical Characteristics SCI timing (2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Parameter Symbol Min Max Unit Test conditions Simple SPI tSPcyc 4 65536 tPcyc Figure 2.52 6 65536 tSPCKWH 0.4 0.6 tSPCKWL 0.4 0.6 tSPcyc - 20 ns - 30 45 - 2.4 V or above 55 - 1.8 V or above 80 - SCK clock cycle output (master) SCK clock cycle input (slave) SCK clock high pulse width SCK clock low pulse width SCK clock rise and fall time 1.8 V or above 1.6 V or above tSPCKr, tSPCKf Data input setup time 2.7 V or above tSU Master Slave 1.6 V or above 105 - 2.7 V or above 40 - 1.6 V or above Data input hold time Master tH Slave 45 - 33.3 - tSPcyc ns ns 40 - SS input setup time tLEAD 1 - tSPcyc SS input hold time tLAG 1 - tSPcyc tOD ns Data output delay Master Slave 1.8 V or above - 40 1.6 V or above - 50 2.4 V or above - 65 1.8 V or above - 100 1.6 V or above Data output hold time Master - 125 -10 - 2.4 V or above -20 - 1.8 V or above -30 - 1.6 V or above -40 - -10 - 2.7 V or above tOH Slave Data rise and fall time Master Slave 1.8 V or above tDr, tDf - 20 1.6 V or above - 30 1.8 V or above - 20 1.6 V or above - 30 ns ns Slave access time tSA - 10 (PCLKA > 32 MHz), 6 (PCLKA 32 MHz) tPcyc Slave output release time tREL - 10 (PCLKA > 32 MHz), 6 (PCLKA 32 MHz) tPcyc R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Figure 2.53 to Figure 2.56 Figure 2.55 and Figure 2.56 PCLKB = PCLKA Page 75 of 137 S3A7 Datasheet 2. Electrical Characteristics tSPCKr tSPCKWH VOH SCKn master select output VOH VOL tSPCKf VOH VOH VOL tSPCKWL VOL tSPcyc tSPCKr tSPCKWH VIH VIH SCKn slave select input VIL (n = 0 to 4, 9) tSPCKf VIH VIL tSPCKWL VIH VIL tSPcyc VOH = 0.7 x VCC, VOL = 0.3 x VCC, VIH = 0.7 x VCC, VIL = 0.3 x VCC Figure 2.52 SCI simple SPI mode clock timing SCKn CKPOL = 0 output SCKn CKPOL = 1 output tSU MISOn input tH MSB IN tDr, tDf MOSIn output DATA tOH MSB OUT LSB IN MSB IN tOD DATA LSB OUT IDLE MSB OUT (n = 0 to 4, 9) Figure 2.53 SCI simple SPI mode timing (master, CKPH = 1) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 76 of 137 S3A7 Datasheet 2. Electrical Characteristics SCKn CKPOL = 1 output SCKn CKPOL = 0 output tSU MISOn input tH MSB IN tOH DATA LSB IN tOD MOSIn output MSB IN tDr, tDf MSB OUT DATA LSB OUT IDLE MSB OUT (n = 0 to 4, 9) Figure 2.54 SCI simple SPI mode timing (master, CKPH = 0) tTD SSn input tLEAD tLAG SCKn CKPOL = 0 input SCKn CKPOL = 1 input tSA tOH MISOn output MSB OUT tSU MOSIn input tOD DATA tREL LSB OUT tH MSB IN MSB IN MSB OUT tDr, tDf DATA LSB IN MSB IN (n = 0 to 4, 9) Figure 2.55 SCI simple SPI mode timing (slave, CKPH = 1) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 77 of 137 S3A7 Datasheet 2. Electrical Characteristics tTD SSn input tLEAD tLAG SCKn CKPOL = 1 input SCKn CKPOL = 0 input tSA tOH tOD LSB OUT (Last data) MISOn output MSB OUT tSU MOSIn input tREL DATA tH MSB OUT LSB OUT tDr, tDf MSB IN DATA LSB IN MSB IN (n = 0 to 4, 9) Figure 2.56 Table 2.39 SCI simple SPI mode timing (slave, CKPH = 0) SCI timing (3) Conditions: VCC = AVCC0 = 2.7 to 5.5 V Parameter Simple IIC (Standard mode) Simple IIC (Fast mode)*3 Note 1. Note 2. Note 3. Symbol Min Max Unit Test conditions SDA input rise time tSr - 1000 ns Figure 2.57 SDA input fall time tSf - 300 ns SDA input spike pulse removal time tSP 0 4 x tIICcyc ns Data input setup time tSDAS 250 - ns Data input hold time tSDAH 0 - ns SCL, SDA capacitive load Cb*2 - 400 pF SDA input rise time tSr - 300 ns SDA input fall time tSf - 300 ns SDA input spike pulse removal time tSP 0 4 x tIICcyc ns Data input setup time tSDAS 100 - ns Data input hold time tSDAH 0 - ns SCL, SDA capacitive load Cb*2 - 400 pF Figure 2.57 tIICcyc: Clock cycle selected in the SMR.CKS[1:0] bits. Cb indicates the total capacity of the bus line. Middle drive output is selected in the Port Drive Capability in the PmnPFS register R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 78 of 137 S3A7 Datasheet 2. Electrical Characteristics VIH SDAn VIL tSr tSf tSP SCLn (n = 0 to 4, 9) P*1 S*1 tSDAH Note 1. S, P, and Sr indicate the following: S: Start condition P: Stop condition Sr: Restart condition Figure 2.57 P*1 Sr*1 tSDAS Test conditions: VIH = VCC x 0.7, VIL = VCC x 0.3 VOL = 0.6 V, IOL = 6 mA SCI simple IIC mode timing R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 79 of 137 S3A7 Datasheet 2.3.10 Table 2.40 2. Electrical Characteristics SPI Timing SPI timing (1 of 2) Conditions: Middle drive output is selected in the Port Drive Capability in the PmnPFS register Parameter SPI RSPCK clock cycle Master Symbol Min Max Unit*1 Test conditions tSPcyc 2*4 4096 tPcyc 6 4096 Figure 2.58 C = 30PF (tSPcyc - tSPCKr - tSPCKf) / 2 - 3 - 3 x tPcyc - (tSPcyc - tSPCKr - tSPCKf) / 2 - 3 - 3 x tPcyc - Slave RSPCK clock high pulse width Master tSPCKWH Slave RSPCK clock low pulse width Master tSPCKWL Slave RSPCK clock rise and fall time Output 2.7 V or above tSPCKr, tSPCKf - 10 15 1.8 V or above - 20 1.6 V or above - 30 - 1 s 10 - ns Master Slave tSU 2.4 V or above 10 - 1.8 V or above 15 - 1.6 V or above Data input hold time ns - 2.4 V or above Input Data input setup time ns 20 - Master (RSPCK is PCLKA/2) tHF 0 - Master (RSPCK is other than above.) tH tPcyc - ns ns Slave tH 20 - SSL setup time Master tLEAD -30 + N x tSpcyc*2 - ns 6 x tPcyc - ns SSL hold time Master -30 + N x tSpcyc*3 - ns 6 x tPcyc - ns Slave Slave R01DS0263EU0140 Rev.1.40 Oct 29, 2018 tLAG Figure 2.59 to Figure 2.64 C = 30PF Page 80 of 137 S3A7 Datasheet Table 2.40 2. Electrical Characteristics SPI timing (2 of 2) Conditions: Middle drive output is selected in the Port Drive Capability in the PmnPFS register Symbol Min Max Unit*1 Test conditions tOD - 14 ns 2.4 V or above - 20 1.8 V or above - 25 Figure 2.59 to Figure 2.64 C = 30PF Parameter SPI Data output delay Master Slave 2.7 V or above 1.6 V or above - 30 2.7 V or above - 50 2.4 V or above - 60 1.8 V or above - 85 - 110 0 - 0 - tSPcyc + 2 x tPcyc 8 x tSPcyc + 2 x tPcyc 1.6 V or above Data output hold time Master tOH Slave Successive transmission delay Master MOSI and MISO rise and fall time Output tTD Slave 6 x tPcyc - - 10 2.4 V or above - 15 1.8 V or above - 20 2.7 V or above tDr, tDf 1.6 V or above Input SSL rise and fall time Output Note 1. Note 2. Note 3. Note 4. ns - 30 - 1 s ns - 10 15 1.8 V or above - 20 1.6 V or above - 30 - 1 - 2 x tPcyc + 100 ns 1.8 V or above - 2 x tPcyc + 140 1.6 V or above - 2 x tPcyc + 180 tSSLr, tSSLf Input Slave output release time ns - 2.7 V or above 2.4 V or above Slave access time ns 2.4 V or above tSA s - 2 x tPcyc + 100 ns 1.8 V or above - 2 x tPcyc + 140 1.6 V or above - 2 x tPcyc + 180 2.4 V or above tREL Figure 2.63 and Figure 2.64 C = 30PF tPcyc: PCLKA cycle. N is set as an integer from 1 to 8 by the SPCKD register. N is set as an integer from 1 to 8 by the SSLND register. The upper limit of RSPCK is 16 MHz. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 81 of 137 S3A7 Datasheet 2. Electrical Characteristics tSPCKr tSPCKWH RSPCKn master select output VOH VOH tSPCKf VOH VOH VOL VOL tSPCKWL VOL tSPcyc tSPCKr tSPCKWH VIH VIH RSPCKn slave select input VIH VIL VIL tSPCKWL VIH VIL tSPcyc VOH = 0.7 x VCC, VOL = 0.3 x VCC, VIH = 0.7 x VCC, VIL = 0.3 x VCC (n = A or B) Figure 2.58 tSPCKf SPI clock timing t TD SSLn0 to SSLn3 output tLEAD t LAG tSSLr, tSSLf RSPCKn CPOL = 0 output RSPCKn CPOL = 1 output tSU MISOn input tH MSB IN tDr, tDf MOSIn output DATA tOH MSB OUT LSB IN MSB IN t OD DATA LSB OUT IDLE MSB OUT (n = A or B) Figure 2.59 SPI timing (master, CPHA = 0) (bit rate: PCLKA division ratio is set to any value other than 1/2) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 82 of 137 S3A7 Datasheet 2. Electrical Characteristics tTD SSLn0 to SSLn3 output t LEAD t LAG tSSLr, t SSLf RSPCKn CPOL = 0 output RSPCKn CPOL = 1 output t SU MISOn input tHF t HF MSB IN t Dr, t Df MOSIn output LSB IN DATA tO H M SB OUT MSB IN tO D DATA LSB OUT IDLE MSB OUT (n = A or B) Figure 2.60 SPI timing (master, CPHA = 0) (bit rate: PCLKA division ratio is set to 1/2) tTD SSLn0 to SSLn3 output tLEAD tLAG tSSLr, t SSLf RSPCKn CPOL = 0 output RSPCKn CPOL = 1 output tSU MISOn input tH MSB IN t OH MOSIn output DATA LSB IN tOD MSB OUT MSB IN tDr, t Df DATA LSB OUT IDLE MSB OUT (n = A or B) Figure 2.61 SPI timing (master, CPHA = 1) (bit rate: PCLKA division ratio is set to any value other than 1/2) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 83 of 137 S3A7 Datasheet 2. Electrical Characteristics tTD SSLn0 to SSLn3 output tLEAD t LAG tSSLr, tSSLf RSPCKn CPOL = 0 output RSPCKn CPOL = 1 output t SU MISOn input t HF MSB IN tOH tH DATA LSB IN tOD MOSIn output MSB OUT MSB IN tDr, tDf DATA LSB OUT IDLE MSB OUT (n = A or B) Figure 2.62 SPI timing (master, CPHA = 1) (bit rate: PCLKA division ratio is set to 1/2) tTD SSLn0 input tLEAD tLAG RSPCKn CPOL = 0 input RSPCKn CPOL = 1 input t SA tOH MISOn output MSB OUT t SU MOSIn input tOD DATA t REL LSB OUT tH MSB IN MSB IN MSB OUT t Dr, tDf DATA LSB IN MSB IN (n = A or B) Figure 2.63 SPI timing (slave, CPHA = 0) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 84 of 137 S3A7 Datasheet 2. Electrical Characteristics tTD SSLn0 input tLEAD tLAG RSPCKn CPOL = 0 input RSPCKn CPOL = 1 input tSA tOH tOD LSB OUT (Last data) MISOn output MSB OUT tSU MOSIn input tREL LSB OUT DATA tH MSB OUT tDr, tDf MSB IN DATA LSB IN MSB IN (n = A or B) Figure 2.64 2.3.11 SPI timing (slave, CPHA = 1) QSPI Timing Table 2.41 QSPI timing Conditions: VCC = AVCC0 = 1.8 to 5.5 V Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register Symbol Min Max Unit*1 Test conditions QSPCLK clock cycle tQScyc 2*4 48 tPcyc Figure 2.65 QSPCLK clock high-level pulse width tQSWH tQScyc x 0.4 - ns QSPCLK clock low-level pulse width tQSWL tQScyc x 0.4 - ns Data input setup time tSU 40 - ns 2.4 V or above 40 - ns 1.8 V or above 80 - ns Parameter QSPI 2.7 V or above Data input hold time tIH 0 - ns SSL setup time tLEAD (N + 0.5) x tQscyc - 15*2 (N + 0.5) x tQscyc + 100*2 ns SSL hold time tLAG (N + 0.5) x tQscyc - 15*3 (N + 0.5) x tQscyc + 100*3 ns ns Data output delay 2.7 V or above tOD 2.4 V or above 1.8 V or above Data output hold time 2.7 V or above tOH 1.8 V or above Successive transmission delay Note 1. Note 2. Note 3. Note 4. tTD - 14 - 20 - 30 -3.3 - -10 - 1 16 Figure 2.66 ns tQscyc tPcyc: PCLKA cycle. N is set to 0 or 1 in SFMSLD. N is set to 0 or 1 in SFMSHD. The upper limit of QSPCLK is 16 MHz. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 85 of 137 S3A7 Datasheet 2. Electrical Characteristics tQSWH tQSWL QSPCLK output tQScyc Figure 2.65 QSPI clock timing tTD QSSL output tLEAD tLAG QSPCLK output tSU QIO0 to 3 input tH MSB IN DATA tOH QIO0 to 3 output Figure 2.66 MSB OUT LSB IN tOD DATA LSB OUT IDLE Transfer/receive timing R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 86 of 137 S3A7 Datasheet 2.3.12 2. Electrical Characteristics IIC Timing Table 2.42 IIC timing Conditions: VCC = AVCC0 = 2.7 to 5.5 V Symbol Min*1 Max Unit Test conditions SCL input cycle time tSCL 6 (12) x tIICcyc + 1300 - ns Figure 2.67 SCL input high pulse width tSCLH 3 (6) x tIICcyc + 300 - ns SCL input low pulse width tSCLL 3 (6) x tIICcyc + 300 - ns SCL, SDA input rise time tSr - 1000 ns SCL, SDA input fall time tSf - 300 ns SCL, SDA input spike pulse removal time tSP 0 1 (4) x tIICcyc ns SDA input bus free time (When wakeup function is disabled) tBUF 3 (6) x tIICcyc + 300 - ns SDA input bus free time (When wakeup function is enabled) tBUF 3 (6) x tIICcyc + 4 x tPcyc + 300 - ns START condition input hold time (When wakeup function is disabled) tSTAH tIICcyc + 300 - ns START condition input hold time (When wakeup function is enabled) tSTAH 1 (5) x tIICcyc + tPcyc + 300 - ns Repeated START condition input setup time tSTAS 1000 - ns STOP condition input setup time tSTOS 1000 - ns Data input setup time tSDAS tIICcyc + 50 - ns Data input hold time tSDAH 0 - ns SCL, SDA capacitive load Cb - 400 pF SCL input cycle time tSCL 6 (12) x tIICcyc + 600 - ns SCL input high pulse width tSCLH 3 (6) x tIICcyc + 300 - ns SCL input low pulse width tSCLL 3 (6) x tIICcyc + 300 - ns SCL, SDA input rise time tSr - 300 ns SCL, SDA input fall time tSf - 300 ns SCL, SDA input spike pulse removal time tSP 0 1 (4) x tIICcyc ns SDA input bus free time (When wakeup function is disabled) tBUF 3 (6) x tIICcyc + 300 - ns SDA input bus free time (When wakeup function is enabled) tBUF 3 (6) x tIICcyc + 4 x tPcyc + 300 - ns START condition input hold time (When wakeup function is disabled) tSTAH tIICcyc + 300 - ns START condition input hold time (When wakeup function is enabled) tSTAH 1(5) x tIICcyc + tPcyc + 300 - ns Repeated START condition input setup time tSTAS 300 - ns STOP condition input setup time tSTOS 300 - ns Data input setup time tSDAS tIICcyc + 50 - ns Data input hold time tSDAH 0 - ns SCL, SDA capacitive load Cb - 400 pF Parameter IIC (standard mode, SMBus) IIC (Fast mode)*2 Note: Note 1. Note 2. Figure 2.67 tIICcyc: IIC internal reference clock (IIC) cycle, tPcyc: PCLKB cycle The value in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1. Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 87 of 137 S3A7 Datasheet 2. Electrical Characteristics VIH SDA0 to SDA2 VIL tBUF tSCLH tSTAH tSTAS tSTOS tSP SCL0 to SCL2 P*1 S*1 P*1 Sr*1 tSf tSCLL tSr tSCL tSDAS tSDAH Note 1. S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Restart condition Figure 2.67 I2C bus interface input/output timing R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 88 of 137 S3A7 Datasheet 2.3.13 Table 2.43 2. Electrical Characteristics SSI Timing SSI timing Conditions: VCC = AVCC0 = 1.6 to 5.5 V Parameter SSI AUDIO_CLK input frequency 2.7 V or above Input clock period Clock high pulse width 1.8 V or above Clock low pulse width 1.8 V or above Max Unit Test conditions - 25 MHz Figure 2.68 - 4 tO 250 - ns tI 250 - ns tHC 100 - ns 200 - 1.6 V or above 100 - 200 - tRC - 25 ns tDTR - 65 ns 1.8 V or above - 105 1.6 V or above - 140 tLC 1.6 V or above Clock rise time 2.7 V or above Set-up time Min 1.6 V or above Output clock period Data delay Symbol tAUDIO 2.7 V or above tSR 1.8 V or above 1.6 V or above Hold time SSIDATA output delay from WS change time 1.8 V or above - 140 - 40 - ns TDTRW - 105 ns - 140 tHC Figure 2.69, Figure 2.70 ns tHTR 1.6 V or above SSISCKn 65 90 ns Figure 2.71 tRC tLC tI, tO Figure 2.68 SSI clock input/output timing R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 89 of 137 S3A7 Datasheet 2. Electrical Characteristics SSISCKn (Input or Output) SSIWSn, SSIDATAn (Input) tSR tHTR SSIWSn, SSIDATAn (Output) tDTR Figure 2.69 SSI data transmit/receive timing (SSICR.SCKP = 0) SSISCKn (Input or Output) SSIWSn, SSIDATAn (Input) tSR tHTR SSIWSn, SSIDATAn (Output) tDTR Figure 2.70 SSI data transmit/receive timing (SSICR.SCKP = 1) SSIWSn (Input) SSIDATAn (Output) tDTRW MSB bit output delay from SSIWSn change time for Slave transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0] Figure 2.71 SSI data output delay from SSIWSn change time R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 90 of 137 S3A7 Datasheet 2.3.14 2. Electrical Characteristics SD/MMC Host Interface Timing Table 2.44 SD/MMC host interface signal timing Conditions: VCC = AVCC0 = 2.7 to 5.5 V Conditions: Middle drive output is selected in the Port Drive Capability in PmnPFS register Parameter Symbol Min Max Unit Test conditions SDCLK clock cycle tSDCYC 62.5 - ns Figure 2.72 SDCLK clock high-level pulse width tSDWH 18.25 - ns SDCLK clock low-level pulse width tSDWL 18.25 - ns SDCLK clock rising time tSDLH - 10 ns SDCLK clock falling time tSDHL - 10 ns SDCMD/SDDAT output data delay tSDODLY -18.25 18.25 ns SDCMD/SDDAT input data setup tSDIS 9.25 - ns SDCMD/SDDAT input data hold tSDIH 23.25 - ns tSDCYC tSDWL SD0CLK (output) tSDHL tSDWH tSDLH tSDODLY(max) tSDODLY(min) SD0CMD/SD0DATm (output) tSDIS tSDIH SD0CMD/SD0DATm (input) (m = 0 to 7) Figure 2.72 2.3.15 SD/MMC host interface signal timing CLKOUT Timing Table 2.45 CLKOUT timing Symbol Min Max Unit*1 Test conditions tCcyc 62.5 - ns Figure 2.73 VCC = 1.8 V or above 125 - VCC = 1.6 V or above 250 - Parameter CLKOUT CLKOUT pin output cycle*1 CLKOUT pin high pulse width*2 VCC = 2.7 V or above VCC = 2.7 V or above tCH 15 - 30 - 150 - 15 - VCC = 1.8 V or above 30 - VCC = 1.6 V or above 150 - VCC = 1.8 V or above VCC = 1.6 V or above CLKOUT pin low pulse width*2 CLKOUT pin output rise time VCC = 2.7 V or above tCL - 12 - 25 - 50 - 12 VCC = 1.8 V or above - 25 VCC = 1.6 V or above - 50 VCC = 2.7 V or above tCr VCC = 1.8 V or above VCC = 1.6 V or above CLKOUT pin output fall time Note 1. Note 2. VCC = 2.7 V or above tCf ns ns ns ns When the EXTAL external clock input or an oscillator is used with division by 1 (the CKOCR.CKOSEL[2:0] bits are 011b and the CKOCR.CKODIV[2:0] bits are 000b) to output from CLKOUT, the above should be satisfied with an input duty cycle of 45 to 55%. When the MOCO is selected as the clock output source (the CKOCR.CKOSEL[2:0] bits are 001b), set the clock output division ratio selection to be divided by 2 (the CKOCR.CKODIV[2:0] bits are 001b). R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 91 of 137 S3A7 Datasheet 2. Electrical Characteristics tCcyc tCH tCf CLKOUT pin output tCr tCL Test conditions: VOH = VCC x 0.7, VOL = VCC x 0.3, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF Figure 2.73 2.4 CLKOUT output timing USB Characteristics 2.4.1 Table 2.46 USBFS Timing USB characteristics Conditions: VCC = AVCC0 = VCC_USB = 3.0 to 3.6 V Parameter Input characteristics Output characteristics Symbol Min Max Unit Test conditions Input high level voltage VIH 2.0 - V - Input low level voltage VIL - 0.8 V - Differential input sensitivity VDI 0.2 - V | USB_DP - USB_DM | Differential common mode range VCM 0.8 2.5 V - Output high level voltage VOH 2.8 VCC_USB V IOH = -200 A Output low level voltage VOL 0.0 0.3 V IOL= 2 mA VCRS 1.3 2.0 V tr 4 20 ns Figure 2.74, Figure 2.75, Figure 2.76 75 300 4 20 75 300 Cross-over voltage Rise time FS Fall time FS LS tf LS Rise/fall time ratio FS tr/tf LS 90 111.11 80 125 44 ns % Output resistance ZDRV 28 VBUS characteristics VBUS input voltage VIH VCC x 0.8 - V - VIL - VCC x 0.2 V - Pull-up, pull-down Pull-down resistor RPD 14.25 24.80 k - Pull-up resistor RPUI 0.9 1.575 k During idle state RPUA 1.425 3.09 k During reception D + sink current IDP_SINK 25 175 A - D - sink current IDM_SINK 25 175 A - DCD source current IDP_SRC 7 13 A - Data detection voltage VDAT_REF 0.25 0.4 V - D + source voltage VDP_SRC 0.5 0.7 V Output current = 250 A D - source voltage VDM_SRC 0.5 0.7 V Output current = 250 A Battery Charging Specification version 1.2 R01DS0263EU0140 Rev.1.40 Oct 29, 2018 (Adjusting the resistance of external elements is not necessary.) Page 92 of 137 S3A7 Datasheet 2. Electrical Characteristics USB_DP, USB_DM VCRS 90% 90% 10% 10% tr Figure 2.74 tf USB_DP and USB_DM output timing Observation point DP 50 pF DM 50 pF Figure 2.75 Test circuit for Full-Speed (FS) connection Observation point DP 200 pF to 600 pF 3.6 V 1.5 K DM 200 pF to 600 pF Observation point Figure 2.76 2.4.2 Table 2.47 Test circuit for Low-Speed (LS) connection USB External Supply USB regulator Parameter VCC_USB supply current Min Typ Max Unit Test conditions VCC_USB_LDO 3.8V - - 50 mA - VCC_USB_LDO 4.5V - - 100 mA - 3.0 - 3.6 V - VCC_USB supply voltage R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 93 of 137 S3A7 Datasheet 2.5 2. Electrical Characteristics ADC14 Characteristics VREFH0 VREFH0 5.5 5.5 A/D Conversion Characteristics (1) 5.0 5.0 A/D Conversion Characteristics (2) 4.0 3.0 2.7 2.4 A/D Conversion Characteristics (4) 4.0 3.0 2.7 2.4 A/D Conversion Characteristics (3) 2.0 A/D Conversion Characteristics (5) A/D Conversion Characteristics (6) 2.0 1.8 1.6 1.0 A/D Conversion Characteristics (7) 1.0 2.4 2.7 1.0 2.0 3.0 5.5 4.0 1.8 AVCC0 5.0 1.0 ADCSR.ADHSC = 0 Figure 2.77 Table 2.48 2.4 2.7 1.6 2.0 3.0 5.5 4.0 AVCC0 5.0 ADCSR.ADHSC = 1 AVCC0 to VREFH0 voltage range A/D conversion characteristics (1) in High-speed A/D conversion mode (1 of 2) Conditions: VCC = AVCC0 = 4.5 to 5.5 V, VREFH0 = 4.5 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Frequency 1 - 64 MHz - Analog input capacitance*2 Analog input resistance Cs Rs Analog input voltage range Ain - - 8 (reference data) pF High-precision channel - - 9 (reference data) pF Normal-precision channel - - 2.5 (reference data) k High-precision channel - - 6.7 (reference data) k Normal-precision channel 0 - VREFH0 V - 12-bit mode Resolution - - 12 Bit - 0.70 - - s High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 1.13 - - s Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Offset error - 0.5 4.5 LSB High-precision channel 6.0 LSB Other than above Full-scale error - 0.75 4.5 LSB High-precision channel 6.0 LSB Other than above Conversion time*1 (Operation at PCLKC = 64 MHz) Permissible signal source impedance Max. = 0.3 k Quantization error - 0.5 - LSB - Absolute accuracy - 1.25 5.0 LSB High-precision channel 8.0 LSB Other than above DNL differential nonlinearity error - 1.0 - LSB - INL integral nonlinearity error - 1.0 3.0 LSB - - - 14 Bit - 14-bit mode Resolution R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 94 of 137 S3A7 Datasheet Table 2.48 2. Electrical Characteristics A/D conversion characteristics (1) in High-speed A/D conversion mode (2 of 2) Conditions: VCC = AVCC0 = 4.5 to 5.5 V, VREFH0 = 4.5 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Parameter time*1 Conversion (Operation at PCLKC = 64 MHz) Permissible signal source impedance Max. = 0.3 k Offset error Full-scale error Min Typ Max Unit Test conditions 0.80 - - s High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 1.22 - - s Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h - 2.0 18 LSB High-precision channel 24.0 LSB Other than above 18 LSB High-precision channel 24.0 LSB Other than above - 3.0 Quantization error - 0.5 - LSB - Absolute accuracy - 5.0 20 LSB High-precision channel 32.0 LSB Other than above DNL differential nonlinearity error - 4.0 - LSB - INL integral nonlinearity error - 4.0 12.0 LSB - Note: Note 1. Note 2. The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics. Table 2.49 A/D conversion characteristics (2) in High-speed A/D conversion mode (1 of 2) Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Frequency 1 - 48 MHz - Analog input capacitance*2 Analog input resistance Cs Rs Analog input voltage range Ain - - 8 (reference data) pF High-precision channel - - 9 (reference data) pF Normal-precision channel - - 2.5 (reference data) k High-precision channel - - 6.7 (reference data) k Normal-precision channel 0 - VREFH0 V - - - 12 Bit - 0.94 - - s High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 1.50 - - s Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h - 0.5 4.5 LSB High-precision channel 6.0 LSB Other than above 4.5 LSB High-precision channel 6.0 LSB Other than above 12-bit mode Resolution time*1 Conversion (Operation at PCLKC = 48 MHz) Permissible signal source impedance Max. = 0.3 k Offset error Full-scale error - 0.75 Quantization error - 0.5 - LSB - Absolute accuracy - 1.25 5.0 LSB High-precision channel 8.0 LSB Other than above DNL differential nonlinearity error - 1.0 - LSB - R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 95 of 137 S3A7 Datasheet Table 2.49 2. Electrical Characteristics A/D conversion characteristics (2) in High-speed A/D conversion mode (2 of 2) Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions INL integral nonlinearity error - 1.0 3.0 LSB - 14-bit mode Resolution - - 14 Bit - 1.06 - - s High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 1.63 - - s Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Offset error - 2.0 18 LSB High-precision channel 24.0 LSB Other than above Full-scale error - 3.0 18 LSB High-precision channel 24.0 LSB Other than above Quantization error - 0.5 - LSB - Absolute accuracy - 5.0 20 LSB High-precision channel 32.0 LSB Other than above DNL differential nonlinearity error - 4.0 - LSB - INL integral nonlinearity error - 4.0 12.0 LSB - Conversion time*1 (Operation at PCLKC = 48 MHz) Note: Note 1. Note 2. Permissible signal source impedance Max. = 0.3 k The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics. Table 2.50 A/D conversion characteristics (3) in High-speed A/D conversion mode (1 of 2) Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Frequency Analog input capacitance*2 Analog input resistance Cs Rs Analog input voltage range Ain Min Typ Max Unit Test conditions 1 - 32 MHz - - - 8 (reference data) pF High-precision channel - - 9 (reference data) pF Normal-precision channel - - 2.5 (reference data) k High-precision channel - - 6.7 (reference data) k Normal-precision channel 0 - VREFH0 V - 12-bit mode Resolution - - 12 Bit - 1.41 - - s High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 2.25 - - s Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Offset error - 0.5 4.5 LSB High-precision channel 6.0 LSB Other than above Full-scale error - 0.75 4.5 LSB High-precision channel 6.0 LSB Other than above Quantization error - 0.5 - LSB - Absolute accuracy - 1.25 5.0 LSB High-precision channel 8.0 LSB Other than above Conversion time*1 (Operation at PCLKC = 32 MHz) Permissible signal source impedance Max. = 1.3 k R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 96 of 137 S3A7 Datasheet Table 2.50 2. Electrical Characteristics A/D conversion characteristics (3) in High-speed A/D conversion mode (2 of 2) Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions DNL differential nonlinearity error - 1.0 - LSB - INL integral nonlinearity error - 1.0 3.0 LSB - - - 14 Bit - 1.59 - - s High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 2.44 - - s Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h - 2.0 18 LSB High-precision channel 24.0 LSB Other than above 18 LSB High-precision channel 24.0 LSB Other than above 14-bit mode Resolution time*1 Conversion (Operation at PCLKC = 32 MHz) Permissible signal source impedance Max. = 1.3 k Offset error Full-scale error - 3.0 Quantization error - 0.5 - LSB - Absolute accuracy - 5.0 20 LSB High-precision channel 32.0 LSB Other than above DNL differential nonlinearity error - 4.0 - LSB - INL integral nonlinearity error - 4.0 12.0 LSB - Note: Note 1. Note 2. The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics. Table 2.51 A/D conversion characteristics (4) in Low-power A/D conversion mode (1 of 2) Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Frequency Min Typ Max Unit Test conditions 1 - 24 MHz - - - 8 (reference data) pF High-precision channel Analog input capacitance*2 Cs - - 9 (reference data) pF Normal-precision channel Analog input resistance Rs - - 2.5 (reference data) k High-precision channel - - 6.7 (reference data) k Normal-precision channel Analog input voltage range Ain 0 - VREFH0 V - - - 12 Bit - 2.25 - - s High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 3.38 - - s Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h - 0.5 4.5 LSB High-precision channel 6.0 LSB Other than above 4.5 LSB High-precision channel 6.0 LSB Other than above - LSB - 12-bit mode Resolution time*1 Conversion (Operation at PCLKC = 24 MHz) Permissible signal source impedance Max. = 1.1 k Offset error Full-scale error Quantization error R01DS0263EU0140 Rev.1.40 Oct 29, 2018 - 0.75 0.5 Page 97 of 137 S3A7 Datasheet Table 2.51 2. Electrical Characteristics A/D conversion characteristics (4) in Low-power A/D conversion mode (2 of 2) Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Absolute accuracy - 1.25 5.0 LSB High-precision channel 8.0 LSB Other than above DNL differential nonlinearity error - 1.0 - LSB - INL integral nonlinearity error - 1.0 3.0 LSB - - - 14 Bit - 2.50 - - s High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 3.63 - - s Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h - 2.0 18 LSB High-precision channel 24.0 LSB Other than above 18 LSB High-precision channel 14-bit mode Resolution time*1 Conversion (Operation at PCLKC = 24 MHz) Permissible signal source impedance Max. = 1.1 k Offset error Full-scale error - 3.0 24.0 LSB Other than above Quantization error - 0.5 - LSB - Absolute accuracy - 5.0 20 LSB High-precision channel 32.0 LSB Other than above DNL differential nonlinearity error - 4.0 - LSB - INL integral nonlinearity error - 4.0 12.0 LSB - Note: Note 1. Note 2. The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics. Table 2.52 A/D conversion characteristics (5) in Low-power A/D conversion mode (1 of 2) Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Frequency Min Typ Max Unit Test conditions 1 - 16 MHz - Analog input capacitance*2 Cs - - 8 (reference) pF High-precision channel - - 9 (reference) pF Normal-precision channel Analog input resistance Rs - - 2.5 (reference) k High-precision channel - - 6.7 (reference) k Normal-precision channel Analog input voltage range Ain 0 - VREFH0 V - - - 12 Bit - 3.38 - - s High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 5.06 - - s Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h - 0.5 4.5 LSB High-precision channel 6.0 LSB Other than above 4.5 LSB High-precision channel 6.0 LSB Other than above 12-bit mode Resolution time*1 Conversion (Operation at PCLKC = 16 MHz) Permissible signal source impedance Max. = 2.2 k Offset error Full-scale error R01DS0263EU0140 Rev.1.40 Oct 29, 2018 - 0.75 Page 98 of 137 S3A7 Datasheet Table 2.52 2. Electrical Characteristics A/D conversion characteristics (5) in Low-power A/D conversion mode (2 of 2) Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Quantization error - 0.5 - LSB - Absolute accuracy - 1.25 5.0 LSB High-precision channel 8.0 LSB Other than above DNL differential nonlinearity error - 1.0 - LSB - INL integral nonlinearity error - 1.0 3.0 LSB - 14-bit mode Resolution Conversion time*1 (Operation at PCLKC = 16 MHz) Permissible signal source impedance Max. = 2.2 k Offset error Full-scale error - - 14 Bit - 3.75 - - s High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 5.44 - - s Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h - 2.0 18 LSB High-precision channel 24.0 LSB Other than above 18 LSB High-precision channel 24.0 LSB Other than above - 3.0 Quantization error - 0.5 - LSB - Absolute accuracy - 5.0 20 LSB High-precision channel 32.0 LSB Other than above DNL differential nonlinearity error - 4.0 - LSB - INL integral nonlinearity error - 4.0 12.0 LSB - Note: Note 1. Note 2. The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics. Table 2.53 A/D conversion characteristics (6) in Low-power A/D conversion mode (1 of 2) Conditions: VCC = AVCC0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.8 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Frequency 1 - 8 MHz - Analog input capacitance*2 Analog input resistance Cs Rs Analog input voltage range Ain - - 8 (reference data) pF High-precision channel - - 9 (reference data) pF Normal-precision channel - - 3.8 (reference data) k High-precision channel - - 8.2 (reference data) k Normal-precision channel 0 - VREFH0 V - 12-bit mode Resolution Conversion time*1 (Operation at PCLKC = 8 MHz) Permissible signal source impedance Max. = 5 k Offset error R01DS0263EU0140 Rev.1.40 Oct 29, 2018 - - 12 Bit - 6.75 - - s High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 10.13 - - s Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h - 1.0 7.5 LSB High-precision channel 10.0 LSB Other than above Page 99 of 137 S3A7 Datasheet Table 2.53 2. Electrical Characteristics A/D conversion characteristics (6) in Low-power A/D conversion mode (2 of 2) Conditions: VCC = AVCC0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.8 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Full-scale error - 1.5 7.5 LSB High-precision channel 10.0 LSB Other than above Quantization error - 0.5 - LSB - Absolute accuracy - 3.0 8.0 LSB High-precision channel 12.0 LSB Other than above DNL differential nonlinearity error - 1.0 - LSB - INL integral nonlinearity error - 1.0 3.0 LSB - 14-bit mode Resolution Conversion time*1 (Operation at PCLKC = 8 MHz) Permissible signal source impedance Max. = 5 k Offset error Full-scale error - - 14 Bit - 7.50 - - s High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 10.88 - - s Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h - 4.0 30.0 LSB High-precision channel 40.0 LSB Other than above 30.0 LSB High-precision channel 40.0 LSB Other than above - 6.0 Quantization error - 0.5 - LSB - Absolute accuracy - 12.0 32.0 LSB High-precision channel 48.0 LSB Other than above DNL differential nonlinearity error - 4.0 - LSB - INL integral nonlinearity error - 4.0 12.0 LSB - Note: Note 1. Note 2. The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics. Table 2.54 A/D conversion characteristics (7) in Low-power A/D conversion mode (1 of 2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.6 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Frequency 1 - 4 MHz - Analog input capacitance*2 Analog input resistance Cs Rs Analog input voltage range Ain - - 8 (reference data) pF High-precision channel - - 9 (reference data) pF Normal-precision channel - - 13.1 (reference data) k High-precision channel - - 14.3 (reference data) k Normal-precision channel 0 - VREFH0 V - 12-bit mode Resolution Conversion time*1 (Operation at PCLKC = 4 MHz) Permissible signal source impedance Max. = 9.9 k R01DS0263EU0140 Rev.1.40 Oct 29, 2018 - - 12 Bit - 13.5 - - s High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 20.25 - - s Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Page 100 of 137 S3A7 Datasheet Table 2.54 2. Electrical Characteristics A/D conversion characteristics (7) in Low-power A/D conversion mode (2 of 2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.6 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 Reference voltage range applied to the VREFH0 and VREFL0. Parameter Min Typ Max Unit Test conditions Offset error - 1.0 7.5 LSB High-precision channel 10.0 LSB Other than above 7.5 LSB High-precision channel 10.0 LSB Other than above Full-scale error - 1.5 Quantization error - 0.5 - LSB - Absolute accuracy - 3.0 8.0 LSB High-precision channel 12.0 LSB Other than above DNL differential nonlinearity error - 1.0 - LSB - INL integral nonlinearity error - 1.0 3.0 LSB - - - 14 Bit - 15.0 - - s High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 21.75 - - s Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h - 4.0 30.0 LSB High-precision channel 40.0 LSB Other than above 30.0 LSB High-precision channel 40.0 LSB Other than above 14-bit mode Resolution time*1 Conversion (Operation at PCLKC = 4 MHz) Permissible signal source impedance Max. = 9.9 k Offset error Full-scale error - 6.0 Quantization error - 0.5 - LSB - Absolute accuracy - 12.0 32.0 LSB High-precision channel 48.0 LSB Other than above DNL differential nonlinearity error - 4.0 - LSB - INL integral nonlinearity error - 4.0 12.0 LSB - Note: Note 1. Note 2. The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics. MCU Sensor Analog input ANn Rs Cin ADC Cs Analog input ANn Rs Cin Figure 2.78 Equivalent circuit for analog input R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 101 of 137 S3A7 Datasheet Table 2.55 2. Electrical Characteristics 14-Bit A/D converter channel classification Classification Channel Conditions Remarks High-precision channel AN000 to AN015 AVCC0 = 1.6 to 5.5 V Normal-precision channel AN016 to AN027 Pins AN000 to AN015 cannot be used as general I/O, IRQ8, IRQ9 inputs, and TS transmission, when the A/D converter is in use Internal reference voltage input channel Internal reference voltage AVCC0 = 2.0 to 5.5 V - Temperature sensor input channel Temperature sensor output AVCC0 = 2.0 to 5.5 V - Table 2.56 A/D internal reference voltage characteristics Conditions: VCC = AVCC0 = VREFH0 = 2.0 to 5.5 V*1 Parameter Min Typ Max Unit Test conditions Internal reference voltage input channel*2 1.36 1.43 1.50 V - Frequency*3 1 - 2 MHz - 5.0 - - s - Sampling Note 1. Note 2. Note 3. Note 4. time*4 The internal reference voltage cannot be selected for input channels when AVCC0 < 2.0 V. The 14-bit A/D internal reference voltage indicates the voltage when the internal reference voltage is input to the 14-bit A/D converter. This is a parameter for ADC14 when the internal reference voltage is used as the high-potential reference voltage. This is a parameter for ADC14 when the internal reference voltage is selected for an analog input channel in ADC14. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 102 of 137 S3A7 Datasheet 2. Electrical Characteristics 3FFFh Full-scale error Integral nonlinearity error (INL) A/D converter output code Ideal line of actual A/D conversion characteristic Actual A/D conversion characteristic Ideal A/D conversion characteristic Differential nonlinearity error (DNL) 1-LSB width for ideal A/D conversion characteristic Differential nonlinearity error (DNL) 1-LSB width for ideal A/D conversion characteristic Absolute accuracy 0000h Offset error 0 Figure 2.79 Analog input voltage VREFH0 (full-scale) Illustration of 14-bit A/D converter characteristic terms Absolute accuracy Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of analog input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D conversion characteristics, is used as the analog input voltage. For example, if 12-bit resolution is used and the reference voltage VREFH0 = 3.072 V, then 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, 1.5 mV are used as the analog input voltages. If analog input voltage is 6 mV, an absolute accuracy of 5 LSB means that the actual A/D conversion result is in the range of 003h to 00Dh, though an output code of 008h can be expected from the theoretical A/D conversion characteristics. Integral nonlinearity error (INL) Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale errors are zeroed, and the actual output code. Differential nonlinearity error (DNL) Differential nonlinearity error is the difference between 1-LSB width based on the ideal A/D conversion characteristics and the width of the actually output code. Offset error Offset error is the difference between the transition point of the ideal first output code and the actual first output code. Full-scale error Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 103 of 137 S3A7 Datasheet 2.6 2. Electrical Characteristics DAC12 Characteristics Table 2.57 D/A conversion characteristics (1) Conditions: VCC = AVCC0 = 1.8 to 5.5 V Reference voltage = VREFH or VREFL selected Parameter Min Typ Max Unit Test conditions Resolution - - 12 bit - Resistive load 30 - - k - Capacitive load - - 50 pF - Output voltage range 0.35 - AVCC0 - 0.47 V DNL differential nonlinearity error - 0.5 1.0 LSB - INL integral nonlinearity error - 2.0 8.0 LSB - Offset error - - 20 mV - Full-scale error - - 20 mV - Output impedance - 5 - - Conversion time - - 30 s - Typ Max Unit Test conditions Table 2.58 D/A conversion characteristics (2) Conditions: VCC = AVCC0 = 1.8 to 5.5 V Reference voltage = AVCC0 or AVSS0 selected Parameter Min Resolution - - 12 bit - Resistive load 30 - - k - Capacitive load - - 50 pF - Output voltage range 0.35 - AVCC0 - 0.47 V - DNL differential nonlinearity error - 0.5 2.0 LSB - INL integral nonlinearity error - 2.0 8.0 LSB - Offset error - - 30 mV - Full-scale error - - 30 mV - Output impedance - 5 - - Conversion time - - 30 s - Table 2.59 D/A conversioncharacteristics (3) Conditions: VCC = AVCC0 = 1.8 to 5.5 V Reference voltage = internal reference voltage selected Parameter Min Typ Max Unit Test conditions Resolution - - 12 bit - Internal reference voltage (Vbgr) 1.36 1.43 1.50 V - Resistive load 30 - - k - Capacitive load - - 50 pF - Output voltage range 0.35 - Vbgr V - DNL differential nonlinearity error - 2.0 16.0 LSB - INL integral nonlinearity error - 8.0 16.0 LSB - Offset error - - 30 mV - Output impedance - 5 - - Conversion time - - 30 s - R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 104 of 137 S3A7 Datasheet 2. Electrical Characteristics Gain error Full-scale error Upper output limit Integral nonlinearity error (INL) Offset error Output analog voltage 1-LSB width for ideal D/A conversion characteristic Ideal output voltage Differential nonlinearity error (DNL) *1 Lower output limit Actual D/A conversion characteristic Offset error Ideal output voltage 000h D/A converter input code FFFh Note 1. Ideal D/A conversion output voltage that is adjusted so that offset and full scale errors are zeroed. Figure 2.80 Illustration of D/A converter characteristic terms Integral nonlinearity error (INL) Integral nonlinearity error is the maximum deviation between the ideal output voltage based on the ideal conversion characteristic when the measured offset and full-scale errors are zeroed, and the actual output voltage. Differential nonlinearity error (DNL) Differential nonlinearity error is the difference between 1-LSB voltage width based on the ideal D/A conversion characteristics and the width of the actual output voltage. Offset error Offset error is the difference between the highest actual output voltage that falls below the lower output limit and the ideal output voltage based on the input code. Full-scale error Full-scale error is the difference between the lowest actual output voltage that exceeds the upper output limit and the ideal output voltage based on the input code. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 105 of 137 S3A7 Datasheet 2.7 2. Electrical Characteristics TSN Characteristics Table 2.60 TSN characteristics Conditions: VCC = AVCC0 = 2.0 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions Relative accuracy - - 1.5 - C 2.4 V or above - - 2.0 - C Below 2.4 V Temperature slope - - -3.65 - mV/C - Output voltage (at 25C) - - 1.05 - V VCC = 3.3 V Temperature sensor start time tSTART - - 5 s - Sampling time - 5 - - s - 2.8 OSC Stop Detect Characteristics Table 2.61 Oscillation stop detection circuit characteristics Parameter Symbol Min Typ Max Unit Test conditions Detection time tdr - - 1 ms Figure 2.81 Main clock OSTDSR.OSTDF td Main clock r OSTDSR.OSTDF MOCO clock td r PLL clock ICLK MOCO clock When the main clock is selected Figure 2.81 ICLK When the PLL clock is selected Oscillation stop detection timing R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 106 of 137 S3A7 Datasheet 2.9 2. Electrical Characteristics POR and LVD Characteristics Table 2.62 Power-on reset circuit and voltage detection circuit characteristics (1) Parameter Voltage detection level*1 Symbol Min Typ Max Unit Test conditions Power-on reset (POR) VPOR 1.27 1.42 1.57 V Figure 2.82, Figure 2.83 Voltage detection circuit (LVD0)*2 Vdet0_0 3.68 3.85 4.00 V Vdet0_1 2.68 2.85 2.96 Figure 2.84 At falling edge VCC Vdet0_2 2.38 2.53 2.64 Vdet0_3 1.78 1.90 2.02 V Figure 2.85 At falling edge VCC V Figure 2.86 At falling edge VCC Voltage detection circuit (LVD1)*3 Voltage detection circuit Note 1. Note 2. Note 3. Note 4. (LVD2)*4 Vdet0_4 1.60 1.69 1.82 Vdet1_0 4.13 4.29 4.45 Vdet1_1 3.98 4.16 4.30 Vdet1_2 3.86 4.03 4.18 Vdet1_3 3.68 3.86 4.00 Vdet1_4 2.98 3.10 3.22 Vdet1_5 2.89 3.00 3.11 Vdet1_6 2.79 2.90 3.01 Vdet1_7 2.68 2.79 2.90 Vdet1_8 2.58 2.68 2.78 Vdet1_9 2.48 2.58 2.68 Vdet1_A 2.38 2.48 2.58 Vdet1_B 2.10 2.20 2.30 Vdet1_C 1.84 1.96 2.05 Vdet1_D 1.74 1.86 1.95 Vdet1_E 1.63 1.75 1.84 Vdet1_F 1.60 1.65 1.73 Vdet2_0 4.11 4.31 4.48 Vdet2_1 3.97 4.17 4.34 Vdet2_2 3.83 4.03 4.20 Vdet2_3 3.64 3.84 4.01 These characteristics apply when noise is not superimposed on the power supply. When a setting causes this voltage detection level to overlap with that of the voltage detection circuit, it cannot be specified whether LVD1 or LVD2 is used for voltage detection. # in the symbol Vdet0_# denotes the value of the OFS1.VDSEL1[2:0] bits. # in the symbol Vdet1_# denotes the value of the LVDLVLR.LVD1LVL[4:0] bits. # in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[2:0] bits. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 107 of 137 S3A7 Datasheet Table 2.63 2. Electrical Characteristics Power-on reset circuit and voltage detection circuit characteristics (2) Parameter Symbol Min Typ Max Unit Test conditions LVD0:enable tPOR - 1.7 - ms - LVD0:disable tPOR - 1.3 - ms - LVD0:enable*1 tLVD0,1,2 - 0.6 - ms - LVD0:disable*2 tLVD1,2 - 0.2 - ms - Response delay*3 tdet - - 350 s Figure 2.82, Figure 2.83 Minimum VCC down time tVOFF 450 - - s Figure 2.82, VCC = 1.0 V or above Power-on reset enable time tW (POR) 1 - - ms Figure 2.83, VCC = below 1.0 V LVD operation stabilization time (after LVD is enabled) Td (E-A) - - 300 s Figure 2.85, Figure 2.86 Hysteresis width (POR) VPORH - 110 - mV - Hysteresis width (LVD0, LVD1 and LVD2) VLVH - 60 - mV LVD0 selected - 100 - mV Vdet1_0 to Vdet1_2 selected. - 60 - Vdet1_3 to Vdet1_9 selected. - 50 - Vdet1_A or Vdet1_B selected. Wait time after power-on reset cancellation Wait time after voltage monitor 0,1,2 reset cancellation Note 1. Note 2. Note 3. - 40 - Vdet1_C or Vdet1_F selected. - 60 - LVD2 selected When OFS1.LVDAS = 0. When OFS1.LVDAS = 1. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet0, Vdet1, and Vdet2 for the POR/LVD. tVOFF VCC VPOR 1.0 V Internal reset signal (active-low) tdet Figure 2.82 tdet tPOR Voltage detection reset timing R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 108 of 137 S3A7 Datasheet 2. Electrical Characteristics VPOR VCC 1.0 V tW(POR) Internal reset signal (active-low) *1 tdet Note: Figure 2.83 tPOR tW(POR) is the time required for a power-on reset to be enabled while the external power VCC is being held below the valid voltage (1.0 V). When VCC turns on, maintain tW(POR) for 1.0 ms or more. Power-on reset timing tVOFF VCC VLVH Vdet0 Internal reset signal (active-low) tdet Figure 2.84 tdet tLVD0 Voltage detection circuit timing (Vdet0) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 109 of 137 S3A7 Datasheet 2. Electrical Characteristics tVOFF VCC VLVH Vdet1 LVCMPCR.LVD1E Td(E-A) LVD1 Comparator output LVD1CR0.CMPE LVD1SR.MON Internal reset signal (active-low) When LVD1CR0.RN = 0 tdet tdet tLVD1 When LVD1CR0.RN = 1 tLVD1 Figure 2.85 Voltage detection circuit timing (Vdet1) tVOFF VCC VLVH Vdet2 LVCMPCR.LVD2E LVD2 Comparator output Td(E-A) LVD2CR0.CMPE LVD2SR.MON Internal reset signal (active-low) When LVD2CR0.RN = 0 tdet tdet tLVD2 When LVD2CR0.RN = 1 tLVD2 Figure 2.86 Voltage detection circuit timing (Vdet2) R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 110 of 137 S3A7 Datasheet 2.10 2. Electrical Characteristics Battery Backup Function Characteristics Table 2.64 Battery Backup Function Characteristics Conditions: VCC = AVCC0 = 1.6V to 5.5V, VBATT = 1.6 to 3.6 V, VSS = AVSS0 = 0V Parameter Symbol Min Typ Max Unit Test conditions Voltage level for switching to battery backup (falling) VDETBATT 1.99 2.09 2.19 V Hysteresis width for switching to battery back up VVBATTH - 100 - mV Figure 2.87, Figure 2.88 VCC-off period for starting power supply switching tVOFFBATT 300 - - s - Voltage detection level VBATT_Power-on reset (VBATT_POR) VVBATPOR 1.30 1.40 1.50 V Figure 2.87, Figure 2.88 Wait time after VBATT_POR reset time cancellation tVBATPOR - - 3 mS - Level for detection of voltage drop on the VBATT pin (falling) VDETBATLVD 2.11 2.2 2.29 V Figure 2.89 1.92 2 2.08 V VBTLVDLVL[1:0] = 10b VBTLVDLVL[1:0] = 11b Hysteresis width for VBATT pin LVD VVBATLVDTH - 50 - mV VBATT pin LVD operation stabilization time td_vbat - - 300 s Figure 2.89 VBATT pin LVD response delay time tdet_vbat - - 350 s Allowable voltage change rising/falling gradient dt/dVCC 1.0 - - ms/V - VCC voltage level for access to the VBATT backup registers V_BKBATT 1.8 - - V - Note: The VCC-off period for starting power supply switching indicates the period in which VCC is below the minimum value of the voltage level for switching to battery backup (VDETBATT). VLVH Vdet0 VCC VVBATH VDETBATT VPOR VBATT VVBATPOR Internal reset signal (active-low) VCC supplied Figure 2.87 tdet tLVD0 tdet Backup power area VBATT supplied VCC supplied Power supply switching and LVD0 reset Timing R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 111 of 137 S3A7 Datasheet 2. Electrical Characteristics VCC VVBATH VDETBATT VBATT VVBATPOR VBATT_POR (active-low) tVBATPOR Backup power area VCC supplied Figure 2.88 VBATT supplied not supplied VCC supplied VBATT_POR reset timing VBATT VVBATLVDTH VDETBATLVD VBTCR2.VBTLVDEN Td_vbat VBATT pin LVD Comparator output VBTCMPCR.VBTCMPE VBTSR.VBTBLDF tdet_vbat Figure 2.89 tdet_vbat VBATT pin voltage detection circuit timing R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 112 of 137 S3A7 Datasheet Table 2.65 2. Electrical Characteristics VBATT-I/O characteristics Parameter VBATWIOn I/O output characteristics (n = 0 to 2) VCC > VDETBATT Symbol Min Typ Max Unit Test conditions VCC = 4.0 to 5.5 V VOH VCC - 0.8 - - V IOH = -200 A VOL - - 0.8 IOL = 200 A VCC = 2.7 to 4.0 V VOH VCC - 0.5 - - IOH = -100 A VOL - - 0.5 IOL = 100 A VCC = VDETBATT to 2.7 V VOH VCC < VDETBATT VBATT = 2.7 to 3.6 V VBATT = 1.6 to 2.7 V 2.11 VCC - 0.3 - - IOH = -50 A VOL - - 0.3 IOL = 50 A VOH VBATT - 0.5 - - IOH = -100 A VOL - - 0.5 IOL = 100 A VOH VBATT - 0.3 - - IOH = -50 A VOL - - 0.3 IOL = 50 A CTSU Characteristics Table 2.66 CTSU characteristics Conditions: VCC = AVCC0 = 1.8 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions External capacitance connected to TSCAP pin Ctscap 9 10 11 nF - TS pin capacitive load Cbase - - 50 pF - Permissible output high current IoH - - -24 mA When the mutual capacitance method is applied 2.12 Segment LCD Controller/Driver Characteristics 2.12.1 Resistance Division Method [Static Display Mode] Table 2.67 Resistance division method LCD characteristics (1) Conditions: VL4 VCC 5.5 V Parameter Symbol Min Typ Max Unit Test conditions LCD drive voltage VL4 2.0 - VCC V - [1/2 Bias Method, 1/4 Bias Method] Table 2.68 Resistance division method LCD characteristics (2) Conditions: VL4 VCC 5.5 V Parameter Symbol Min Typ Max Unit Test conditions LCD drive voltage VL4 2.7 - VCC V - [1/3 Bias Method] Table 2.69 Resistance division method LCD characteristics (3) Conditions: VL4 VCC 5.5 V Parameter Symbol Min Typ Max Unit Test conditions LCD drive voltage VL4 2.5 - VCC V - R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 113 of 137 S3A7 Datasheet 2.12.2 2. Electrical Characteristics Internal Voltage Boosting Method [1/3 Bias Method] Table 2.70 Internal voltage boosting method LCD characteristics Conditions: VCC = AVCC0 = 1.8 V to 5.5 V Parameter Symbol Conditions LCD output voltage variation range VL1 C1 to C4*1 = 0.47 F Min Typ Max Unit Test conditions VLCD = 04h 0.90 1.0 1.08 V - VLCD = 05h 0.95 1.05 1.13 V - VLCD = 06h 1.00 1.10 1.18 V - VLCD = 07h 1.05 1.15 1.23 V - VLCD = 08h 1.10 1.20 1.28 V - VLCD = 09h 1.15 1.25 1.33 V - VLCD = 0Ah 1.20 1.30 1.38 V - VLCD = 0Bh 1.25 1.35 1.43 V - VLCD = 0Ch 1.30 1.40 1.48 V - VLCD = 0Dh 1.35 1.45 1.53 V - VLCD = 0Eh 1.40 1.50 1.58 V - VLCD = 0Fh 1.45 1.55 1.63 V - VLCD = 10h 1.50 1.60 1.68 V - VLCD = 11h 1.55 1.65 1.73 V - VLCD = 12h 1.60 1.70 1.78 V - VLCD = 13h 1.65 1.75 1.83 V - Doubler output voltage VL2 C1 to C4*1 = 0.47 F 2 x VL1 - 0.1 2 x VL1 2 x VL1 V - Tripler output voltage VL4 C1 to C4*1 = 0.47 F 3 x VL1 - 0.15 3 x VL1 3 x VL1 V - Reference voltage setup time*2 tVL1S 5 - - ms Figure 2.90 LCD output voltage variation range*3 tVLWT 500 - - ms Note 1. Note 2. Note 3. C1 to C4*1 = 0.47 F This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = 0.47 F 30% This is the time required to wait from when the reference voltage is specified using the VLCD register (or when the internal voltage boosting method is selected (by setting the MDSET[1:0] bits in the LCDM0 register to 01b) if the default value reference voltage is used) until voltage boosting starts (VLCON = 1). This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 114 of 137 S3A7 Datasheet 2. Electrical Characteristics [1/4 Bias Method] Table 2.71 Internal voltage boosting method LCD characteristics Conditions: VCC = AVCC0 = 1.8 V to 5.5 V Parameter Symbol Conditions LCD output voltage variation range VL1 Doubler output voltage VL2 C1 to C5*1 = 0.47 F C1 to C5*1 = 0.47 F C5*1 Min Typ Max Unit Test conditions VLCD = 04h 0.90 1.0 1.08 V - VLCD = 05h 0.95 1.05 1.13 V - VLCD = 06h 1.00 1.10 1.18 V - VLCD = 07h 1.05 1.15 1.23 V - VLCD = 08h 1.10 1.20 1.28 V - VLCD = 09h 1.15 1.25 1.33 V - VLCD = 0Ah 1.20 1.30 1.38 V - VLCD = 0Bh 1.25 1.35 1.43 V - VLCD = 0Ch 1.30 1.40 1.48 V - 2VL1 - 0.08 2VL1 2VL1 V - Tripler output voltage VL3 C1 to = 0.47 F 3VL1 - 0.12 3VL1 3VL1 V - Quadruply output voltage VL4*4 C1 to C5*1 = 0.47 F 4VL1 - 0.16 4VL1 4VL1 V - Reference voltage setup time*2 tVL1S 5 - - ms Figure 2.90 LCD output voltage variation range*3 tVLWT 500 - - ms Note 1. Note 2. Note 3. Note 4. C1 to C5*1 = 0.47 F This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL3 and GND C5: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = C5 = 0.47 F 30% This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the internal voltage boosting method is selected (by setting the MDSET1 and MDSET0 bits in the LCDM0 register to 01b) if the default value reference voltage is used) until voltage boosting starts (VLCON = 1). This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1). VL4 must be 5.5 V or lower. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 115 of 137 S3A7 Datasheet 2.12.3 2. Electrical Characteristics Capacitor Split Method [1/3 Bias Method] Table 2.72 Internal voltage boostingmethod LCD characteristics Conditions: VCC = AVCC0 = 2.2 V to 5.5 V Parameter Symbol Conditions VL4 voltage*1 VL4 C1 to C4 = 0.47 F*2 voltage*1 VL2 C1 to C4 = 0.47 F*2 VL1 voltage*1 VL1 C1 to C4 = 0.47 F*2 VL2 Capacitor split wait Note 1. Note 2. time*1 tWAIT Min Typ Max Unit Test conditions - VCC - V - 2/3 x VL4 - 0.07 2/3 x VL4 2/3 x VL4 + 0.07 V - 1/3 x VL4 - 0.08 1/3 x VL4 1/3 x VL4 + 0.08 V - 100 - - ms Figure 2.90 This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1). This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = 0.47 F 30% MDSET0, MDSET1 VLCON 00b 01b or 10b tVL1S tVLWT, tWAIT LCDON Figure 2.90 LCD reference voltage setup time, voltage boosting wait time, and capacitor split wait time R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 116 of 137 S3A7 Datasheet 2.13 2. Electrical Characteristics Comparator Characteristics Table 2.73 ACMPHS characteristics Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VSS = AVSS0 = 0 V Parameter Symbol Min Typ Max Unit Test conditions Input offset voltage VIOCMP - 5 40 mV - Input voltage range VICMP 0 - AVCC0 V - Internal reference voltage - 1.36 1.44 1.50 V - Input signal cycle tPCMP 10 - - s - Output delay time td - 50 100 ns Input amplitude 100 mV Stabilization wait time during input channel switching*1 tWAIT 300 - - ns Input amplitude 100 mV Operation stabilization wait time*2 tCMP 1 - - s 3.3 V AVCC0 5.5 V 3 - - s 2.7 V AVCC0 < 3.3 V Note 1. Note 2. Period of time from when the comparator input channel is switched until the comparator is switched to output. Period of time from when the comparator operation is enabled (CMPCTL.HCMPON = 1) until the comparator satisfies the DC/AC characteristics. Table 2.74 ACMPLP characteristics Conditions: VCC = AVCC0 = 1.8 to 5.5 V, VSS = AVSS0 = 0 V Parameter Symbol Min Typ Max Unit Test conditions Reference voltage range VREF 0 - VCC -1.4 V - Input voltage range VI 0 - VCC V - Internal reference voltage - 1.36 1.44 1.50 V - Output delay Td VCC = 3.0 Slew rate of input signal > 50 mV/s Offset voltage High-speed mode - - 1.2 s Low-speed mode - - 5 s Window mode - - 2 s High-speed mode - - - 50 mV - Low-speed mode - - - 40 mV - Window mode Internal reference voltage for window mode Operation stabilization wait time R01DS0263EU0140 Rev.1.40 Oct 29, 2018 - - - 60 mV - VRFH - 0.76 x VCC - V - VRFL - 0.24 x VCC - V - Tcmp 100 - - s - Page 117 of 137 S3A7 Datasheet 2.14 2. Electrical Characteristics OPAMP Characteristics Table 2.75 OPAMP characteristics Conditions: 1.8 V AVCC0 = VCC 5.5 V, VSS = AVSS0 = 0 V Parameter Symbol Conditions Min Typ Max Common mode input range Vicm1 Low power mode 0.2 - AVCC0 - 0.5 V Vicm2 High-speed mode 0.3 - AVCC0 - 0.6 V Output voltage range Vo1 Low power mode 0.1 - AVCC0 - 0.1 V Vo2 High-speed mode 0.1 - AVCC0 - 0.1 V Vioff 3 -10 - 10 mV Input offset voltage Unit Open gain Av 60 120 - dB Gain-bandwidth (GB) product GBW1 Low power mode - 0.04 - MHz GBW2 High-speed mode - 1.7 - MHz Phase margin PM CL = 20 pF 50 - - deg Gain margin GM CL = 20 pF 10 - - dB - 230 - nV/Hz - 200 - nV/Hz - 90 - nV/Hz Equivalent input noise Vnoise1 f = 1 kHz Vnoise2 f = 10 kHz Vnoise3 f = 1 kHz Vnoise4 f = 2 kHz Low power mode High-speed mode - 70 - nV/Hz Power supply reduction ratio PSRR - 90 - dB Common mode signal reduction ratio CMRR - 90 - dB Stabilization wait time Tstd1 Low power mode 650 - - s High-speed mode Tstd2 13 - - s Low power mode 650 - - s Tstd4 CL = 20 pF Operational amplifier and reference current circuit are activated simultaneously High-speed mode 13 - - s Tset1 CL = 20 pF Low power mode - - 750 s High-speed mode - - 13 s Low power mode - 0.02 - V/s Tstd3 Settling time CL = 20 pF Only operational amplifier is activated *1 Tset2 Slew rate Tslew1 CL = 20 pF - 1.1 - V/s Load current Iload1 Low power mode -100 - 100 A Iload2 High-speed mode -100 - 100 A - - 20 pF Tslew2 Load capacitance Note 1. High-speed mode CL When the operational amplifier reference current circuit is activated in advance. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 118 of 137 S3A7 Datasheet 2.15 2. Electrical Characteristics Flash Memory Characteristics 2.15.1 Code Flash Memory Characteristics Table 2.76 Code flash characteristics (1) Parameter Symbol Min Typ Max Unit Test conditions Reprogramming/erasure cycle*1 NPEC 1000 - - Times - tDRP 20*2, *3 - - Year Ta = +85C Data hold time Note 1. Note 2. Note 3. After 1000 times of NPEC The reprogram/erase cycle is the number of erasure for each block. When the reprogram/erase cycle is n times (n = 1,000), erasing can be performed n times for each block. For instance, when 8-byte programming is performed 256 times for different addresses in 2-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming the same address for several times as one erasure is not enabled. (overwriting is prohibited). Characteristic when using the flash memory programmer and the self-programming library provided by Renesas Electronics. This result is obtained from reliability testing. Table 2.77 Code flash characteristics (2) High-speed operating mode Conditions: VCC = AVCC0 = 2.7 to 5.5 V FCLK = 1 MHz Parameter FCLK = 32 MHz Symbol Min Typ Max Min Typ Max Unit tP8 - 116 998 - 54 506 s Programming time 8-byte Erasure time 2-KB tE2K - 9.03 287 - 5.67 222 ms Blank check time 8-byte tBC8 - - 56.8 - - 16.6 s 2-KB tBC2K - - 1899 - - 140 s Erase suspended time tSED - - 22.5 - - 10.7 s Startup area switching setting time tSAS - 21.7 585 - 12.1 447 ms Access window time tAWS - 21.7 585 - 12.1 447 ms OCD/serial programmer ID setting time tOSIS - 21.7 585 - 12.1 447 ms Flash memory mode transition wait time 1 tDIS 2 - - 2 - - s Flash memory mode transition wait time 2 tMS 5 - - 5 - - s Note: Note: Note: Does not include the time until each operation of the flash memory is started after instructions are executed by the software. The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. The frequency accuracy of FCLK must be 3.5%. Confirm the frequency accuracy of the clock source. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 119 of 137 S3A7 Datasheet Table 2.78 2. Electrical Characteristics Code flash characteristics (3) Middle-speed operating mode Conditions: VCC = AVCC0 = 1.8 to 5.5 V, Ta = -40 to +85C FCLK = 1 MHz Parameter Symbol Min Typ FCLK = 8 MHz Max Min Typ Max Unit Programming time 8-byte tP8 - 157 1411 - 101 966 s Erasure time 2-KB tE2K - 9.10 289 - 6.10 228 ms Blank check time 8-byte tBC8 - - 87.7 - - 52.5 s tBC2K - - 1930 - - 414 s Erase suspended time 2-KB tSED - - 32.7 - - 21.6 s Startup area switching setting time tSAS - 22.5 592 - 14.0 464 ms Access window time tAWS - 22.5 592 - 14.0 464 ms OCD/serial programmer ID setting time tOSIS - 22.5 592 - 14.0 464 ms Flash memory mode transition wait time 1 tDIS 2 - - 2 - - s Flash memory mode transition wait time 2 tMS 720 - - 720 - - ns Note: Note: Note: Does not include the time until each operation of the flash memory is started after instructions are executed by the software. The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. The frequency accuracy of FCLK must be 3.5%. Confirm the frequency accuracy of the clock source. 2.15.2 Data Flash Memory Characteristics Table 2.79 Data flash characteristics (1) Parameter Reprogramming/erasure Data hold time cycle*1 After 10000 times of NDPEC Symbol Min Typ Max Unit Test conditions NDPEC 100,000 1,000,000 - Times - tDDRP 20*2, *3 - - Year Ta = +85C 5*2, *3 - - Year - 1*2, *3 - Year After 100000 times of NDPEC After 1000000 times of NDPEC Note 1. Note 2. Note 3. Ta = +25C The reprogram/erase cycle is the number of erasure for each block. When the reprogram/erase cycle is n times (n = 100,000), erasing can be performed n times for each block. For instance, when 1-byte programming is performed 1,000 times for different addresses in 1-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming the same address for several times as one erasure is not enabled. (overwriting is prohibited). Characteristics when using the flash memory programmer and the self-programming library provided by Renesas Electronics. These results are obtained from reliability testing. Table 2.80 Data flash characteristics (2) High-speed operating mode Conditions: VCC = AVCC0 = 2.7 to 5.5 V FCLK = 4 MHz Parameter FCLK = 32 MHz Symbol Min Typ Max Min Typ Max Unit Programming time 1-byte tDP1 - 52.4 463 - 42.1 387 s Erasure time 1-KB tDE1K - 8.98 286 - 6.42 237 ms Blank check time 1-byte tDBC1 - - 24.3 - - 16.6 s tDBC1K - - 1872 - - 512 s Suspended time during erasing 1-KB tDSED - - 13.0 - - 10.7 s Data flash STOP recovery time tDSTOP 5 - - 5 - - s Note 1. Note 2. Note 3. Does not include the time until each operation of the flash memory is started after instructions are executed by the software. The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. The frequency accuracy of FCLK must be 3.5%. Confirm the frequency accuracy of the clock source. R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 120 of 137 S3A7 Datasheet Table 2.81 2. Electrical Characteristics Data flash characteristics (3) Middle-speed operating mode Conditions: VCC = AVCC0 = 1.8 to 5.5 V, Ta = -40 to +85C FCLK = 4 MHz Parameter FCLK = 8 MHz Symbol Min Typ Max Min Typ Max Unit Programming time 1-byte tDP1 - 94.7 886 - 89.3 849 s Erasure time 1-KB tDE1K - 9.59 299 - 8.29 273 ms Blank check time 1-byte tDBC1 - - 56.2 - - 52.5 s tDBC1K - - 2.17 - - 1.51 ms Suspended time during erasing 1-KB tDSED - - 23.0 - - 21.7 s Data flash STOP recovery time tDSTOP 720 - - 720 - - ns Note 1. Note 2. Note 3. 2.16 Does not include the time until each operation of the flash memory is started after instructions are executed by the software. The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. The frequency accuracy of FCLK must be 3.5%. Confirm the frequency accuracy of the clock source. Boundary Scan Table 2.82 Boundary scan Conditions: VCC = AVCC0 = 2.4 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions TCK clock cycle time tTCKcyc 100 - - ns Figure 2.91 TCK clock high pulse width tTCKH 45 - - ns TCK clock low pulse width tTCKL 45 - - ns TCK clock rise time tTCKr - - 5 ns TCK clock fall time tTCKf - - 5 ns TMS setup time tTMSS 20 - - ns TMS hold time tTMSH 20 - - ns TDI setup time tTDIS 20 - - ns TDI hold time tTDIH 20 - - ns TDO data delay tTDOD - - 70 ns tBSSTUP tRESWP - - - Boundary Scan circuit start up Note 1. time*1 Figure 2.92 Figure 2.93 Boundary scan does not function until Power-On-Reset becomes negative. tTCKcyc tTCKH TCK tTCKf tTCKL Figure 2.91 tTCKr Boundary scan TCK timing R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 121 of 137 S3A7 Datasheet 2. Electrical Characteristics TCK tTMSS tTMSH t TDIS tTDIH TMS TDI tTDOD TDO Figure 2.92 Boundary scan input/output timing VCC RES tBSSTUP (= tRESWP) Figure 2.93 2.17 Boundary scan execute Boundary scan circuit start up timing Joint Test Action Group (JTAG) Table 2.83 JTAG (Debug) characteristics (1) Conditions: VCC = AVCC0 = 2.4 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions TCK clock cycle time tTCKcyc 80 - - ns Figure 2.94 TCK clock high pulse width tTCKH 35 - - ns TCK clock low pulse width tTCKL 35 - - ns TCK clock rise time tTCKr - - 5 ns TCK clock fall time tTCKf - - 5 ns TMS setup time tTMSS 16 - - ns TMS hold time tTMSH 16 - - ns TDI setup time tTDIS 16 - - ns TDI hold time tTDIH 16 - - ns TDO data delay time tTDOD - - 70 ns R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Figure 2.95 Page 122 of 137 S3A7 Datasheet Table 2.84 2. Electrical Characteristics JTAG (Debug) characteristics (2) Conditions: VCC = AVCC0 = 1.6 to 2.4 V Parameter Symbol Min Typ Max Unit Test conditions Figure 2.94 TCK clock cycle time tTCKcyc 250 - - ns TCK clock high pulse width tTCKH 120 - - ns TCK clock low pulse width tTCKL 120 - - ns TCK clock rise time tTCKr - - 5 ns TCK clock fall time tTCKf - - 5 ns TMS setup time tTMSS 50 - - ns TMS hold time tTMSH 50 - - ns TDI setup time tTDIS 50 - - ns TDI hold time tTDIH 50 - - ns TDO data delay time tTDOD - - 150 ns Figure 2.95 tTCKcyc tTCKH TCK tTCKf tTCKL Figure 2.94 tTCKr JTAG TCK timing TCK tTMSS tTMSH tTDIS tTDIH TMS TDI tTDOD TDO Figure 2.95 JTAG input/output timing R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 123 of 137 S3A7 Datasheet 2.17.1 Table 2.85 2. Electrical Characteristics Serial Wire Debug (SWD) SWD characteristics (1) Conditions: VCC = AVCC0 = 2.4 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time tSWCKcyc 80 - - ns Figure 2.96 SWCLK clock high pulse width tSWCKH 35 - - ns SWCLK clock low pulse width tSWCKL 35 - - ns SWCLK clock rise time tSWCKr - - 5 ns SWCLK clock fall time tSWCKf - - 5 ns SWDIO setup time tSWDS 16 - - ns SWDIO hold time tSWDH 16 - - ns SWDIO data delay time tSWDD 2 - 70 ns Table 2.86 Figure 2.97 SWD characteristics (2) Conditions: VCC = AVCC0 = 1.6 to 2.4 V Parameter Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time tSWCKcyc 250 - - ns Figure 2.96 SWCLK clock high pulse width tSWCKH 120 - - ns SWCLK clock low pulse width tSWCKL 120 - - ns SWCLK clock rise time tSWCKr - - 5 ns SWCLK clock fall time tSWCKf - - 5 ns SWDIO setup time tSWDS 50 - - ns SWDIO hold time tSWDH 50 - - ns SWDIO data delay time tSWDD 2 - 150 ns Figure 2.97 tSWCKcyc tSWCKH SWCLK tSWCKf tSWCKL Figure 2.96 tSWCKr SWD SWCLK timing R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 124 of 137 S3A7 Datasheet 2. Electrical Characteristics SWCLK tSWDS tSWDH SWDIO (Input) tSWDD SWDIO (Output) tSWDD SWDIO (Output) tSWDD SWDIO (Output) Figure 2.97 SWD input/output timing R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 125 of 137 S3A7 Datasheet Appendix 1. Package Dimensions Appendix 1.Package Dimensions Information on the latest version of the package dimensions or mountings is displayed in "Packages" on the Renesas Electronics Corporation website. JEITA Package Code P-TFLGA145-7x7-0.50 RENESAS Code PTLG0145KA-A Previous Code 145F0G MASS[Typ.] 0.1g w S B b1 D b w S A ZD A M S AB M S AB e A e N M L K J E H B G F E D C B x4 v Index mark (Laser mark) Figure 1.1 S ZE A y S 1 2 3 4 5 6 7 8 9 10 11 12 13 Reference Dimension in Millimeters Symbol Min D E v w A e b b1 x y ZD ZE Nom 7.0 7.0 Max 0.15 0.20 1.05 0.21 0.29 0.5 0.25 0.34 0.29 0.39 0.08 0.08 0.5 0.5 LGA 145-pin R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 126 of 137 S3A7 Datasheet Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS (Typ) [g] P-LFQFP144-20x20-0.50 PLQP0144KA-B -- 1.2 Unit: mm HD *1 D 108 73 *2 E 72 144 37 1 36 NOTE 4 Index area NOTE 3 F S *3 bp 0.25 A1 T c y S A2 A e Lp L1 Detail F Figure 1.2 HE 109 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. Reference Dimensions in millimeters Symbol M Min Nom Max D 19.9 20.0 20.1 20.1 E 19.9 20.0 A2 1.4 HD 21.8 22.0 22.2 HE 21.8 22.0 22.2 A 1.7 A1 0.05 0.15 bp 0.17 0.20 0.27 c 0.09 0.20 T 0q 3.5q 8q e 0.5 x 0.08 y 0.10 Lp 0.45 0.6 0.75 L1 1.0 LQFP 144-pin R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 127 of 137 S3A7 Datasheet Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS (Typ) [g] P-LFBGA121-8x8-0.65 PLBG0121JA-A -- 0.15 Unit: m w S A D A ZD ZE 11 10 9 8 7 6 5 4 3 2 1 B E L K J H G F E D C B A w S B INDEX MARK INDEX MARK A y1 A2 S S Reference Dimensions in millimet Symbol y e S Ib Figure 1.3 BGA 121-pin R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Ix M Min Nom M D 7.90 8.00 8. E 7.90 8.00 8. w -- 0.20 -- A1 S AB A 1.11 1.21 1.3 A1 0.25 0.30 0.3 A2 -- 0.91 -- 06 Page 128 of 137 S3A7 Datasheet Appendix 1. Package Dimensions JEITA Package Code P-TFLGA100-7x7-0.65 RENESAS Code PTLG0100JA-A Previous Code 100F0G MASS[Typ.] 0.1g w S B b1 D x M S b w S A ZD x M S AB e A e A AB K J H G B E F E D C B x4 y S v Index mark (Laser mark) Figure 1.4 S ZE A 1 2 3 Index mark 4 5 6 7 8 9 10 Reference Dimension in Millimeters Symbol Min Nom D 7.0 E 7.0 v w A e 0.65 b 0.31 0.35 b1 0.385 0.435 x y ZD 0.575 ZE 0.575 Max 0.15 0.20 1.05 0.39 0.485 0.08 0.10 LGA 100-pin R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 129 of 137 S3A7 Datasheet Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS (Typ) [g] P-LFQFP100-14x14-0.50 PLQP0100KB-B -- 0.6 HD Unit: mm *1 D 51 75 *2 E 50 100 HE 76 26 1 25 NOTE 4 Index area NOTE 3 F S y S *3 0.25 T A1 Lp L1 Detail F Reference Dimensions in millimeters Symbol bp M Min Nom Max D 13.9 14.0 14.1 14.1 E 13.9 14.0 A2 1.4 HD 15.8 16.0 16.2 HE 15.8 16.0 16.2 A 1.7 A1 0.05 0.15 bp 0.15 0.20 0.27 c 0.09 0.20 T 0q 3.5q 8q e 0.5 x 0.08 y 0.08 Lp 0.45 0.6 0.75 L1 1.0 c A2 A e NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. (c) 2015 Renesas Electronics Corporation. All rights reserved. Figure 1.5 LQFP 100-pin R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 130 of 137 S3A7 Datasheet Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS (Typ) [g] P-LFQFP64-10x10-0.50 PLQP0064KB-C -- 0.3 Unit: mm HD *1 D 48 33 64 HE 32 *2 E 49 17 1 16 NOTE 4 Index area NOTE 3 F S y S *3 bp 0.25 c A1 T A2 A e Lp L1 Detail F M NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. Reference Dimensions in millimeters Symbol Min Nom Max D 9.9 10.0 10.1 10.1 E 9.9 10.0 A2 1.4 HD 11.8 12.0 12.2 HE 11.8 12.0 12.2 A 1.7 A1 0.05 0.15 bp 0.15 0.20 0.27 c 0.09 0.20 T 0q 3.5q 8q e 0.5 x 0.08 y 0.08 Lp 0.45 0.6 0.75 L1 1.0 (c) 2015 Renesas Electronics Corporation. All rights reserved. Figure 1.6 LQFP 64-pin R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 131 of 137 S3A7 Datasheet Appendix 1. Package Dimensions JEITA Package code P-HWQFN64-8x8-0.40 RENESAS code Previous code MASS(TYP.)[g] PWQN0064LA-A P64K8-40-9B5-3 0.16 D 33 48 DETAIL OF A PART 32 49 E A A1 17 64 c2 16 1 INDEX AREA A S y S Referance Symbol D2 A Lp EXPOSED DIE PAD 16 1 64 17 Dimension in Millimeters Min Nom Max D 7.95 8.00 8.05 E 7.95 8.00 8.05 A 0.80 A1 0.00 b 0.17 e Lp B E2 32 49 0.30 33 ZD e b x M 0.40 0.50 x 0.05 y 0.05 1.00 ZE c2 48 0.23 0.40 ZD ZE 0.20 1.00 0.15 0.20 D2 6.50 E2 6.50 0.25 S AB 2013 Renesas Electronics Corporation. All rights reserved. Figure 1.7 QFN 64-pin R01DS0263EU0140 Rev.1.40 Oct 29, 2018 Page 132 of 137 Revision History Rev. Date 1.00 Feb 23, 2016 S3A7 Microcontroller Group Datasheet Summary 1st release 1.30 Feb 7, 2018 2nd release 1.40 Oct 29, 2018 3rd release Website and Support Visit the following vanity URLs to learn about key elements of the Synergy Platform, download components and related documentation, and get support. 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Except as expressly provided herein, no part of this document or content may be copied, reproduced, republished, posted, publicly displayed, encoded, translated, transmitted or distributed in any other medium for publication or distribution or for any commercial enterprise, without prior written consent from Renesas. Arm(R) and Cortex(R) are registered trademarks of Arm Limited. CoreSightTM is a trademark of Arm Limited. CoreMark(R) is a registered trademark of the Embedded Microprocessor Benchmark Consortium. Magic PacketTM is a trademark of Advanced Micro Devices, Inc. SuperFlash(R) is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Other brands and names mentioned in this document may be the trademarks or registered trademarks of their respective holders. Colophon S3A7 Microcontroller Group Datasheet Publication Date: Rev.1.40 Oct 29, 2018 Published by: Renesas Electronics Corporation Address List General Precautions 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during poweroff state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-evaluation test for the given product. Notice 1. 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"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; industrial robots; etc. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc. Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user's manual or other Renesas Electronics document. 6. When using Renesas Electronics products, refer to the latest product information (data sheets, user's manuals, application notes, "General Notes for Handling and Using Semiconductor Devices" in the reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified ranges. 7. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you. 8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. You are responsible for carefully and sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You shall comply with any applicable export control laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or transactions. 10. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or transfers the product to a third party, to notify such third party in advance of the contents and conditions set forth in this document. 11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. (Rev.4.0-1 November 2017) http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics Corporation TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan Renesas Electronics America Inc. 1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A. Tel: +1-408-432-8888, Fax: +1-408-434-5351 Renesas Electronics Canada Limited 9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3 Tel: +1-905-237-2004 Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K Tel: +44-1628-651-700 Renesas Electronics Europe GmbH Arcadiastrasse 10, 40472 Dusseldorf, Germany Tel: +49-211-6503-0, Fax: +49-211-6503-1327 Renesas Electronics (China) Co., Ltd. Room 1709 Quantum Plaza, No.27 ZhichunLu, Haidian District, Beijing, 100191 P. R. China Tel: +86-10-8235-1155, Fax: +86-10-8235-7679 Renesas Electronics (Shanghai) Co., Ltd. Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, 200333 P. R. China Tel: +86-21-2226-0888, Fax: +86-21-2226-0999 Renesas Electronics Hong Kong Limited Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong Tel: +852-2265-6688, Fax: +852 2886-9022 Renesas Electronics Taiwan Co., Ltd. 13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan Tel: +886-2-8175-9600, Fax: +886 2-8175-9670 Renesas Electronics Singapore Pte. Ltd. 80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949 Tel: +65-6213-0200, Fax: +65-6213-0300 Renesas Electronics Malaysia Sdn.Bhd. Unit 1207, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: +60-3-7955-9390, Fax: +60-3-7955-9510 Renesas Electronics India Pvt. Ltd. No.777C, 100 Feet Road, HAL 2nd Stage, Indiranagar, Bangalore 560 038, India Tel: +91-80-67208700, Fax: +91-80-67208777 Renesas Electronics Korea Co., Ltd. 17F, KAMCO Yangjae Tower, 262, Gangnam-daero, Gangnam-gu, Seoul, 06265 Korea Tel: +82-2-558-3737, Fax: +82-2-558-5338 (c) 2018 Renesas Electronics Corporation. All rights reserved. Colophon 7.2 Back cover Renesas SynergyTM Platform S3A7 Microcontroller Group R01DS0263EU0140