August 3, 2004 © Cypress MicroSystems, Inc. 2002 – 2004 — Document No. 38-12012 Rev. *I 1
PSoC™ Mixed Signal Array Final Dat a Sheet
CY8C27143, CY8C27243,
CY8C27443, CY8C27543, and CY8C27643
PSoC™ Functional Overview
The PSoC™ family consists of many Mixed Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of conve-
nient pinouts and packages.
The PSoC a rchi tec ture, as il lus trat ed on th e l ef t, is com pri se d of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system. The PSoC CY8C27x43 family can have up to five IO
port s that c onnec t to the gl obal di git al and a nalog i ntercon nect s,
providing access to 8 digital blocks and 12 analog blocks.
The PSoC Core
The PSoC Core is a powerful engine that supports a rich fea-
ture se t . Th e co re in cl ud es a C PU , memo r y, clock s, an d c on f ig -
urable GPIO (General Purpo se IO).
The M8C CP U core is a po werful proce ssor with speeds up to
24 MHz, providi ng a four MI PS 8-bit Harvard arc hitect ure mic ro-
Features
■Powerful Harvard Architecture Processor
❐M8C Processor Speeds to 24 MHz
❐8x8 Multiply, 32-Bit Accumulate
❐Low Power at High S peed
❐3.0 to 5.25 V Operat i ng Voltage
❐Operating Voltages Down to 1.0V Using On-
Chip Switch Mode Pump (SMP)
❐Industrial Temperature Range: -40°C to +85°C
■Advanced Peripherals (PSoC Blocks)
❐12 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
❐8 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Up to 2 Full-Duplex UARTs
- Multiple SPI™ Masters or Slaves
- Connectable to all GPIO Pins
❐Complex Peripherals by Combining Blocks
■Precis ion, Programmable Clocking
❐Internal 2.5% 24/48 MHz Oscillator
❐24/48 MHz with Optional 32 kHz Crystal
❐Optional External Oscillator, up to 24 MHz
❐Internal Oscillator for Watchdog and Sleep
■Flexible On-Chip Memory
❐16K Bytes Flash Program Storage 50,000
Erase/ Write Cycles
❐256 Bytes SRAM Data Storage
❐In-System Serial Programming (ISSP™)
❐Partial Flash Updates
❐Flexible Protection Modes
❐EEPROM Emulation in Flash
■Programmable Pin Configurations
❐25 mA Sink on all GPIO
❐Pull up, Pull down, H igh Z, Strong, or Open
Drain Dri ve Modes on all GPIO
❐Up to 12 Analog Inputs on GPIO
❐Four 30 mA Analog Outputs on GPIO
❐Configurable Interrupt on all GPIO
■Additional System Resources
❐I2C™ Slave, Master, and Multi-Master to
400 kHz
❐Watchdog and Sleep Timers
❐User-Configurable Low Voltage Detection
❐Integrated Supervisory Circuit
❐On-Chip Precision Voltage Reference
■Complete Development Tools
❐Free Development Software
(PSoC™ Designer)
❐Full-Featured, In-Circuit Emulator and
Programmer
❐Full Speed Emulation
❐Complex Breakpoint Structure
❐128K Bytes Trace Memory
DIGITAL SYST EM
SRAM
256 Bytes
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
Global Dig it al Inte rco nnect Global Ana lo g Int erc onnect
PSoC
CORE
CPU Core (M8C)
SROM Flash 16K
Digital
Block
Array
Multiply
Accum.
Switch
Mode
Pump
Internal
Voltage
Ref.
Digital
Clocks
POR and LVD
System R esets
Decimator
SYSTE M R ESO URCES
ANALOG SYSTEM
Analog
Ref
Analog
Input
Muxing
I C
2
(2 Rows,
8 Blo c ks)
Port 4 Port 3 Port 2 Port 1 Port 0 Analog
Drivers
System Bus
Analog
Block
Array
(4 Colu mns,
12 Blocks)
Port 5
August 3, 2004 Document No. 38-12012 Rev. *I 2
CY8C27x43 Final Data Sheet PSoC™ Over view
processor. The CPU utilizes an interrupt controller with 17 vec-
tors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory e nc om p as s es 16 KB of Flas h f or pro gra m s t ora ge , 25 6
bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the Flash. Program Flash utilizes four protec-
tion levels on blocks of 64 bytes, allowing customized software
IP protection.
The PSoC device incorporates flexible internal clock genera-
tors, including a 24 MHz IMO (internal main oscillator) accurate
to 2.5% over temperature and voltage. The 24 MHz IMO can
also be doubled to 48 MHz for use by the digital system. A low
power 32 kHz ILO (internal low speed oscillator) is provided for
the Sleep timer and WDT. If crystal accuracy is desired, the
ECO (32.768 kHz external crystal oscillator) is available for use
as a Real T ime Clock (R T C) and can optiona lly ge nerat e a crys -
tal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the P SoC device.
PSoC GPIO s pro vid e co nne ct ion to the CPU, di gital an d ana lo g
resour ces of th e devi ce. Each pin’ s dri ve mod e may b e selec ted
from eight options, allowing great flexibility in external interfac-
ing. Every pin al so has the c apa bility to gen erate a syste m inter-
rupt on high level, low level, and change from last read.
The Digital System
The Digital System is composed of 8 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other b lock s to form 8 , 16, 2 4, and 32-bit p eriphe rals, wh ich
are called user module references.
Digital System Block Diagram
Digital peripheral configurations include those listed below.
■PWMs (8 to 32 bit)
■PWMs with Dead band (8 to 32 bit)
■Counters (8 to 32 bit)
■Timers (8 to 32 bit)
■UART 8 bit with selectable parity (up to 2)
■SPI master and slave (up to 2)
■I2C slave and master (1 available as a System Resource)
■Cyclical R edundancy Checker/Gener ator ( 8 to 32 bit)
■IrDA (up to 2)
■Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operat ion s. Th is configura bil ity free s y our d esigns fro m th e co n-
straints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the opti-
mum choice of system resources for your application. Family
resources are shown in the table titled “PSoC Device Charac-
teristics” on page 3.
The Analog System
The Analog System is composed of 12 configurable blocks,
each comprised of an opamp circuit allowing the creation of
complex analog signal flows. Analog peripherals are very flexi-
ble and can be customized to support specific application
requirements. Some of the more common PSoC analog func-
tions (most available as user modules) are listed below.
■Analog-to-digital converters (up to 4, with 6- to 14-bit resolu-
tion, selec t ab le as Inc r emental, Delta Sigma, and SAR)
■Filters (2, 4, 6, and 8 pole band-pass, low-pass, and notch)
■Amplifiers (up to 4, with selectable gain to 48x)
■Instrumentation amplifiers (up to 2, with selectable gain to
93x)
■Comparators (up to 4, with 16 selectable thresholds)
■DACs (up to 4, with 6- to 9-bit resolution)
■Multiplying DACs (up to 4, with 6- to 9-bit resolution)
■High current output dr ivers (four with 30 mA drive as a Core
Resource)
■1.3V reference (as a System Resourc e)
■DTMF dialer
■Modulators
■Correlators
■Peak detectors
■Many other topologies possible
DIGITA L SYSTEM
To System Bus
Digital Clocks
From Core
Digit al PSoC Block Array
To An alog
System
8
Row Input
Configuration
Row Output
Configuration
88
8
Row 1
DBB10 DBB11 DCB12 DCB13
Row Input
Configuration
4
4
Row Output
Configuration
Row 0
DBB00 DBB01 DCB02 DCB03
4
4
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
Port 4 Port 3 Port 2 Port 1 Port 0Port 5
August 3, 2004 Document No. 38-12012 Rev. *I 3
CY8C27x43 Final Data Sheet PSoC™ Over view
Analog blocks are provided in columns of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in the figure below.
Analog System Block Diagram
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems. Addi-
tional resources include a multiplier, decimator, switch mode
pump, low voltage detection, and power on reset. Brief state-
ments describing the merits of each system resource are pre-
sen ted below.
■Digital clock dividers provide three customizable clock fre-
quencie s for use in applic ations . The clo cks can be route d to
both the di git al and ana log syste ms. Additiona l clock s can be
generated using digital PSoC blocks as clock dividers.
■A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bi t acc umula te, to assi st in both genera l math as well
as digital filters.
■The decimator provides a custom hardware filter for digital
signal process ing applications inc luding t he c reati on of Delta
Sigma ADCs.
■The I2C module provides 100 and 400 kHz communication
over two wires. Slave, master, and multi-master modes are
all supported.
■Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, w hile the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■An interna l 1.3V referenc e provides an absolute re ference for
the analog system, including ADCs and DACs.
■An integrated sw it ch mode pum p (S MP) gene rate s norm al
operating volt ages f rom a single 1.2V b attery c ell, provi ding a
low cost boo st con ve r ter.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
3 analog blocks. The following table lists the resources
available for specific PSoC device groups. The PSoC device
covered by this data sheet is shown in the second row of the
table.
ACB00 ACB01
Block Array
Array Inpu t Configuration
ACI1[1:0] ACI2[1:0]
ACB02 ACB03
ASC12 ASD13
ASD22 ASC23ASD20
ACI0[1:0] ACI3[1:0]
P0[6]
P0[4]
P0[2]
P0[0]
P2[2]
P2[0]
P2[6]
P2[4]
RefIn
AGNDIn
P0[7]
P0[5]
P0[3]
P0[1]
P2[3]
P2[1]
Reference
Generators AGNDIn
RefIn
Bandga
p
RefHi
RefLo
AGND
ASD11
ASC21
ASC10
Interface to
Digital System
M8C Interface (Address Bus, Data Bus, Etc.)
Analog Referenc e
PSoC Device Characteristics
PSoC Part
Number
Digital
IO
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
CY8C29x66 up to
64 416 12 4 4 12
CY8C27x43 up t o
44 2 8 12 4 4 12
CY8C24x23 up to
24 1 4 12 226
CY8C24x23A up to
24 1 4 12 226
CY8C22x13 up to
16 148113
August 3, 2004 Document No. 38-12012 Rev. *I 4
CY8C27x43 Final Data Sheet PSoC™ Over view
Getting Started
The quick es t p a t h to und ers t an din g the PSoC sili co n is by rea d-
ing this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an over-
view of the PSoC integrated circuit and presents specific pin,
register, and electrical specifications. For in-depth information,
along with detailed programming information, reference the
PSoC™ Mixed Signal Array Technical Reference Manual.
For up-to- date Or dering, Packag ing, an d Electri cal Specificatio n
information, reference the latest PSoC device data sheets on
the web at http://www.cypress.com/psoc.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
at http://www.onfulfillment.com/cypressstore/ contains develop-
ment kits, C compilers, and all accessories for PSoC develop-
ment. Click on PSoC (Programmable System-on-Chip) to view
a current list of available items.
Tele-Training
Free PSoC "Tele-training" is available for beginners and taught
by a live m ark etin g or ap pli ca tio n eng in eer ov er th e pho ne. Five
training classes are available to accelerate the learning curve
including introduction, designing, debugging, advanced design,
advanced analog, as well as application-specific classes cover-
ing topics like PSoC and the LIN bus. For days and times of the
tele-training, see http://www.cypress.com/support/training.cfm.
Consultants
Certified PSoC Consultants offer everything from technical
assist anc e to com plete d PSoC d esign s. To contac t or beco me a
PSoC Consultant, go to the following Cypress support web site:
http://www.cypress.com/support/cypros.cfm.
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at http://www.cypress.com/support/login.cfm.
Application Notes
A long list of application notes will assist you in every aspect of
your design effort. To locate the PSoC application notes, go to
http://www.cypress.com/design/results.cfm.
Development To ols
The Cypress MicroSystems PSoC Designer is a Microsoft®
Windows-based, integrated development environment for the
Programmable System-on-Chip (PSoC) devices. The PSoC
Designer IDE and application runs on Windows NT 4.0, Win-
dows 2000, Windows Millennium (Me), or Windows XP. (Refer-
ence the PSoC Designer Functional Flow diagram below.)
PSoC Designer helps the customer to select an operating con-
figuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro as sembler for the CPUs.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
PSoC Designer Subsystems
Commands
Results
PSoCTM
Designer
Core
Engine
PSoC
Configuration
Sheet
Manufacturing
Information
File
Device
Database
Importable
Design
Database
Device
Programmer
Graphical Designer
Interface Context
Sensitive
Help
Emulation
Pod In-Circuit
Emulator
Project
Database
Application
Database
User
Modules
Library
PSoCTM
Designer
August 3, 2004 Document No. 38-12012 Rev. *I 5
CY8C27x43 Final Data Sheet PSoC™ Over view
PSoC Designer Software Subsystems
Device Editor
The De vice Edit or sub syst em allo ws th e user to sele ct di ffere nt
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic configu-
ration allows for changing configurations at run time.
PSoC Designer sets up power-on initialization tables for
selected PSoC block configurations and creates source code
for an appl ica tio n fr amew ork. Th e f ram ewor k co ntai ns s oftwar e
to operate the selected components and, if the project uses
more than one operating configuration, contains routines to
switch between different sets of PSoC block configurations at
run t im e. PS o C D esigne r c a n pr i nt ou t a co n fig ur a t ion s he et fo r
a given project configuration for use during application pro-
gram ming in co nju nct ion with t he De vice Data Sh eet . Once the
framework is generated, the user can add application-specific
code to flesh out the framework. It’s also possible to change the
selecte d com pon ents and regenera te the fram ew or k.
Design Browser
The Design Browser allows users to select and import precon-
figu r e d desi g ns int o the u se r’s pro je ct . Use r s can ea s il y br o wse
a catalog of preconfigured designs to facilitate time-to-design.
Examples pro vid ed in the tool s i ncl ud e a 30 0-baud mod em, LIN
Bus master and slave, fan controller, and magnetic card reader.
Applicati on Ed itor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble, com-
pile, link, and build.
Assembler. The macro assembler allows the assembly code
to be merged seamlessly with C code. The link libraries auto-
matical ly us e abso lute a ddre ssing or ca n be co mpil ed in re lativ e
mode, and linked with other software modules to get absolute
addressing.
C Language Compiler. A C language compiler is available
that supports Cypress MicroSystems’ PSoC family devices.
Even if you have never worked in the C language before, the
product quickly allows you to create complete C programs for
the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a phys ical system while provi ding an i nter nal vie w of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the des ig ner in gett ing started.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is avail-
able for development support. This hardware has the capability
to program sing le dev ic es .
The emula tor cons ist s of a base un it that co nne cts to th e PC by
way of the parallel or USB port. The base unit is universal and
will operate with all PSoC devices. Emulation pods for each
device famil y are a vaila ble s epa rate ly. The emulatio n p od t akes
the place of the PSoC device in the target board and performs
full speed (24 MHz) operation.
August 3, 2004 Document No. 38-12012 Rev. *I 6
CY8C27x43 Final Data Sheet PSoC™ Over view
Designing with User Modules
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
anal og and digital hardware blocks give the PSoC architecture
a unique flexibil ity tha t p ays divi dends in mana ging s pecifi catio n
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its function and
connectivity to other blocks, multiplexers, buses, and to the IO
pins. I tera tiv e de vel op men t cy cl es perm it y ou to ada pt th e hard-
ware as well as the software. This substantially lowers the risk
that you will have to select a different part to meet the final
design requirements.
To speed the development process, the PSoC Designer Inte-
grated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library con-
tains over 50 common peripherals such as ADCs, DACs Tim-
ers, Counters, UARTs, and other not-so common peripherals
such as DTMF Generators and Bi-Quad analog filter sections.
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters
that allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Mod-
ule configures one or more digital PSoC blocks, one for each 8
bits of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides high-
level functions to control and respond to hardware events at
run-time. The API also provides optional interrupt service rou-
tines that you can adapt as needed.
The API functions are documented in user module data sheets
that are vie wed d irec tl y in the PSo C D esi gn er IDE. Th es e data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the set-
ting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. You pick the user modules you
need for your project and map them onto the PSoC blocks with
poin t-an d-c lic k simp lic ity. Next, you b uil d si gnal ch ain s by int er-
connecting user modules to each other and the IO pins. At this
stage, you also configure the clock source connections and
enter parameter values directly or by selecting values from
drop-down menus. When you are ready to test the hardware
configura tio n or move on to develo ping co de for the proj ect, yo u
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
the device to your specification and provides the high-level user
module API functions.
User Module and Source Code Development Flows
The next step is to write your main program, and any sub-rou-
tines using PSoC Designer’s Application Editor subsystem.
The Application Editor includes a Project Manager that allows
you to open the project source code files (including all gener-
ated code files) from a hierarchal view. The source code editor
provides syntax coloring and advanced edit features for both C
and assembly language. File search capabilities include simple
string searches and recursive “grep-style” patterns. A single
mouse click invokes the Build Manager. It employs a profes-
sional-strength “makefile” system to automatically analyze all
file dependencies and run the compiler and assembler as nec-
essary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in
a console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
The last ste p in the developm ent proces s t ak es pla ce insi de the
PSoC Designer’s Debugger subsystem. The Debugger down-
loads the HEX image to the In-Circuit Emulator (ICE) where it
runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoi nt ev ents that inc lu de m oni tori ng ad dres s and da ta bus
values, memory locations and external signals.
Debugger
Interface
to ICE
Application Editor
Device Editor
Project
Manager
Source
Code
Editor
Storage
Inspector
User
Module
Selection
Placement
and
Parameter
-ization
Generate
Application
Build
All
Event &
Breakpoint
Manager
Build
Manager
Source
Code
Generator
August 3, 2004 Document No. 38-12012 Rev. *I 7
CY8C27x43 Final Data Sheet PSoC™ Over view
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this doc-
ument.
Units of Measure
A units of measure table is located in the Electrical Specifica-
tions section. Table 3-1 on page 17 lists all the abbreviations
used to measure the PSoC devices.
Numeric Naming
Hexidecimal numbers are represented with all letters in upper-
case with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah ’ ). H e xi dec im al nu mb ers m ay al so be re pr es en t ed by a ‘0 x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’ or ‘b’ are decimal.
Table of Contents
For an in depth discussion and more information on your PSoC
device, obtain the PSoC Mixed Signal Array Technical Refer-
ence Manual. This document encompasses and is organized
into the following chapters and sections.
1. Pin Information ............. ..... ...... ...... ................ ...... ...... ... 8
1.1 Pinouts ................................................................... 8
1.1.1 8-Pin Part Pinout ................................ ............. ....8
1.1.2 20-Pin Part Pinout ........................ .... .... ......... .... ..9
1.1.3 28-Pin Part Pinout ........................ .... .... ......... ....10
1.1.4 44-Pin Part Pinout ........................ .... .... ......... ....11
1.1.5 48-Pin Part Pinouts ...........................................12
2. Register Reference ..................................................... 14
2.1 Register Conventions ........................................... 14
2.2 Register Mapping Tables ..................................... 14
3. Electrical Specifications ............................................ 17
3.1 Absolute Ma xi mu m Rating s ........ ................. ...... . 18
3.2 Operating Temperature ....................................... 18
3.3 DC Electrical Characteristics ................................ 19
3.3.1 DC Chip-Level Specifications .............................19
3.3.2 DC General Purpose IO Specifications ..............19
3.3.3 DC Operational Amplifier Specifications ............20
3.3.4 DC Analog Output Buffer Specifications ............22
3.3.5 DC Switch Mode Pump Specifications ...............23
3.3.6 DC Analog Reference Specifications .................24
3.3.7 DC Analog PSoC Block Specifications ...............26
3.3.8 DC POR and LVD Specifications .......................26
3.3.9 DC Programming Specifications ........................27
3.4 AC Electrical Characteristics ................................ 28
3.4.1 AC Chip- L e vel Sp e c ifications .............................28
3.4.2 AC General Purpose IO Specifications ..............30
3.4.3 AC Operational Amplifier Specifications .............31
3.4.4 AC Digital Block Specifications ....... .. .. .... ..... .... ..32
3.4.5 AC Analog Output Buffer Specifications ............. 33
3.4.6 AC External Clock Specification s .......................34
3.4.7 AC Pr og ramming Spec ifications ........ ............. ....34
3.4.8 AC I2C Sp e c ification s .................... ............. ........3 5
4. Packaging Information ............................................... 36
4.1 Packaging Dimensions ......................................... 36
4.2 Thermal Impedances .......................................... 41
4.3 Capacitance on Crystal Pins ............................... 41
5. Ordering Information .................................................. 42
5.1 Ordering Code Definitions ................................... 43
6. Sales and Service Information .................................. 44
6.1 Revision History ................................................... 44
6.2 Copyrights and Code Protection .......................... 44
Acronym Description
AC alternating current
ADC analog-to-digital converter
API application programming interface
CPU central processing unit
CT continuous time
DAC digital- to-analog converter
DC direct current
ECO external crystal oscillator
EEPROM electrically erasable programmable read-only memory
FSR full scale range
GPIO general purpose IO
GUI graphical user interface
HBM human bod y model
ICE in-circuit emulator
ILO internal low speed oscillator
IMO internal main oscillator
IO input/output
IPOR imprecise power on reset
LSb least-significant bit
LVD low voltage detect
MSb most-significant bit
PC program counter
PLL phase-locked loop
POR pow er on r e set
PPOR precisio n power on re set
PSoC™ Programmable System-on-Chip™
PWM pulse width modulator
RAM random access memory
SC switched capacitor
SLIMO slow IMO
SMP switch mode pump
August 3, 2004 Document No. 38-12012 Rev. *I 8
1. Pin Information
This chapter describes, lists, and illustrates the CY8C27x43 PSoC device pins and pinout configurations.
1.1 Pinouts
The CY8C27x43 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled w ith a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, an d XRES are not capable of Digital IO.
1.1.1 8-Pin Part Pinout
Table 1-1. 8-Pin Part Pinout (PDIP)
Pin
No. Type Pin
Name Description CY8C27143 8-Pin PSoC Device
Digital Analog
1IO IO P0[5] Analog column mux input and column output.
2IO IO P0[3] Analog column mux input and column output.
3IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL)
4Power Vss Ground connection.
5IO P1[0] Crystal Output (XTALout), I2C Serial Data
(SDA)
6IO IO P0[2] Analog column mux input and column output.
7IO IO P0[4] Analog column mux input and column output.
8Power Vdd Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
PDIP
1
2
3
4
AIO, P0[5]
AIO, P0[3]
I2C SCL, XTALin, P1[1]
Vss
8
7
6
5
Vdd
P0[4], AIO
P0[2], AIO
P1[0 ], XTAL ou t, I2C SD
A
August 3, 2004 Document No. 38-12012 Rev. *I 9
CY8C27x43 Final Data Sheet 1. Pin Information
1.1.2 20-Pin Part Pinout
Table 1-2. 20-Pin Part Pinout (SSOP, SOIC)
Pin
No. Type Pin
Name Description CY8C27243 20-Pin PSoC Device
Digital Analog
1IO I P0[7] Anal og col um n mux inpu t.
2IO IO P0[5] Analog colum n mux inpu t and colum n outp ut.
3IO IO P0[3] Analog colum n mux inpu t and colum n outp ut.
4IO I P0[1] Anal og col um n mux inpu t.
5Power SMP Switch Mode Pump (SMP) connection to
exter nal com pon ents required.
6IO P1[7] I2C Serial Clock (SCL)
7IO P1[5] I2C Serial Data (SDA)
8IO P1[3]
9IO P1[1] Crystal Input (XT ALin), I2C Serial Clock (SCL)
10 Power Vss Ground conn ection.
11 IO P1[0] Crystal Output (XTALout), I2C Serial Data
(SDA)
12 IO P1[2]
13 IO P1[4] Optional External Clock Input (EXTCLK)
14 IO P1[6]
15 Input XRES Active high external reset with internal pull
down.
16 IO I P0[0] Anal og col um n mux inpu t.
17 IO IO P0[2] Analog colum n mux inpu t and colum n outp ut.
18 IO IO P0[4] Analog colum n mux inpu t and colum n outp ut.
19 IO I P0[6] Anal og col um n mux inpu t.
20 Power Vdd Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
SSOP
SOIC
Vdd
P0[6], AI
P0[4], AIO
P0[2], AIO
P0[0], AI
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SD
A
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
August 3, 2004 Document No. 38-12012 Rev. *I 10
CY8C27x43 Final Data Sheet 1. Pin Information
1.1.3 28-Pin Part Pinout
Table 1-3. 28-Pin Part Pinout (PDIP, SSOP, SOIC)
Pin
No. Type Pin
Name Description CY8C27443 28-Pin PSoC Device
Digital Analog
1IO I P0[7] Analog column mux input.
2IO IO P0[5] Analog column mux input and column output.
3IO IO P0[3] Analog column mux input and column output.
4IO I P0[1] Analog column mux input.
5IO P2[7]
6IO P2[5]
7IO I P2[3] Direct switched capacitor block input.
8IO I P2[1] Direct switched capacitor block input.
9Power SMP Swi tch Mode Pump (SMP) connec tion to
external components required.
10 IO P1[7] I2C Serial Clock (SCL)
11 IO P1[5] I2C Serial Data (SDA)
12 IO P1[3]
13 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL)
14 Power Vss Ground connection.
15 IO P1[0] Crystal Output (XTALou t), I2C Serial Data
(SDA)
16 IO P1[2]
17 IO P1[4] Optiona l External Clock Input (EXTCLK)
18 IO P1[6]
19 Input XRES Active high external reset with internal pull
down.
20 IO I P2[0] Direct switched capacitor block input.
21 IO I P2[2] Direct switched capacitor block input.
22 IO P2[4] External Analog Ground (AGND)
23 IO P2[6] External Voltage Reference (VRef)
24 IO I P0[0] Analog column mux input.
25 IO IO P0[2] Analog column mux input and column output.
26 IO IO P0[4] Analog column mux input and column output.
27 IO I P0[6] Analog column mux input.
28 Power Vdd Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
P2[7]
P2[5]
AI, P2[3]
AI, P2[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
Vdd
P0[6], AI
P0[4], AIO
P0[2], AIO
P0[0], AI
P2[6], External VRef
P2[4], External AGND
P2[2], AI
P2[0], AI
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SD
A
PDIP
SSOP
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
August 3, 2004 Document No. 38-12012 Rev. *I 11
CY8C27x43 Final Data Sheet 1. Pin Information
1.1.4 44-Pin Part Pinout
Table 1-4. 44-Pin Part Pinout (TQFP)
Pin
No. Type Pin
Name Description CY8C27543 44-Pin PSoC Device
Digital Analog
1IO P2[5]
2IO I P2[3] Direct switched capacitor block input.
3IO I P2[1] Direct switched capacitor block input.
4IO P4[7]
5IO P4[5]
6IO P4[3]
7IO P4[1]
8Power SMP Switch Mode Pump (SMP) connection to
exter na l compon ents required.
9IO P3[7]
10 IO P3[5]
11 IO P3[3]
12 IO P3[1]
13 IO P1[7] I2C Serial Clock (SCL)
14 IO P1[5] I2C Serial Data (SDA)
15 IO P1[3]
16 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL)
17 Power Vss Ground connection.
18 IO P1[0] Crystal Output (XTALout), I2C Serial Data
(SDA)
19 IO P1[2]
20 IO P1[4] Optional External Clock Input (EXTCLK)
21 IO P1[6]
22 IO P3[0]
23 IO P3[2]
24 IO P3[4]
25 IO P3[6]
26 Input XRES Active high external reset with internal pull
down.
27 IO P4[0]
28 IO P4[2]
29 IO P4[4]
30 IO P4[6]
31 IO I P2[0] Direct switched capacitor block input.
32 IO I P2[2] Direct switched capacitor block input.
33 IO P2[4] External Anal og Ground (AGND )
34 IO P2[6] External Volt age Re feren ce (VRef)
35 IO I P0[0] Analog column mux input.
36 IO IO P0[2] Analog column mux input and column ou tput.
37 IO IO P0[4] Analog column mux input and column ou tput.
38 IO I P0[6] Analog column mux input.
39 Power Vdd Supply vol tage .
40 IO I P0[7] Analog column mux input.
41 IO IO P0[5] Analog column mux input and column ou tput.
42 IO IO P0[3] Analog column mux input and column ou tput.
43 IO I P0[1] Analog column mux input.
44 IO P2[7]
LEGEND: A = Analog, I = Input, and O = Output.
TQFP
P3[1] P2[7]
P2[5] P2[4], External AGN
D
A
I, P2[3] P2[2], AI
A
I, P2[1] P2[0], AI
P4[7] P4[6]
P4[5] P4[4]
P4[3] P4[2]
P4[1] P4[0]
SMP XRES
P3[7] P3[6]
P3[5] P3[4]
P3[3] P3[2]
I2C S CL, P 1 [7] P0[1], AI
I2C SDA, P1[5] P0[3], AIO
P1[3] P0[5], AIO
I2C S CL, X TALin, P1[ 1] P0[7], AI
Vss Vdd
I2C SDA, XTALout, P1[0] P0[6], AI
P1[2] P0[4], AIO
EXTCLK, P1[4] P0[2], AIO
P1[6] P0[0], AI
P3[0] P2[ 6], External VRe
f
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
44
43
42
41
40
39
38
37
36
35
34
13
14
15
16
17
18
19
20
21
22
12
August 3, 2004 Document No. 38-12012 Rev. *I 12
CY8C27x43 Final Data Sheet 1. Pin Information
1.1.5 48-Pin Part Pinouts
Table 1-5. 48-Pin Part Pinout (SSOP)
Pin
No. Type Pin
Name Description CY8C27643 48-Pin PSoC Device
Digital Analog
1IO I P0[7] A nalog column mux input.
2IO IO P0[5] Analog column mux input and column output.
3IO IO P0[3] Analog column mux input and column output.
4IO I P0[1] A nalog column mux input.
5IO P2[7]
6IO P2[5]
7IO I P2[3] Direct switched capacitor block input.
8IO I P2[1] Direct switched capacitor block input.
9IO P4[7]
10 IO P4[5]
11 IO P4[3]
12 IO P4[1]
13 Power SMP Switch Mode Pump (SMP) connection to
ext ernal components requir ed.
14 IO P3[7]
15 IO P3[5]
16 IO P3[3]
17 IO P3[1]
18 IO P5[3]
19 IO P5[1]
20 IO P1[7] I2C Serial Clock (SCL)
21 IO P1[5] I2C Serial Data (SDA)
22 IO P1[3]
23 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL)
24 Pow er Vss Ground connection.
25 IO P1[0] Crystal Output (XTALout), I2C Serial Data
(SDA)
26 IO P1[2]
27 IO P1[4] Optional External Clock Input (EXTCLK)
28 IO P1[6]
29 IO P5[0]
30 IO P5[2]
31 IO P3[0]
32 IO P3[2]
33 IO P3[4]
34 IO P3[6]
35 Input XRES Active high external reset with internal pull
down.
36 IO P4[0]
37 IO P4[2]
38 IO P4[4]
39 IO P4[6]
40 IO I P2[0] Direct switched capacitor block input.
41 IO I P2[2] Direct switched capacitor block input.
42 IO P2[4] External Analog Ground (AGND)
43 IO P2[6] External Voltage Reference (VRef)
44 IO I P0[0] A nalog column mux input.
45 IO IO P0[2] Analog column mux input and column output.
46 IO IO P0[4] Analog column mux input and column output.
47 IO I P0[6] A nalog column mux input.
48 Power Vdd Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
SSOP
AI, P0[7] Vdd
AIO, P0[5] P0[6], AI
AIO, P0[3] P0[4], AIO
AI, P0[1] P0[2], AIO
P2[7] P0[0], AI
P2[5] P2[6], External VRef
AI, P2[3] P2[4], Exte rnal AGND
AI, P2[1] P2[2], AI
P4[7] P2[0], AI
P4[5] P4[6]
P4[3] P4[4]
P4[1] P4[2]
SMP P4[0]
P3[7] XRES
P3[5] P3[6]
P3[3] P3[4]
P3[1] P3[2]
P5[3] P3[0]
P5[1] P5[2]
I2C SCL, P1[7] P5[0]
I2C SDA, P1[5] P1[6]
P1[3] P1[4], EXT CLK
I
2C SCL, XTALin, P1[1] P1[2]
Vss P1[0], XTALout, I2C SD
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
43
44
42
40
41
39
38
37
36
35
33
34
32
31
30
29
28
27
26
25
August 3, 2004 Document No. 38-12012 Rev. *I 13
CY8C27x43 Final Data Sheet 1. Pin Information
Table 1-6. 48-Pin Part Pinout (MLF*)
Pin
No. Type Pin
Name Description CY8C27643 48-Pin PSoC Device
Digital Analog
1IO I P2[3] Direct switched capacitor block input.
2IO I P2[1] Direct switched capacitor block input.
3IO P4[7]
4IO P4[5]
5IO P4[3]
6IO P4[1]
7Power SMP Switch Mode Pump (SMP) connection to
external components required.
8IO P3[7]
9IO P3[5]
10 IO P3[3]
11 IO P3[1]
12 IO P5[3]
13 IO P5[1]
14 IO P1[7] I2C Serial Clock (SCL)
15 IO P1[5] I2C Serial Data (SDA)
16 IO P1[3]
17 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL)
18 Power Vss Ground connection.
19 IO P1[0] Crystal Output (XTALout), I2C Serial Data
(SDA)
20 IO P1[2]
21 IO P1[4] Optional External Clock Input (EXTCLK)
22 IO P1[6]
23 IO P5[0]
24 IO P5[2]
25 IO P3[0]
26 IO P3[2]
27 IO P3[4]
28 IO P3[6]
29 Input XRES Active high external reset with internal pull
down.
30 IO P4[0]
31 IO P4[2]
32 IO P4[4]
33 IO P4[6]
34 IO I P2[0] Direct switched capacitor block input.
35 IO I P2[2] Direct switched capacitor block input.
36 IO P2[4] External Analog Gr ound (AGND)
37 IO P2[6] External Voltage Reference (VRef)
38 IO I P0[0] Analog column mux input.
39 IO IO P0[2] Analog column mux input and column output.
40 IO IO P0[4] Analog column mux input and column output.
41 IO I P0[6] Analog column mux input.
42 Power Vdd Supply voltage.
43 IO I P0[7] Analog column mux input.
44 IO IO P0[5] Analog column mux input and column output.
45 IO IO P0[3] Analog column mux input and column output.
46 IO I P0[1] Analog column mux input.
47 IO P2[7]
48 IO P2[5]
LEGEND: A = Analog, I = Input, and O = Output.
* The MLF package has a center pad that must be connected to ground (Vss).
MLF
(Top View)
P2[5]
P2[7]
P0[1] , AI
P0[3] , AIO
P0[5] , AIO
P0[7] , AI
Vdd
P0[6] , AI
P0[4] , AIO
P0[2] , AIO
P0[0] , AI
P2[6] , Extern al VRe
f
10
11
12
A
I, P2[3]
A
I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
35
34
33
32
31
30
29
28
27
26
25
36
48
47
46
45
44
43
42
41
40
39
38
37
P2[2], AI
P2[0], AI
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P2[4], External AGN
D
1
2
3
4
5
6
7
8
9
13
14
15
16
17
18
19
20
21
22
23
24
P5[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C S C L , X T A L in , P 1 [1 ]
Vss
I2C SDA, XTALout, P1[0]
P1[2]
E XT CLK , P 1 [4 ]
P1[6]
P5[0]
P5[2]
August 3, 2004 © Cypress MicroSystems, Inc. 2003 — Document No. 38-12012 Rev. *I 14
2. Register Reference
This chapter lists the registers of the CY8C27x43 PSoC device. For detailed register information, reference the PSoC™ Mixed Sig-
nal Array Technical Reference Manual.
2.1 Register Conventions
The register conventions specific to this section are listed in the
following table.
2.2 Register Mapping Tables
The PSoC device has a total register address space of 512
bytes. The register space is referred to as IO space and is
divided into two ban ks. The XOI bit in the Flag regist er (CPU_F)
determines which bank the user is currently in. When the XOI
bit is set the user is in bank 1.
Note In the following register mapping tables, blank fields are
reserved and should not be accessed.
Convention Description
R Read register or bit(s)
W Write register or bit(s)
L Logi cal re giste r or bit(s)
C Clearable register or bit(s)
# Access is bit specific
August 3, 2004 Document No. 38-12012 Rev. *I 15
CY8C27x43 Final Data Sheet 2. Register Reference
Regi ster Map Bank 0 Table: User Space
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
Name
Addr
(0,Hex)
Access
PRT0DR 00 RW 40 ASC10CR0 80 RW C0
PRT0IE 01 RW 41 ASC10CR1 81 RW C1
PRT0GS 02 RW 42 ASC10CR2 82 RW C2
PRT0DM2 03 RW 43 ASC10CR3 83 RW C3
PRT1DR 04 RW 44 ASD11CR0 84 RW C4
PRT1IE 05 RW 45 ASD11CR1 85 RW C5
PRT1GS 06 RW 46 ASD11CR2 86 RW C6
PRT1DM2 07 RW 47 ASD11CR3 87 RW C7
PRT2DR 08 RW 48 ASC12CR0 88 RW C8
PRT2IE 09 RW 49 ASC12CR1 89 RW C9
PRT2GS 0A RW 4A ASC12CR2 8A RW CA
PRT2DM2 0B RW 4B ASC12CR3 8B RW CB
PRT3DR 0C RW 4C ASD13CR0 8C RW CC
PRT3IE 0D RW 4D ASD13CR1 8D RW CD
PRT3GS 0E RW 4E ASD13CR2 8E RW CE
PRT3DM2 0F RW 4F ASD13CR3 8F RW CF
PRT4DR 10 RW 50 ASD20CR0 90 RW D0
PRT4IE 11 RW 51 ASD20CR1 91 RW D1
PRT4GS 12 RW 52 ASD20CR2 92 RW D2
PRT4DM2 13 RW 53 ASD20CR3 93 RW D3
PRT5DR 14 RW 54 ASC21CR0 94 RW D4
PRT5IE 15 RW 55 ASC21CR1 95 RW D5
PRT5GS 16 RW 56 ASC21CR2 96 RW I2C_CFG D6 RW
PRT5DM2 17 RW 57 ASC21CR3 97 RW I2C_SCR D7 #
18 58 ASD22CR0 98 RW I2C_DR D8 RW
19 59 ASD22CR1 99 RW I2C_MSCR D9 #
1A 5A ASD22CR2 9A RW INT_CLR0 DA RW
1B 5B ASD22CR3 9B RW INT_CLR1 DB RW
1C 5C ASC23CR0 9C RW DC
1D 5D ASC23CR1 9D RW INT_CLR3 DD RW
1E 5E ASC23CR2 9E RW INT_MSK3 DE RW
1F 5F ASC23CR3 9F RW DF
DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW
DBB00DR1 21 W 61 A1 INT_MSK1 E1 RW
DBB00DR2 22 RW 62 A2 INT_VC E2 RC
DBB00CR0 23 # ARF_CR 63 RW A3 RES_WDT E3 W
DBB01DR0 24 # CMP_CR0 64 # A4 DEC_DH E4 RC
DBB01DR1 25 W ASY_CR 65 # A5 DEC_DL E5 RC
DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW
DBB01CR0 27 # 67 A7 DEC_CR1 E7 RW
DCB02DR0 28 # 68 A8 MUL_X E8 W
DCB02DR1 29 W 69 A9 MUL_Y E9 W
DCB02DR2 2A RW 6A AA MUL_DH EA R
DCB02CR0 2B # 6B AB MUL_DL EB R
DCB03DR0 2C # 6C AC ACC_DR1 EC RW
DCB03DR1 2D W 6D AD ACC_DR0 ED RW
DCB03DR2 2E RW 6E AE ACC_DR3 EE RW
DCB03CR0 2F # 6F AF ACC_DR2 EF RW
DBB10DR0 30 # ACB00CR3 70 RW RDI0RI B0 RW F0
DBB10DR1 31 W ACB00CR0 71 RW RDI0SYN B1 RW F1
DBB10DR2 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2
DBB10CR0 33 # ACB00CR2 73 RW RDI0LT0 B3 RW F3
DBB11DR0 34 # ACB01CR3 74 RW RDIOLT1 B4 RW F4
DBB11DR1 35 W ACB01CR0 75 RW RDI0RO0 B5 RW F5
DBB11DR2 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6
DBB11CR0 37 # ACB01CR2 77 RW B7 CPU_F F7 RL
DCB12DR0 38 # ACB02CR3 78 RW RDI1RI B8 RW F8
DCB12DR1 39 W ACB02CR0 79 RW RDI1SYN B9 RW F9
DCB12DR2 3A RW ACB02CR1 7A RW RDI1IS BA RW FA
DCB12CR0 3B # ACB02CR2 7B RW RDI1LT0 BB RW FB
DCB13DR0 3C # ACB03CR3 7C RW RDI1LT1 BC RW FC
DCB13DR1 3D W ACB03CR0 7D RW RDI1RO0 BD RW FD
DCB13DR2 3E RW ACB03CR1 7E RW RDI1RO1 BE RW CPU_SCR1 FE #
DCB13CR0 3F # ACB03CR2 7F RW BF CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific.
August 3, 2004 Document No. 38-12012 Rev. *I 16
CY8C27x43 Final Data Sheet 2. Register Reference
Register Map Bank 1 Table: Configuration Space
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
Name
Addr
(1,Hex)
Access
PRT0DM0 00 RW 40 ASC10CR0 80 RW C0
PRT0DM1 01 RW 41 ASC10CR1 81 RW C1
PRT0IC0 02 RW 42 ASC10CR2 82 RW C2
PRT0IC1 03 RW 43 ASC10CR3 83 RW C3
PRT1DM0 04 RW 44 ASD11CR0 84 RW C4
PRT1DM1 05 RW 45 ASD11CR1 85 RW C5
PRT1IC0 06 RW 46 ASD11CR2 86 RW C6
PRT1IC1 07 RW 47 ASD11CR3 87 RW C7
PRT2DM0 08 RW 48 ASC12CR0 88 RW C8
PRT2DM1 09 RW 49 ASC12CR1 89 RW C9
PRT2IC0 0A RW 4A ASC12CR2 8A RW CA
PRT2IC1 0B RW 4B ASC12CR3 8B RW CB
PRT3DM0 0C RW 4C ASD13CR0 8C RW CC
PRT3DM1 0D RW 4D ASD13CR1 8D RW CD
PRT3IC0 0E RW 4E ASD13CR2 8E RW CE
PRT3IC1 0F RW 4F ASD13CR3 8F RW CF
PRT4DM0 10 RW 50 ASD20CR0 90 RW GDI_O_IN D0 RW
PRT4DM1 11 RW 51 ASD20CR1 91 RW GDI_E_IN D1 RW
PRT4IC0 12 RW 52 ASD20CR2 92 RW GDI_O_OU D2 RW
PRT4IC1 13 RW 53 ASD20CR3 93 RW GDI_E_OU D3 RW
PRT5DM0 14 RW 54 ASC21CR0 94 RW D4
PRT5DM1 15 RW 55 ASC21CR1 95 RW D5
PRT5IC0 16 RW 56 ASC21CR2 96 RW D6
PRT5IC1 17 RW 57 ASC21CR3 97 RW D7
18 58 ASD22CR0 98 RW D8
19 59 ASD22CR1 99 RW D9
1A 5A ASD22CR2 9A RW DA
1B 5B ASD22CR3 9B RW DB
1C 5C ASC23CR0 9C RW DC
1D 5D ASC23CR1 9D RW OSC_GO_EN DD RW
1E 5E ASC23CR2 9E RW OSC_CR4 DE RW
1F 5F ASC23CR3 9F RW OSC_CR3 DF RW
DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW
DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW
DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW
23 AMD_CR0 63 RW A3 VLT_CR E3 RW
DBB01FN 24 RW 64 A4 VLT_CMP E4 R
DBB01IN 25 RW 65 A5 E5
DBB01OU 26 RW AMD_CR1 66 RW A6 E6
27 ALT_CR0 67 RW A7 E7
DCB02FN 28 RW ALT_CR1 68 RW A8 IMO_TR E8 W
DCB02IN 29 RW CLK_CR2 69 RW A9 ILO_TR E9 W
DCB02OU 2A RW 6A AA BDG_TR EA RW
2B 6B AB ECO_TR EB W
DCB03FN 2C RW 6C AC EC
DCB03IN 2D RW 6D AD ED
DCB03OU 2E RW 6E AE EE
2F 6F AF EF
DBB10FN 30 RW ACB00CR3 70 RW RDI0RI B0 RW F0
DBB10IN 31 RW ACB00CR0 71 RW RDI0SYN B1 RW F1
DBB10OU 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2
33 ACB00CR2 73 RW RDI0LT0 B3 RW F3
DBB11FN 34 RW ACB01CR3 74 RW RDIOLT1 B4 RW F4
DBB11IN 35 RW ACB01CR0 75 RW RDI0RO0 B5 RW F5
DBB11OU 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6
37 ACB01CR2 77 RW B7 CPU_F F7 RL
DCB12FN 38 RW ACB02CR3 78 RW RDI1RI B8 RW F8
DCB12IN 39 RW ACB02CR0 79 RW RDI1SYN B9 RW F9
DCB12OU 3A RW ACB02CR1 7A RW RDI1IS BA RW FA
3B ACB02CR2 7B RW RDI1LT0 BB RW FB
DCB13FN 3C RW ACB03CR3 7C RW RDI1LT1 BC RW FC
DCB13IN 3D RW ACB03CR0 7D RW RDI1RO0 BD RW FD
DCB13OU 3E RW ACB03CR1 7E RW RDI1RO1 BE RW CPU_SCR1 FE #
3F ACB03CR2 7F RW BF CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific.
August 3, 2004 Document No. 38-12012 Rev. *I 17
3. Electrical S pecifications
This chapter presents the DC and AC electrical specifications of the CY8C27x43 PSoC device. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.
Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted. Specifications for devices running at greater
than 12 MHz are valid for -40oC ≤ TA ≤ 70oC and TJ ≤ 82oC.
Figure 3-1. Voltage versus CPU Frequency
The following table lists the units of measure that are used in this chapter.
5.25
4.75
3.00
93 kHz 12 MHz 24 MHz
CPU Frequency
Vdd Voltage
Valid
Operating
Region
Table 3-1: Units of Measure
Symbol Unit of Me asure Symbol Unit of Measure
oCdegree Cel sius µWmicro watts
dB decibels mA milli-ampere
fF femto farad ms milli-second
Hz hertz mV milli-volts
KB 1024 bytes nA nano amp ere
Kbit 1024 bits ns nanosecond
kHz kilohertz nV nanovolts
kΩkilohm Ωohm
MHz megahertz pA pico ampe re
MΩmegaohm pF pico farad
µAmicro ampere pp peak-to-peak
µFmicro f arad ppm parts per m illion
µHmicro henry ps picosecond
µsmicrosecond sps samples per second
µVmicro volts σsigma: one standard deviation
µVrms micro volts root-mean-square Vvolts
August 3, 2004 Document No. 38-12012 Rev. *I 18
CY8C27x43 Final Data Sheet 3. Electrical Specifications
3.1 Absolute Maximum Ratings
3.2 Operating Temperature
Ta ble 3-2. Absolute Maximum Ratings
Symbol Description Min Typ Max Units Notes
TSTG Storage Temperature -55 –+100 oCHigher storage temperatures will reduce data
retention time.
TAAmbient Temperature with Power Applied -40 –+85 oC
Vdd Supply Voltage on Vdd Relative to Vss -0.5 –+6.0 V
VIO DC Input Vol ta ge Vss- 0.5 –Vdd + 0.5 V
–DC Voltage Applied to Tri-state Vss - 0.5 –Vdd + 0.5 V
IMIO Maximum Current into any Port Pi n -25 –+50 mA
IMAIO Maximum Current into any P ort Pin C onfigured as Analog
Driver -50 –+50 mA
ESD Electro Static Discharge V o ltage 2000 – – V Human Body Model ESD
–Latch -up Curren t – – 200 mA
Table 3- 3. Operating Temperature
Symbol Description Min Typ Max Units Notes
TAAmbient Temperature -40 –+85 oC
TJJunction Temperature -40 –+100 oCThe temperature rise from ambient to junction is
pa ckage spe cific. See “Thermal Impedances”
on page 41. The user must limit the power con-
sumption to comply with this requirement.
August 3, 2004 Document No. 38-12012 Rev. *I 19
CY8C27x43 Final Data Sheet 3. Electrical Specifications
3.3 DC Electrical Characterist ics
3.3.1 DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C , re sp e cti ve ly. Typica l pa r am ete r s app ly t o 5 V an d 3 .3V a t 2 5°C a nd
are for de sign guidance only.
3.3.2 DC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C , re sp e cti ve ly. Typica l pa r am ete r s app ly t o 5 V an d 3 .3V a t 2 5°C a nd
are for de sign guidance only.
Table 3-4. DC Chip-Level Specifications
Symbol Description Min Typ Max Units Notes
Vdd Supply Voltage 3.00 –5.25 V
IDD Supply Current – 5 8 mA Conditions are Vdd = 5.0V, TA = 25 oC, CPU = 3
MHz, 48 MHz = Disabled. VC1 = 1.5 MHz, VC2
= 93.75 kHz, VC3 = 93.75 kHz.
IDD3 Supply Current –3.3 6.0 mA Cond i tions are V dd = 3.3V, TA = 25 oC, CPU = 3
MHz, 48 MHz = Disabled, VC1 = 1.5 MHz, VC2
= 93.75 kHz, VC3 = 93.75 kHz.
ISB Sleep (Mode) Current with POR, LVD, Sleep Timer, and
WDT.a
a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compare d wit h de vi c e s t ha t ha ve si m i la r fu n ct i o ns
enabled.
– 3 6.5 µAConditions are with internal slow speed oscilla-
tor, Vdd = 3.3V, -40 oC ≤ TA ≤ 55 oC.
ISBH Sleep (Mode) Current with POR, LVD, Sleep Timer, and
WDT at high temperature.a– 4 25 µAConditions are with internal slow speed oscilla-
tor, Vdd = 3.3V, 55 oC < TA ≤ 85 oC.
ISBXTL Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and external crys tal.a– 4 7.5 µACondi tions are with properly loaded, 1 µW max,
32.768 kH z crystal. Vd d = 3.3V, -40 oC ≤ TA ≤
55 oC.
ISBXTLH Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT,
and external crystal at high temperature.a– 5 26 µAConditions are w ith pr operly l oaded , 1 µW max,
32.768 kHz crystal. Vdd = 3.3V, 55 oC < T A ≤ 85
oC.
VREF Reference Voltag e (Bandgap) for Silicon A b
b. Refer to the Order ing Info rm atio n chapter on page 4 2.
1.275 1.300 1.325 VTrimmed for appropriate Vdd.
VREF Reference Voltag e (Bandgap) for Silicon B b1.280 1.300 1.320 VTrimmed for appropriate Vdd.
Ta ble 3-5. DC GPIO Specifications
Symbol Description Min Typ Max Units Notes
RPU Pull up Resistor 4 5.6 8 kΩ
RPD Pull down Res is tor 4 5.6 8 kΩ
VOH High Output Level Vdd - 1.0 – – V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads,
4 on even port pins (for example, P0[2], P1[4]),
4 on odd por t pins (for example, P0[3], P1[5])).
VOL Low Outpu t Level – – 0.7 5 V IOL = 25 mA, Vd d = 4.75 to 5.25 V (8 to tal l oads ,
4 on even port pins (for example, P0[2], P1[4]),
4 on odd por t pins (for example, P0[3], P1[5])).
VIL Input Low Level – – 0.8 V Vdd = 3.0 to 5.25
VIH Input High Level 2.1 – V Vdd = 3.0 to 5.25
VHInput Hysterisis –60 –mV
IIL Input Leakage (Absolute Value) –1–nA Gross tested to 1 µA.
CIN Capacitive Load on Pins as Input – 3.5 10 pF Package and pin dependent. Temp = 25oC.
COUT Capacitive Load on Pins as Output –3.5 10 pF Package and pin dependent. Temp = 25oC.
August 3, 2004 Document No. 38-12012 Rev. *I 20
CY8C27x43 Final Data Sheet 3. Electrical Specifications
3.3. 3 DC Operational Ampli fier Specifications
The f ol low ing tables l ist gua rant eed max imum and min imum spe cif icat ion s f or t he voltage an d te mpe ratu re ran ges : 4. 75V to 5 .25 V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C , re sp e cti ve ly. Typica l pa r am ete r s app ly t o 5 V an d 3 .3V a t 2 5°C a nd
are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at
25°C and are for design guidance only.
Table 3-6. 5V DC Operational A mpli fier S p eci fica tions
Symbol Description Min Typ Max Units Notes
VOSOA Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–1.6
1.3
1.2
10
8
7.5
mV
mV
mV
–
–
TCVOSOA Average Input Offset Voltage Drift – 7.0 35.0 µV/oC
IEBOA Input Leakage Current (Port 0 Analog Pins) – 20 – pA Gross tested to 1 µA.
CINOA Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent. Temp = 25oC.
VCMOA Common Mode Voltage Range
Common Mode Voltage Range (high power or high
opamp bias)
0.0 – Vdd
Vdd - 0.5 V T he common-mode input voltage range is mea-
sured through an analog output buffer. The
specification includes the limitations imposed
by the characteristics of the analog output
buffer.
0.5 –
CMRROA Common Mode Rejection Ratio
Power = Low
Power = Medium
Power = High
60
60
60
– – dB Specification is applicable at high power. For all
other bias modes (except high power, high
opamp bias), minimum is 60 dB.
GOLOA Open Loop Gain
Power = Low
Power = Medium
Power = High
60
60
80
– – dB Specification is applicable at high power. For all
other bias modes (except high power, high
opamp bias), minimum is 60 dB.
VOHIGHOA High Output Voltage Swing (in ternal signa ls)
Power = Low
Power = Medium
Power = High
Vdd - 0.2
Vdd - 0.2
Vdd - 0.5
–
–
–
–
–
–
V
V
V
VOLOWOA Low Output V oltage Swing (internal signals)
Power = Low
Power = Medium
Power = High
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
ISOA Supply Current (includ i ng associated AGN D buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
–
–
–
–
–
–
150
300
600
1200
2400
4600
200
400
800
1600
3200
6400
µA
µA
µA
µA
µA
µA
PSRROA Supply Volta g e Rej ectio n Ratio 60 – – dB 0V ≤ VIN ≤ (Vdd - 2.25) or
(Vdd - 1.25V) ≤ VIN ≤ Vdd.
August 3, 2004 Document No. 38-12012 Rev. *I 21
CY8C27x43 Final Data Sheet 3. Electrical Specifications
Table 3-7. 3.3V DC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
VOSOA Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
High Power is 5 Volts Only
–
–1.65
1.32 10
8 mV
mV
TCVOSOA Average Input Offset Voltage Drift – 7.0 35.0 µV/oC
IEBOA Input Leakage Current (Port 0 Analog Pins) – 20 – pA Gross tested to 1 µA.
CINOA Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent. Temp = 25oC.
VCMOA Common Mode Voltage Range 0.2 – Vdd - 0.2 V The common-mode input voltage range is
measured through an analog output buffer.
The specification includes the limitations
imposed by the characteristics of the analog
output buffer.
CMRROA Common Mode Rejection Ratio
Power = Low
Power = Medium
Power = High
50
50
50
– – dB Specification is applicable at high power. For
all other bias modes (except high power , high
opamp bias), minimum is 60 dB.
GOLOA Open Loop Gain
Power = Low
Power = Medium
Power = High
60
60
80
– – dB Specification is applicable at high power. For
all other bias modes (except high power , high
opamp bias), minimum is 60 dB.
VOHIGHOA High Output Voltage Swing (in ternal signa ls)
Power = Low
Power = Medium
Power = High is 5V only
Vdd - 0.2
Vdd - 0.2
Vdd - 0.2
–
–
–
–
–
–
V
V
V
VOLOWOA Low Output V oltage Swing (internal signals)
Power = Low
Power = Medium
Power = High
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
ISOA Supply Current (includ i ng associated AGN D buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
–
–
–
–
–
–
150
300
600
1200
2400
4600
200
400
800
1600
3200
6400
µA
µA
µA
µA
µA
µA
PSRROA Supply Volta ge R ej ection Ratio 50 – – dB 0V ≤ VIN ≤ (Vdd - 2.25) or
(Vdd - 1.25V ) ≤ VIN ≤ Vdd.
August 3, 2004 Document No. 38-12012 Rev. *I 22
CY8C27x43 Final Data Sheet 3. Electrical Specifications
3.3.4 DC Analog Output Buffer Specifications
The f ol low ing tables l ist gua rant eed max imum and min imum spe cif icat ion s f or t he voltage an d te mpe ratu re ran ges : 4. 75V to 5 .25 V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C , re sp e cti ve ly. Typica l pa r am ete r s app ly t o 5 V an d 3 .3V a t 2 5°C a nd
are for de sign guidance only.
Table 3-8. 5V DC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units Notes
VOSOB Input Off set Voltage (Absolute Value) – 3 12 mV
TCVOSOB A verage Input Offset Volt age Dri ft –+6 –µV/°C
VCMOB Common-Mode Input Voltage Range 0.5 –Vdd - 1.0 V
ROUTOB Output Resistance
Power = Low
Power = High –
–1
1–
–
Ω
Ω
VOHIGHOB High Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
Power = High 0.5 x Vdd + 1.3
0.5 x Vdd + 1.3
–
––
–V
V
VOLOWOB Low Output Voltage Swing (Load = 32 ohms to Vdd/2)
Power = Low
Power = High –
––
–0.5 x Vdd - 1.3
0.5 x Vdd - 1.3
V
V
ISOB Supply Current Including Bias Cell (No Load)
Power = Low
Power = High –
–1.1
2.6 5.1
8.8 mA
mA
PSRROB Supply Voltage Rejection Rat io 60 – – dB
Table 3-9. 3.3V DC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units Notes
VOSOB Input Offset Voltage (Absolute Value) – 3 12 mV
TCVOSOB Average Input Offset Voltage Drift –+6 –µV/°C
VCMOB Common-Mode Input Voltage Range 0.5 -Vdd - 1.0 V
ROUTOB Output Resistance
Power = Low
Power = High –
–1
1–
–
Ω
Ω
VOHIGHOB High Output Voltage Swing (Load = 1k ohms to Vdd/2)
Power = Low
Power = High 0.5 x Vdd + 1.0
0.5 x Vdd + 1.0
–
––
–V
V
VOLOWOB Low Output Vo ltage Swing (Load = 1k ohms to Vdd/2)
Power = Low
Power = High –
––
–0.5 x Vdd - 1.0
0.5 x Vdd - 1.0
V
V
ISOB Supply Current Including Bias Cell (No Load)
Power = Low
Power = High –0.8
2.0 2.0
4.3 mA
mA
PSRROB Supply Volta ge R ej ection Ratio 60 – – dB
August 3, 2004 Document No. 38-12012 Rev. *I 23
CY8C27x43 Final Data Sheet 3. Electrical Specifications
3.3.5 DC Switch Mode Pump Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C , re sp e cti ve ly. Typica l pa r am ete r s app ly t o 5 V an d 3 .3V a t 2 5°C a nd
are for design guidance only.
Figure 3-2. Basic Switch Mode Pump Circuit
Table 3-10. DC Switch Mode Pump (SMP) Specifications
Symbol Description Min Typ Max Units Notes
VPUMP 5V 5V Output Voltage 4.75 5.0 5.25 V Conf igura tion of f ootnot e a. Average, neglecting
ripple. SMP trip voltage is set to 5.0V.
a. L1 = 2 µH inductor, C1 = 10 µF capacitor, D1 = Schottky diode. See Figure 3-2.
VPUMP 3V 3V Output Voltage 3.00 3.25 3.60 V Config urati on of foo tnote a. Average, neglecting
ripple. SMP trip voltage is set to 3.25V.
IPUMP Availa bl e Output Curren t
VBAT = 1.5V, VPUMP = 3.25V
VBAT = 1.8V, VPUMP = 5.0V
8
5–
––
–mA
mA
Configuration of foot note a.
SMP trip voltage is set to 3.25V.
SMP trip voltage is set to 5.0V.
VBAT5V Input Voltage Range from Battery 1.8 – 5.0 V Configuration of footnot e a. SMP trip voltage is
set to 5.0V.
VBAT3V Input Voltage Range from Battery 1.0 – 3.3 V Configuration of footnot e a. SMP trip voltage is
set to 3.25V.
VBATSTART Minimum Input Voltage from Battery to Start Pump 1.1 – – V Configurati on of footnot e a.
∆VPUMP_Line Line Regulation (over VBAT range) – 5 – %VOConf i gura tion of footnote a. VO is the “Vdd
Value for PUMP Trip” specified by the VM[2:0]
setting in the DC POR and LVD S pecification,
Table 3-16 on page 26.
∆VPUMP_Load Load Regulation – 5 – %VOConf i gura tion of footnote a. VO is the “Vdd
Value for PUMP Trip” specified by the VM[2:0]
setting in the DC POR and LVD S pecification,
Table 3-16 on page 26.
∆VPUMP_Ripple Output Voltage Ripple (depends on capacitor/load) – 100 – mVpp Configuration of footnote a. Load is 5mA.
E3Efficiency 35 50 – % Configuration of footnote a. Load is 5 mA. SMP
trip voltage is set to 3.25V.
FPUMP Switching Frequency – 1.3 – MHz
DCPUMP Switching Duty Cycle – 50 – %
Battery
C1
D1
+PSoCTM
Vdd
Vss
SMP
V
BAT
VPUM
P
L1
August 3, 2004 Document No. 38-12012 Rev. *I 24
CY8C27x43 Final Data Sheet 3. Electrical Specifications
3.3.6 DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The guarant eed spe cificati ons are m easure d throug h the Anal og Contin uous Time PSoC blocks. Th e power levels for AGND refe r to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 3-11. Silicon Revision A – 5V DC Analog Reference Specifications
Symbol Description Min Typ Max Units
BG Bandg ap Voltage Referenc e 1.274 1.30 1.326 V
–AGND = Vdd/2a
a. AGND tolerance includes the offsets of the local buffer in the PSoC block.
Vdd/2 - 0.030 Vdd/ 2 - 0.004 Vdd/2 + 0.003 V
–AGND = 2 x BandGapa2 x BG - 0.043 2 x BG - 0.010 2 x BG + 0.024 V
–AGND = P2[4] (P2[4] = Vdd/2)aP2[4] - 0.013 P2[4] P2[4] + 0.014 V
–AGND = BandGapaBG - 0.009 BG BG + 0.009 V
–AGND = 1.6 x BandGapa1.6 x BG - 0.018 1.6 x BG 1.6 x BG + 0.018 V
–AGND Block to Block Variation (AGND = Vdd/2)a-0.034 0.000 0.034 V
–RefHi = Vdd/2 + BandGap Vdd/2 + BG - 0.140 Vdd/2 + BG - 0.018 Vdd/2 + BG + 0.103 V
–RefH i = 3 x BandGap 3 x BG - 0.112 3 x BG - 0.018 3 x BG + 0.076 V
–RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) 2 x BG + P2[6] - 0.113 2 x BG + P2[6] - 0.018 2 x BG + P2[6] + 0.077 V
–RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + BG - 0.130 P2[4] + BG - 0.016 P2[4] + BG + 0.098 V
–RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] - 0.133 P2[4] + P2[6] - 0.016 P2[4] + P2[6] + 0.100 V
–RefHi = 3.2 x BandGap 3.2 x BG - 0.112 3.2 x BG 3.2 x BG + 0.076 V
–RefLo = Vdd/2 – Ba ndGap Vdd/2 - BG - 0.051 Vdd/2 - BG + 0.024 Vdd/2 - BG + 0.098 V
–RefLo = BandGap BG - 0.082 BG + 0.023 BG + 0.129 V
–RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2 x BG - P2[6] - 0.084 2 x BG - P2[6] + 0.025 2 x BG - P2[6] + 0.134 V
–RefLo = P2[4] – BandGap (P2[4] = Vdd/2) P2[4] - BG - 0.056 P2[4] - BG + 0.026 P2[4] - BG + 0.107 V
–RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] - 0.057 P2[4] - P2[6] + 0.026 P2[4] - P2[6] + 0.110 V
Table 3-12. Silicon Revision B – 5V DC Analog Reference Specifications
Symbol Description Min Typ Max Units
BG Bandg ap Voltage Referenc e 1.28 1.30 1.32 V
–AGND = Vdd/2a
a. AGND tolerance includes the offsets of the local buffer in the PSoC block.
Vdd/2 - 0.030 Vdd/2 Vdd/2 + 0.007 V
–AGND = 2 x BandGapa2 x BG - 0.043 2 x BG 2 x BG + 0.024 V
–AGND = P2[4] (P2[4] = Vdd/2)aP2[4] - 0.011 P2[4] P2[4] + 0.011 V
–AGND = BandGapaBG - 0.009 BG BG + 0.009 V
–AGND = 1.6 x BandGapa1.6 x BG - 0.018 1.6 x BG 1.6 x BG + 0.018 V
–AGND Block to Block Variation (AGND = Vdd/2)a-0.034 0.000 0.034 V
–RefHi = Vdd/2 + BandGap Vdd/2 + BG - 0.1 Vdd/2 + BG - 0.01 Vdd/2 + BG + 0.1 V
–RefH i = 3 x BandGap 3 x BG - 0.06 3 x BG - 0.0 1 3 x BG + 0.06 V
–RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) 2 x BG + P2[6] - 0.06 2 x BG + P2[6] - 0.01 2 x BG + P2[6] + 0.06 V
–RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + BG - 0.06 P2[4] + BG - 0.01 P2[4] + BG + 0.06 V
–RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] - 0.06 P2[4] + P2[6] - 0.01 P2[4] + P2[6] + 0.06 V
–RefHi = 3.2 x BandGap 3.2 x BG - 0.06 3.2 x BG - 0.01 3.2 x BG + 0.06 V
–RefLo = Vdd/2 – Ba ndGap Vdd/2 - BG - 0.051 Vdd/2 - BG + 0.01 Vdd/2 - BG + 0.06 V
–RefLo = BandGap BG - 0.06 BG + 0.01 BG + 0.06 V
–RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2 x BG - P2[6] - 0.04 2 x BG - P2[6] + 0.01 2 x BG - P2[6] + 0.04 V
–RefLo = P2[4] – BandGap (P2[4] = Vdd/2) P2[4] - BG - 0.056 P2[4] - BG + 0.01 P2[4] - BG + 0.056 V
–RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] - 0.056 P2[4] - P2[6] + 0.01 P2[4] - P2[6] + 0.056 V
August 3, 2004 Document No. 38-12012 Rev. *I 25
CY8C27x43 Final Data Sheet 3. Electrical Specifications
Table 3-13. Silicon Revision A – 3.3V DC Analog Reference Specifications
Symbol Description Min Typ Max Units
BG Bandg ap Voltage Referenc e 1.274 1.30 1.326 V
–AGND = Vdd/2a
a. AGND tolerance includes the offsets of the local buffer in the PSoC block.
Note See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.
Vdd/2 - 0.027 Vdd/2 - 0.003 Vdd/2 + 0.002 V
–AGND = 2 x BandGapaNot Allowed
–AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.008 P2[4] + 0.001 P2[4] + 0.009 V
–AGND = BandGapaBG - 0.009 BG BG + 0.009 V
–AGND = 1.6 x BandGapa1.6 x BG - 0.018 1.6 x BG 1.6 x BG + 0.018 V
–AGND Block to Block Variation (AGND = Vdd/2)a-0.034 0.000 0.034 mV
–RefHi = Vdd/2 + BandGap Not Allowed
–RefH i = 3 x BandGap Not Allowed
–RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Not Allowed
–RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Not Allowed
–RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] + P2[6] - 0.075 P2[4] + P2[6] - 0.009 P2[4] + P2[6] + 0.057 V
–RefHi = 3.2 x BandGap Not Allowed
–RefLo = Vdd/2 - Ba ndGap Not Allowed
–RefLo = BandGap Not Allowed
–RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Not Allowed
–RefLo = P2[4] – BandGap (P2[4] = Vdd/2) Not Allowed
–RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] - 0.048 P2[4] - P2[6] + 0.022 P2[4] - P2[6] + 0.092 V
Table 3-14. Silicon Revision B – 3.3V DC Analog Reference Specifications
Symbol Description Min Typ Max Units
BG Bandg ap Voltage Referenc e 1.28 1.30 1.32 V
–AGND = Vdd/2a
a. AGND tolerance includes the offsets of the local buffer in the PSoC block.
Note See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.
Vdd/2 - 0.027 Vdd/2 Vdd/2 + 0.005 V
–AGND = 2 x BandGapaNot Allowed
–AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.008 P2[4] P2[4] + 0.009 V
–AGND = BandGapaBG - 0.009 BG BG + 0.009 V
–AGND = 1.6 x BandGapa1.6 x BG - 0.018 1.6 x BG 1.6 x BG + 0.018 V
–AGND Block to Block Variation (AGND = Vdd/2)a-0.034 0.000 0.034 mV
–RefHi = Vdd/2 + BandGap Not Allowed
–RefH i = 3 x BandGap Not Allowed
–RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Not Allowed
–RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Not Allowed
–RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] + P2[6] - 0.06 P2[4] + P2[6] - 0.01 P2[4] + P2[6] + 0.057 V
–RefHi = 3.2 x BandGap Not Allowed
–RefLo = Vdd/2 - Ba ndGap Not Allowed
–RefLo = BandGap Not Allowed
–RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Not Allowed
–RefLo = P2[4] – BandGap (P2[4] = Vdd/2) Not Allowed
–RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] - 0.048 P2[4] - P2[6] + 0.01 P2[4] - P2[6] + 0.048 V
August 3, 2004 Document No. 38-12012 Rev. *I 26
CY8C27x43 Final Data Sheet 3. Electrical Specifications
3.3.7 DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
3.3.8 DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Mixed Signal Array Technical
Reference Manual for more information on the VLT_CR register.
Table 3-15. DC Analog PSoC Block Specifications
Symbol Description Min Typ Max Units Notes
RCT Resistor Unit Value (Continuous Time) –12.2 – kΩ
CSC Capacitor Unit Value (Switch Cap) –80 –fF
Table 3-16. DC POR and LVD Specifications
Symbol Description Min Typ Max Units Notes
VPPOR0R
VPPOR1R
VPPOR2R
Vdd Valu e for PPOR Trip (positive ramp )
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b –2.91
4.39
4.55 –V
V
V
VPPOR0
VPPOR1
VPPOR2
Vdd Value for PPOR Trip ( negative ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b –2.82
4.39
4.55 –V
V
V
VPH0
VPH1
VPH2
PPOR Hysteresis
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
–
–
–
92
0
0
–
–
–
mV
mV
mV
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Vdd Valu e for LVD Tr ip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.86
2.96
3.07
3.92
4.39
4.55
4.63
4.72
2.92
3.02
3.13
4.00
4.48
4.64
4.73
4.81
2.98a
3.08
3.20
4.08
4.57
4.74b
4.82
4.91
a. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
b. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
V
V
V
V
V
V
V
V
V
VPUMP0
VPUMP1
VPUMP2
VPUMP3
VPUMP4
VPUMP5
VPUMP6
VPUMP7
Vdd Value for PUMP Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.96
3.03
3.18
4.11
4.55
4.63
4.72
4.90
3.02
3.10
3.25
4.19
4.64
4.73
4.82
5.00
3.08
3.16
3.32
4.28
4.74
4.82
4.91
5.10
V
V
V
V
V
V
V
V
V
August 3, 2004 Document No. 38-12012 Rev. *I 27
CY8C27x43 Final Data Sheet 3. Electrical Specifications
3.3.9 DC Programm i ng Specifi c at ions
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-17. DC Programming Specifications
Symbol Description Min Typ Max Units Notes
IDDP Supply Current During Programming or Verify – 5 25 mA
VILP Input Low Voltage During Programming or Verify – – 0.8 V
VIHP Input High V oltage During Programming or Verify 2.2 – – V
IILP Input Current when Applying Vilp to P1[0] or P1[1] During
Progra mm i ng or Verify – – 0.2 mA Driving inter nal pull- dow n resistor.
IIHP Input Current when Applying Vihp to P1[0] or P1[1] During
Progra mm i ng or Verify – – 1.5 mA Driving inter nal pull- dow n resistor.
VOLV Output Low Vol tage Duri ng Programming o r Verify – – Vss + 0.75 V
VOHV Output High Voltage During Programming or Verify Vdd - 1.0 –Vdd V
FlashENPB Flash Endurance (per block) 50,000 – – – Erase/write cycles per block.
FlashENT Flash Enduran ce (t otal )a
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of
25,00 0 max i mu m c yc l es ea c h, or 36 x4 bl oc k s o f 12 , 5 00 max i mu m cyc l e s ea c h ( to li m it t he to t al nu mb er of cy c les to 36 x5 0, 0 00 an d that no single block ever sees more than
50,000 cycl es).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to
the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
1,800,000 – – – Erase/write cycles.
FlashDR Flash Data Retent ion 10 – – Years
August 3, 2004 Document No. 38-12012 Rev. *I 28
CY8C27x43 Final Data Sheet 3. Electrical Specifications
3.4 AC Electr ical Characteristics
3.4.1 AC Chip-Lev el Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Figure 3-3. PLL Lock Timing Diagram
Table 3-18. AC Chip-Level Specifications
Symbol Description Min Typ Max Units Notes
FIMO Internal Main Oscillator Frequency 23.4 24 24.6aMHz Trimmed. Utilizing factory trim values.
FCPU1 CPU Frequenc y (5V Nominal ) 0.93 24 24.6a,b
a. 4.75V < Vdd < 5.25V.
b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
MHz T r immed. Utilizing factory trim values.
FCPU2 CPU Frequency (3.3V Nominal) 0.93 12 12.3b,c
c. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller T rims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V .
MHz T r immed. Utilizing factory trim values.
F48M Digital PSoC Blo ck Freq uency 048 49.2a,b,d
d. See the individual user module data sheets for information on maximum frequencies for user modules.
MHz Refer to the AC Digital Block Specifications
below.
F24M Digital PSoC Blo ck Freq uency 024 24.6b, d MHz
F32K1 Internal Low Speed Oscilla tor Frequency 15 32 64 kHz
F32K2 External Crystal Oscillator –32.768 –kHz Accuracy is capacitor and crystal dependent.
50% duty cycle.
FPLL PLL Frequency –23.986 –MHz Multiple (x732) of crystal frequency.
Jitter24M2 24 MHz Period Jitter (PLL) – – 600 ps
TPLLSLEW PLL Lock Time 0.5 –10 ms
TPLLSLEWS-
LOW PLL Lock Time for Low Gain Setting 0.5 –50 ms
TOS External Crystal Oscillator St a rtup to 1% –1700 2620 ms
TOSACC External Crystal Oscillator Sta rtup to 100 ppm –2800 3800 ms The crystal o s cil la tor fr eque ncy i s wi th in 100 pp m of its
fina l value by the end of the Tosacc period. Correct
opera tion assumes a properly loaded 1 uW max imum
drive level 32.768 kHz crystal. 3.0V ≤ Vdd ≤ 5.5V, -40
oC ≤ TA ≤ 85 oC.
Jitter32k 32 kHz Period Jitter –100 ns
TXRST External Reset Pulse Width 10 – – µs
DC24M 24 MHz Duty Cycle 40 50 60 %
Step24M 24 MHz Trim Step Size – 50 – kHz
Fout48M 48 MHz Output Frequency 46.8 48.0 49.2a,c MHz Trimmed. Utilizing factory trim values.
Jitter24M1 24 MHz Period Jitter (IMO) –600 ps
FMAX Maximum frequency of signal on row input or row output. – – 12.3 MHz
TRAMP Supply Ramp Time 0 – – µs
24 MHz
FPLL
PLL
E
nable TPLLSLEW
PLL
Gain 0
August 3, 2004 Document No. 38-12012 Rev. *I 29
CY8C27x43 Final Data Sheet 3. Electrical Specifications
Figure 3-4. PLL Lock for Low Gain Setting Timing Diagram
Figure 3-5. External Crystal Oscillator Startup Timing Diagram
Figure 3-6. 24 MHz Period Jitter (IMO) Timing Diagram
Figure 3-7. 32 kHz Period Jitter (ECO) Timing Diagram
24 MHz
FPLL
PLL
E
nable TPLLSLEWLOW
PLL
Gain 1
32 kHz
F32K2
32K
S
elect TOS
Jitter24M1
F
24M
Jitter32k
F
32K2
August 3, 2004 Document No. 38-12012 Rev. *I 30
CY8C27x43 Final Data Sheet 3. Electrical Specifications
3.4. 2 AC General Pur pose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Figure 3-8. GPIO Timing Diagram
Table 3-19. AC GPIO Specifications
Symbol Description Min Typ Max Units Notes
FGPIO GPIO Oper ating Frequ ency 0 – 12 MHz
TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 3 – 18 ns Vdd = 4.5 to 5.25V, 10% - 90%
TFallF Fall T ime, Normal Strong Mode, Cload = 50 pF 2 – 18 ns Vdd = 4.5 to 5.25V, 10% - 90%
TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 10 27 – ns Vdd = 3 to 5.25V, 10% - 90%
TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 10 22 – ns Vdd = 3 to 5.25V, 10% - 90%
TFallF
TFallS
TRiseF
TRiseS
90%
10%
GPIO
Pin
Output
V
oltage
August 3, 2004 Document No. 38-12012 Rev. *I 31
CY8C27x43 Final Data Sheet 3. Electrical Specifications
3.4.3 AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Settling time s, sl ew rates , and gain bandwidth are bas ed on the Analog C onti nu ous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.
Table 3-20. 5V AC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
TROA Rising Settling Time from 80% of ∆V to 0.1 % of ∆V (10 pF
load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
–
–
–
3.9
0.72
0.62
µs
µs
µs
TSOA Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
–
–
–
5.9
0.92
0.72
µs
µs
µs
SRROA Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
0.15
1.7
6.5
–
–
–
–
–
–
V/µs
V/µs
V/µs
SRFOA Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
0.01
0.5
4.0
–
–
–
–
–
–
V/µs
V/µs
V/µs
BWOA Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
0.75
3.1
5.4
–
–
–
–
–
–
MHz
MHz
MHz
ENOA Noise at 1 kHz (P ower = Medium, Opamp Bias = High) – 100 – nV/rt-Hz
Table 3-21. 3.3V AC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
TROA Rising Settling Time from 80% of ∆V to 0.1 % of ∆V (10 pF
load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High –
––
–3.92
0.72
µs
µs
TSOA Falling Settling Time from 20% of ∆V to 0.1% of ∆V (10 pF
load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High –
––
–5.41
0.72
µs
µs
SRROA Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High 0.31
2.7 –
––
–V/µs
V/µs
SRFOA Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High 0.24
1.8 –
––
–V/µs
V/µs
BWOA Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High 0.67
2.8 –
––
–MHz
MHz
ENOA Noise at 1 kHz ( P ower = Medium, Opamp Bias = High) – 100 – nV/rt-Hz
August 3, 2004 Document No. 38-12012 Rev. *I 32
CY8C27x43 Final Data Sheet 3. Electrical Specifications
3.4.4 AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-22. AC Digital Block Specifications
Function Description Min Typ Max Units Notes
All
Functions Maximum Block Clocking Frequency (> 4.75V) 49.2 4.75V < Vdd < 5.25V.
Maximum Block Clocking Frequency (< 4.75V) 24.6 3.0V < Vdd < 4.75V.
Timer Capt u re Pul s e Width 50a
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
– – ns
Maximum Frequency, No Capture – – 49.2 MHz 4.75V < Vdd < 5.25V.
Maximum Frequency, With Capture – – 24.6 MHz
Counter Enable Pulse Width 50a– – ns
Maximum Frequency, No Enable Input – – 49.2 MHz 4.75V < Vdd < 5.25V.
Maximum Frequency, Enable Input – – 24.6 MHz
Dead Band Kill Pulse Wid th:
Asynchronous Restart Mode 20 – – ns
Synchronous Restart Mode 50a– – ns
Disable Mode 50a– – ns
Maximum Frequenc y – – 49.2 MHz 4.75V < Vdd < 5.25V.
CRCPRS
(PRS Mode) Maximum Inpu t Clock Fr equenc y – – 49.2 MHz 4.75V < Vdd < 5.25V.
CRCPRS
(CRC Mode) Maximum Input Clock Fr equenc y – – 24.6 MHz
SPIM Maximum Input Clock Fr equenc y – – 8.2 MHz Maximum data rate at 4.1 MH z due to 2 x over
clocking.
SPIS Maximum Input Clock Fr equenc y – – 4.1 ns
Width of SS_ Negated Between Transmissions 50a– – ns
Transmitter Maximum Input Clock Frequency b
Silicon A
Silicon B
b. Refer to the Order ing Info rm atio n chapter on page 4 2.
–
–
–
–
16.4
24.6
MHz
MHz
Maximum data rate at 2.05 MHz due to 8 x over
clocking.
Maximum data rate at 3.08 MHz due to 8 x over
clocking.
Receiver Maximum Input Clock Frequency b
Silicon A
Silicon B
–
–
–
–
16.4
24.6
MHz
MHz
Maximum data rate at 2.05 MHz due to 8 x over
clocking.
Maximum data rate at 3.08 MHz due to 8 x over
clocking.
August 3, 2004 Document No. 38-12012 Rev. *I 33
CY8C27x43 Final Data Sheet 3. Electrical Specifications
3.4.5 AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-23. 5V AC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units Notes
TROB Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High –
––
–2.5
2.5
µs
µs
TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High –
––
–2.2
2.2
µs
µs
SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Power = Low
Power = High 0.65
0.65 –
––
–V/µs
V/µs
SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Power = Low
Power = High 0.65
0.65 –
––
–V/µs
V/µs
BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Power = Low
Power = High
0.8
0.8 –
––
–MHz
MHz
BWOB Large Signal Bandwidth, 1Vpp, 3dB BW , 100pF Load
Power = Low
Power = High
300
300 –
––
–kHz
kHz
Table 3-24. 3.3V AC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units Notes
TROB Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High –
––
–3.8
3.8
µs
µs
TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High –
––
–2.6
2.6
µs
µs
SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Power = Low
Power = High 0.5
0.5 –
––
–V/µs
V/µs
SRFOB Falling Sl ew Rate (80% to 20%), 1V Step, 100pF Load
Power = Low
Power = High 0.5
0.5 –
––
–V/µs
V/µs
BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load
Power = Low
Power = High
0.7
0.7 –
––
–MHz
MHz
BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
Power = Low
Power = High
200
200 –
––
–kHz
kHz
August 3, 2004 Document No. 38-12012 Rev. *I 34
CY8C27x43 Final Data Sheet 3. Electrical Specifications
3.4.6 AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
3.4. 7 AC Programmin g Spec ificat ions
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 3-25. 5V AC Extern al Clock Specifications
Symbol Description Min Typ Max Units Notes
FOSCEXT Frequency 0.093 –24.6MHz
– Hi gh Period 20.6 –5300 ns
– Low Period 20.6 ––ns
– Power Up IMO to Switch 150 – – µs
Ta ble 3-26. 3.3V AC External Clock Specifications
Symbol Description Min Typ Max Units Notes
FOSCEXT Frequency with CPU Clock divide by 1a
a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
0.093 –12.3MHz
FOSCEXT Frequency with CPU Clock divide by 2 or greaterb
b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty per-
cent duty cycle requirement is met.
0.186 –24.6MHz
– Hi gh Period wi th CPU Clock divide by 1 41.7 –5300 ns
– Low Period wi th CPU Clock divide by 1 41.7 ––ns
– Power Up IMO to Switch 150 – – µs
Table 3-27. AC Programming Specifications
Symbol Description Min Typ Max Units Notes
TRSCLK Rise Time of SCLK 1 – 20 ns
TFSCLK Fall Time of SCL K 1 – 20 ns
TSSCLK Data Set up Time to Falling Edge of SCLK 40 – – ns
THSCLK Data Hold Time from Falling Edge of SCLK 40 – – ns
FSCLK Frequency of SCLK 0 – 8 MHz
TERASEB Flash Erase Time (Block) –10 –ms
TWRITE Flash Block Write Time –10 –ms
TDSCLK Data Out Delay from Falling Edge of SCLK – – 45 ns Vdd > 3.6
TDSCLK3 Data Out Delay from Falling Edge of SCLK – – 50 ns 3.0 ≤ Vdd ≤ 3.6
August 3, 2004 Document No. 38-12012 Rev. *I 35
CY8C27x43 Final Data Sheet 3. Electrical Specifications
3.4.8 AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Figure 3-9. Definition for Timing for Fast/Standard Mode on the I2C Bus
Table 3-28. AC Characteristics of the I2C SDA and SCL Pins
Symbol Description Sta ndard Mod e Fast Mode Units NotesMin Max Min Max
FSCLI2C SCL Clock Frequency 0 100 0 400 kHz
THDSTAI2C Hold Time (repeated) ST ART Condition. After this period, the
first clock pulse is generated. 4.0 –0.6–µs
TLOWI2C LOW Period of the SCL Clock 4.7 –1.3–µs
THIGHI2C HIGH Period of the SCL Clock 4.0 –0.6–µs
TSUSTAI2C Set-up Time for a Repeated START Condition 4.7 –0.6–µs
THDDATI2C Data Hold Time 0 –0–µs
TSUDATI2C Data Set-up Time 250 –100a
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if
the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
–ns
TSUSTOI2C Set-up Time for STOP Condition 4.0 –0.6–µs
TBUFI2C Bus Free Time Between a STOP and START Condition 4.7 –1.3–µs
TSPI2C Pulse Width of spikes are suppressed by the input filter . –– 0 50 ns
S
DA
SCL
SSr SP
TBUFI2C
TSPI2C
THDSTAI2C
TSUSTOI2C
TSUSTAI2C
TLOWI2C
THIGHI2C
THDDATI2C
THDSTAI2C
TSUDATI2C
August 3, 2004 © Cypress MicroSystems, Inc. 2003 — Document No. 38-12012 Rev. *I 36
4. Packaging Information
This chapter illustrates the packaging specifications for the CY8C27x43 PSoC device, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dime ns ion s at
http://www.cypress.com/support/link.cfm?mr=poddim.
4.1 Packaging Dimensions
Figure 4-1. 8-Lead (300-Mil) PDIP
51-85075 - *A
August 3, 2004 Document No. 38-12012 Rev. *I 37
CY8C27x43 Final Data Sheet 4. Packaging Information
Figure 4-2. 20-Lead (210-Mil) SSOP
Figure 4-3. 20-Lead (300-Mil) Molded SOIC
51-85077 - *C
51-85024 - *B
August 3, 2004 Document No. 38-12012 Rev. *I 38
CY8C27x43 Final Data Sheet 4. Packaging Information
Figure 4-4. 28-Lead (300-Mil) Molded DIP
Figure 4-5. 28-Lead (210-Mil) SSOP
51-85014 - *D
51-85079 - *C
August 3, 2004 Document No. 38-12012 Rev. *I 39
CY8C27x43 Final Data Sheet 4. Packaging Information
Figure 4-6. 28-Lead (300-Mil) Molded SOIC
Figure 4-7. 44-Lead TQFP
51-85026 - *C
51-85064-B
51-85064 - *B
August 3, 2004 Document No. 38-12012 Rev. *I 40
CY8C27x43 Final Data Sheet 4. Packaging Information
Figure 4-8. 48-Lead (300-Mil) SSOP
Figure 4-9. 48-Lead (7x7 mm) MLF
51-85061-C
51-85061 - *C
0.80 DIA.
6.70
6.90
C
1.00 MAX.
N
SEATING
PLANE
N
2
2
0.23±0.05
0.50
11
0.08
0°-12°
0.30-0.45
0.05 MAX.
C
0.20 REF.
0.80 MAX.
PIN1 ID
5.45
0.42±0.18
(4X)
7.10
6.80
6.70
6.80
7.10
6.90
5.55
5.45
5.55
0.20 R.
0.45
Y
X
TOP VIEW BOTTOM VIEW
SIDE VIEW
E-PAD
DIMENSIONS IN mm MIN.
MAX.
E-PAD SIZE PADDLE SIZE
51X51 53X53
(X, Y MAX.) 51-85152 - *B
August 3, 2004 Document No. 38-12012 Rev. *I 41
CY8C27x43 Final Data Sheet 4. Packaging Information
4.2 Thermal Impedances
4.3 Capacitance on Crystal Pins
Table 4-1. Thermal Impedances per Package
Package Typical θJA *
8 PDIP 120 oC/W
20 SSOP 95 oC/W
20 SOIC 79 oC/W
28 PDIP 67 oC/W
28 SSOP 95 oC/W
28 SOIC 71 oC/W
44 TQFP 58 oC/W
48 SSOP 69 oC/W
48 MLF 18 oC/W
* TJ = TA + POWER x θJA
Table 4-2: Typical Package Capacitance on Crystal Pins
Package Package Capacitance
8 PDIP 2.8 pF
20 SSOP 2.6 pF
20 SOIC 2.5 pF
28 PDIP 3.5 pF
28 SSOP 2.8 pF
28 SOIC 2.7 pF
44 TQFP 2.6 pF
48 SSOP 3.3 pF
48 MLF 2.3 pF
August 3, 2004 Document No. 38-12012 Rev. *I 42
5. Ordering Information
The following table lists the CY8C27x43 PSoC device family’s key package features and ordering codes.
Table 5-1. CY8C27x43 PSoC Device Family Key Features and Ordering Information
Package Ordering
Code
Flash
(Kbytes)
RAM
(Bytes)
Switch Mo de
Pump
Temperature
Range
Digital Blocks
(Rows of 4)
Analog Blocks
(Col umns of 3)
Digital IO
Pins
Analog
Inputs
Analog
Outputs
XRES Pin
CY8C27x43 Silicon B – These parts are lead free and offer the following improvements. The DEC_CR1 register selections are enhanced to allow
any digital block to be the decimator clock source, the ECO EX and ECO EXW bits in the CPU_SCR1 register are readable, and the accuracy of
the analog reference is enhanced (see the Electrical Specifications chapter). All silicon A errata are fixed in silicon B.
8 Pin (300 Mil) DIP CY8C27143-24PXI 16 256 No -40C to +85C 812 6 4 4 No
20 Pin (210 Mil) SSOP CY8C27243-24PVXI 16 256 Yes -40C to +85C 812 16 8 4 Yes
20 Pin (210 Mil) SSOP
(Tape and Reel) CY8C27243-24PVXIT 16 256 Yes -40C to +85C 812 16 8 4 Yes
20 Pin (300 Mil) SOIC CY8C27243-24SXI 16 256 Yes -40C to +85C 812 16 8 4 Yes
20 Pin 300 Mil) SOIC
(Tape and Reel) CY8C27243-24SXIT 16 256 Yes -40C to +85C 812 16 8 4 Yes
28 Pin (300 Mil) DIP CY8C27443-24PXI 16 256 Yes -40C to +85C 812 24 12 4Yes
28 Pin (210 Mil) SSOP CY8C27443-24PVXI 16 256 Yes -40C to +85C 812 24 12 4Yes
28 Pin (210 Mil) SSOP
(Tape and Reel) CY8C27443-24PVXIT 16 256 Yes -40C to +85C 812 24 12 4Yes
28 Pin (300 Mil) SOIC CY8C27443-24SXI 16 256 Yes -40C to +85C 812 24 12 4Yes
28 Pin (300 Mil) SOIC
(Tape and Reel) CY8C27443-24SXIT 16 256 Yes -40C to +85C 812 24 12 4Yes
44 Pin TQFP CY8C27543-24AXI 16 256 Yes -40C to +85C 812 40 12 4Yes
44 Pin TQFP
(Tape and Reel) CY8C27543-24AXIT 16 256 Yes -40C to +85C 812 40 12 4Yes
48 Pin (300 Mil) SSOP CY8C27643-24PVXI 16 256 Yes -40C to +85C 812 44 12 4Yes
48 Pin (300 Mil) SSOP
(Tape and Reel) CY8C27643-24PVXIT 16 256 Yes -40C to +85C 812 44 12 4Yes
48 Pin (7x7) MLF CY8C27643-24LFXI 16 256 Yes -40C to +85C 812 44 12 4Yes
48 Pin (7x7) MLF
(Tape and Reel) CY8C27643-24LFXIT 16 256 Yes -40C to +85C 812 44 12 4Yes
CY8C27x43 Silicon A – Silicon A is not recommended for new designs.
8 Pin (300 Mil) DIP CY8C27143-24PI 16 256 No -40C to +85C 812 6 4 4 No
20 Pin (210 Mil) SSOP CY8C27243-24PVI 16 256 Yes -40C to +85C 812 16 8 4 Yes
20 Pin (210 Mil) SSOP
(Tape and Reel) CY8C27243-24PVIT 16 256 Yes -40C to +85C 812 16 8 4 Yes
20 Pin (300 Mil) SOIC CY8C27243-24SI 16 256 Yes -40C to +85C 812 16 8 4 Yes
20 Pin 300 Mil) SOIC
(Tape and Reel) CY8C27243-24SIT 16 256 Yes -40C to +85C 812 16 8 4 Yes
28 Pin (300 Mil) DIP CY8C27443-24PI 16 256 Yes -40C to +85C 812 24 12 4Yes
28 Pin (210 Mil) SSOP CY8C27443-24PVI 16 256 Yes -40C to +85C 812 24 12 4Yes
August 3, 2004 Document No. 38-12012 Rev. *I 43
CY8C27x43 Final Data Sheet 5. Ordering Information
5.1 Ordering Code Definitions
28 Pin (210 Mil) SSOP
(Tape and Reel) CY8C27443-24PVIT 16 256 Yes -40C to +85C 812 24 12 4Yes
28 Pin (300 Mil) SOIC CY8C27443-24SI 16 256 Yes -40C to +85C 812 24 12 4Yes
28 Pin (300 Mil) SOIC
(Tape and Reel) CY8C27443-24SIT 16 256 Yes -40C to +85C 812 24 12 4Yes
44 Pin TQFP CY8C27543-24AI 16 256 Yes -40C to +85C 812 40 12 4Yes
44 Pin TQFP
(Tape and Reel) CY8C27543-24AIT 16 256 Yes -40C to +85C 812 40 12 4Yes
48 Pin (300 Mil) SSOP CY8C27643-24PVI 16 256 Yes -40C to +85C 812 44 12 4Yes
48 Pin (300 Mil) SSOP
(Tape and Reel) CY8C27643-24PVIT 16 256 Yes -40C to +85C 812 44 12 4Yes
48 Pin (7x7) MLF CY8C27643-24LFI 16 256 Yes -40C to +85C 812 44 12 4Yes
48 Pin (7x7) MLF
(Tape and Reel) CY8C27643-24LFIT 16 256 Yes -40C to +85C 812 44 12 4Yes
Table 5-1. CY8C27x43 PSoC Device Family Key Features and Ordering Information (continued)
Package Ordering
Code
Flash
(Kbytes)
RAM
(Bytes)
Switch Mode
Pump
Temperature
Range
Digital Blocks
(Rows of 4)
Analog Blocks
(Columns of 3)
Digital IO
Pins
Analog
Inputs
Analog
Outputs
XRES Pin
C
Y 8 C 27 xxx-SPxx
Package Ty pe: Thermal Rating:
P = PDIP PX = PDI P Pb Free C = Commercial
S = SOIC SX = SOIC Pb Free I = Industrial
PV = SSOP PVX = SSOP Pb Free E = Extended
LF = MLF LFX = MLF Pb Free
A = TQFP AX = TQFP Pb Free
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress MicroSystems
Company ID: CY = Cypress
August 3, 2004 © Cypress MicroSystems, Inc. 2002 – 2004 — Document No. 38-12012 Rev. *I 44
6. Sales and Service Information
To obt ain info rmatio n about Cypress Micro System s or PSoC sa les an d techn ical s upport, reference the follow ing i nforma tion or go to
the section titled “Getting Started” on page 4 in this document.
Cypress MicroSystems
6.1 Revision History
6.2 Copyrights and Code Protection
Copyrights
© Cypress MicroSystems, Inc. 2000 – 2004. All rights reserved. PSoC™, PSoC Designer™, and Programmable System-on-Chip™ are trademarks of Cypress MicroSys-
tems, Inc. All other trademarks or registered trademarks referenced herein are property of the respective corporations.
The information contained herein is subject to change without notice. Cypress MicroSystems assumes no responsibility for the use of any circuitry other than circuitry
embodied in a Cypress MicroSystems product. Nor does it convey or imply any license under patent or other rights. Cypress MicroSys tem s does n ot a u tho riz e it s pr odu c ts
for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of
Cypress MicroSystems products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress
MicroSystems against all charges. Cypress MicroSystems products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety
applicati ons, unles s pursuant to an express writt en agr eement wi th Cypr ess Mi croSystems.
Flash Code Protection
Note the following details of the Flash code protection features on Cypress MicroSystems devices.
Cypress MicroSystems products meet the specifications contained in their particular Cypress MicroSystems Data Sheets. Cypress MicroSystems believes that its family of
products is one of the most secure fam ilies of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cyp ress Mi croSystems,
that ca n breach the code prot ection fe atures. An y of these meth ods, to ou r knowled ge, would b e dishonest an d possibl y illegal . Neither Cyp ress MicroSystems no r any
other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
Cypress MicroSystems is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress Micro-
Systems are committed to continuously improving the code protection features of our products.
2700 162nd Street SW
Building D
Ly nnwood, WA 98037
Phone: 800.669.0557
Facsimile: 425.787.4641
Web Sites: Company Information – http://www.cypress.com
Sal e s – http://www.cypress.com/aboutus/sales_locations.cfm
Technical Support – http://www.cypress.com/support/login.cfm
Table 6-1. CY8C27x43 Data Sheet Revision History
Document T itle: CY8C27143, CY8C27243, CY8C27443, CY8C27543, and CY8C27643 PSoC Mixed Signal Array Final Data Sheet
Document Number: 38-12012
Revision ECN # Issue Date Origin of Change Des cription of Change
** 127087 7/01/2003 New Silic o n. New document (Revision **).
*A 128780 7/29/2003 Engineering and
NWJ. New electrical spec additions, fix of Core Architecture links, corrections to some text, tables, draw-
ings, and format.
*B 128992 8/14/2003 NWJ Interrupt controller table fixed, refinements to Electrical Spec section and Register chapter .
*C 129283 8/28/2003 NWJ Significant changes to the Electrical Specifications section.
*D 129442 9/09/2003 NWJ Changes made to Electrical Spec section. Added 20/28-Lead SOIC packages and pinouts.
*E 130129 10/13/2003 NWJ Revised document for Silicon R evision A.
*F 130651 10/28/2003 NWJ Refinements to Electrical Specification section and I2C chapter .
*G 131298 11/18/2003 NWJ Revisions to GDI, RDI, and Digital Block chapters. Revisions to AC Digital Block Spec and miscella-
neous regi ster changes.
*H 229416 See ECN SFV New data sheet format and organization. Reference the PSoC Mixed Signal Array Technical Refer-
ence Manual for addit ional informat i o n. Title chan ge .
*I 247529 See ECN SFV Added Silicon B information to this dat a sheet.
Distribution: External Public Posting: None
