PSoCTM Mixed Signal Array Final Data Sheet CY8C27143, CY8C27243, CY8C27443, CY8C27543, and CY8C27643 Features Powerful Harvard Architecture Processor M8C Processor Speeds to 24 MHz 8x8 Multiply, 32-Bit Accumulate Low Power at High Speed 3.0 to 5.25 V Operating Voltage Operating Voltages Down to 1.0V Using OnChip Switch Mode Pump (SMP) Industrial Temperature Range: -40C to +85C Precision, Programmable Clocking Internal 2.5% 24/48 MHz Oscillator 24/48 MHz with Optional 32 kHz Crystal Optional External Oscillator, up to 24 MHz Internal Oscillator for Watchdog and Sleep Flexible On-Chip Memory 16K Bytes Flash Program Storage 50,000 Erase/Write Cycles 256 Bytes SRAM Data Storage In-System Serial Programming (ISSPTM) Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash Advanced Peripherals (PSoC Blocks) 12 Rail-to-Rail Analog PSoC Blocks Provide: - Up to 14-Bit ADCs - Up to 9-Bit DACs - Programmable Gain Amplifiers - Programmable Filters and Comparators 8 Digital PSoC Blocks Provide: - 8- to 32-Bit Timers, Counters, and PWMs - CRC and PRS Modules - Up to 2 Full-Duplex UARTs - Multiple SPITM Masters or Slaves - Connectable to all GPIO Pins Complex Peripherals by Combining Blocks Programmable Pin Configurations 25 mA Sink on all GPIO Pull up, Pull down, High Z, Strong, or Open Drain Drive Modes on all GPIO Up to 12 Analog Inputs on GPIO Four 30 mA Analog Outputs on GPIO Configurable Interrupt on all GPIO Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 System Bus SRAM 256 Bytes Global Analog Interconnect SROM Flash 16K CPU Core (M8C) Interrupt Controller Sleep and Watchdog Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM Digital Clocks Analog Block Array (2 Rows, 8 Blocks) (4 Columns, 12 Blocks) Multiply Accum. POR and LVD Decimator I 2C System Resets SYSTEM RESOURCES August 3, 2004 Analog Ref Analog Input Muxing Internal Voltage Ref. Complete Development Tools Free Development Software (PSoCTM Designer) Full-Featured, In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory The PSoCTM family consists of many Mixed Signal Array with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, as well as programmable interconnects. This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts and packages. The PSoC architecture, as illustrated on the left, is comprised of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global busing allows all the device resources to be combined into a complete custom system. The PSoC CY8C27x43 family can have up to five IO ports that connect to the global digital and analog interconnects, providing access to 8 digital blocks and 12 analog blocks. ANALOG SYSTEM Digital Block Array I2CTM Slave, Master, and Multi-Master to 400 kHz Watchdog and Sleep Timers User-Configurable Low Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference PSoCTM Functional Overview Analog Drivers PSoC CORE Global Digital Interconnect Additional System Resources The PSoC Core Switch Mode Pump The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO). The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture micro- (c) Cypress MicroSystems, Inc. 2002 - 2004 -- Document No. 38-12012 Rev. *I 1 CY8C27x43 Final Data Sheet PSoCTM Overview processor. The CPU utilizes an interrupt controller with 17 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT). Memory encompasses 16 KB of Flash for program storage, 256 bytes of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. PSoC GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin's drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. The Digital System The Digital System is composed of 8 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Port 5 Port 4 Port 3 Port 2 To System Bus Digital Clocks From Core Port 1 Port 0 To Analog System DIGITAL SYSTEM Digital peripheral configurations include those listed below. PWMs (8 to 32 bit) PWMs with Dead band (8 to 32 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8 bit with selectable parity (up to 2) SPI master and slave (up to 2) I2C slave and master (1 available as a System Resource) Cyclical Redundancy Checker/Generator (8 to 32 bit) IrDA (up to 2) Pseudo Random Sequence Generators (8 to 32 bit) The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled "PSoC Device Characteristics" on page 3. The Analog System The Analog System is composed of 12 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are listed below. Analog-to-digital converters (up to 4, with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR) Filters (2, 4, 6, and 8 pole band-pass, low-pass, and notch) Amplifiers (up to 4, with selectable gain to 48x) Instrumentation amplifiers (up to 2, with selectable gain to 93x) Comparators (up to 4, with 16 selectable thresholds) DACs (up to 4, with 6- to 9-bit resolution) Multiplying DACs (up to 4, with 6- to 9-bit resolution) High current output drivers (four with 30 mA drive as a Core Resource) 1.3V reference (as a System Resource) DTMF dialer Modulators Correlators Peak detectors Many other topologies possible Row 0 DBB00 DBB01 DCB02 4 Row Output Configuration Row Input Configuration Digital PSoC Block Array DCB03 4 8 8 Row 1 DBB10 DBB11 DCB12 8 4 Row Output Configuration Row Input Configuration 8 DCB13 4 GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Digital System Block Diagram August 3, 2004 Document No. 38-12012 Rev. *I 2 CY8C27x43 Final Data Sheet PSoCTM Overview Analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks, as shown in the figure below. P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] AGNDIn RefIn P0[7] P2[3] P2[1] Additional System Resources System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset. Brief statements describing the merits of each system resource are presented below. Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. A multiply accumulate (MAC) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math as well as digital filters. The decimator provides a custom hardware filter for digital signal processing applications including the creation of Delta Sigma ADCs. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3V reference provides an absolute reference for the analog system, including ADCs and DACs. An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.2V battery cell, providing a low cost boost converter. P2[6] P2[4] P2[2] P2[0] Array Input Configuration ACI3[1:0] Block Array ASC10 ASD11 ASC12 ASD13 ASD20 ASC21 ASD22 ASC23 PSoC Device Characteristics Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators M8C Interface (Address Bus, Data Bus, Etc.) Analog System Block Diagram August 3, 2004 AGNDIn RefIn Bandgap Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3 analog blocks. The following table lists the resources available for specific PSoC device groups. The PSoC device covered by this data sheet is shown in the second row of the table. PSoC Device Characteristics PSoC Part Number Analog Blocks ACB03 Analog Columns ACB02 Analog Outputs ACB01 Analog Inputs ACB00 Digital Blocks ACI2[1:0] Digital Rows ACI1[1:0] Digital IO ACI0[1:0] CY8C29x66 up to 64 4 16 12 4 4 12 CY8C27x43 up to 44 2 8 12 4 4 12 CY8C24x23 up to 24 1 4 12 2 2 6 CY8C24x23A up to 24 1 4 12 2 2 6 CY8C22x13 up to 16 1 4 8 1 1 3 Document No. 38-12012 Rev. *I 3 CY8C27x43 Final Data Sheet PSoCTM Overview Getting Started Development Tools The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, reference the PSoCTM Mixed Signal Array Technical Reference Manual. The Cypress MicroSystems PSoC Designer is a Microsoft(R) Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.) Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store at http://www.onfulfillment.com/cypressstore/ contains development kits, C compilers, and all accessories for PSoC development. Click on PSoC (Programmable System-on-Chip) to view a current list of available items. Tele-Training PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family. Context Sensitive Help Graphical Designer Interface PSoCTM Designer Results Free PSoC "Tele-training" is available for beginners and taught by a live marketing or application engineer over the phone. Five training classes are available to accelerate the learning curve including introduction, designing, debugging, advanced design, advanced analog, as well as application-specific classes covering topics like PSoC and the LIN bus. For days and times of the tele-training, see http://www.cypress.com/support/training.cfm. PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. Commands For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest PSoC device data sheets on the web at http://www.cypress.com/psoc. Importable Design Database PSoC Configuration Sheet Device Database Consultants PSoC Designer Core Engine TM Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant, go to the following Cypress support web site: http://www.cypress.com/support/cypros.cfm. Technical Support PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm. Application Database Manufacturing Information File Project Database User Modules Library Application Notes A long list of application notes will assist you in every aspect of your design effort. To locate the PSoC application notes, go to http://www.cypress.com/design/results.cfm. August 3, 2004 Emulation Pod Document No. 38-12012 Rev. *I In-Circuit Emulator Device Programmer PSoC Designer Subsystems 4 CY8C27x43 Final Data Sheet PSoCTM Overview PSoC Designer Software Subsystems Device Editor Debugger The Device Editor subsystem allows the user to select different onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. PSoC Designer sets up power-on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the framework is generated, the user can add application-specific code to flesh out the framework. It's also possible to change the selected components and regenerate the framework. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. Hardware Tools In-Circuit Emulator Design Browser The Design Browser allows users to select and import preconfigured designs into the user's project. Users can easily browse a catalog of preconfigured designs to facilitate time-to-design. Examples provided in the tools include a 300-baud modem, LIN Bus master and slave, fan controller, and magnetic card reader. Application Editor In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build. A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of the parallel or USB port. The base unit is universal and will operate with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. Assembler. The macro assembler allows the assembly code to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compiler. A C language compiler is available that supports Cypress MicroSystems' PSoC family devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the PSoC family devices. The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. August 3, 2004 Document No. 38-12012 Rev. *I 5 CY8C27x43 Final Data Sheet PSoCTM Overview Designing with User Modules The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses, and to the IO pins. Iterative development cycles permit you to adapt the hardware as well as the software. This substantially lowers the risk that you will have to select a different part to meet the final design requirements. Device Editor User Module Selection The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You pick the user modules you need for your project and map them onto the PSoC blocks with point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, you perform the "Generate Application" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions. August 3, 2004 Source Code Generator Generate Application Application Editor To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called "User Modules." User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals such as DTMF Generators and Bi-Quad analog filter sections. Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides highlevel functions to control and respond to hardware events at run-time. The API also provides optional interrupt service routines that you can adapt as needed. Placement and Parameter -ization Project Manager Source Code Editor Build Manager Build All Debugger Interface to ICE Storage Inspector Event & Breakpoint Manager User Module and Source Code Development Flows The next step is to write your main program, and any sub-routines using PSoC Designer's Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive "grep-style" patterns. A single mouse click invokes the Build Manager. It employs a professional-strength "makefile" system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a HEX file image suitable for programming. The last step in the development process takes place inside the PSoC Designer's Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. Document No. 38-12012 Rev. *I 6 CY8C27x43 Final Data Sheet PSoCTM Overview Document Conventions Table of Contents Acronyms Used For an in depth discussion and more information on your PSoC device, obtain the PSoC Mixed Signal Array Technical Reference Manual. This document encompasses and is organized into the following chapters and sections. The following table lists the acronyms that are used in this document. Acronym Description 1. AC alternating current ADC analog-to-digital converter API application programming interface CPU central processing unit CT continuous time DAC digital-to-analog converter DC direct current ECO external crystal oscillator EEPROM electrically erasable programmable read-only memory FSR full scale range GPIO general purpose IO GUI graphical user interface HBM human body model ICE in-circuit emulator ILO internal low speed oscillator IMO internal main oscillator IO input/output IPOR imprecise power on reset LSb least-significant bit LVD low voltage detect MSb most-significant bit PC program counter PLL phase-locked loop POR power on reset PPOR precision power on reset PSoCTM Programmable System-on-ChipTM PWM pulse width modulator RAM random access memory SC switched capacitor SLIMO slow IMO SMP switch mode pump Pin Information ............................................................. 8 1.1 Pinouts ................................................................... 8 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 8-Pin Part Pinout .................................................8 20-Pin Part Pinout ...............................................9 28-Pin Part Pinout .............................................10 44-Pin Part Pinout .............................................11 48-Pin Part Pinouts ...........................................12 2. Register Reference ..................................................... 14 2.1 Register Conventions ........................................... 14 2.2 Register Mapping Tables ..................................... 14 3. Electrical Specifications ............................................ 17 3.1 Absolute Maximum Ratings ................................ 18 3.2 Operating Temperature ....................................... 18 3.3 DC Electrical Characteristics ................................ 19 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8 3.3.9 3.4 DC Chip-Level Specifications .............................19 DC General Purpose IO Specifications ..............19 DC Operational Amplifier Specifications ............20 DC Analog Output Buffer Specifications ............22 DC Switch Mode Pump Specifications ...............23 DC Analog Reference Specifications .................24 DC Analog PSoC Block Specifications ...............26 DC POR and LVD Specifications .......................26 DC Programming Specifications ........................27 AC Electrical Characteristics ................................ 28 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 AC Chip-Level Specifications .............................28 AC General Purpose IO Specifications ..............30 AC Operational Amplifier Specifications .............31 AC Digital Block Specifications ..........................32 AC Analog Output Buffer Specifications .............33 AC External Clock Specifications .......................34 AC Programming Specifications .........................34 AC I2C Specifications .........................................35 4. Packaging Information ............................................... 36 4.1 Packaging Dimensions ......................................... 36 4.2 Thermal Impedances .......................................... 41 4.3 Capacitance on Crystal Pins ............................... 41 Units of Measure 5. A units of measure table is located in the Electrical Specifications section. Table 3-1 on page 17 lists all the abbreviations used to measure the PSoC devices. Ordering Information .................................................. 42 5.1 Ordering Code Definitions ................................... 43 6. Sales and Service Information .................................. 44 6.1 Revision History ................................................... 44 6.2 Copyrights and Code Protection .......................... 44 Numeric Naming Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexidecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (e.g., 01010100b' or `01000011b'). Numbers not indicated by an `h' or `b' are decimal. August 3, 2004 Document No. 38-12012 Rev. *I 7 1. Pin Information This chapter describes, lists, and illustrates the CY8C27x43 PSoC device pins and pinout configurations. 1.1 Pinouts The CY8C27x43 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a "P") is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO. 1.1.1 8-Pin Part Pinout Table 1-1. 8-Pin Part Pinout (PDIP) Pin No. Type Pin Name Description Digital Analog 1 IO IO P0[5] Analog column mux input and column output. 2 IO IO P0[3] Analog column mux input and column output. 3 IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL) Vss Ground connection. P1[0] Crystal Output (XTALout), I2C Serial Data (SDA) 4 Power 5 IO 6 IO IO P0[2] Analog column mux input and column output. 7 IO IO P0[4] Analog column mux input and column output. Vdd Supply voltage. 8 Power CY8C27143 8-Pin PSoC Device AIO, P0[5] AIO, P0[3] I2C SCL, XTALin, P1[1] Vss 8 1 2 PDIP 7 6 3 5 4 Vdd P0[4], AIO P0[2], AIO P1[0], XTALout, I2C SDA LEGEND: A = Analog, I = Input, and O = Output. August 3, 2004 Document No. 38-12012 Rev. *I 8 CY8C27x43 Final Data Sheet 1.1.2 1. Pin Information 20-Pin Part Pinout Table 1-2. 20-Pin Part Pinout (SSOP, SOIC) Pin No. Type Digital Analog Pin Name 1 IO I P0[7] Analog column mux input. 2 IO IO P0[5] Analog column mux input and column output. 3 IO IO P0[3] Analog column mux input and column output. 4 IO I P0[1] Analog column mux input. SMP Switch Mode Pump (SMP) connection to external components required. 5 Power 6 IO P1[7] I2C Serial Clock (SCL) 7 IO P1[5] I2C Serial Data (SDA) 8 IO P1[3] 9 IO 10 Power P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL) Vss Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA) 11 IO P1[0] 12 IO P1[2] 13 IO P1[4] 14 IO P1[6] 15 Input XRES 1 2 3 4 5 6 7 8 9 10 SSOP SOIC 20 19 18 17 16 15 14 13 12 11 Vdd P0[6], AI P0[4], AIO P0[2], AIO P0[0], AI XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA Active high external reset with internal pull down. IO I P0[0] Analog column mux input. 17 IO IO P0[2] Analog column mux input and column output. 18 IO IO P0[4] Analog column mux input and column output. 19 IO I P0[6] Analog column mux input. Vdd Supply voltage. Power AI, P0[7] AIO, P0[5] AIO, P0[3] AI, P0[1] SMP I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss Optional External Clock Input (EXTCLK) 16 20 CY8C27243 20-Pin PSoC Device Description LEGEND: A = Analog, I = Input, and O = Output. August 3, 2004 Document No. 38-12012 Rev. *I 9 CY8C27x43 Final Data Sheet 1.1.3 1. Pin Information 28-Pin Part Pinout Table 1-3. 28-Pin Part Pinout (PDIP, SSOP, SOIC) Pin No. Type Digital Analog Pin Name 1 IO I P0[7] Analog column mux input. 2 IO IO P0[5] Analog column mux input and column output. 3 IO IO P0[3] Analog column mux input and column output. 4 IO I P0[1] Analog column mux input. 5 IO 6 IO 7 IO 8 IO 9 P2[7] P2[5] I P2[3] I P2[1] Direct switched capacitor block input. SMP Switch Mode Pump (SMP) connection to external components required. Power Direct switched capacitor block input. 10 IO P1[7] I2C Serial Clock (SCL) 11 IO P1[5] I2C Serial Data (SDA) 12 IO P1[3] 13 IO 14 Power P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL) Vss Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA) 15 IO P1[0] 16 IO P1[2] 17 IO P1[4] 18 IO P1[6] 19 Input XRES Active high external reset with internal pull down. Direct switched capacitor block input. IO I P2[0] 21 IO I P2[2] Direct switched capacitor block input. 22 IO P2[4] External Analog Ground (AGND) 23 IO P2[6] External Voltage Reference (VRef) 24 IO I P0[0] Analog column mux input. 25 IO IO P0[2] Analog column mux input and column output. 26 IO IO P0[4] Analog column mux input and column output. 27 IO I P0[6] Analog column mux input. Vdd Supply voltage. Power AI, P0[7] AIO, P0[5] AIO, P0[3] AI, P0[1] P2[7] P2[5] AI, P2[3] AI, P2[1] SMP I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PDIP SSOP SOIC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6], AI P0[4], AIO P0[2], AIO P0[0], AI P2[6], External VRef P2[4], External AGND P2[2], AI P2[0], AI XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA Optional External Clock Input (EXTCLK) 20 28 CY8C27443 28-Pin PSoC Device Description LEGEND: A = Analog, I = Input, and O = Output. August 3, 2004 Document No. 38-12012 Rev. *I 10 CY8C27x43 Final Data Sheet 1.1.4 1. Pin Information 44-Pin Part Pinout Table 1-4. 44-Pin Part Pinout (TQFP) P4[7] 5 IO P4[5] 6 IO P4[3] 7 IO Switch Mode Pump (SMP) connection to external components required. 9 IO P3[7] 10 IO P3[5] 11 IO P3[3] 12 IO P3[1] 13 IO P1[7] I2C Serial Clock (SCL) 14 IO P1[5] I2C Serial Data (SDA) 15 IO P1[3] 16 IO Power P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL) Vss Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA) 18 IO P1[0] 19 IO P1[2] 20 IO P1[4] 21 IO P1[6] 22 IO P3[0] 23 IO P3[2] 24 IO P3[4] 25 IO 26 Optional External Clock Input (EXTCLK) 1 2 3 4 5 6 7 8 9 10 11 TQFP 33 32 31 30 29 28 27 26 25 24 23 P2[4], External AGND P2[2], AI P2[0], AI P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[6] Input XRES Active high external reset with internal pull down. 27 IO P4[0] 28 IO P4[2] 29 IO P4[4] 30 IO 31 IO I P2[0] 32 IO I P2[2] Direct switched capacitor block input. 33 IO P2[4] External Analog Ground (AGND) 34 IO P2[6] External Voltage Reference (VRef) 35 IO I P0[0] Analog column mux input. 36 IO IO P0[2] Analog column mux input and column output. 37 IO IO P0[4] Analog column mux input and column output. 38 IO I P0[6] Analog column mux input. Vdd Supply voltage. 39 P2[5] AI, P2[3] AI, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] 12 13 14 15 SMP 44 P4[1] Power 17 P2[6], External VRef IO 34 Direct switched capacitor block input. 4 22 P2[1] AI AIO AIO AI I I2C SDA, XTALout, P1[0] P1[2] EXTCLK, P1[4] P1[6] P3[0] Direct switched capacitor block input. IO 16 17 18 19 20 21 P2[3] 3 P0[6], P0[4], P0[2], P0[0], P2[5] I2C SCL, XTALin, P1[1] Vss I P0[3], AIO P0[5], AIO IO I2C SDA, P1[5] P1[3] IO 2 P2[7] P0[1], AI 1 8 CY8C27543 44-Pin PSoC Device Description 38 37 36 35 Pin Name P0[7], AI Vdd Analog 43 42 41 40 39 Type Digital P3[1] I2C SCL, P1[7] Pin No. P4[6] Power Direct switched capacitor block input. 40 IO I P0[7] Analog column mux input. 41 IO IO P0[5] Analog column mux input and column output. 42 IO IO P0[3] Analog column mux input and column output. 43 IO I P0[1] Analog column mux input. 44 IO P2[7] LEGEND: A = Analog, I = Input, and O = Output. August 3, 2004 Document No. 38-12012 Rev. *I 11 CY8C27x43 Final Data Sheet 1.1.5 1. Pin Information 48-Pin Part Pinouts Table 1-5. 48-Pin Part Pinout (SSOP) Pin No. Type Digital Analog Pin Name 1 IO I P0[7] Analog column mux input. 2 IO IO P0[5] Analog column mux input and column output. 3 IO IO P0[3] Analog column mux input and column output. 4 IO I P0[1] Analog column mux input. 5 IO 6 IO 7 IO I P2[3] Direct switched capacitor block input. 8 IO I P2[1] Direct switched capacitor block input. 9 IO P4[7] 10 IO P4[5] 11 IO P4[3] 12 IO P4[1] 13 P2[7] P2[5] Power SMP Switch Mode Pump (SMP) connection to external components required. 14 IO P3[7] 15 IO P3[5] 16 IO P3[3] 17 IO P3[1] 18 IO P5[3] 19 IO P5[1] 20 IO P1[7] I2C Serial Clock (SCL) 21 IO P1[5] I2C Serial Data (SDA) 22 IO P1[3] 23 IO 24 Power P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL) Vss Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA) 25 IO P1[0] 26 IO P1[2] 27 IO P1[4] 28 IO P1[6] 29 IO P5[0] 30 IO P5[2] 31 IO P3[0] 32 IO P3[2] 33 IO P3[4] 34 IO 35 AI, P0[7] AIO, P0[5] AIO, P0[3] AI, P0[1] P2[7] P2[5] AI, P2[3] AI, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Vdd P0[6], AI P0[2], AIO P0[4], AIO P0[0], AI P2[6], External VRef P2[4], External AGND P2[2], AI P2[0], AI P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] P5[2] P5[0] P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA Optional External Clock Input (EXTCLK) P3[6] Input XRES Active high external reset with internal pull down. 36 IO P4[0] 37 IO P4[2] 38 IO P4[4] 39 IO 40 IO I P2[0] 41 IO I P2[2] Direct switched capacitor block input. 42 IO P2[4] External Analog Ground (AGND) 43 IO P2[6] External Voltage Reference (VRef) 44 IO I P0[0] Analog column mux input. 45 IO IO P0[2] Analog column mux input and column output. 46 IO IO P0[4] Analog column mux input and column output. 47 IO I P0[6] Analog column mux input. Vdd Supply voltage. 48 CY8C27643 48-Pin PSoC Device Description P4[6] Power Direct switched capacitor block input. LEGEND: A = Analog, I = Input, and O = Output. August 3, 2004 Document No. 38-12012 Rev. *I 12 CY8C27x43 Final Data Sheet 1. Pin Information Table 1-6. 48-Pin Part Pinout (MLF*) Direct switched capacitor block input. P2[1] Direct switched capacitor block input. 3 IO P4[7] 4 IO P4[5] 5 IO P4[3] 6 IO P3[7] 9 IO P3[5] 10 IO P3[3] 11 IO P3[1] 12 IO P5[3] 13 IO P5[1] 14 IO P1[7] I2C Serial Clock (SCL) 15 IO P1[5] I2C Serial Data (SDA) 16 IO P1[3] 17 IO 18 Power P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL) Vss Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA) 19 IO P1[0] 20 IO P1[2] 21 IO P1[4] 22 IO P1[6] 23 IO P5[0] 24 IO P5[2] 25 IO P3[0] 26 IO P3[2] 27 IO P3[4] 28 IO 29 Optional External Clock Input (EXTCLK) (Top View) P2[4], External AGND P2[2], AI P2[0], AI P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] P3[6] Input XRES Active high external reset with internal pull down. 30 IO P4[0] 31 IO P4[2] 32 IO P4[4] 33 IO 34 IO I P2[0] 35 IO I P2[2] Direct switched capacitor block input. 36 IO P2[4] External Analog Ground (AGND) 37 IO P2[6] External Voltage Reference (VRef) 38 IO I P0[0] Analog column mux input. 39 IO IO P0[2] Analog column mux input and column output. 40 IO IO P0[4] Analog column mux input and column output. 41 IO I P0[6] Analog column mux input. Vdd Supply voltage. 42 MLF 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 17 18 19 20 21 22 23 24 IO 1 2 3 4 5 6 I2C SCL, XTALin, P1[1] Vss I2C SDA, XTALout, P1[0] P1[2] EXTCLK, P1[4] P1[6] P5[0] P5[2] 8 AI, P2[3] AI, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] 15 16 Switch Mode Pump (SMP) connection to external components required. I2C SDA, P1[5] P1[3] SMP 48 47 46 45 44 43 P4[1] Power 38 37 P2[3] I Vdd P0[6], AI P0[4], AIO P0[2], AIO P0[0], AI P2[6], External VRef I IO 42 41 40 39 IO 2 P2[5] P2[7] P0[1], AI 1 7 CY8C27643 48-Pin PSoC Device Description P0[3], AIO P0[5], AIO P0[7], AI Pin Name Analog 13 14 Type Digital P5[1] I2C SCL, P1[7] Pin No. P4[6] Power Direct switched capacitor block input. 43 IO I P0[7] Analog column mux input. 44 IO IO P0[5] Analog column mux input and column output. 45 IO IO P0[3] Analog column mux input and column output. 46 IO I P0[1] Analog column mux input. 47 IO P2[7] 48 IO P2[5] LEGEND: A = Analog, I = Input, and O = Output. * The MLF package has a center pad that must be connected to ground (Vss). August 3, 2004 Document No. 38-12012 Rev. *I 13 2. Register Reference This chapter lists the registers of the CY8C27x43 PSoC device. For detailed register information, reference the PSoCTM Mixed Signal Array Technical Reference Manual. 2.1 Register Conventions The register conventions specific to this section are listed in the following table. Convention Description R Read register or bit(s) W Write register or bit(s) L Logical register or bit(s) C Clearable register or bit(s) # Access is bit specific August 3, 2004 2.2 Register Mapping Tables The PSoC device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in bank 1. Note In the following register mapping tables, blank fields are reserved and should not be accessed. (c) Cypress MicroSystems, Inc. 2003 -- Document No. 38-12012 Rev. *I 14 CY8C27x43 Final Data Sheet 2. Register Reference Register Map Bank 0 Table: User Space INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL_X MUL_Y MUL_DH MUL_DL ACC_DR1 ACC_DR0 ACC_DR3 ACC_DR2 RW RW RW RW RW RW RW CPU_F RW RW RW RW RW RW RW CPU_SCR1 CPU_SCR0 Document No. 38-12012 Rev. *I Access I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 Addr (0,Hex) RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDIOLT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 RDI1RI B8 RDI1SYN B9 RDI1IS BA RDI1LT0 BB RDI1LT1 BC RDI1RO0 BD RDI1RO1 BE BF # Access is bit specific. Access August 3, 2004 ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 Addr (0,Hex) 00 RW 40 01 RW 41 02 RW 42 03 RW 43 04 RW 44 05 RW 45 06 RW 46 07 RW 47 08 RW 48 09 RW 49 0A RW 4A 0B RW 4B 0C RW 4C 0D RW 4D 0E RW 4E 0F RW 4F 10 RW 50 11 RW 51 12 RW 52 13 RW 53 14 RW 54 15 RW 55 16 RW 56 17 RW 57 18 58 19 59 1A 5A 1B 5B 1C 5C 1D 5D 1E 5E 1F 5F DBB00DR0 20 # AMX_IN 60 RW DBB00DR1 21 W 61 DBB00DR2 22 RW 62 DBB00CR0 23 # ARF_CR 63 RW DBB01DR0 24 # CMP_CR0 64 # DBB01DR1 25 W ASY_CR 65 # DBB01DR2 26 RW CMP_CR1 66 RW DBB01CR0 27 # 67 DCB02DR0 28 # 68 DCB02DR1 29 W 69 DCB02DR2 2A RW 6A DCB02CR0 2B # 6B DCB03DR0 2C # 6C DCB03DR1 2D W 6D DCB03DR2 2E RW 6E DCB03CR0 2F # 6F DBB10DR0 30 # ACB00CR3 70 RW DBB10DR1 31 W ACB00CR0 71 RW DBB10DR2 32 RW ACB00CR1 72 RW DBB10CR0 33 # ACB00CR2 73 RW DBB11DR0 34 # ACB01CR3 74 RW DBB11DR1 35 W ACB01CR0 75 RW DBB11DR2 36 RW ACB01CR1 76 RW DBB11CR0 37 # ACB01CR2 77 RW DCB12DR0 38 # ACB02CR3 78 RW DCB12DR1 39 W ACB02CR0 79 RW DCB12DR2 3A RW ACB02CR1 7A RW DCB12CR0 3B # ACB02CR2 7B RW DCB13DR0 3C # ACB03CR3 7C RW DCB13DR1 3D W ACB03CR0 7D RW DCB13DR2 3E RW ACB03CR1 7E RW DCB13CR0 3F # ACB03CR2 7F RW Blank fields are Reserved and should not be accessed. Name Access Addr (0,Hex) Name Access Addr (0,Hex) Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW # RW # RW RW RW RW RW RW RC W RC RC RW RW W W R R RW RW RW RW RL # # 15 CY8C27x43 Final Data Sheet 2. Register Reference Register Map Bank 1 Table: Configuration Space RW RW RW RW RW RW RW C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF GDI_O_IN D0 GDI_E_IN D1 GDI_O_OU D2 GDI_E_OU D3 D4 D5 D6 D7 D8 D9 DA DB DC OSC_GO_EN DD OSC_CR4 DE OSC_CR3 DF OSC_CR0 E0 OSC_CR1 E1 OSC_CR2 E2 VLT_CR E3 VLT_CMP E4 E5 E6 E7 IMO_TR E8 ILO_TR E9 BDG_TR EA ECO_TR EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 CPU_F F7 F8 F9 FA FB FC FD CPU_SCR1 FE CPU_SCR0 FF Document No. 38-12012 Rev. *I Access RW RW RW RW RW RW RW Addr (1,Hex) RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDIOLT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 RDI1RI B8 RDI1SYN B9 RDI1IS BA RDI1LT0 BB RDI1LT1 BC RDI1RO0 BD RDI1RO1 BE BF # Access is bit specific. Access August 3, 2004 ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 Addr (1,Hex) 00 RW 40 01 RW 41 02 RW 42 03 RW 43 04 RW 44 05 RW 45 06 RW 46 07 RW 47 08 RW 48 09 RW 49 0A RW 4A 0B RW 4B 0C RW 4C 0D RW 4D 0E RW 4E 0F RW 4F 10 RW 50 11 RW 51 12 RW 52 13 RW 53 14 RW 54 15 RW 55 16 RW 56 17 RW 57 18 58 19 59 1A 5A 1B 5B 1C 5C 1D 5D 1E 5E 1F 5F DBB00FN 20 RW CLK_CR0 60 RW DBB00IN 21 RW CLK_CR1 61 RW DBB00OU 22 RW ABF_CR0 62 RW 23 AMD_CR0 63 RW DBB01FN 24 RW 64 DBB01IN 25 RW 65 DBB01OU 26 RW AMD_CR1 66 RW 27 ALT_CR0 67 RW DCB02FN 28 RW ALT_CR1 68 RW DCB02IN 29 RW CLK_CR2 69 RW DCB02OU 2A RW 6A 2B 6B DCB03FN 2C RW 6C DCB03IN 2D RW 6D DCB03OU 2E RW 6E 2F 6F DBB10FN 30 RW ACB00CR3 70 RW DBB10IN 31 RW ACB00CR0 71 RW DBB10OU 32 RW ACB00CR1 72 RW 33 ACB00CR2 73 RW DBB11FN 34 RW ACB01CR3 74 RW DBB11IN 35 RW ACB01CR0 75 RW DBB11OU 36 RW ACB01CR1 76 RW 37 ACB01CR2 77 RW DCB12FN 38 RW ACB02CR3 78 RW DCB12IN 39 RW ACB02CR0 79 RW DCB12OU 3A RW ACB02CR1 7A RW 3B ACB02CR2 7B RW DCB13FN 3C RW ACB03CR3 7C RW DCB13IN 3D RW ACB03CR0 7D RW DCB13OU 3E RW ACB03CR1 7E RW 3F ACB03CR2 7F RW Blank fields are Reserved and should not be accessed. Name Access Addr (1,Hex) Name Access Addr (1,Hex) Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 RW RW RW RW RW RW RW RW RW RW RW R W W RW W RL # # 16 3. Electrical Specifications This chapter presents the DC and AC electrical specifications of the CY8C27x43 PSoC device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. Specifications are valid for -40oC TA 85oC and TJ 100oC, except where noted. Specifications for devices running at greater than 12 MHz are valid for -40oC TA 70oC and TJ 82oC. 5.25 Vdd Voltage lid n g Va ati n r pe gi o e R O 4.75 3.00 93 kHz CPU Frequency 12 MHz 24 MHz Figure 3-1. Voltage versus CPU Frequency The following table lists the units of measure that are used in this chapter. Table 3-1: Units of Measure Symbol Unit of Measure Symbol Unit of Measure degree Celsius W micro watts dB decibels mA milli-ampere fF femto farad ms milli-second Hz hertz mV milli-volts KB 1024 bytes nA nano ampere Kbit 1024 bits ns nanosecond kHz kilohertz nV nanovolts k kilohm ohm MHz megahertz pA pico ampere M megaohm pF pico farad A micro ampere pp peak-to-peak F micro farad ppm H micro henry ps picosecond s microsecond sps samples per second V micro volts sigma: one standard deviation micro volts root-mean-square V volts o C Vrms August 3, 2004 parts per million Document No. 38-12012 Rev. *I 17 CY8C27x43 Final Data Sheet 3.1 3. Electrical Specifications Absolute Maximum Ratings Table 3-2. Absolute Maximum Ratings Symbol Description Min Typ Max Units TSTG Storage Temperature -55 - +100 oC TA Ambient Temperature with Power Applied -40 - +85 o Vdd Supply Voltage on Vdd Relative to Vss -0.5 - +6.0 V VIO DC Input Voltage Vss- 0.5 - Vdd + 0.5 V - DC Voltage Applied to Tri-state Vss - 0.5 - Vdd + 0.5 V IMIO Maximum Current into any Port Pin -25 - +50 mA IMAIO Maximum Current into any Port Pin Configured as Analog Driver -50 - +50 mA ESD Electro Static Discharge Voltage 2000 - - V - Latch-up Current - - 200 mA 3.2 Notes Higher storage temperatures will reduce data retention time. C Human Body Model ESD Operating Temperature Table 3-3. Operating Temperature Symbol Description Min Typ Max Units TA Ambient Temperature -40 - +85 oC TJ Junction Temperature -40 - +100 oC August 3, 2004 Document No. 38-12012 Rev. *I Notes The temperature rise from ambient to junction is package specific. See "Thermal Impedances" on page 41. The user must limit the power consumption to comply with this requirement. 18 CY8C27x43 Final Data Sheet 3.3 3.3.1 3. Electrical Specifications DC Electrical Characteristics DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-4. DC Chip-Level Specifications Symbol Description Min Typ Max Units Notes Vdd Supply Voltage 3.00 - 5.25 V IDD Supply Current - 5 8 mA Conditions are Vdd = 5.0V, TA = 25 oC, CPU = 3 MHz, 48 MHz = Disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. IDD3 Supply Current - 3.3 6.0 mA Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3 MHz, 48 MHz = Disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. ISB Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT.a - 3 6.5 A Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC TA 55 oC. ISBH Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temperature.a - 4 25 A Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 oC < TA 85 oC. ISBXTL Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal.a - 4 7.5 A Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. Vdd = 3.3V, -40 oC TA ISBXTLH Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal at high temperature.a - 5 26 A Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. Vdd = 3.3V, 55 oC < TA 85 55 oC. o C. VREF Reference Voltage (Bandgap) for Silicon A b 1.275 1.300 1.325 V Trimmed for appropriate Vdd. VREF Reference Voltage (Bandgap) for Silicon B b 1.280 1.300 1.320 V Trimmed for appropriate Vdd. a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar functions enabled. b. Refer to the Ordering Information chapter on page 42. 3.3.2 DC General Purpose IO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-5. DC GPIO Specifications Symbol Description Min 4 Typ 5.6 Max 8 Units Notes k RPU Pull up Resistor RPD Pull down Resistor 4 5.6 8 k VOH High Output Level Vdd - 1.0 - - V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). VOL Low Output Level - - 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 0.8 V Vdd = 3.0 to 5.25 V Vdd = 3.0 to 5.25 VIL Input Low Level - - VIH Input High Level 2.1 - VH Input Hysterisis - 60 - mV IIL Input Leakage (Absolute Value) - 1 - nA Gross tested to 1 A. CIN Capacitive Load on Pins as Input - 3.5 10 pF Package and pin dependent. Temp = 25oC. COUT Capacitive Load on Pins as Output - 3.5 10 pF Package and pin dependent. Temp = 25oC. August 3, 2004 Document No. 38-12012 Rev. *I 19 CY8C27x43 Final Data Sheet 3.3.3 3. Electrical Specifications DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at 25C and are for design guidance only. Table 3-6. 5V DC Operational Amplifier Specifications Symbol VOSOA Description Min Typ Max Units Notes Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High - 1.6 10 mV Power = Medium, Opamp Bias = High - 1.3 8 mV Power = High, Opamp Bias = High - 1.2 7.5 mV TCVOSOA Average Input Offset Voltage Drift - 7.0 35.0 V/oC Gross tested to 1 A. IEBOA Input Leakage Current (Port 0 Analog Pins) - 20 - pA CINOA Input Capacitance (Port 0 Analog Pins) - 4.5 9.5 pF Package and pin dependent. Temp = 25oC. VCMOA Common Mode Voltage Range 0.0 - Vdd V Common Mode Voltage Range (high power or high opamp bias) 0.5 - Vdd - 0.5 The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. - - dB Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. - - dB Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. CMRROA GOLOA VOHIGHOA VOLOWOA ISOA PSRROA Common Mode Rejection Ratio Power = Low 60 Power = Medium 60 Power = High 60 Open Loop Gain Power = Low 60 Power = Medium 60 Power = High 80 High Output Voltage Swing (internal signals) Power = Low Vdd - 0.2 - - V Power = Medium Vdd - 0.2 - - V Power = High Vdd - 0.5 - - V Power = Low - - 0.2 V Power = Medium - - 0.2 V Power = High - - 0.5 V Power = Low, Opamp Bias = Low - 150 200 A Power = Low, Opamp Bias = High - 300 400 A Power = Medium, Opamp Bias = Low - 600 800 A Power = Medium, Opamp Bias = High - 1200 1600 A Power = High, Opamp Bias = Low - 2400 3200 A Power = High, Opamp Bias = High - 4600 6400 A Supply Voltage Rejection Ratio 60 - - dB Low Output Voltage Swing (internal signals) Supply Current (including associated AGND buffer) August 3, 2004 Document No. 38-12012 Rev. *I 0V VIN (Vdd - 2.25) or (Vdd - 1.25V) VIN Vdd. 20 CY8C27x43 Final Data Sheet 3. Electrical Specifications Table 3-7. 3.3V DC Operational Amplifier Specifications Symbol VOSOA Description Min Typ Max Units Notes Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High - 1.65 10 mV Power = Medium, Opamp Bias = High - 1.32 8 mV - 7.0 35.0 V/oC High Power is 5 Volts Only TCVOSOA Average Input Offset Voltage Drift IEBOA Input Leakage Current (Port 0 Analog Pins) - 20 - pA Gross tested to 1 A. CINOA Input Capacitance (Port 0 Analog Pins) - 4.5 9.5 pF Package and pin dependent. Temp = 25oC. VCMOA Common Mode Voltage Range 0.2 - Vdd - 0.2 V The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. CMRROA Common Mode Rejection Ratio - - dB Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. - - dB Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. GOLOA VOHIGHOA VOLOWOA ISOA PSRROA Power = Low 50 Power = Medium 50 Power = High 50 Open Loop Gain Power = Low 60 Power = Medium 60 Power = High 80 High Output Voltage Swing (internal signals) Power = Low Vdd - 0.2 - - V Power = Medium Vdd - 0.2 - - V Power = High is 5V only Vdd - 0.2 - - V Power = Low - - 0.2 V Power = Medium - - 0.2 V Power = High - - 0.2 V Power = Low, Opamp Bias = Low - 150 200 A Power = Low, Opamp Bias = High - 300 400 A Power = Medium, Opamp Bias = Low - 600 800 A Power = Medium, Opamp Bias = High - 1200 1600 A Power = High, Opamp Bias = Low - 2400 3200 A Power = High, Opamp Bias = High - 4600 6400 A Supply Voltage Rejection Ratio 50 - - dB Low Output Voltage Swing (internal signals) Supply Current (including associated AGND buffer) August 3, 2004 Document No. 38-12012 Rev. *I 0V VIN (Vdd - 2.25) or (Vdd - 1.25V) VIN Vdd. 21 CY8C27x43 Final Data Sheet 3.3.4 3. Electrical Specifications DC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-8. 5V DC Analog Output Buffer Specifications Symbol Description Min Typ Max Units VOSOB Input Offset Voltage (Absolute Value) - 3 12 mV TCVOSOB Average Input Offset Voltage Drift - +6 - V/C VCMOB Common-Mode Input Voltage Range 0.5 - Vdd - 1.0 V ROUTOB Output Resistance Power = Low - 1 - Power = High - 1 - High Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low 0.5 x Vdd + 1.3 - - V 0.5 x Vdd + 1.3 - - V VOHIGHOB Power = High VOLOWOB ISOB PSRROB Notes Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low - - 0.5 x Vdd - 1.3 V Power = High - - 0.5 x Vdd - 1.3 V Power = Low - 1.1 5.1 mA Power = High - 2.6 8.8 mA Supply Voltage Rejection Ratio 60 - - dB Supply Current Including Bias Cell (No Load) Table 3-9. 3.3V DC Analog Output Buffer Specifications Symbol Description Min Typ Max Units VOSOB Input Offset Voltage (Absolute Value) - 3 12 mV TCVOSOB Average Input Offset Voltage Drift - +6 - V/C VCMOB Common-Mode Input Voltage Range 0.5 - Vdd - 1.0 V ROUTOB Output Resistance Power = Low - 1 - Power = High - 1 - Power = Low 0.5 x Vdd + 1.0 - - V Power = High 0.5 x Vdd + 1.0 - - V Power = Low - - 0.5 x Vdd - 1.0 V Power = High - - 0.5 x Vdd - 1.0 V VOHIGHOB VOLOWOB ISOB High Output Voltage Swing (Load = 1k ohms to Vdd/2) Low Output Voltage Swing (Load = 1k ohms to Vdd/2) Supply Current Including Bias Cell (No Load) 0.8 2.0 mA Power = High - 2.0 4.3 mA Supply Voltage Rejection Ratio 60 - - dB Power = Low PSRROB Notes August 3, 2004 Document No. 38-12012 Rev. *I 22 CY8C27x43 Final Data Sheet 3.3.5 3. Electrical Specifications DC Switch Mode Pump Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-10. DC Switch Mode Pump (SMP) Specifications Symbol Description Min Typ Max Units Notes VPUMP 5V 5V Output Voltage 4.75 5.0 5.25 V Configuration of footnote a. Average, neglecting ripple. SMP trip voltage is set to 5.0V. VPUMP 3V 3V Output Voltage 3.00 3.25 3.60 V Configuration of footnote a. Average, neglecting ripple. SMP trip voltage is set to 3.25V. IPUMP Available Output Current VBAT = 1.5V, VPUMP = 3.25V 8 - - mA VBAT = 1.8V, VPUMP = 5.0V 5 - - mA SMP trip voltage is set to 5.0V. VBAT5V Input Voltage Range from Battery 1.8 - 5.0 V Configuration of footnote a. SMP trip voltage is set to 5.0V. VBAT3V Input Voltage Range from Battery 1.0 - 3.3 V Configuration of footnote a. SMP trip voltage is set to 3.25V. VBATSTART Minimum Input Voltage from Battery to Start Pump 1.1 - - V Configuration of footnote a. VPUMP_Line Line Regulation (over VBAT range) - 5 - %VO Configuration of footnote a. VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 3-16 on page 26. VPUMP_Load Load Regulation - 5 - %VO Configuration of footnote a. VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 3-16 on page 26. Configuration of footnote a. SMP trip voltage is set to 3.25V. VPUMP_Ripple Output Voltage Ripple (depends on capacitor/load) - 100 - mVpp Configuration of footnote a. Load is 5mA. E3 Efficiency 35 50 - % Configuration of footnote a. Load is 5 mA. SMP trip voltage is set to 3.25V. FPUMP Switching Frequency - 1.3 - MHz DCPUMP Switching Duty Cycle - 50 - % a. L1 = 2 H inductor, C1 = 10 F capacitor, D1 = Schottky diode. See Figure 3-2. D1 Vdd L1 VBAT + VPUMP C1 SMP Battery PSoCTM Vss Figure 3-2. Basic Switch Mode Pump Circuit August 3, 2004 Document No. 38-12012 Rev. *I 23 CY8C27x43 Final Data Sheet 3.3.6 3. Electrical Specifications DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Table 3-11. Silicon Revision A - 5V DC Analog Reference Specifications Symbol Description Min Typ Max Units BG Bandgap Voltage Reference 1.274 1.30 1.326 V - AGND = Vdd/2a Vdd/2 - 0.030 Vdd/2 - 0.004 Vdd/2 + 0.003 V 2 x BG - 0.043 2 x BG - 0.010 2 x BG + 0.024 V P2[4] - 0.013 P2[4] P2[4] + 0.014 V BG - 0.009 BG BG + 0.009 V 1.6 x BG - 0.018 1.6 x BG 1.6 x BG + 0.018 V 0.000 0.034 V - AGND = 2 x BandGapa - AGND = P2[4] (P2[4] = - AGND = BandGapa - Vdd/2)a a AGND = 1.6 x BandGap - AGND Block to Block Variation (AGND = Vdd/2) -0.034 - RefHi = Vdd/2 + BandGap Vdd/2 + BG - 0.140 Vdd/2 + BG - 0.018 Vdd/2 + BG + 0.103 V - RefHi = 3 x BandGap 3 x BG - 0.112 3 x BG - 0.018 3 x BG + 0.076 V - RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) 2 x BG + P2[6] - 0.113 2 x BG + P2[6] - 0.018 2 x BG + P2[6] + 0.077 V - RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + BG - 0.130 P2[4] + BG - 0.016 P2[4] + BG + 0.098 V - RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] - 0.133 P2[4] + P2[6] - 0.016 P2[4] + P2[6] + 0.100 V - RefHi = 3.2 x BandGap 3.2 x BG - 0.112 3.2 x BG 3.2 x BG + 0.076 V - RefLo = Vdd/2 - BandGap Vdd/2 - BG - 0.051 Vdd/2 - BG + 0.024 Vdd/2 - BG + 0.098 V - RefLo = BandGap BG - 0.082 BG + 0.023 BG + 0.129 V - RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2 x BG - P2[6] - 0.084 2 x BG - P2[6] + 0.025 2 x BG - P2[6] + 0.134 V - RefLo = P2[4] - BandGap (P2[4] = Vdd/2) P2[4] - BG - 0.056 P2[4] - BG + 0.026 P2[4] - BG + 0.107 V - RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] - 0.057 P2[4] - P2[6] + 0.026 P2[4] - P2[6] + 0.110 V a a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Table 3-12. Silicon Revision B - 5V DC Analog Reference Specifications Symbol Description Min Typ Max Units BG Bandgap Voltage Reference 1.28 1.30 1.32 V - AGND = Vdd/2a Vdd/2 - 0.030 Vdd/2 Vdd/2 + 0.007 V - AGND = 2 x BandGapa 2 x BG - 0.043 2 x BG 2 x BG + 0.024 V P2[4] - 0.011 P2[4] P2[4] + 0.011 V BG - 0.009 BG BG + 0.009 V 1.6 x BG - 0.018 1.6 x BG 1.6 x BG + 0.018 V - - - AGND = P2[4] (P2[4] = Vdd/2)a a AGND = BandGap a AGND = 1.6 x BandGap - AGND Block to Block Variation (AGND = -0.034 0.000 0.034 V - RefHi = Vdd/2 + BandGap Vdd/2 + BG - 0.1 Vdd/2 + BG - 0.01 Vdd/2 + BG + 0.1 V - RefHi = 3 x BandGap 3 x BG - 0.06 3 x BG - 0.01 3 x BG + 0.06 V - RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) 2 x BG + P2[6] - 0.06 2 x BG + P2[6] - 0.01 2 x BG + P2[6] + 0.06 V - RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + BG - 0.06 P2[4] + BG - 0.01 P2[4] + BG + 0.06 V - RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] - 0.06 P2[4] + P2[6] - 0.01 P2[4] + P2[6] + 0.06 V - RefHi = 3.2 x BandGap 3.2 x BG - 0.06 3.2 x BG - 0.01 3.2 x BG + 0.06 V - RefLo = Vdd/2 - BandGap Vdd/2 - BG - 0.051 Vdd/2 - BG + 0.01 Vdd/2 - BG + 0.06 V - RefLo = BandGap BG - 0.06 BG + 0.01 BG + 0.06 V - RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2 x BG - P2[6] - 0.04 2 x BG - P2[6] + 0.01 2 x BG - P2[6] + 0.04 V - RefLo = P2[4] - BandGap (P2[4] = Vdd/2) P2[4] - BG - 0.056 P2[4] - BG + 0.01 P2[4] - BG + 0.056 V - RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] - 0.056 P2[4] - P2[6] + 0.01 P2[4] - P2[6] + 0.056 V Vdd/2)a a. AGND tolerance includes the offsets of the local buffer in the PSoC block. August 3, 2004 Document No. 38-12012 Rev. *I 24 CY8C27x43 Final Data Sheet 3. Electrical Specifications Table 3-13. Silicon Revision A - 3.3V DC Analog Reference Specifications Symbol Description Min Typ Max Units BG Bandgap Voltage Reference 1.274 1.30 1.326 V - AGND = Vdd/2a Vdd/2 - 0.027 Vdd/2 - 0.003 Vdd/2 + 0.002 V - AGND = 2 x BandGap Not Allowed - AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.008 P2[4] + 0.001 P2[4] + 0.009 V BG - 0.009 BG BG + 0.009 V 1.6 x BG - 0.018 1.6 x BG 1.6 x BG + 0.018 V -0.034 0.000 0.034 mV P2[4] + P2[6] - 0.009 P2[4] + P2[6] + 0.057 V P2[4] - P2[6] + 0.022 P2[4] - P2[6] + 0.092 V a - AGND = - BandGapa a AGND = 1.6 x BandGap - AGND Block to Block Variation (AGND = - RefHi = Vdd/2 + BandGap Not Allowed - RefHi = 3 x BandGap Not Allowed - RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Not Allowed - RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Not Allowed - RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] + P2[6] - 0.075 - RefHi = 3.2 x BandGap Not Allowed - RefLo = Vdd/2 - BandGap Not Allowed - RefLo = BandGap Not Allowed - RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Not Allowed - RefLo = P2[4] - BandGap (P2[4] = Vdd/2) Not Allowed - RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] - 0.048 Vdd/2)a a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Note See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V. Table 3-14. Silicon Revision B - 3.3V DC Analog Reference Specifications Symbol Description Min Typ Max Units BG Bandgap Voltage Reference 1.28 1.30 1.32 V - AGND = Vdd/2a Vdd/2 - 0.027 Vdd/2 Vdd/2 + 0.005 V P2[4] - 0.008 P2[4] P2[4] + 0.009 V BG - 0.009 BG BG + 0.009 V 1.6 x BG - 0.018 1.6 x BG 1.6 x BG + 0.018 V -0.034 0.000 0.034 mV P2[4] + P2[6] - 0.01 P2[4] + P2[6] + 0.057 V P2[4] - P2[6] + 0.01 P2[4] - P2[6] + 0.048 V - AGND = 2 x - AGND = P2[4] (P2[4] = Vdd/2) - - AGND = BandGapa Not Allowed BandGapa AGND = 1.6 x BandGapa - AGND Block to Block Variation (AGND = - RefHi = Vdd/2 + BandGap Not Allowed - RefHi = 3 x BandGap Not Allowed - RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Not Allowed - RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Not Allowed - RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] + P2[6] - 0.06 - RefHi = 3.2 x BandGap Not Allowed - RefLo = Vdd/2 - BandGap Not Allowed - RefLo = BandGap Not Allowed - RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Not Allowed - RefLo = P2[4] - BandGap (P2[4] = Vdd/2) Not Allowed - RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] - 0.048 Vdd/2)a a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Note See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V. August 3, 2004 Document No. 38-12012 Rev. *I 25 CY8C27x43 Final Data Sheet 3.3.7 3. Electrical Specifications DC Analog PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-15. DC Analog PSoC Block Specifications Symbol Description Min Typ Max Units RCT Resistor Unit Value (Continuous Time) - 12.2 - k CSC Capacitor Unit Value (Switch Cap) - 80 - fF 3.3.8 Notes DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Mixed Signal Array Technical Reference Manual for more information on the VLT_CR register. Table 3-16. DC POR and LVD Specifications Symbol Description Min Typ Max Units Notes Vdd Value for PPOR Trip (positive ramp) VPPOR0R PORLEV[1:0] = 00b VPPOR1R PORLEV[1:0] = 01b VPPOR2R PORLEV[1:0] = 10b 2.91 - 4.39 V - 4.55 V V Vdd Value for PPOR Trip (negative ramp) VPPOR0 PORLEV[1:0] = 00b VPPOR1 PORLEV[1:0] = 01b VPPOR2 PORLEV[1:0] = 10b 2.82 - 4.39 V - 4.55 V V PPOR Hysteresis VPH0 PORLEV[1:0] = 00b - 92 - mV VPH1 PORLEV[1:0] = 01b - 0 - mV VPH2 PORLEV[1:0] = 10b - 0 - mV Vdd Value for LVD Trip VLVD0 VM[2:0] = 000b 2.86 2.92 2.98a V VLVD1 VM[2:0] = 001b 2.96 3.02 3.08 VLVD2 VM[2:0] = 010b 3.07 3.13 3.20 VLVD3 VM[2:0] = 011b 3.92 4.00 4.08 VLVD4 VM[2:0] = 100b 4.39 4.48 4.57 VLVD5 VM[2:0] = 101b 4.55 4.64 4.74b VLVD6 VM[2:0] = 110b 4.63 4.73 4.82 VLVD7 VM[2:0] = 111b 4.72 4.81 4.91 V V V V V V V V Vdd Value for PUMP Trip VPUMP0 VM[2:0] = 000b 2.96 3.02 3.08 VPUMP1 VM[2:0] = 001b 3.03 3.10 3.16 VPUMP2 VM[2:0] = 010b 3.18 3.25 3.32 VPUMP3 VM[2:0] = 011b 4.11 4.19 4.28 VPUMP4 VM[2:0] = 100b 4.55 4.64 4.74 VPUMP5 VM[2:0] = 101b 4.63 4.73 4.82 VPUMP6 VM[2:0] = 110b 4.72 4.82 4.91 VPUMP7 VM[2:0] = 111b 4.90 5.00 5.10 V V V V V V V V V a. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. b. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply. August 3, 2004 Document No. 38-12012 Rev. *I 26 CY8C27x43 Final Data Sheet 3.3.9 3. Electrical Specifications DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-17. DC Programming Specifications Symbol Description Min Typ Max Units Notes IDDP Supply Current During Programming or Verify - 5 25 mA VILP Input Low Voltage During Programming or Verify - - 0.8 V VIHP Input High Voltage During Programming or Verify 2.2 - - V IILP Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify - - 0.2 mA Driving internal pull-down resistor. IIHP Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify - - 1.5 mA Driving internal pull-down resistor. VOLV Output Low Voltage During Programming or Verify - - Vss + 0.75 V VOHV Output High Voltage During Programming or Verify Vdd - 1.0 - Vdd V FlashENPB Flash Endurance (per block) 50,000 - - - Erase/write cycles per block. 1,800,000 - - - Erase/write cycles. 10 - - Years FlashENT Flash Endurance FlashDR Flash Data Retention (total)a a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. August 3, 2004 Document No. 38-12012 Rev. *I 27 CY8C27x43 Final Data Sheet 3.4 3. Electrical Specifications AC Electrical Characteristics 3.4.1 AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-18. AC Chip-Level Specifications Symbol Description Min Typ Max Units Notes FIMO Internal Main Oscillator Frequency 23.4 24 24.6a MHz Trimmed. Utilizing factory trim values. FCPU1 CPU Frequency (5V Nominal) 0.93 24 24.6a,b MHz Trimmed. Utilizing factory trim values. FCPU2 CPU Frequency (3.3V Nominal) 0.93 12 12.3b,c MHz Trimmed. Utilizing factory trim values. F48M Digital PSoC Block Frequency 0 48 49.2a,b,d MHz Refer to the AC Digital Block Specifications below. F24M Digital PSoC Block Frequency 0 24 24.6b, d MHz F32K1 Internal Low Speed Oscillator Frequency 15 32 64 kHz F32K2 External Crystal Oscillator - 32.768 - kHz Accuracy is capacitor and crystal dependent. 50% duty cycle. FPLL PLL Frequency - 23.986 - MHz Multiple (x732) of crystal frequency. Jitter24M2 24 MHz Period Jitter (PLL) - - 600 ps TPLLSLEW PLL Lock Time 0.5 - 10 ms TPLLSLEWS- PLL Lock Time for Low Gain Setting 0.5 - 50 ms TOS External Crystal Oscillator Startup to 1% - 1700 2620 ms TOSACC External Crystal Oscillator Startup to 100 ppm - 2800 3800 ms Jitter32k 32 kHz Period Jitter - 100 TXRST External Reset Pulse Width 10 - - s DC24M 24 MHz Duty Cycle 40 50 60 % Step24M 24 MHz Trim Step Size - 50 - kHz Fout48M 48 MHz Output Frequency 46.8 48.0 49.2a,c MHz Jitter24M1 24 MHz Period Jitter (IMO) - 600 FMAX Maximum frequency of signal on row input or row output. - - 12.3 MHz TRAMP Supply Ramp Time 0 - - s LOW a. b. c. d. The crystal oscillator frequency is within 100 ppm of its final value by the end of the Tosacc period. Correct operation assumes a properly loaded 1 uW maximum drive level 32.768 kHz crystal. 3.0V Vdd 5.5V, -40 o C TA 85 oC. ns Trimmed. Utilizing factory trim values. ps 4.75V < Vdd < 5.25V. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 3.0V < Vdd < 3.6V. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V. See the individual user module data sheets for information on maximum frequencies for user modules. PLL Enable TPLLSLEW 24 MHz FPLL PLL Gain 0 Figure 3-3. PLL Lock Timing Diagram August 3, 2004 Document No. 38-12012 Rev. *I 28 CY8C27x43 Final Data Sheet 3. Electrical Specifications PLL Enable TPLLSLEWLOW 24 MHz FPLL PLL Gain 1 Figure 3-4. PLL Lock for Low Gain Setting Timing Diagram 32K Select 32 kHz TOS F32K2 Figure 3-5. External Crystal Oscillator Startup Timing Diagram Jitter24M1 F24M Figure 3-6. 24 MHz Period Jitter (IMO) Timing Diagram Jitter32k F32K2 Figure 3-7. 32 kHz Period Jitter (ECO) Timing Diagram August 3, 2004 Document No. 38-12012 Rev. *I 29 CY8C27x43 Final Data Sheet 3.4.2 3. Electrical Specifications AC General Purpose IO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-19. AC GPIO Specifications Symbol FGPIO Description Min GPIO Operating Frequency 0 Typ - Max 12 Units Notes MHz TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 3 - 18 ns Vdd = 4.5 to 5.25V, 10% - 90% TFallF Fall Time, Normal Strong Mode, Cload = 50 pF 2 - 18 ns Vdd = 4.5 to 5.25V, 10% - 90% TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 10 27 - ns Vdd = 3 to 5.25V, 10% - 90% TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 10 22 - ns Vdd = 3 to 5.25V, 10% - 90% 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS Figure 3-8. GPIO Timing Diagram August 3, 2004 Document No. 38-12012 Rev. *I 30 CY8C27x43 Final Data Sheet 3.4.3 3. Electrical Specifications AC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Power = High and Opamp Bias = High is not supported at 3.3V. Table 3-20. 5V AC Operational Amplifier Specifications Symbol TROA TSOA SRROA SRFOA BWOA ENOA Description Min Typ Max Units Notes Rising Settling Time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low - - 3.9 s Power = Medium, Opamp Bias = High - - 0.72 s Power = High, Opamp Bias = High - - 0.62 s Power = Low, Opamp Bias = Low - - 5.9 s Power = Medium, Opamp Bias = High - - 0.92 s Power = High, Opamp Bias = High - - 0.72 s Power = Low, Opamp Bias = Low 0.15 - - V/s Power = Medium, Opamp Bias = High 1.7 - - V/s Power = High, Opamp Bias = High 6.5 - - V/s Power = Low, Opamp Bias = Low 0.01 - - V/s Power = Medium, Opamp Bias = High 0.5 - - V/s Power = High, Opamp Bias = High 4.0 - - V/s Power = Low, Opamp Bias = Low 0.75 - - MHz Power = Medium, Opamp Bias = High 3.1 - - MHz Power = High, Opamp Bias = High 5.4 - - MHz Noise at 1 kHz (Power = Medium, Opamp Bias = High) - 100 - nV/rt-Hz Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Gain Bandwidth Product Table 3-21. 3.3V AC Operational Amplifier Specifications Symbol TROA TSOA SRROA SRFOA BWOA ENOA Description Min Typ Max Units Notes Rising Settling Time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low - - 3.92 s Power = Low, Opamp Bias = High - - 0.72 s Power = Low, Opamp Bias = Low - - 5.41 s Power = Medium, Opamp Bias = High - - 0.72 s Power = Low, Opamp Bias = Low 0.31 - - V/s Power = Medium, Opamp Bias = High 2.7 - - V/s Power = Low, Opamp Bias = Low 0.24 - - V/s Power = Medium, Opamp Bias = High 1.8 - - V/s Power = Low, Opamp Bias = Low 0.67 - - MHz Power = Medium, Opamp Bias = High 2.8 - - MHz Noise at 1 kHz (Power = Medium, Opamp Bias = High) - 100 - nV/rt-Hz Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Gain Bandwidth Product August 3, 2004 Document No. 38-12012 Rev. *I 31 CY8C27x43 Final Data Sheet 3.4.4 3. Electrical Specifications AC Digital Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-22. AC Digital Block Specifications Function Description Min Typ Max Units All Functions Maximum Block Clocking Frequency (> 4.75V) Timer Capture Pulse Width 50a - - ns Maximum Frequency, No Capture - - 49.2 MHz Maximum Frequency, With Capture - - 24.6 MHz Enable Pulse Width 50a - - ns Maximum Frequency, No Enable Input - - 49.2 MHz Maximum Frequency, Enable Input - - 24.6 MHz Asynchronous Restart Mode 20 - - ns Synchronous Restart Mode 50a - - ns a - - ns Counter Dead Band 49.2 Maximum Block Clocking Frequency (< 4.75V) Notes 4.75V < Vdd < 5.25V. 24.6 3.0V < Vdd < 4.75V. 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. Kill Pulse Width: Disable Mode 50 - - 49.2 MHz 4.75V < Vdd < 5.25V. CRCPRS Maximum Input Clock Frequency (PRS Mode) Maximum Frequency - - 49.2 MHz 4.75V < Vdd < 5.25V. CRCPRS Maximum Input Clock Frequency (CRC Mode) - - 24.6 MHz SPIM Maximum Input Clock Frequency - - 8.2 MHz SPIS Maximum Input Clock Frequency - - 4.1 ns Width of SS_ Negated Between Transmissions 50a - - ns Silicon A - - 16.4 MHz Maximum data rate at 2.05 MHz due to 8 x over clocking. Silicon B - - 24.6 MHz Maximum data rate at 3.08 MHz due to 8 x over clocking. Silicon A - - 16.4 MHz Maximum data rate at 2.05 MHz due to 8 x over clocking. Silicon B - - 24.6 MHz Maximum data rate at 3.08 MHz due to 8 x over clocking. Transmitter Receiver Maximum Input Clock Frequency Maximum data rate at 4.1 MHz due to 2 x over clocking. b Maximum Input Clock Frequency b a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). b. Refer to the Ordering Information chapter on page 42. August 3, 2004 Document No. 38-12012 Rev. *I 32 CY8C27x43 Final Data Sheet 3.4.5 3. Electrical Specifications AC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-23. 5V AC Analog Output Buffer Specifications Symbol TROB TSOB SRROB SRFOB BWOB BWOB Description Min Typ Max Units Notes Rising Settling Time to 0.1%, 1V Step, 100pF Load Power = Low - - 2.5 s Power = High - - 2.5 s Power = Low - - 2.2 s Power = High - - 2.2 s Power = Low 0.65 - - V/s Power = High 0.65 - - V/s Power = Low 0.65 - - V/s Power = High 0.65 - - V/s Power = Low 0.8 - - MHz Power = High 0.8 - - MHz Power = Low 300 - - kHz Power = High 300 - - kHz Falling Settling Time to 0.1%, 1V Step, 100pF Load Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Table 3-24. 3.3V AC Analog Output Buffer Specifications Symbol TROB TSOB SRROB SRFOB BWOB BWOB Description Min Typ Max Units Notes Rising Settling Time to 0.1%, 1V Step, 100pF Load Power = Low - - 3.8 s Power = High - - 3.8 s Power = Low - - 2.6 s Power = High - - 2.6 s Power = Low 0.5 - - V/s Power = High 0.5 - - V/s Power = Low 0.5 - - V/s Power = High 0.5 - - V/s Power = Low 0.7 - - MHz Power = High 0.7 - - MHz Power = Low 200 - - kHz Power = High 200 - - kHz Falling Settling Time to 0.1%, 1V Step, 100pF Load Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load August 3, 2004 Document No. 38-12012 Rev. *I 33 CY8C27x43 Final Data Sheet 3.4.6 3. Electrical Specifications AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-25. 5V AC External Clock Specifications Symbol FOSCEXT Description Min Frequency Typ Max 0.093 - 24.6 Units Notes MHz - High Period 20.6 - 5300 ns - Low Period 20.6 - - ns - Power Up IMO to Switch 150 - - s Table 3-26. 3.3V AC External Clock Specifications Symbol FOSCEXT FOSCEXT - Description Min Typ Max Units Frequency with CPU Clock divide by 1 0.093 - 12.3 MHz Frequency with CPU Clock divide by 2 or greaterb 0.186 - 24.6 MHz High Period with CPU Clock divide by 1 41.7 - 5300 ns - Low Period with CPU Clock divide by 1 41.7 - - ns - Power Up IMO to Switch 150 - - s a Notes a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met. 3.4.7 AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-27. AC Programming Specifications Symbol Description Min Typ Max Units Notes TRSCLK Rise Time of SCLK 1 - 20 ns TFSCLK Fall Time of SCLK 1 - 20 ns TSSCLK Data Set up Time to Falling Edge of SCLK 40 - - ns THSCLK Data Hold Time from Falling Edge of SCLK 40 - - ns FSCLK Frequency of SCLK 0 - 8 MHz TERASEB Flash Erase Time (Block) - 10 - ms TWRITE Flash Block Write Time - 10 - ms TDSCLK Data Out Delay from Falling Edge of SCLK - - 45 ns Vdd > 3.6 TDSCLK3 Data Out Delay from Falling Edge of SCLK - - 50 ns 3.0 Vdd 3.6 August 3, 2004 Document No. 38-12012 Rev. *I 34 CY8C27x43 Final Data Sheet 3.4.8 3. Electrical Specifications AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-28. AC Characteristics of the I2C SDA and SCL Pins Standard Mode Symbol Description Min Fast Mode Max Min Max Units FSCLI2C SCL Clock Frequency 0 100 0 400 kHz THDSTAI2C Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. 4.0 - 0.6 - s TLOWI2C LOW Period of the SCL Clock 4.7 - 1.3 - s THIGHI2C HIGH Period of the SCL Clock 4.0 - 0.6 - s TSUSTAI2C Set-up Time for a Repeated START Condition 4.7 - 0.6 - s THDDATI2C Data Hold Time 0 - 0 - s TSUDATI2C Data Set-up Time 250 - 100 - ns TSUSTOI2C Set-up Time for STOP Condition 4.0 - 0.6 - s TBUFI2C Bus Free Time Between a STOP and START Condition 4.7 - 1.3 - s TSPI2C Pulse Width of spikes are suppressed by the input filter. - - 0 50 ns a Notes a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. SDA TLOWI2C TSUDATI2C THDSTAI2C TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C Sr TSUSTOI2C P S Figure 3-9. Definition for Timing for Fast/Standard Mode on the I2C Bus August 3, 2004 Document No. 38-12012 Rev. *I 35 4. Packaging Information This chapter illustrates the packaging specifications for the CY8C27x43 PSoC device, along with the thermal impedances for each package and the typical package capacitance on crystal pins. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/support/link.cfm?mr=poddim. 4.1 Packaging Dimensions 51-85075 - *A Figure 4-1. 8-Lead (300-Mil) PDIP August 3, 2004 (c) Cypress MicroSystems, Inc. 2003 -- Document No. 38-12012 Rev. *I 36 CY8C27x43 Final Data Sheet 4. Packaging Information 51-85077 - *C Figure 4-2. 20-Lead (210-Mil) SSOP 51-85024 - *B Figure 4-3. 20-Lead (300-Mil) Molded SOIC August 3, 2004 Document No. 38-12012 Rev. *I 37 CY8C27x43 Final Data Sheet 4. Packaging Information 51-85014 - *D Figure 4-4. 28-Lead (300-Mil) Molded DIP 51-85079 - *C Figure 4-5. 28-Lead (210-Mil) SSOP August 3, 2004 Document No. 38-12012 Rev. *I 38 CY8C27x43 Final Data Sheet 4. Packaging Information 51-85026 - *C Figure 4-6. 28-Lead (300-Mil) Molded SOIC 51-85064-B 51-85064 - *B Figure 4-7. 44-Lead TQFP August 3, 2004 Document No. 38-12012 Rev. *I 39 CY8C27x43 Final Data Sheet 4. Packaging Information 51-85061 - *C 61-C 51 -850 Figure 4-8. 48-Lead (300-Mil) SSOP 0.08 6.90 7.10 C 1.00 MAX. 0.05 MAX. X 0.80 MAX. 6.70 6.80 0.230.05 0.20 REF. N N PIN1 ID 0.20 R. 1 1 2 2 0.45 0.80 DIA. 6.70 6.80 6.90 7.10 E-PAD 5.45 5.55 Y 0.30-0.45 0-12 0.50 0.420.18 (4X) 5.45 5.55 C SEATING PLANE TOP VIEW SIDE VIEW BOTTOM VIEW E-PAD SIZE PADDLE SIZE DIMENSIONS IN mm MIN. MAX. (X, Y MAX.) 51X51 Figure 4-9. 48-Lead (7x7 mm) MLF August 3, 2004 Document No. 38-12012 Rev. *I 51-85152 - *B 53X53 40 CY8C27x43 Final Data Sheet 4.2 4. Packaging Information Thermal Impedances Table 4-1. Thermal Impedances per Package Package Typical JA * 8 PDIP 120 oC/W 20 SSOP 95 oC/W 20 SOIC 79 oC/W 28 PDIP 67 oC/W 28 SSOP 95 oC/W 28 SOIC 71 oC/W 44 TQFP 58 oC/W 48 SSOP 69 oC/W 48 MLF 18 oC/W * TJ = TA + POWER x JA 4.3 Capacitance on Crystal Pins Table 4-2: Typical Package Capacitance on Crystal Pins Package Package Capacitance 8 PDIP 2.8 pF 20 SSOP 2.6 pF 20 SOIC 2.5 pF 28 PDIP 3.5 pF 28 SSOP 2.8 pF 28 SOIC 2.7 pF 44 TQFP 2.6 pF 48 SSOP 3.3 pF 48 MLF 2.3 pF August 3, 2004 Document No. 38-12012 Rev. *I 41 5. Ordering Information The following table lists the CY8C27x43 PSoC device family's key package features and ordering codes. XRES Pin Analog Outputs Analog Inputs Digital IO Pins (Columns of 3) Analog Blocks Digital Blocks (Rows of 4) Temperature Range Switch Mode Pump Ordering Code RAM (Bytes) Package Flash (Kbytes) Table 5-1. CY8C27x43 PSoC Device Family Key Features and Ordering Information CY8C27x43 Silicon B - These parts are lead free and offer the following improvements. The DEC_CR1 register selections are enhanced to allow any digital block to be the decimator clock source, the ECO EX and ECO EXW bits in the CPU_SCR1 register are readable, and the accuracy of the analog reference is enhanced (see the Electrical Specifications chapter). All silicon A errata are fixed in silicon B. 8 Pin (300 Mil) DIP CY8C27143-24PXI 16 256 No -40C to +85C 8 12 6 4 4 No 20 Pin (210 Mil) SSOP CY8C27243-24PVXI 16 256 Yes -40C to +85C 8 12 16 8 4 Yes 20 Pin (210 Mil) SSOP (Tape and Reel) CY8C27243-24PVXIT 16 256 Yes -40C to +85C 8 12 16 8 4 Yes 20 Pin (300 Mil) SOIC CY8C27243-24SXI 16 256 Yes -40C to +85C 8 12 16 8 4 Yes 20 Pin 300 Mil) SOIC (Tape and Reel) CY8C27243-24SXIT 16 256 Yes -40C to +85C 8 12 16 8 4 Yes 28 Pin (300 Mil) DIP CY8C27443-24PXI 16 256 Yes -40C to +85C 8 12 24 12 4 Yes 28 Pin (210 Mil) SSOP CY8C27443-24PVXI 16 256 Yes -40C to +85C 8 12 24 12 4 Yes 28 Pin (210 Mil) SSOP (Tape and Reel) CY8C27443-24PVXIT 16 256 Yes -40C to +85C 8 12 24 12 4 Yes 28 Pin (300 Mil) SOIC CY8C27443-24SXI 16 256 Yes -40C to +85C 8 12 24 12 4 Yes 28 Pin (300 Mil) SOIC (Tape and Reel) CY8C27443-24SXIT 16 256 Yes -40C to +85C 8 12 24 12 4 Yes 44 Pin TQFP CY8C27543-24AXI 16 256 Yes -40C to +85C 8 12 40 12 4 Yes 44 Pin TQFP (Tape and Reel) CY8C27543-24AXIT 16 256 Yes -40C to +85C 8 12 40 12 4 Yes 48 Pin (300 Mil) SSOP CY8C27643-24PVXI 16 256 Yes -40C to +85C 8 12 44 12 4 Yes 48 Pin (300 Mil) SSOP (Tape and Reel) CY8C27643-24PVXIT 16 256 Yes -40C to +85C 8 12 44 12 4 Yes 48 Pin (7x7) MLF CY8C27643-24LFXI 16 256 Yes -40C to +85C 8 12 44 12 4 Yes 48 Pin (7x7) MLF (Tape and Reel) CY8C27643-24LFXIT 16 256 Yes -40C to +85C 8 12 44 12 4 Yes CY8C27x43 Silicon A - Silicon A is not recommended for new designs. 8 Pin (300 Mil) DIP CY8C27143-24PI 16 256 No -40C to +85C 8 12 6 4 4 No 20 Pin (210 Mil) SSOP CY8C27243-24PVI 16 256 Yes -40C to +85C 8 12 16 8 4 Yes 20 Pin (210 Mil) SSOP (Tape and Reel) CY8C27243-24PVIT 16 256 Yes -40C to +85C 8 12 16 8 4 Yes 20 Pin (300 Mil) SOIC CY8C27243-24SI 16 256 Yes -40C to +85C 8 12 16 8 4 Yes 20 Pin 300 Mil) SOIC (Tape and Reel) CY8C27243-24SIT 16 256 Yes -40C to +85C 8 12 16 8 4 Yes 28 Pin (300 Mil) DIP CY8C27443-24PI 16 256 Yes -40C to +85C 8 12 24 12 4 Yes 28 Pin (210 Mil) SSOP CY8C27443-24PVI 16 256 Yes -40C to +85C 8 12 24 12 4 Yes August 3, 2004 Document No. 38-12012 Rev. *I 42 CY8C27x43 Final Data Sheet 5. Ordering Information RAM (Bytes) Switch Mode Pump Temperature Range Digital Blocks (Rows of 4) Digital IO Pins Analog Inputs Analog Outputs XRES Pin 28 Pin (210 Mil) SSOP (Tape and Reel) CY8C27443-24PVIT 16 256 Yes -40C to +85C 8 12 24 12 4 Yes 28 Pin (300 Mil) SOIC CY8C27443-24SI 16 256 Yes -40C to +85C 8 12 24 12 4 Yes 28 Pin (300 Mil) SOIC (Tape and Reel) CY8C27443-24SIT 16 256 Yes -40C to +85C 8 12 24 12 4 Yes 44 Pin TQFP CY8C27543-24AI 16 256 Yes -40C to +85C 8 12 40 12 4 Yes 44 Pin TQFP (Tape and Reel) CY8C27543-24AIT 16 256 Yes -40C to +85C 8 12 40 12 4 Yes 48 Pin (300 Mil) SSOP CY8C27643-24PVI 16 256 Yes -40C to +85C 8 12 44 12 4 Yes 48 Pin (300 Mil) SSOP (Tape and Reel) CY8C27643-24PVIT 16 256 Yes -40C to +85C 8 12 44 12 4 Yes 48 Pin (7x7) MLF CY8C27643-24LFI 16 256 Yes -40C to +85C 8 12 44 12 4 Yes 48 Pin (7x7) MLF (Tape and Reel) CY8C27643-24LFIT 16 256 Yes -40C to +85C 8 12 44 12 4 Yes Package 5.1 Ordering Code (Columns of 3) Flash (Kbytes) Analog Blocks Table 5-1. CY8C27x43 PSoC Device Family Key Features and Ordering Information (continued) Ordering Code Definitions CY 8 C 27 xxx-SPxx Package Type: P = PDIP S = SOIC PV = SSOP LF = MLF A = TQFP PX = PDIP Pb Free SX = SOIC Pb Free PVX = SSOP Pb Free LFX = MLF Pb Free AX = TQFP Pb Free Thermal Rating: C = Commercial I = Industrial E = Extended Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress MicroSystems Company ID: CY = Cypress August 3, 2004 Document No. 38-12012 Rev. *I 43 6. Sales and Service Information To obtain information about Cypress MicroSystems or PSoC sales and technical support, reference the following information or go to the section titled "Getting Started" on page 4 in this document. Cypress MicroSystems 2700 162nd Street SW Building D Lynnwood, WA 98037 Phone: 800.669.0557 Facsimile: 425.787.4641 Web Sites: 6.1 Company Information - http://www.cypress.com Sales - http://www.cypress.com/aboutus/sales_locations.cfm Technical Support - http://www.cypress.com/support/login.cfm Revision History Table 6-1. CY8C27x43 Data Sheet Revision History Document Title: CY8C27143, CY8C27243, CY8C27443, CY8C27543, and CY8C27643 PSoC Mixed Signal Array Final Data Sheet Document Number: 38-12012 Revision ECN # Issue Date Origin of Change ** 127087 7/01/2003 New Silicon. *A 128780 7/29/2003 Engineering and NWJ. *B 128992 8/14/2003 NWJ *C 129283 8/28/2003 NWJ *D 129442 9/09/2003 NWJ *E 130129 10/13/2003 NWJ *F 130651 10/28/2003 NWJ *G 131298 11/18/2003 NWJ *H 229416 See ECN *I 247529 See ECN Distribution: External Public 6.2 SFV SFV Posting: None Description of Change New document (Revision **). New electrical spec additions, fix of Core Architecture links, corrections to some text, tables, drawings, and format. Interrupt controller table fixed, refinements to Electrical Spec section and Register chapter. Significant changes to the Electrical Specifications section. Changes made to Electrical Spec section. Added 20/28-Lead SOIC packages and pinouts. Revised document for Silicon Revision A. Refinements to Electrical Specification section and I2C chapter. Revisions to GDI, RDI, and Digital Block chapters. Revisions to AC Digital Block Spec and miscellaneous register changes. New data sheet format and organization. Reference the PSoC Mixed Signal Array Technical Reference Manual for additional information. Title change. Added Silicon B information to this data sheet. Copyrights and Code Protection Copyrights (c) Cypress MicroSystems, Inc. 2000 - 2004. All rights reserved. PSoCTM, PSoC DesignerTM, and Programmable System-on-ChipTM are trademarks of Cypress MicroSystems, Inc. All other trademarks or registered trademarks referenced herein are property of the respective corporations. The information contained herein is subject to change without notice. Cypress MicroSystems assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress MicroSystems product. Nor does it convey or imply any license under patent or other rights. Cypress MicroSystems does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress MicroSystems products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress MicroSystems against all charges. Cypress MicroSystems products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress MicroSystems. Flash Code Protection Note the following details of the Flash code protection features on Cypress MicroSystems devices. Cypress MicroSystems products meet the specifications contained in their particular Cypress MicroSystems Data Sheets. Cypress MicroSystems believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress MicroSystems, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress MicroSystems nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress MicroSystems is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress MicroSystems are committed to continuously improving the code protection features of our products. August 3, 2004 (c) Cypress MicroSystems, Inc. 2002 - 2004 -- Document No. 38-12012 Rev. *I 44