19-0021; Rev 2; 1/94 MAXIM Quad 8-Bit DACs with Rail-to-Rail Voltage Outputs General Description The MAX505 and MAX506 are CMOS, quad, 8-bit voltage- output digital-to-analog converters (DACs). The parts operate with a single +5V supply or dual +5V supplies. Internal, precision output buffers swing rail-to-rail. The reference input range includes both supply rails. Offset, gain, and linearity are factory calibrated to provide 1LSB total unadjusted error (TUE) over the full operating temperature range. The MAX505 contains double-buffered logic inputs, which allow all analog outputs to be simultaneously updated using the asynchronous load DAC (LDAC) control signal. The MAXS505 also has four separate reference inputs, allowing each DACs full-scale range to be independently set. The MAXS506 has separate input latches for each of its four DACs. Datais transferred to the input latches from a common 8-bit input port. The DACs are individually selected through address inputs AO and A1, and updated by bringing WR low. All MAX506 DACs share a common reference input. All logic inputs are TTL and +5V CMOS compatible. Applications Minimum Component Count Analog Systems Digital Offset/Gain Adjustment Arbitrary Function Generators Industrial Process Control Automatic Test Equipment Programmable Attenuators Features @ Operate from Single +5V Supply or Dual +5V Supplies Output Suffer Amplifiers Swing Rail-to-Rail @ Reference Input Range Includes Both Supply Rails @ Factory-Calibrated for 1LSB TUE @ Double-Buffered Digital Inputs (MAX505) @ Microprocessor and TTL/CMOS Compatible @ Require No External Adjustments @ Pin-Compatible Upgrades to MX7225/MX7226 @ Now Avaitable in Tiny SSOP Package Ordering Information PART TEMP.RANGE PIN-PACKAGE (LSBs) MAX505ACNG OCto+7C 24NarowPlasicDIP_ +1 MAX505BCNG OCto+70U 24NarowPlsicDIP +114 MAX505ACWG OCto+70C 24 Wide SO +H MAX505BCWG OCto+70C 24 Wide SO +1% MAX505ACAG OCto+70C 24SSOP +H MAX50SBCAG OCto+70C 24SSOP 41% MAX505BC/D O'Cto+70C Dice +1% Ordering information continued on last page. * Contact factory for dice specifications. **Contact factory for availability and processing to MIL-STD-883. Pin Configurations Functional Diagrams YREFB yap VREFD VREFC VREFA 5 14121, 20 12 INPUT DAC ] ; Ea LATCH [LATCH Y DACA >|, VouTa D7 (MSB A } 10.004 PINS 910 | P 1 INPUT LA[ DAC vou LATCH LATCH py nace , B [vB {zi _T J < 24 DAC 24 UAH LATCH 1 sett > Voure C Neen aca | a Sl vou D nd 0 wl MAAXLAA 5 AT 19 CONTROL A 18] Losic MAXS05 Functional Diagrams continued 8 go 7 on last page. U Vss_AGND_DGND TOP VIEW . Voure [11 | ia] Vourc Vouta [2 | 23] Vouto Vss [3] 22] Voo VREFB [4 OXEOS B VREFC VREFA [5] 20] VREFD AGND [6 | lig] 40 DGNO [7| a] At iDAC [| 7] WR (MSB)07 [9] 16] DO(LS8) 6 fro] 15] Bt bs [ia] 14] 02 D4 [12] [13] 03 DIP/SO/SSOP Pin Contigurations continued on last page. MA AXLAA Call toll free 1-800-998-8800 for free samples or literature. Maxim Integrated Products 1 90SXVW/SOSXVNMAX505/MAXS506 Quad 8-Bit DACs with Rail-to-Rail Voltage Outputs ABSOLUTE MAXIMUM RATINGS VDDtOAGND .. 0... . eee e eee ee -0.3V, +8V Voo toDGND ........ 2... c eee eee -0.3V, +6V VSStoAGND 1.0.0.0... 0c ccc cece eens -7V,0.3V VsstoDGND 1.0.0.0... ccc ccc cence eee -7V, 0.3V VOD tO VSS ... cece een eens -0.3V, +12V Digital Input Voltage to DGND ........... 0.3V, (VoD + 0.3V) VREF ... 2. eee (Vsg - 0.3V), (VoD + 0.3V) VouT (Note 1). 0.0... eee Vss, VoD Continuous Power Dissipation (Ta = +70C) MAX505 Plastic DIP (derate 13.33MW/C above +70C) .... 1067mW Wide SO (derate 11.76mW/C above +70C) ....... 941mW CERDIP (derate 12.50mW/C above +70C) ...... 1000mW SSOP (derate 8SmW/C above +70C) .............. 640mW MAX506 Plastic DIP (derate 11.11mW/C above +70C)...... 889mW Wide SO (derate 10.00mW/C above +70C) ....... 800mwWw CERDIP (derate 11.11mW/C above +70C)........ 88g9mw Operating Temperature Ranges: MAX5O_ Ce nee 0C to +70C MAX50_EF wee eee -40C to +85C MAX50_M__ ow. eee ee eee -55C to +125C Storage Temperature Range .............. 65C to +168C Lead Temperature (soldering, 10sec) .............. +300C Note 1: The outputs may be shorted to Vpp, Vss, or AGND if the package power dissipation is not exceeded. Typical short-circuit current to AGND is 50mA. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Vop = +5V 10%, Vss = OV to -5.5V, AGND = DGND = OV, VREF = 4V, RL = 10k, C_ = 100pF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX| UNITS STATIC ACCURACY Resolution 8 Bits VREF = +4V, MAXS0_A #1 Vgs = OV or -5V 410% MAX50_B +1% Total Unadjusted Error TUE = LSB VREF = -4V, MAXS50_A Ea Vss = -5V +10% MAX50_B +1% Differential Nonlinearity DNL Guaranteed monotonic +1 LSB MAX50_C 14 Code = 00 hex, Ves = OV MAX50_E 16 MAX50_M 20 Zero-Code Error ZCE = mV MAX50_C +14 Code = 00 hex, Vs = -5V 10% MAXSO_E #16 MAX50_M +20 Code = 00 hex, Zero-Code Error Supply Rejection Vop = 5V +10%, 1 2 mV Vss = OV or -5V 10% Zero-Code Temperature Coefficient Code = 00 hex +10 pvc Full-Scale Error Code = FF hex +14 mV Code = FF hex, MAX50_C 1 4 Full-Scale Error Supply Rejection Vpp = +5V 10%, MAX50_E 1 8 mV Vsg = OV or -5V +10% MAX50_M 12 Full-Scale-Error Temperature _ Coefficient Code = FF hex +10 pwVC MAXIANQuad 8-Bit DACs with Rail-to-Rail Voltage Outputs ELECTRICAL CHARACTERISTICS (continued) (Vpp = +5V +10%, Vss = OV to -5.5V, AGND = DGND = OV, VREF = 4V, RL = 10kQ, CL = 100pF, Ta = TmIN to Tmax, unless otherwise noted.) 90SXVW/SOSXUW PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX| UNITS REFERENCE INPUTS Input Voltage Range Vss Vpp Vv MAX505 16-24 Input Resistance (Note 2) Code = 55 hex kQ MAX506 4 6 J MAX505 15 Input Capacitance (Note 3) Code = 00 hex pF MAX506 40 Channel-to-Channel Isolation MAX505 (Note 4) -60 dB AC Feedthrough MAX505 (Note 5) -70 dB DAC OUTPUTS Full-Scale Output Voltage Vss VbD Vv VouT = 4V, load regulation < 1/4LSB 2 Resistive Load Vout = -4V, load regulation < VALSB 2 a VouT = Vpp MAX50__C/E load regulation< 1.5LSB} 10 Vout = Vpp MAX50_M load regulation < 2LSB 10 DIGITAL INPUTS Logic High VIH 2.4 v Logic Low ViL 0.8 Vv Input Current Measured at VIH and ViL +1 pA Input Capacitance 8 pF Input Coding Binary DYNAMIC PERFORMANCE MAX50_C 1.0 Voltage-Output Slew Rate Positive and negative MAX50_E 0.7 Vius MAX50_M 0.5 Output Settling Time To +1/2LSB, 10kQ11 100pF load (Note 6) 6 ps Digital Feedthrough rode, poner, WR = Voo, all digital inputs 5 nv-s VREF = 4Vp-p at 1kHz, Vpp = 5V, Vss = -5V, 87 dB Signal to (Noise + Distortion) Ratio code = FF hex VREF = 4Vp-p at 20KHz, Vss = -5V +10% -74 dB Multiplying Bandwidth VREF = 0.5Vp-p, 3dB bandwidth 1 MHz Wideband Amplifier Noise 60 uVRMS MAMXLAA 3MAX505/MAX506 Quad 8-Bit DACs with Rail-to-Rail Voltage Outputs ELECTRICAL CHARACTERISTICS (continued) (Vpp = +5V 10%, Vss = OV to -5.5V, AGND = DGND = OV, VREF = 4V, Rt = 10kQ, CL = 100pF, Ta = TIN to Tmax, unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX UNITS POWER SUPPLIES Positive Supply Voltage Vpb For specified performance 45 5.5 Vv Negative Supply Voltage Vss For specified performance 5.5 0 Vv MAX E 5 1 Positive Supply Current IDD Gigtal nipute er a\op VEO 5 mA ; Vsg = -5V +10%, outputs MAX50__C/E 5 10 Negative Supply Current Iss unpenes at digital inputs MAX50_M 5 12 mA SWITCHING CHARACTERISTICS Address to WR Setup tas 5 8 ns Address to WR Hold tAH 5 -4 ns Data to WR Setup tps 45 35 ns Data to WR Hold tOH 0-13 ns WR Pulse Width twa 4020 ns LDAC Pulse Width tLe 40 20 ns Note 2: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex. Note 3: Input capacitance is code dependent. The highest input capacitance occurs at code = 00 hex. Note 4: Note 5: Note 6: lout (mA) OUTPUT SINK CURRENT vs. (VouT-Vss) es o=-n o SCH NWEN AND 01423456 7 8 9101112 Vourt-Vss (V) SUPPLY CURRENT (mA) SUPPLY CURRENT vs. TEMPERATURE Vop =+5.5V =-5.5V =-4,75 DIGITAL INPUTS = +5V TEMPERATURE (C) lbp (mA) 0 -60 -40 -20 0 20 40 60 80 100 120140 0 5-4 VREF = 10kHz, 4Vp-p. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the code of all other DACs to 00 hex. VREF = 10kHz, 4Vp-p. DAC code = 00 hex. Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex. Typical Operating Characteristics SUPPLY CURRENT vs. REFERENCE VOLTAGE 3 2 -| 0 1 p= 48V Logic INPUTS = +5V 2 VREF VOLTAGE (V) 3.94 55 MA AXIANQuad 8-Bit DACs with Rail-to-Rail Voltage Outputs THD + NOISE AT DAC OUTPUT THD + NOISE AT DAC OUTPUT vs. REFERENCE FREQUENCY vs. REFERENCE FREQUENCY AND AMPLITUDE AND AMPLITUDE 10% 0 a ey PUT CODE = FF HEX % = ir Usa = = SWEPT ig ya 2 a 2 2 8s = + + 4 01% + 0.01% - 0.01% FREQ = 1kHz = 90 90 0.0 1.0 203.0 40 50 6070 80 90 10 10 100 1k 10k 100k REFERENCE AMPLITUDE (Vp-p) REFERENCE FREQUENCY (Hz) REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE Vop = +5V Vss = AGND = 425C =2.5VDC + Vpp = +5V Vss = +5V = +25C =2.5VDC + SINE WAVE -10 RELATIVE OUTPUT (8) 8 RELATIVE OUTPUT (4B) -40 1k 10k = 100k~=Ss1M 40M 1k 10k = 100k = 10M FREQUENCY (Hz) FREQUENCY (Hz} DIGITAL FEEDTHROUGH - OUTPUT SOURCE CURRENT GLITCH IMPULSE (0 TO 1 vs. VouT DIGITAL TRANSITION) 25 TTT Voo = ReF =45V SS= -20 Ne INPUT = FF HEX N -15 N\ lout (mA) N -10 NX \ A= DIGITAL INPUTS, 5V/div 0 36 38 40 42 44 46 48 50 B= Voura, 10mV/div Vout (V) TIMEBASE = 1S 0701 DIGITAL TRANSITION ON ALL DATA BITS (WITH WR HIGH) VREFA = AGND MAMAXLAA Typical Operating Characteristics (continued) REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE Vp = +5V Vss = AGND =+25C = 2.5VDC + SINE WAVE RELATIVE OUTPUT (dB) 1k 10k 100k 1M FREQUENCY (Hz) 10M ZERO-CODE ERROR vs. NEGATIVE SUPPLY VOLTAGE 48 = +5V = 46 Tas 425C E S 44 i 42 a 3 40 2 E38 36 34 0 Vss (V) DIGITAL FEEDTHROUGH GLITCH IMPULSE (1 TO 0 DIGITAL TRANSITION) GND GND A= DIGITAL INPUTS, 5V/div B = Vouta, 10mV/div TIMEBASE = 1ps 170.0 DIGITAL TRANSITION ON ALL DATA BITS (WITH WR HIGH) VREFA = AGND 90SXVW/SOSXVWQuad 8-Bit DACs with Rail-to-Rail Voltage Outputs Typical Operating Characteristics (continued) REFERENCE FEEDTHROUGH POSITIVE SETTLING TIME REFERENCE FEEDTHROUGH (Vss = AGND) O0Hz AT 4000Hz GND MAX505/MAX506 GND : A= DIGITAL {NPUT, SWdiv A= VREFA, 10Vp-p A=VREFA, 10Vp-p UT, = Voura, S0}V/di B=Vouta, t00uV/div, UNLOADED B= Voura, 2V/div Boe stray UNLOADED TIMEBASE = 100us/div TIMEBASE = 11s ae eo ea CODEC ALLOS COE = ALL Os ALL BITS OFF TO ALL BITS ON LOAD =e LOAD =e RL = 10kQ2, Ce = 100pF POSITIVE SETTLING TIME NEGATIVE SETTLING TIME NEGATIVE SETTLING TIME (Vss = -5V) (Vss = AGND) (Vss = -5V) A= DIGITAL INPUT, SV/div A= DIGITAL INPUT, 5V/div A= DIGITAL INPUT, 5V/div B= Vouta, 2V/div B= Vouta, 2V/div B= Vouta, 2V/div TIMEBASE = Ips TIMEBASE = 1s TIMEBASE = 1s Vp = +5V Vop = +5V Vop = +5V VREFA = +5V VREFA = +5V VREFA = 45V ALL BITS OFF TO ALL BITS ON ALL BITS ON TO ALL BITS OFF ALL BITS ON TO ALL BITS OFF Ri = 10kQ, CL = 100pF RL = 10kQ, CL = 100pF RL = 10kQ, CL = 100pF 6 MAAXIAAQuad 8-Bit DACs with Rail-to-Rail Voltage Outputs Pin Description PIN NAME FUNCTION MAX505 MAX506 1 1 Voute | DAC B Output Voltage 2 2 VouTa | DAC A Output Voltage 3 3 Vss Negative Power Supply 4 VREFB | Reference Voltage Input for DAC B 4 VREF | Reference Voltage Input for DAC A to DAC D 5 VREFA | Reference Voltage Input for DAC A 6 5 AGND | Analog Ground 7 6 DGND | Digital Ground 8 (DAG oad DAC eet ect ;ariving this asynchronous input low transfers the contents of each 9 7 D7 Data Bit 7 (MSB) 10 8 D6 Data Bit 6 aa) 9 DS Data Bit 5 12 10 D4 Data Bit 4 13 11 D3 Data Bit 3 14 12 D2 Data Bit 2 15 13 D1 Data Bit 1 16 14 Do Data Bit 0 (LSB) 17 15 WR Write Input (active low). Used to load data into the DAC input latch selected by AO and A1. 18 16 Al DAC Address select bit (MSB) 19 17 AO DAC Address select bit (LSB) 20 VREFD | Reference Voltage Input for DAC D 21 VREFC | Reference Voltage Input for DAC C 22 18 Vop Positive Supply Voltage 23 19 Voutp | DAC D Output Voltage 24 20 Voutc | DAC C Output Voltage MAAXLMNA 90SXVW/SOSXUWMAX505/MAX506 Quad 8-Bit DACs with Rail-to-Rail Voltage Outputs Detailed Description Digital-to-Analog Section The MAX505/MAX506 contain four matched voltage-out- put DACs. The DACs are inverted R-2R ladder networks that convert 8-bit digital words into equivalent analog output voltages in proportion to the applied reference voltage(s). Each DAC in the MAX505 has a separate reference input, while al! four DACs in the MAX506 share a common reference input. Figure 1 shows a simplified functional diagram of one of the DACs. SHOWN FOR ALL 1 ON DAC Figure 1. DAC Simplified Circuit Diagram Power Supplies and Reference Input The MAX505/MAX506 can be used for multiplying applications. The reference accepts both DC and AC signals. The voltage at each VREF input sets the full-scale output voltage for its respective DAC. The VREF input impedance is code dependent, with the lowest value (16kQ for the MAX505 and 4kQ for the MAX506) occuring when the input code is 55 hex. The maximum value, essentially infinity, occurs when the input code is 00 hex. Since the VREF input im- pedance is code dependent, the DACs reference sour- ces must have a low output impedance (no more than 32Q for the MAX505 and 8Q for the MAX506) to maintain output linearity. The VREF input capacitance is also code dependent: 15pF maximum for the MAX505 and 40pF maximum for the MAX506. The output voltage for any DAC can be represented by a digitally programmable voltage source as: Vout = (NB x VREF) / 256 where Ng is the numeric value of the DACs binary input code. Output Buffer Amplifiers All MAX505/MAX506 voltage outputs are internally buf- fered by precision unity-gain followers that slew at 1V/us. With a OV to +4V (or +4V to OV) output transition, the amplifier outputs will settle to 1/2LSB in typically 6us when loaded with 10kQ in parallel with 100pF. The buffer amplifiers are stable with any combination of resistive loads = 2kQ and capacitive loads < 300pF. Digital Inputs and Interface Logic The digital inputs are compatible with both TTL and 5V CMOS logic. However, the power-supply current (IDD) depends on the input logic levels. Supply current is specified for CMOS input levels (best case). Supply current increases by about 2mA when driven with TTL logic levels. Address lines AO and A1 select which DAC receives data from the data bus as shown in Table 1. When WR is low, the addressed DAC's input latch is transparent. Data is latched when WR is high. Figure 2 shows the MAX505/MAX506 input control logic. The MAX506 DAC outputs represent the data held in the four 8-bit input latches. The MAX505 has double- buffered inputs; in addition to the input registers, there are individual DAC latches (see Functional Diagrams). . MAXILAANQuad 8-Bit DACs with Rail-to-Rail Voltage Outputs [DAC TOAL 5 ONLY) LATCHES Ad S. TOINPUT uw => Ri TO Ne Al VY TO INPUT LATCH D D- 8 =D Rise =D- -_> > Figure 2. MAX505/MAX506 Input Control Logic In the MAX505, data is transferred from the input latches to the DAC latches by pulling the LDA control input low. This operation simultaneously updates all four outputs. Since LDAC is asynchronous with respect to WR, be sure that incorrect data is not latched to the output. Table 1a is the write-cycle truth table for the MAX505. Table 1b is the write-cycle truth table for the MAX506. Figure 3 shows the MAX505/MAX506 write-cycle timing. If simultaneous updating is not required, tie LDAC low to keep the DAC latches transparent. To avoid output glitches, insure that data is valid before WR goes low (MAX506). This also applies to the MAX505 if WR and LDAC are low simultaneously. On power-up, all MAX505/MAX506 latches are internally preset with all Os. MA AXLAA Table 1a. MAX505 DAC Addressing (partial list) LDAC | WR | Ai | AO LATCH STATE H xX X | Input and DAC data latched H L L L | DACA input latch transparent All4 DACs DAC latches transparent isters transparent and i | DACAI latches transparent t all 4 DACs DA\ DAC B input latch transparent H L H L | DAC Cinput latch transparent H L H|H DAC D input latch transparent H = High State, L = Low State, X = Don't Care Table 1b. MAX506 DAC Addressing (partial list) wR | At AO LATCH STATE H xX xX Input data latched L L L DAC A input latch transparent L L H DAC B input latch transparent L H L DAC C input latch transparent L H H DAC D input latch transparent H = High State, L = Low State, X = Don't Care 90SXVW/SOSXVWMAX505/MAX506 Quad 8-Bit DACs with Rail-to-Rail Voltage Outputs oes YY CMMMMMMMMM@EC_ paTA YI fp DATA VALID - FIO oars ONLI ACTMATED PON wimane EDGE, T MUST STAY LOW FOR tip (OR LONGER) AFTER WR GOES HIGH. Figure 3. MAX505/MAX506 Write-Cycle Timing Diagram Applications Information Power Supply and Reference Operating Ranges The MAX505/MAXS506 are fully specified to operate with Vpob = 5V+10% and Vss = OV to -5.5V. 8-bit performance is guaranteed for both single- and dual-supply operation. The zero-code output error is guaranteed to be less than 14mV when operating from a single +5V supply. The DACs work well with reference voltages from Vss to Vpp. Vss should never be more positive than either AGND or DGND. No input should be more positive than Vpp. Power-Supply Bypassing and Ground Management In single-supply operation (AGND = DGND = Vss = OV), AGND, DGND, and Vss should be connected together in a "star" ground at the chip. This ground should then return to the highest quality ground available. Bypass Vpp witha 0. 1pF capacitor, located as close to VoD and AGND as possible. In dual-supply operation, where DGND = AGND, Vop and Vss should be bypassed with 0.1pF capacitors to AGND. These capacitors should be placed as close to the supply pins as possible. To minimize digital noise on AGND, DGND and AGND should have separate return paths to the highest quality ground available. 10 Careful PCB layout minimizes crosstalk between DAC outputs, reference inputs, and digital inputs. Figures 4 and 5 show suggested circuit board layouts to minimize crosstalk. SYSTEM GND COMPONENT SIDE MAX505 (TOP VIEW) Figure 4. Suggested MAX505 PCB Layout for Minimizing Crosstalk MAAXILANQuad 8-Bit DACs with Rail-to-Rail Voltage Outputs SYSTEM GND Yours ) Vortec on = = : Vs = ta vet =a = 5s MSB6) @ 1S8 2 9 COMPONENT SIDE MAX506 (TOP VIEW) REFERENCE INPUTS (VssTOVop) = 45V ) ee) ee 22| VREFA, VREFQ VREFO Vop | DAC B DIGTAL INPUTS J NOT SHOWN 24 DAC THe Voute DACA SL 2 > VOUTA > Voure 23 VOUTD 4 DAC D Vss AGND __DGND MUM 13 G 7 MAX505 ~5V (OR GND} Figure 5. Suggested MAX506 PCB Layout for Minimizing Crosstalk Unipolar Output, 2-Quadrant Multiplication In unipolar operation, the output voltages and the refer- ence input(s) are the same polarity. Figures 6 and 7 show the MAX505/MAX506 unipolar configurations. If the ref- erence inputs are positive, both devices can be operated from a single supply. {f dual supplies are used, the reference input can vary from Vss to Vpp. Table 2 is the unipolar code table. Bipolar Output, 2-Quadrant Multiplication Bipolar output 2-quadrant multiplication is achieved by offsetting AGND positively or negatively. Offsetting AGND Positively - Single or Dual Supplies AGND can be biased above DGND to provide an arbitrary nonzero output voltage for a 0 input code, as shown in Figure 8. The output voltage at VouTA is: VOUTA = VBIAS + (NB/256)(VIN), where Ng represents the digital inout word. Since AGND is common to all four DACs, all outputs will be offset by VBiAs in the same manner. AGND should not be biased more than +1V above DGND. MA AXIAA Figure 6. MAX505 Unipolar Output Circuit REFERENCE INPUTS (VssTO Von) 45V 4] 18} VREF] Voo DACA Su DAC ut SU 2 > VouTA > VOUTB 20 > Vourc 19 > VouTD DIGTAL INPUTS T NOT SHOWN DAC C DAC D Vss AGND DGND Ts I i -5V (OR GND MAX506 (ORGNO} + Figure 7. MAX506 Unipolar Output Circuit 11 90SXVW/SOSXUWMAX505/MAX506 Quad 8-Bit DACs with Rail-to-Rail Voltage Outputs Table 2. Unipolar Code Tabie Table 3. Bipolar Code Table DAC CONTENTS DAC CONTENTS ANALOG OUTPUT ANALOG OUTPUT MSB LsB MSB LSB 255 127 1111 1111 wwner (72 1111 1111 veer (737) 1000 0001 | +VREF 26 | 1000 0001 VRE ( 1000 0000 ovner (223 |= + VREF 1000 0000 ov 1 0111 1111 -vrer( 5] 0111 1411 wre (325 128 ; 0000 0001 avner (33 0000 0001 was] 128 0000 0000 0000 0000 -vrer (735 |= VREF 8 Note: 1LSB = (VREF) (2) = +VREF (e Offsetting AGND Negatively - Dual Supplies +5V An alternate method of generating bipolar outputs uses 5 Figure 9's circuits. In these circuits, AGND is biased VREFA Woo negatively (up to -2.5V with respect to DGND) to provide an arbitrary negative output voltage for a 0 input code. V > The output voltage at VouTA is: N a DACA - VOUTA = -(R2/R1) (2.5V) + + (Np/256) (2.5V) (R2/R1 + 1) 8] scnp MAAKLAA where Ng represents the digital input word. Since AGND Veuas Vsg DGND MAXS05 is common to all four DACs, all outputs will be offset by TB Tr Vailas in the same manner. Table 3, with VREF = 2.5V, = -5V(0R GND) shows the digital code vs. output voltage for Figure 9's circuits with R1 = 4-Quadrant Multiplication 1 oY : Each DAC output may be configured for 4-quadrant VREF a multiplication using Figure 10's circuit. One op amp and two resistors are required per channel. With Rt = R2: VouT = VREF [((2)(NB/256) -1], VIN - 2S Voua where NB represents the digital word in DAC register A. DAC A . Recommended values for resistors R1 and R2 are 330kQ 5] eno MAXUM (40.1%). Table 3 shows the digital code vs. output voit- Veus Vss DGND MAX506 age for Figure 10's circuit. i Te = -SV(ORGND) = * DIGITAL INPUTS NOT SHOWN 12 Figure 8. AGND Bias Circuits (Positive Offset) MAAXLAAQuad 8-Bit DACs with Rail-to-Rail Voltage Outputs REFERENCE INPUTS + 5 }4 121 120 + OIGITAL Vv INPUTS NOT SHOWN te Voura 24 VouTc 23 Vouto MaUmM MAX505 Figure 9a. MAX505 AGND Bias Circuit (Negative Offset) REFERENCE INPUT 45V Ope 4 wit DIGITAL +5V INPUTS NOT SHOWN Ht Our man 1% MAX873 \,o5v Ri Figure 9b. MAX506 AGND Bias Circuit (Negative Offset) MA AXIAA 13 90SXVW/SOSXVNMAX505/MAX506 Quad 8-Bit DACs with Rail-to-Rail Voltage Outputs REFERENCE INPUTS ones +V. 5 |4 jar} mit ad hi DACA : | | VOUTA DAC B i Voure ICL7612A Vout DIGITAL INPUTS NOT SHOWN MAGA MAXS506 v AGND_DGND one 3 5] oI AGND OR -5V DIGITAL INPUTS NOT SHOWN 45V DACC Us S | 24 2 Voutc ICL7612A DACD PSL Vour PAMGLAA MAX505 Vss AGND_DGND -v a AGND OR -SV NOTE: CONNECT ICL7612A PIN 8 TO AGND Figure 10a, MAX505 Bipolar Output Circuit REFERENCE INPUT 45V 01 4 win Vout NOTE: CONNECT ICL7612A PIN 8 TO AGND Figure 10b. MAX506 Bipolar Output Circuit 14 MAMXIAA__Functional Diagrams (continued) Quad 8-Bit DACs with Rail-to-Rail Voltage Outputs __. Pin Configurations (continued) * Contact factory for dice specifications. **Contact factory for availability and processing to MIL-STD-883. MAAXLAA VREF Voo 4 118 TOP VIEW 2. Vouta =e DACA Voure [1 | Voura [2 | = ; SL. Vours Vss [3 | XE DACB . vReF [| AGND (5 PUT Py DAC . Le Voutc DGND [6 | (ms8)07 [7 | 6 [3 DACD Le Vou 05 [a] 4 fro} MAX506 DIP/SO 7 7 o Vss_AGND DGND Ordering Information PART TEMP.RANGE PIN-PACKAGE (LSBs) MAXSOSAENG -40Cto+85C 24NanowPlasicDIP +1 MAXSO5BENG -40Cto+85C 24NarowPlasicDIP_ 4116 MAXSO5AEWG -40Cto+85C 24 WideSO H MAX505BEWG -40C to +85C 24 Wide SO t1% MAX50SAEAG -40C to +85C 24SSOP +1 MAX505BEAG -40Cto+85C 24SSOP t1% MAXSOSAMRG -55C to +125C 24NarowCERDIP +1 MAXS505BMRG -S5'Cto +125C 24NanowCERDIP +116 MAXSO6ACPP O'Cto+70C 20 Plastic DIP +1 MAX506BCPP OCto+70C 20PlasticDIP +116 MAX506ACWP O'Cto+70C 20 Wide SO +1 MAXS5O6BCWP OCto+70C 20 Wide SO il MAX506BC/D OCto+70C _Dice* +1% MAX506AEPP -40C to +85C 20 Plastic DIP 1 MAXS506BEPP -40Cto+85C 20PlasticDIP +14 MAX5O06AEWP -40Cto+85C 20 Wide SO +1 MAX506BEWP -40C to +85C 20 Wide SO ti% MAXSO6AMJP -55C to +125C 20 CERDIP** + MAX506BMJP -55Cto +125C 20 CERDIP** +1% 18 90SXVW/SOSXUWQuad 8-Bit DACs with Rail-to-Rail Voltage Outputs Chip Topographies MAX505 MAXS05/MAX506 06 DS D4 03 02 D1 0.126" (3.200 mm) TRANSISTOR COUNT: 1717; SUBSTRATE CONNECTED TO VoD. DS D403 D2 D1 0.126" (3.200 mm) TRANSISTOR COUNT: 1717, SUBSTRATE CONNECTED TO VoD. Package information POO e Ae ROE r | some Me | > Ohne DIM INCHES MILLIMETERS MIN | MAX | MIN | MAX | A | 0.068 | 0.078 1.73 1.99 A1 | 0.002 | 0.008 0.05 0.21 B 0.010 | 0.015 0.25 0.38 Cc | 0.005 | 0.009 0.13 0.22 D | 0.278 | 0.328 7.07 8.33 E 0.205 | 0.212 5.20 5.38 e 0.0256 BSC 0.65 BSC H 0.301 0.311 7.65 7.90 L 0.022 | 0.037 0.55 0.95 a 0 8 O 3 21-0002A a r F 24-PIN PLASTIC \ SHRINK tc SMALL-OUTLINE PACKAGE Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 1994 Maxim Integrated Products Printed USA MAAXLAA is a registered trademark of Maxim Integrated Products.