MK3721DTR - Integrated Circuit Systems, Inc.

MDS 3721 C 1Revisi on 070601

Integrated C ircuit Systems ● 5 25 Race Street, San Jose, CA 95126 ● tel (408) 2 95-9800 ● www.icst.com

LOW COST 16.2 - 28 MHZ 3.3 VOLT VCXO

MK3721

Description

The MK3721 series of devices includes the original

MK3721S and the new MK3721D. The MK3721D is a

drop-in replacement for the MK3721S device.

Compared to the earlier device, the MK3721D offers a

wider operating frequency range and improved power

supply noise rejection.

The MK3721 is ICS’ lowest cost, low jitter, high

performance 3.3 volt VCXO designed to replace

expensive discrete VCXOs modules. The on-chip

Voltage Controlled Crystal Oscillator accepts a 0 to 3.3

V input voltage to cause the output clocks to vary by

±100 ppm. Using ICS’ patented VCXO techniques, the

device uses an inexpensive external pullable crystal in

the range of 16.2 - 28 MHz to produce a VCXO output

clock at that same frequency.

ICS manufactures the largest variety of Set-Top Box

and multimedia clock synthesizers for all applications.

If more clock outputs are needed, see the MK3732 or

MK377x family of parts. Consult ICS to eliminate

VCXOs, crystals, and oscillators from your board.

The frequency of the on-chip VCXO is adjusted by an

external control voltage input into pin VIN. Because

VIN is a high impedance input, it can be driven directly

from an PWM RC integrator circuit. Frequency output

increases with VIN voltage input. The usable range of

VIN is 0 to 3V.

Features

•MK3721D is a drop-in replacement for the earlier

MK3721S device

•Packaged in 8 pin SOIC

•Operational frequency range of 16.2 MHz to 28 MHz

•Uses an inexpensive external crystal

•On-chip patented VCXO with pull range of 200ppm

(minimum)

•VCXO tuning voltage of 0 to 3.3 V

•Operating voltage of 3.3 V

•12 mA output drive capability at TTL levels

•Advanced, low power, sub-micron CMOS process

•For frequencies between 1 MHz and 8 MHz, use the

MK3713D. For higher than 28 MHz, use the

MK3732-05.

MK3721D is Recommended for New Designs.

Block Diagram

Voltage

Controlled

Crystal

Oscillator

VIN

16.2-28 MHz

Pullable

Crystal

16.2-28 MHz Clock

(REFOUT)

GND

VDD

LOW COST 16.2 - 28 MHZ 3.3 VOLT VCXO

MDS 3721 C 2Revision 070601

Integrated C ircuit Systems ● 525 R ace Street, San Jose, CA 95126 ● tel (40 8) 295-9800 ● www.icst.com

MK3721

Pin A ssign ment

Pin Descriptions

VDD

VIN

GND

REFOUT

X21

MK3721S

MK3721D

8 Pin (150 mil) SOIC

Number Pin

Name Pin

Type Pin Description

1 XI Input Crystal connection. Connect to the external pullable crystal.

2 VDD Power Connect to +3.3 V (0.01uf decoupling capacitor recommended).

3 VIN Input Voltage input to VCXO. Zero to 3.3V signal which controls the VCXO

frequency.

4 GND Power Connect to ground.

5 DC -- Do not connect anything to this pin.

6 REFOUT Output VCXO CMOS level clock output matches the nominal frequency of the

crystal.

7 DC -- Do not connect anything to this pin.

8 X2 Input Crystal connection. Connect to a pullable 16.2 - 28 MHz crystal.

LOW COST 16.2 - 28 MHZ 3.3 VOLT VCXO

MDS 3721 C 3Revision 070601

Integrated C ircuit Systems ● 525 R ace Street, San Jose, CA 95126 ● tel (40 8) 295-9800 ● www.icst.com

MK3721

External Component Selection

The MK3721 requires a minimum number of external

components for proper operation.

Decoupling Capacitors

A decoupling capacitor of 0.01µF should be connected

between VDD and GND on pins 2 and 4 as close to the

MK3721 as possibl e. For opti mu m devic e

performance, the decoupling capacitor should be

mounted on the component side of the PCB. Avoid the

use of vias in the decoupling circuit.

Series Termination Resistor

When the PCB trace between the clock output and the

load is over 1 inch, series termination should be used.

To series terminate a 50Ω trace (a commonly used

trace impedance) place a 33Ω resistor in series with

the clock line, as close to the clock output pin as

poss ible. T he nomi nal impedan ce of the cl ock out put i s

20Ω.

Quartz Crysta l

The MK3721 VCXO function consists of the external

crystal and the integrated VCXO oscillator circuit. To

assure the best system performance (frequency pull

range) and reliability, a crystal device with the

recommended parameters (shown below) must be

used, and the layout guidelines discussed in the

following section shown must be followed.

The frequency of oscillation of a quartz crystal is

determined by its “cut” and by the load capacitors

connected to it. The MK3721 incorporates on-chip

variable load capacitors that “pull” (change) the

frequency of the crystal. The crystal specified for use

with the MK3721 is designed to have zero frequency

error when the total of on-chip + stray capacitance is

14pF.

Recommended Crystal Parameters:

Initial Accuracy at 25°C±20 ppm

Temperature Stability ±30 ppm

Aging ±20 ppm

Load Capacitance 14 pf

Shunt Capacitance, C0 7 pF Max

C0/C1 Ratio 250 Max

Equivalent Series Resistance 35 Ω Max

The e xte rnal crys tal must be conn ect ed a s clos e to the

chip as possible and should be on the same side of the

PCB as the MK3721. There should be no via’s between

the crystal pins and the X1 and X2 device pins. There

should be no signal traces underneath or close to the

crystal. See application note MAN05.

Crystal Tuning Load Capacitors

The crystal traces should include pads for small fixed

capacitors, one between X1 and ground, and another

between X2 and ground. Stuffing of these capacitors

on the PCB is optional. The need for these capacitors

is determined at system prototype evaluation, and is

influenced by the particular crystal used (manufacture

and frequency) and by PCB layout. The typical required

capacitor value is 1 to 4 pF.

To determine the need for and value of the crystal

adjustment capacitors, you will need a PC board of

your final layout, a frequency counter capable of about

1 ppm resolution and accuracy, two power supplies,

and some samples of the crystals which you plan to

use in production, along with measured initial accuracy

for each crystal at the specified crystal load

capacitance, CL.

To determine the value of the crystal capacitors:

1. Connect VDD of the MK3721 to 3.3V. Connect pin 3

of the MK3721 to the second power supply. Adjust the

voltage on pin 3 to 0V. Measure and record the

frequency of the CLK output.

2. Adjust the voltage on pin 3 to 3.3V. Measure and

record the frequency of the same output.

To calculate the centering error:

Where:

ftarget = nominal crystal frequency

errorxtal =actual initial accuracy (in ppm) of the crystal

being measured

If the centering error is less than ±25 ppm, no

adjustment is needed. If the centering error is more

than 25ppm negative, the PC board has excessive

stray capacitance and a new PCB layout should be

Error 106xf3.0V ftetarg

–()f0V ftetarg

–()+

ftetarg

------------------------------------------------------------------------------ errorxtal

–=

LOW COST 16.2 - 28 MHZ 3.3 VOLT VCXO

MDS 3721 C 4Revision 070601

Integrated C ircuit Systems ● 525 R ace Street, San Jose, CA 95126 ● tel (40 8) 295-9800 ● www.icst.com

MK3721

considered to reduce stray capacitance. (Alternately,

the crystal may be re-specified to a higher load

capacitance. Contact ICS MicroClock for details.) If the

centering error is more than 25ppm positive, add

identical fixed centering capacitors from each crystal

pin to ground. The value for each of these caps (in pF)

is given by:

External Capacitor =

2 x (centering error)/(trim sensitivity)

Trim sensitivity is a parameter which can be supplied

by your crystal vendor. If you do not know the value,

assume it is 30 ppm/pF. After any changes, repeat the

measurement to verify that the remaining error is

acceptably low (typically less than ±25ppm).

Absolute Maximum Rating s

Stresses above the ratings listed below can cause permanent damage to the MK3721. These ratings,

which are standard values for ICS commercially rated parts, are stress ratings only . Functional operation of

the device at these or any other conditions above those indicated in the operational sections of the

specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can

affect product reliability. Electrical parameters are guaranteed only over the recommended operating

temperature range.

Recommended Oper ation Conditio ns

Item Rating

Supply Voltage, VDD 7V

All Inputs and Outputs -0.5V to VDD+0.5V

Ambient Operating Temperature 0 to +70°C

Storage Temperature -65 to +150°C

Soldering Temperature 260°C

Parameter Min. Typ. Max. Units

Ambient Operating Temperature 0 – +70 °C

Power Supply Voltage (measured in respect to GND) +3.15 +3.45 V

Reference crystal parameters Refer to page 3

LOW COST 16.2 - 28 MHZ 3.3 VOLT VCXO

MDS 3721 C 5Revision 070601

Integrated C ircuit Systems ● 525 R ace Street, San Jose, CA 95126 ● tel (40 8) 295-9800 ● www.icst.com

MK3721

DC Electrical Characteristics

VDD=3.3V ±5% , Ambient temperature 0 to +70°C, unless stated otherwise

AC Electrical Characteristics

VDD = 3. 3V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise

Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.

Parameter Symbol Conditions Min. Typ. Max. Units

Operati ng Voltage VDD 3.15 3.45 V

Output High Volta ge VOH IOH = -12 mA 2.4 V

Output Low Voltage VOL IOL = 12 mA 0.4 V

Output High Voltage (CMOS

Level) VOH IOH = -4 mA VDD-0.4 V

Operating Supply Current IDD No load 6 mA

Short Circuit Current IOS ±50 mA

VIN, VCXO Control Voltage VIA 03.3V

Parameter Symbol Conditions Min. Typ. Max. Units

Output Frequency

MK3721D FO16.2 28 MHz

MK3721S FO24 MHz 24 MHz

Crystal Pullability

MK3721D FP0V< VIN < 3.3V, Note 1 + 115 ppm

MK3721S FP0V< VIN < 3.3V, Note 1 + 100 ppm

VCXO Gain

MK3721D VIN = VDD/2 + 1V, Note 1 120 ppm/V

MK3721S VIN = VDD/2 + 1V, Note 1 140 ppm/V

Output Rise Time tOR 0.8 to 2.0V, CL=15pF 1.5 ns

Output Fall Time tOF 2.0 to 0.8V, CL=15pF 1.5 ns

Output Clock Duty Cycle tDMeasured at 1.4V, CL=15pF 40 50 60 %

Maximum Output Jitter,

short term tJCL=15pF 110 ps

LOW COST 16.2 - 28 MHZ 3.3 VOLT VCXO

MDS 3721 C 6Revision 070601

Integrated C ircuit Systems ● 525 R ace Street, San Jose, CA 95126 ● tel (40 8) 295-9800 ● www.icst.com

MK3721

h x 450

Pin 1

Index

Area

Package Outline and Package Dimensions (8 pin SOIC)

Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

Note 1: MK3721D is recommended for new designs.

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)

assumes no responsibility for either its use or for the infring ement of any patents or other rig hts of th ird parties, which would

result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial

applications. Any oth er ap pl ic atio ns su ch as those req uiring ext end ed tem pera ture range, hig h re lia bi lity, or other ex trao rdi nary

environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any

circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or

critical medical instruments.

Part / Order Number

(Note 1) Marking Shipping

packaging Package Temperature

MK3721D MK3721D Tubes 8 pin SOIC 0 to +70° C

MK3721DTR MK3721D Tape and Reel 8 pin SOIC 0 to +70° C

MK3721S MK3721S T ubes 8 pin SOIC 0 to +70° C

MK3721STR MK3721S Tape and Reel 8 pin SOIC 0 to +70° C

Millimeters Inches

Symbol MinMaxMinMax

A 1.35 1.75 0.0532 0.0688

A1 1.10 0.25 0.0040 0.0098

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.0075 0.0098

D 4.80 5.00 .1890 .1968

E 3.80 4.00 0.1497 0.1574

e 1.27 Basic 0.050 Basic

H 5.80 6.20 0.2284 0.2440

h 0.25 0.50 0.010 0.020

L 0.40 1.27 0.016 0.050

°8°0°8°