NCP1360, NCP1365 Low Power Offline Constant Current & Constant Voltage Primary Side PWM Current-Mode Controller with/without High Voltage Startup Current Source The NCP1360/65 offers a new solution targeting output power levels from a few watts up to 20 W in a universal-mains flyback application. Thanks to a novel method this new controller saves the secondary feedback circuitry (opto-coupler and TL431 reference) while achieving excellent line and load regulation. The NCP1360/65 operates in valley-lockout quasi-resonant peak current mode control mode at nominal load to provide high efficiency. When the secondary-side power starts diminishing, the switching frequency naturally increases until a voltage-controlled oscillator (VCO) takes the lead, synchronizing the MOSFET turn-on in a drain-source voltage valley. The frequency is thus reduced by stepping into successive valleys until the number 4 is reached. Beyond this point, the frequency is linearly decreased in valley-switching mode until a minimum is hit. This technique keeps the output in regulation with the tiniest dummy load. Valley lockout during the first four drain-source valleys prevents erratic discrete jumps and provides good efficiency in lighter load situations. * * * * * * * Reference 5% Voltage Regulation 10% Current Regulation 560 V Startup Current Source No Frequency Clamp, 80 or 110 kHz Maximum Switching Frequency Options Quasi-Resonant Operation with Valley Switching Operation Fixed Peak Current & Deep Frequency Foldback @ Light Load Operation External Constant Voltage Feedback Adjustment Cycle by Cycle Peak Current Limit Build-In Soft-Start Over & Under Output Voltage Protection Cable Drop Compensation (None, 150 mV, 300 mV or 450 mV option) Wide Operation VCC Range (up to 28 V) (c) Semiconductor Components Industries, LLC, 2016 June, 2018 - Rev. 7 8 SOIC-7 CASE 751U 1 TSOP-6 CASE 318G 1 XXXXX ALYWX G xxxAYWG G 1 A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package (Note: Microdot may be in either location) See detailed ordering and shipping information on page 27 of this data sheet. * Primary-Side Feedback Eliminates Opto-coupler and TL431 * MARKING DIAGRAMS ORDERING INFORMATION Features * * * * www.onsemi.com * * * * * * * Low Start-up Current (2.5 mA typ.) with NCP1360 Clamped Gate-drive Output for MOSFET CS & Vs/ZCD pin Short and Open Protection Internal Temperature Shutdown Less than 10 mW No-Load Performance at High Line with NCP1365 Version Less than 30 mW No-Load Performance at High Line with NCP1360 Version These are Pb-Free Devices Typical Applications * Low power ac-dc Adapters for Chargers. * Ac-dc USB chargers for Cell Phones, Tablets and Cameras 1 Publication Order Number: NCP1360/D NCP1360, NCP1365 NCP1360 NCP1365 VCC 1 6 VS/ZCD GND 2 5 COMP DRV CS 4 3 VS/ZCD 1 COMP 2 CS DRV 8 HV 3 6 VCC 4 5 GND (Top View) (Top View) Figure 1. Pin Connections 2 Ac 0 Vout Ac 3 0 5 1 2 3 4 NCP1365 Vs/ZCD 8 HV Comp CS DRV 4 6 VCC 1 5 GND 0 Figure 2. NCP1365 Typical Application Circuit 2 Ac 0 Ac 3 0 5 4 5 6 NCP1360 CS DRV Comp GND ZCD Vcc 3 4 2 1 1 0 Figure 3. NCP1360 Typical Application Circuit www.onsemi.com 2 Out NCP1360, NCP1365 IHV Vcc NCP1365 Only UVLO Vdd VCC(Reset) VCC(OVP) DbleHiccup POReset EN_UVP VCC and Logic Management of double hiccup Vcc(clamp) Rlim POReset Double_Hiccup_ends Zero Crossing & Signal Sampling SS QR multi-mode Valley lockout & Valley Switching & VCO management Sampled Vout Control Law & Primary Peak Current Control SS FB_CC CC Control Vref_CC Reset Soft Start Blanking Latch Vs / ZCD HV FB_CV CBC UVLO Clamp S VCC(OVP) OVP_Cmp R SCP OVP 126% Vref_CV2 DRV Q 4 clk Counter Vref_CV1 Vcc FB Latch Comp OTA S UVP_Cmp VUVP Vref_CV2 Peak current Freeze VDD ICS R S Q EN_UVP GND Q VCC(Reset) POReset UVP R DbleHiccup 1/Kcomp FB Reset ICS_EN CS LEB1 Note: OVP: Over Voltage Protection UVP: Under Voltage Protection OCP: Over Current Protection SCP: Short Circuit Protection CBC: CaBle Compensation tLEB1 > tLEB2 Max_Ipk reset Count VILIM OCP Timer OCP Reset Timer POReset DbleHiccup R Reset Counter LEB2 4 clk Counter Q S SCP VCS(Stop) ICS_EN CS pin Open (VCS > 2 V) & Short (VCS < 50 mV) detection is activated at each startup CS pin Fault Figure 4. Functional Block Diagram: A Version www.onsemi.com 3 NCP1360, NCP1365 PIN FUNCTION DESCRIPTION Pin out NCP1365 Pin out NCP1360 Name Function 1 6 Vs/ZCD Connected to the auxiliary winding; this pin senses the voltage output for the primary regulation and detects the core reset event for the Quasi-Resonant mode of operation. 2 5 Comp 3 4 CS 4 3 DRV Controller switch driver. 5 2 GND Ground reference. 6 1 VCC This pin is connected to an external auxiliary voltage and supplies the controller. 7 - NC Not Connected for creepage distance between high and low Voltage pins 8 - HV Connected the high-voltage rail, this pin injects a constant current into the VCC capacitor for starting-up the power supply. This is the error amplifier output. The network connected between this pin and the ground adjusts the regulation loop bandwidth. This pin monitors the primary peak current. MAXIMUM RATINGS Symbol Rating Value VCC(MAX) Maximum Power Supply voltage, VCC pin, continuous voltage VCC/t Maximum slew rate on VCC pin during startup phase VDRV(MAX) IDRV(MAX) VMAX IMAX VHV RJ-A TJ(MAX) Unit -0.3 to 28 V +0.4 V/ms -0.3, VDRV (Note 1) -300, +500 V mA -0.3, 5.5 -2, +5 V mA -0.3 to 560 V Thermal Resistance Junction-to-Air 200 C/W Maximum Junction Temperature 150 C Operating Temperature Range -40 to +125 C Storage Temperature Range -60 to +150 C 2 kV Machine Model ESD Capability (All pins except DRV) per JEDEC JESD22-A115C 200 V Charged-Device Model ESD Capability per JEDEC JESD22-C101E 500 V Maximum driver pin voltage, DRV pin, continuous voltage Maximum current for DRV pin Maximum voltage on low power pins (except pins DRV and VCC) Current range for low power pins (except pins DRV and VCC) High Voltage pin voltage Human Body Model ESD Capability per JEDEC JESD22-A114F Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC otherwise 2. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78. www.onsemi.com 4 NCP1360, NCP1365 ELECTRICAL CHARACTERISTICS: (VCC = 12 V, CDRV = 1 nF, For typical values TJ = 25C, for min/max values TJ = -40C to +125C, Max TJ = 150C, unless otherwise noted) Conditions Symbol Min Typ Max Unit VHV = 100 V IHV 70 100 150 mA VHV = 400 V, options NCP1365AABCY and NCP1365BABCY All other NCP1365 options IHV_LKG - 0.1 1.0 mA - 0.1 1.3 IHV = 95% of IHV@VHV = 100 V, VCC = VCC(on) - 0.2 V VHV(min) - 22 25 V Characteristics HIGH VOLTAGE STARTUP SECTION (NCP1365 only) Startup current sourced by VCC pin Leakage current at HV Minimum Start-up HV voltage SUPPLY SECTION AND VCC MANAGEMENT VCC level at which driving pulses are authorized VCC increasing VCC(on) 16 18 20 V VCC level at which driving pulses are stopped VCC decreasing VCC(off) 6.0 6.5 7.0 V VCC(reset) - 5.6 - V VCC(Clamp) - 4.2 - V Minimal current into VCC pin that keeps the controller Latched (NCP1365, A & C fault mode version) ICC(Clamp) - - 20 mA Minimal current into VCC pin that keeps the controller Latched (NCP1360, A & C fault mode version) ICC(Clamp) - - 6 mA Rlim - 7 - kW Over Voltage threshold VCC(OVP) 24 26 28 V VCC < VCC(on) & VCC increasing from 0 V ICC1 - 2.5 5.0 mA Internal IC consumption, steady state Fsw = 65 kHz, CDRV = 1 nF ICC2 - 1.7 2.5 mA Internal IC consumption, frequency foldback mode VCO mode, Fsw = 1 kHz, CDRV = 1 nF ICC3 - 0.8 1.2 mA VCO mode, Fsw = fVCO(min), VComp = GND, CDRV = 1 nF fVCO(min) = 200 Hz fVCO(min) = 600 Hz fVCO(min) = 1.2 kHz ICC4 Current Sense Voltage Threshold VComp = VComp(max), VCS increasing Cycle by Cycle Leading Edge Blanking Duration Internal Latch / Logic Reset Level VCC clamp level VCC clamp level (A & C version) Activated after Latch protection @ ICC = 100 mA Current-limit resistor in series with the latch SCR Over Voltage Protection Start-up supply current, controller disabled or latched (Only valid with NCP1360 ) Internal IC consumption when STBY mode is activated mA - - - 200 220 270 250 280 330 VILIM 0.76 0.80 0.84 V Options NCP1365AABCY, NCP1365BABCY, NCP1360AABCY, NCP1360BABCY only all other options tLEB1 250 300 360 ns 240 300 360 VCS > (VILIM+ 100 mV) to DRV turn-off tILIM - 50 100 CURRENT COMPARATOR Cycle by Cycle Current Sense Propagation Delay ns Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. The timer can be reset if there are 4 DRV cycles without overload or short circuit conditions 4. Guaranteed by Design. www.onsemi.com 5 NCP1360, NCP1365 ELECTRICAL CHARACTERISTICS: (VCC = 12 V, CDRV = 1 nF, For typical values TJ = 25C, for min/max values TJ = -40C to +125C, Max TJ = 150C, unless otherwise noted) Characteristics Conditions Symbol Min Typ Max Unit When CS pin w VILIM (Note 3) TOCP 50 70 90 ms VCS(stop) 1.08 1.2 1.32 V tLEB2 - 120 - ns - - - 120 160 200 - - - CURRENT COMPARATOR Timer Delay Before Latching in Overload Condition Threshold for Immediate Fault Protection Activation Leading Edge Blanking Duration for VCS(stop) Maximum peak current level at which VCO takes over or frozen peak current VComp < 1.9 V, VCS increasing option X (~15%VILIM) option Y (~20%VILIM) option Z (~25%VILIM) VCS(VCO) mV REGULATION BLOCK Internal Voltage reference for Constant Current regulation TJ = 25C -40C < TJ < 125C Vref_CC 0.98 0.97 1.00 1.00 1.02 1.03 V Internal Voltage reference for Constant Voltage regulation TJ = 25C -40C < TJ < 125C Vref_CV1 2.450 2.425 2.500 2.500 2.550 2.575 V Vref_CV2 - Vref_CV1+ (CBC/2) - V Error Amplifier Current Capability IEA - 40 - mA Error Amplifier Gain GEA 150 200 250 mS VComp(max) VComp(min) Vcomp(offset) - - - 4.9 0 1.1 - - - KComp - 4.0 - VComp decreasing VComp decreasing VComp decreasing VComp decreasing VComp increasing VComp increasing VComp increasing VComp increasing VH2D VH3D VH4D VHVCOD VHVCOI VH4I VH3I VH2I - - - - - - - - 2.50 2.30 2.10 1.90 2.50 2.70 2.90 3.10 - - - - - - - - Minimal difference between any two valleys VComp increasing or VComp decreasing DVH 176 - - mV Internal Dead Time generation for VCO mode Entering in VCO when Vcomp is decreasing and crosses VHVCOD TDT(start) - 2 - ms Internal Dead Time generation for VCO mode Leaving VCO mode when Vcomp is increasing and crosses VHVCOI TDT(ends) - 1 - ms Internal Dead Time generation for VCO mode When in VCO mode VComp = VHVCOD - 100 mV VComp = 1.3 V VComp = 0.8 V VComp < 0.4 V - 200 Hz option (Note 4) VComp < 0.4 V - 600 Hz option (Note 4) VComp < 0.4 V - 1.2 kHz option (Note 4) TDT - - - - - - 6 25 220 5000 1667 833 - - - - - - Internal Voltage reference for Constant Voltage regulation when cable compensation is enabled Error Amplifier Output Voltage Internal offset on Comp pin Internal Current Setpoint Division Ratio Valley Thresholds Transition from 1st to 2nd valley Transition from 2nd to 3rd valley Transition from 3rd to 4th valley Transition from 4th valley to VCO Transition from VCO to 4th valley Transition from 4th to 3rd valley Transition from 3rd to 2nd valley Transition from 2nd to 1st valley V - V ms Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. The timer can be reset if there are 4 DRV cycles without overload or short circuit conditions 4. Guaranteed by Design. www.onsemi.com 6 NCP1360, NCP1365 ELECTRICAL CHARACTERISTICS: (VCC = 12 V, CDRV = 1 nF, For typical values TJ = 25C, for min/max values TJ = -40C to +125C, Max TJ = 150C, unless otherwise noted) Characteristics Conditions Symbol VComp = GND fVCO(MIN) Min Typ Max Unit 150 450 0.9 200 600 1.2 250 750 1.5 Hz Hz kHz - No Clamp 80 110 - N/A 85 117 kHz kHz REGULATION BLOCK Minimum Operating Frequency in VCO Mode Maximum Operating Frequency fMAX Option Option 75 103 DEMAGNETIZATION INPUT - ZERO VOLTAGE DETECTION CIRCUIT and VOLTAGE SENSE VZCD threshold voltage VZCD decreasing VZCD(TH) 25 45 65 mV VZCD Hysteresis VZCD increasing VZCD(HYS) 15 30 45 mV After tBLANK_ZCD if VZCD < VZCD(short) U Latched VZCD(short) 30 50 70 mV Propagation Delay from valley detection to DRV high VZCD decreasing from 4 V to 0 V tDEM - - 170 ns Delay after on-time that the Vs/ZCD is still pulled to ground (Note 4) tshort_ZCD - 0.7 - ms tblank_ZCD 1.2 1.5 1.8 ms Timeout while in Soft-start Timeout after soft-start complete toutSS tout 36 4.5 44 5.5 52 6.5 VCC > VCC(on) VZCD = 4 V, DRV is low IZCD - - 0.1 RSNK RSRC - - 7 12 - - Threshold voltage for output short circuit or aux. winding short circuit detection Blanking delay after on-time (Vs/ZCD pin is disconnected from the internal circuitry) Timeout after last demagnetization transition Input leakage current ms mA DRIVE OUTPUT - GATE DRIVE Drive resistance DRV Sink DRV Source W Rise time CDRV = 1 nF, from 10% to 90% tr - 45 80 ns Fall time CDRV = 1 nF, from 90% to 10% tf - 30 60 ns DRV Low voltage VCC = VCC(off) + 0.2 V, CDRV = 220 pF, RDRV = 33 kW VDRV(low) 6.0 - - V DRV High voltage VCC = VCC(OVP)-0.2 V, CDRV = 220 pF, RDRV = 33 kW VDRV(high) - - 13.0 V Current Sense peak current rising from 0.2 V to 0.8 V tSS 3 4 5 ms Thermal Shutdown Device switching (Fsw 65 kHz) (Note 4) TSHTDN - 150 - C Thermal Shutdown Hysteresis Device switching (Fsw 65 kHz) (Note 4) TSHTDN(HYS) - 40 - C Number of Drive cycle before latch confirmation VComp = VComp(max), VCS > VCS(stop) Or Internal sampled Vout > VOVP Tlatch_count - 4 - - SOFT START Internal Fixed Soft Start Duration FAULT PROTECTION Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. The timer can be reset if there are 4 DRV cycles without overload or short circuit conditions 4. Guaranteed by Design. www.onsemi.com 7 NCP1360, NCP1365 ELECTRICAL CHARACTERISTICS: (VCC = 12 V, CDRV = 1 nF, For typical values TJ = 25C, for min/max values TJ = -40C to +125C, Max TJ = 150C, unless otherwise noted) Characteristics Conditions Symbol Min Typ Max Unit Fault level detection for OVP U Latched (VCC = VCC(clamp) with low consumption mode) Internal sampled Vout increasing VOVP = Vref_CV2+26% VOVP 2.95 3.15 3.35 V Fault level detection for UVP U Double Hiccup autorecovery (UVP detection is disabled during TEN_UVP) Internal sampled Vout decreasing Fault Mode Option A & B Fault Mode Option C with 300 mV CBC Fault Mode Option Version E VUVP 1.4 1.516 0.70 1.5 1.625 0.75 1.6 1.733 0.80 Starting at the beginning of the Soft start TEN_UVP - 37 - ms When VCS > VCS_min ICS - 55 - mA CS pin open VCS(open) 0.8 - - V VCS_min - 50 70 mV TCS_short - 3 - ms - - - - None 150 300 450 - - - - FAULT PROTECTION Blanking time for UVP detection Pull-up Current Source on CS pin for Open or Short circuit detection CS pin Open detection CS pin Short detection CS pin Short detection timer (Note 4) V CABLE DROP COMPENSATION Offset applied on Vref_CV1 at the maximum constant current CBC Option A Option B Option C Option D mV Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. The timer can be reset if there are 4 DRV cycles without overload or short circuit conditions 4. Guaranteed by Design. www.onsemi.com 8 NCP1360, NCP1365 FAULT MODE STATES TABLE WHATEVER THE VERSION Event Overcurrent VCS > VILIM Timer Protection Next Device Status OCP timer Double Hiccup Release to Normal Operation Mode * Resume to normal operation: if 4 pulses from FB Reset & then Reset timer * Resume operation after Double Hiccup Winding short VCS > VCS(stop) Immediate 4 consecutive pulses with VCS > VCS(stop) before Latching VCC is decreasing to VCC(clamp) and waiting for unplug from line VCC < VCC(reset) CS pin Fault: Short & Open Immediate Double Hiccup Resume operation after Double Hiccup Low supply VCC < VCC(off) 10 ms timer Double Hiccup Resume operation after Double Hiccup Internal TSD 10 ms timer Double Hiccup Resume operation after Double Hiccup & T < (TSHTDN - TSHTDN(Hyst)) ZCD short VZCD < VZCD(short) after tBLANK_ZCD time Immediate Double Hiccup Resume operation after Double Hiccup (VCC(on) < VCC < VCC(reset)) FAULT MODE STATES TABLE ACCORDING THE CONTROLLER VERSIONS Event A Version B Version C Version High supply VCC > VCC(ovp) Latched_Timer Autorecovery Latched_Timer Internal Vout OVP: Vout > 126% Vref_CV2 Latched_4clk Autorecovery Latched_4clk Internal Vout UVP: Vout < 60% Vref_CV2, when Vout is decreasing only Autorecovery Autorecovery Latched_Timer FAULT TYPE MODE DEFINITION Fault Mode Timer Protection Next Device Status Release to Normal Operation Mode Latched_Timer 10 ms timer Latched VCC is decreasing to VCC(clamp) and waiting for unplug from line VCC < VCC(reset) Latched_4clk Immediate 4 consecutive pulses with VOUT > 126% Vref_CV2 before Latching VCC is decreasing to VCC(clamp) and waiting for unplug from line VCC < VCC(reset) Autorecovery Immediate Resume operation after Double Hiccup Resume operation after Double Hiccup (VCC(on) < VCC < VCC(reset)) www.onsemi.com 9 NCP1360, NCP1365 CHARACTERIZATION CURVES 20 7.0 19.5 6.9 6.8 6.7 18.5 VCC(off) (V) VCC(on) (V) 19 18 17.5 6.1 -25 0 25 50 75 100 125 150 6.0 -50 25 50 75 100 125 TJ, TEMPERATURE (C) Figure 6. VCC Minimum Operating versus Temperature 28.0 6.4 27.5 150 27.0 VCC(OVP) (V) 6.0 5.8 5.6 5.4 5.2 26.5 26.0 25.5 25.0 5.0 24.5 4.8 -25 0 25 50 75 100 125 150 24.0 -50 -25 0 25 50 75 100 125 TJ, TEMPERATURE (C) TJ, TEMPERATURE (C) Figure 7. VCC(reset) versus Temperature Figure 8. VCC(OVP) versus Temperature 1.0 150 0.9 140 0.8 130 0.7 IHV_LKG (mA) 160 120 110 100 0.5 0.4 0.3 80 0.2 70 0.1 -25 0 25 50 75 100 125 150 150 0.6 90 60 -50 0 TJ, TEMPERATURE (C) 6.6 4.6 -50 -25 Figure 5. VCC Startup Threshold versus Temperature 6.2 VCC(reset) (V) 6.4 6.2 16.5 IHV (mA) 6.5 6.3 17 16 -50 6.6 0 -50 -25 0 25 50 75 100 125 150 TJ, TEMPERATURE (C) TJ, TEMPERATURE (C) Figure 9. Startup Current Source versus Temperature Figure 10. HV Pin Leakage versus Temperature www.onsemi.com 10 NCP1360, NCP1365 CHARACTERIZATION CURVES 2.4 24 2.0 ICC2 (mA) 18 16 1.6 1.4 12 1.2 -25 0 25 50 75 100 125 150 1.0 -50 25 50 75 100 125 TJ, TEMPERATURE (C) Figure 12. ICC2 versus Temperature 0.25 0.95 0.24 0.90 0.23 0.85 0.22 0.80 0.75 0.70 150 0.21 0.20 0.19 0.18 0.17 0.60 0.16 0.55 0.15 -25 0 25 50 75 100 125 150 0.14 -50 -25 0 25 50 75 100 125 TJ, TEMPERATURE (C) TJ, TEMPERATURE (C) Figure 13. ICC3 versus Temperature Figure 14. Standby Current Consumption (200 Hz option) versus Temperature 0.84 150 1.32 1.30 0.83 1.28 0.82 1.26 VCS(stop) (V) 0.81 0.80 0.79 1.24 1.22 1.20 1.18 1.16 0.78 1.14 0.77 0.76 -50 0 TJ, TEMPERATURE (C) 1.00 0.50 -50 -25 Figure 11. Minimum Voltage for HV Startup Current Source versus Temperature 0.65 VILIM (V) 1.8 14 10 -50 ICC3 (mA) 2.0 20 ICC4 (mA) VHV(min) (V) 22 1.10 -25 0 25 50 75 100 125 150 1.08 -50 -25 0 25 50 75 100 125 150 TJ, TEMPERATURE (C) TJ, TEMPERATURE (C) Figure 15. Max Peak Current Limit versus Temperature Figure 16. Second Peak Current Limit for Fault Protection versus Temperature www.onsemi.com 11 NCP1360, NCP1365 CHARACTERIZATION CURVES 1.02 2.60 2.58 2.56 2.54 Vref_CV1 (V) Vref_CC (V) 1.01 1.00 2.52 2.50 2.48 2.46 0.99 2.44 2.42 0 25 50 75 100 125 150 2.40 -50 0 25 50 75 100 125 TJ, TEMPERATURE (C) TJ, TEMPERATURE (C) Figure 18. Internal Voltage Reference for Constant Voltage Regulation versus Temperature 3.35 1.58 3.30 1.56 3.25 1.54 3.20 1.52 VUVP (V) 1.60 3.15 3.10 1.48 1.46 3.00 1.44 2.95 1.42 -25 0 25 50 75 100 125 150 150 1.50 3.05 1.40 -50 -25 0 25 50 75 100 125 150 TJ, TEMPERATURE (C) TJ, TEMPERATURE (C) Figure 19. Output Over Voltage Level versus Temperature (Fault Mode Options A, B & C) Figure 20. Output Under Voltage Level versus Temperature (Fault Mode Options A & B) 360 180 340 160 320 140 300 120 280 100 260 80 240 -50 -25 Figure 17. Internal Voltage Reference for Constant Current Regulation versus Temperature 3.40 2.90 -50 tLEB1 (ns) -25 tLEB2 (ns) VOVP (V) 0.98 -50 -25 0 25 50 75 100 125 150 60 -50 -25 0 25 50 75 100 125 150 TJ, TEMPERATURE (C) TJ, TEMPERATURE (C) Figure 21. Cycle-by-Cycle Leading Edge Blanking Duration versus Temperature Figure 22. Leading Edge Blanking Duration for VCS(stop) Level versus Temperature www.onsemi.com 12 NCP1360, NCP1365 CHARACTERIZATION CURVES 100 52 50 48 60 toutSS (ms) tILIM (ns) 80 40 46 44 42 40 20 38 -25 0 25 50 75 100 125 150 36 -50 0 25 50 75 100 125 150 TJ, TEMPERATURE (C) TJ, TEMPERATURE (C) Figure 24. Timeout After Last Demagnetization Transition in Soft-Start versus Temperature 6.5 95 6.3 90 6.1 85 5.9 80 5.7 75 5.5 5.3 70 65 5.1 60 4.9 55 4.7 50 4.5 -50 -25 Figure 23. Cycle-by-Cycle Current Sense Propagation Delay versus Temperature TOCP (ms) tout (ms) 0 -50 -25 0 25 50 75 100 125 150 45 -50 -25 0 25 50 75 100 125 TJ, TEMPERATURE (C) TJ, TEMPERATURE (C) Figure 25. Timeout After Last Demagnetization Transition versus Temperature Figure 26. Timer Delay Before Latching in Overload Condition versus Temperature 65 150 45 60 40 VZCD(HYS) (mV) VZCD(TH) (mV) 55 50 45 40 35 30 25 35 20 30 25 -50 -25 0 25 50 75 100 125 150 15 -50 -25 0 25 50 75 100 125 TJ, TEMPERATURE (C) TJ, TEMPERATURE (C) Figure 27. Zero Voltage Detection Threshold Voltage versus Temperature Figure 28. Zero Voltage Detection Hysteresis versus Temperature www.onsemi.com 13 150 NCP1360, NCP1365 CHARACTERIZATION CURVES 1.8 8.0 7.8 7.6 7.4 1.6 VDRV(low) (V) Tblank_ZCD (ms) 1.7 1.5 1.4 7.2 7.0 6.8 6.6 6.4 1.3 6.2 1.2 -50 -25 0 25 50 75 100 125 150 6.0 -50 -25 0 25 50 75 100 125 TJ, TEMPERATURE (C) TJ, TEMPERATURE (C) Figure 29. Blanking Delay for ZCD Detection versus Temperature Figure 30. VDRV(low) versus Temperature 13.0 150 80 70 12.5 50 tr (ns) VDRV(high) (V) 60 12.0 11.5 40 30 11.0 20 10.5 10.0 -50 10 -25 0 25 50 75 100 125 150 0 25 50 75 100 125 TJ, TEMPERATURE (C) Figure 31. VDRV(high) versus Temperature Figure 32. Gate Drive Rise Time versus Temperature 150 250 240 50 230 220 GEA (mS) 40 tf (ns) -25 TJ, TEMPERATURE (C) 60 30 20 210 200 190 180 170 10 0 -50 0 -50 160 -25 0 25 50 75 100 125 150 150 -50 -25 0 25 50 75 100 125 TJ, TEMPERATURE (C) TJ, TEMPERATURE (C) Figure 33. Gate Drive Fall Time versus Temperature Figure 34. Error Amplifier Gain versus Temperature www.onsemi.com 14 150 NCP1360, NCP1365 50 -30 48 -32 46 -34 44 -36 42 -38 IEA (mA) IEA (mA) CHARACTERIZATION CURVES 40 38 -40 -42 36 -44 34 -46 32 -48 30 -50 -25 0 25 50 75 100 125 150 -50 -50 -25 0 25 50 75 100 125 150 TJ, TEMPERATURE (C) TJ, TEMPERATURE (C) Figure 35. Error Amplifier Max. Source Capability versus Temperature Figure 36. Error Amplifier Max. Sink Capability versus Temperature 200 70 65 60 VZCD(short) (mV) VCS(VCO) (mV) 180 160 140 55 50 45 40 120 35 100 -50 0 25 50 75 100 125 150 30 -50 -25 0 25 50 75 100 125 TJ, TEMPERATURE (C) TJ, TEMPERATURE (C) Figure 37. Minimum or Frozen Peak Current on CS Pin versus Temperature (Frozen Peak Current optionY) Figure 38. Threshold Level for Detecting Output or Aux. Winding Short versus Temperature 75 39 70 38 65 37 60 36 55 ICS (mA) TEN_UVP (ms) 40 -25 35 34 50 45 33 40 32 35 31 30 30 -50 -25 0 25 50 75 100 125 150 25 -50 -25 0 25 50 75 100 125 TJ, TEMPERATURE (C) TJ, TEMPERATURE (C) Figure 39. Startup Blanking Time for UVP Detection versus Temperature Figure 40. Pull-up Current Source for Detecting Open or Short on CS Pin versus Temperature www.onsemi.com 15 150 150 NCP1360, NCP1365 CHARACTERIZATION CURVES 75 1.20 70 1.10 65 VCS(open) (V) VCS_min (mV) 60 55 50 45 40 35 0.90 0.80 0.70 30 25 -50 1.00 -25 0 25 50 75 100 125 150 0.60 -50 -25 0 25 50 75 100 125 TJ, TEMPERATURE (C) TJ, TEMPERATURE (C) Figure 41. CS Pin Short Detection Threshold versus Temperature Figure 42. CS Pin Open Detection Threshold versus Temperature www.onsemi.com 16 150 NCP1360, NCP1365 APPLICATION INFORMATION The NCP1365/60 is a flyback power supply controller providing a means to implement primary side constant-voltage and constant-current regulation. This technique does not need a secondary side feedback circuitry, associated bias current and an opto-coupler. NCP1365/60 implements a current-mode architecture operating in quasi-resonant mode. The controller prevents valley-jumping instability and steadily locks out in a selected valley as the power demand goes down. As long as the controller is able to detect a valley, the new cycle or the following drive remains in a valley. Due to a dedicated valley detection circuitry operating at any line and load conditions, the power supply efficiency will always be optimized. In order to prevent any high switching frequency two frequency clamp options are available. * Quasi-Resonance Current-mode operation: implementing quasi-resonance operation in peak current-mode control optimizes the efficiency by switching in the valley of the MOSFET drain-source voltage. Thanks to a proprietary circuitry, the controller locks-out in a selected valley and remains locked until the input voltage significantly changes. Only the four first valleys could be locked out. When the load current diminishes, valley switching mode of operation is kept but without valley lock-out. Valley-switching operation across the entire input/output conditions brings efficiency improvement and lets the designer build higher-density converters. * Frequency Clamp: As the frequency is not fixed and dependent on the line, load and transformer specifications, it is important to prevent switching frequency runaway for applications requiring maximum switching frequencies up to 90 kHz or 130 kHz. Two frequency clamp options at 80 kHz or 110 kHz are available for this purpose. In case frequency clamp is not needed, a specific version of the 1365/60 exists in which the clamp is deactivated. * Primary Side Constant Current Regulation: Battery charging applications request constant current regulation. NCP1360/65 controls and regulates the output current at a constant level regardless of the input and output voltage conditions. This function offers tight over power protection by estimating and limiting the maximum output current from the primary side, without any particular sensor. * Primary Side Constant Voltage Regulation: By monitoring the auxiliary winding voltage on the primary side, it is possible to determine the end of the transformer demagnetization in order to indirectly measure the output voltage. The end of the auxiliary winding demagnetization corresponds to that of the secondary winding affected by the transformer turns ratio. This auxiliary voltage value captured at this moment will be used to build the primary-side peak current setpoint in order to control the output voltage. Vout Vnom CV mode CC mode 0 Inom Iout Figure 43. Constant-Voltage & Constant-Current Mode * Soft-Start: 4 ms internal fixed soft start guarantees a * * * peak current starting from zero to its nominal value with smooth transition in order to prevent any overstress on the power components at each startup. Cycle-by-Cycle peak current limit: If the max peak current reaches the VILIM level, the over current protection timer is enabled and starts counting. If the overload lasts TOCP delay, then the fault is latched and the controller stops immediately driving the power MOSFET. The controller enters in a double hiccup mode before autorecovering with a new startup cycle. VCC Over Voltage Protection: If the VCC voltage reaches the VCC(OVP) threshold the controller enters in latch mode. Thus it stops driving pulse on DRV pin: A & C version - (Latched VCC(OVP)): VCC capacitor is internally discharged to the VCC(Clamp) level with a very low power consumption: the controller is completely disabled. Resuming operation is possible by unplugging the line in order to releasing the internal VCC thyristor with a VCC current lower than the ICC(Clamp). B version - (Autorecovery): it enters in double hiccup mode before resuming operation. Winding Short-Circuit Protection: An additional comparator senses the CS signal and stops the controller if VCS reaches VILIM +50% (after a reduced LEB: tLEB2 ). Short circuit protection is enabled only if 4 consecutive pulses reach SCP level. This small counter prevents any false triggering of short circuit protection during surge test for instance. This fault is latched and operations will be resumed like in a case of VCC Over Voltage Protection. www.onsemi.com 17 NCP1360, NCP1365 * Vout Over Voltage Protection: if the internally-built * * * power mosfet until the junction temperature decreases by TSHTDN(HYS) , then the operation is resumed after a double hiccup mode. output voltage becomes higher than VOVP level (Vref_CV1 + 26%) a fault is detected. A & C version: This fault is latched and operations are resumed like in the VCC Over Voltage Protection case. B version: the part enters in double hiccup mode before resuming operations. Vout Under Voltage Protection: After each circuit power on sequence, Vout UVP detection is enabled only after the startup timer TEN_UVP. This timer ensures that the power supply is able to fuel the output capacitor before checking the output voltage in on target. After this startup blanking time, UVP detection is enabled and monitors the Output voltage level. When the power supply is running in constant-current mode and when the output voltage falls below VUVP level, the controller stops sending drive pulses and enters a double hiccup mode before resuming operations (A & B version), or latches off (C version). Vs/ZCD Pin Short Protection: at the beginning of each off-time period, the Vs /ZCD pin is tested to check whether it is shorted or left open. In case a fault is detected, the controller enters in a double hiccup mode before resuming operations. Temperature Shutdown: if the junction temperature reaches the TSHTDN level, the controller stop driving the Startup Operation The high-voltage startup current source is connected to the bulk capacitor via the HV pin, it charges the VCC capacitor. During startup phase, it delivers 100 mA to fuel the VCC capacitor. When VCC pin reaches VCC(on) level, the NCP1360/65 is enabled. Before sending the first drive pulse to the power MOSFET, the CS pin has been tested for an open or shorted situation. If CS pin is properly wired, then the controller sends the first drive pulse to the power MOSFET. After sending these first pulses, the controller checks the correct Vs/ZCD pin wiring. Considering the Vs/ZCD pin properly wired, the controller engages a softstart sequence. The softstart sequence controls the max peak current from the minimal frozen primary peak current (VCS(VCO) = 120 mV: 15% of VILIM ) to the nominal pulse width by smoothly increasing the level. Figure 44 illustrates a standard connection of the HV pin to the bulk capacitor. If the controller is in a latched fault mode (ex VCC_OVP has been detected), the power supply will resume the operation after unplugging the converter from the ac line outlet. Due the extremely low controller consumption in latched mode, the release of the latch could be very long. The unplug duration for releasing the latch will be dependent on the bulk capacitor size. Vbulk RHV L 1 Vs/ZCD N 2 COMP 2 4 HV 8 CS Vcc 6 DRV GND 5 CVcc Vaux Figure 44. HV Startup Connection to the Bulk Capacitor Protecting the Controller Against Negative Spikes The following calculation illustrates the time needed for releasing the latch state: t unplug u C bulkV in_ac 2 I HV As with any controller built upon a CMOS technology, it is the designer's duty to avoid the presence of negative spikes on sensitive pins. Negative injection has the bad habit to forward-bias the controller substrate and can induce erratic behaviors. Sometimes, the injection can be so strong that internal parasitic SCRs are triggered and latch the controller. The HV pin can be the problem in certain circumstances. During the turn-off sequence, e.g. when the user unplugs the power supply, the controller is still fed by its VCC capacitor and keeps activating the MOSFET ON and (eq. 1) For the following typical application with a 10 mF bulk capacitor and a wide mains input range, in the worst case the power supply needs to be unplug at least for 38 seconds @ 265 V ac and 12 seconds @ 85 Vac. It is important to note that the previous recommendation is no longer valid with the B version, as all the faults are set to autorecovery mode only. www.onsemi.com 18 NCP1360, NCP1365 OFF with a peak current limited by Rsense . Unfortunately, if the quality factor Q of the resonating network formed by Lp and Cbulk is high (e.g. the MOSFET RDS(on) + Rsense are small), conditions are met to make the circuit resonate and a negative ringing can potentially appear at the HV pin. Simple and inexpensive cures exist to prevent the internal parasitic SCR activation. One of them consist of inserting a resistor in series with the HV pin to keep the negative current at the lowest when the bulk swings negative (Figure 44). Another option (Figure 45) consists of connecting the HV pin directly to the line or neutral input via a high-voltage diode. This configuration offers the benefits to release a latch state immediately after unplugging the power supply from the mains outlet. There is no delay for resetting the controller as there no capacitor keeps the HV bias. RHV resistor value must be sized as follow in order to guarantee a correct behavior of the HV startup in the worst case conditions: R HV t V in,ac_min 2 * V HV(min)_max I HV_max (eq. 2) Where: * Vin,ac_min is minimal input voltage, for example 85 V ac for universal input mains. * VHV(min)_max is the worst case of the minimal input voltage needed for the HV startup current source (25 V-max). * IHV_max is the maximum current delivered by the HV startup current source (150 mA-max) With this typical example R HV t 85 2 * 25 150 m + 633 kW, then any value below this one will be ok. Vbulk L 1 Vs/ZCD N 2 COMP 2 4 HV 8 CS VCC 6 DRV GND 5 CVcc Vaux Figure 45. Recommended HV Startup Connection for Fast Release after a Latched Fault Primary Side Regulation: Constant Current Operation Figure 46 portrays idealized primary and secondary transformer currents of a flyback converter operating in Discontinuous Conduction Mode (DCM). Ip(t) I p , pk Is(t), IOUT I s , pk = I p , pk time N ps IOUT = <Is(t)> ton tdemag tsw Figure 46. Primary and Secondary Transformer Current Waveforms www.onsemi.com 19 time NCP1360, NCP1365 When the primary power MOSFET is turned on, the primary current is illustrated by the green curve of Figure 46. When the power MOSFET is turned off the primary side current drops to zero and the current into the secondary winding immediately rises to its peak value equal to the primary peak current divided by the primary to secondary turns ratio. This is an ideal situation in which the leakage inductance action is neglected. The output current delivered to the load is equal to the average value of the secondary winding current, thus we can write: I out +t i sec(t) u+ I p,pk t demag V FB_CC + V ref_CC I out + Ns (eq. 5) R sense Internal constant current regulation block is building the constant current feedback information as follow: VAUX(t) Vout N pa N ps V ref_CC 8N psI out + V f ( I sec ) Vout N pa N ps time 0V * VIN N p (eq. 8) In primary side constant voltage regulation, the output voltage is sensed via the auxiliary winding. During the on-time period, the energy is stored in the transformer gap. During the off-time this energy stored in the transformer is delivered to the secondary and auxiliary windings. As illustrated by Figure 47, when the transformer energy is delivered to the secondary, the auxiliary voltage sums the output voltage scaled by the auxiliary and secondary turns ratios and the secondary forward diode voltage. This secondary forward diode voltage could be split in two elements: the first part is the forward voltage of the diode (Vf ), and the second is related to the dynamic resistance of the diode multiplied by secondary current (Rd w Is (t)). Where this second term will be dependant of the load and line conditions. sense resistor on CS pin: V CS (eq. 7) Primary Side Regulation: Constant Voltage Operation * Ip,pk is the magnetizing peak current sensed across the I p,pk + 8N psR sense R sense + (eq. 4) Np V ref_CC The output current value is set by choosing the sense resistor value: Where: * tsw is the switching period * tdemag is the demagnetizing time of the transformer * Nps is the secondary to primary turns ratio, where Np and Ns are respectively the transformer primary and secondary turns: N ps + (eq. 6) As the controller monitors the primary peak current via the sense resistor and due to the internal current setpoint divider (Kcomp ) between the CS pin and the internal feedback information, the output current could be written as follow: (eq. 3) 2N ps t sw t sw t demag a N ps I p , pk Ip(t) Is(t), IOUT I s , pk = I p , pk N ps IOUT = <Is(t)> ton tdemag tsw Figure 47. Typical Idealized Waveforms of a Flyback Transformer in DCM www.onsemi.com 20 time time NCP1360, NCP1365 To reach an accurate primary-side constant-voltage regulation, the controller detects the end of the demagnetization time and precisely samples output voltage level seen on the auxiliary winding. As this moment coincides with the secondary-side current equal to zero, the diode forward voltage drop becomes independent from the loading conditions. Thus when the secondary current Is (t) reaches zero ampere, the auxiliary is sensed: V aux + V out N pa down via the resistor divider to Vref_CV1 level before building the constant voltage feedback error. V ref_CV1 + V ref_CV1 + Na (eq. 10) Np (eq. 11) V aux R s2 N pa R s1 ) R s2 N ps V out (eq. 12) Once the sampled Vout is applied to the negative input terminal of the operational transconductance amplifier (OTA) and compared to the internal voltage reference an adequate voltage feedback is built. The OTA output being pinned out, it is possible to compensate the converter and adjust step load response to what the project requires. Where: Npa is the auxiliary to primary turns ratio, where Np & Na are respectively the primary and auxiliary turns: N pa + R s1 ) R s2 By inserting Equation 9 into Equation 11 we obtain the following equation: (eq. 9) N ps R s2 Figure 48 illustrates how the constant voltage feedback has been built. The auxiliary winding voltage must be scaled Auxiliary Vs / ZCD Rs1 Zero Crossing & Signal Sampling Rs2 Comp Sampled V out OTA tblank_ZCD R1 tShort_ZCD Vref_CV1 FB_CV C2 C1 Figure 48. Constant Voltage Feedback Arrangement 1. An internal switch grounds the Vs /ZCD pin during ton +tshort_ZCD in order to protect the pin from negative voltage. 2. In order to prevent any misdetection from the zero crossing block an internal switch disconnects Vs /ZCD pin until tblank_ZCD time (1.5 ms typ.) ends. When the power MOSFET is released at the end of the on time, because of the transformer leakage inductance and the drain lumped capacitance some voltage ringing appears on the drain node. These voltage ringings are also visible on the auxiliary winding and could cheat the controller detection circuits. To avoid false detection operations, two protecting circuits have been implemented on the Vs /ZCD pin (see Figure 49): www.onsemi.com 21 NCP1360, NCP1365 Figure 49. Vs /ZCD Pin Waveforms Constant-Current and Constant-Voltage Overall Regulation: is detected by monitoring the transformer auxiliary winding voltage. Turning on the power switch once the transformer is demagnetized (or reset) reduces turn-on switching losses. Once the transformer is demagnetized, the drain voltage starts ringing at a frequency determined by the transformer magnetizing inductance and the drain lumped capacitance, eventually settling at the input voltage value. A QR controller takes advantage of the drain voltage ringing and turns on the power switch at the drain voltage minimum or "valley" to reduce turn-on switching losses and electromagnetic interference (EMI). As sketched by Figure 50, a valley is detected once the ZCD pin voltage falls below the QR flyback demagnetization threshold, VZCD(TH) , typically 45 mV. The controller will switch once the valley is detected or increment the valley counter depending on FB voltage. As already presented in the two previous paragraphs, the controller integrates two different feedback loops: the first one deals with the constant-current regulation scheme while the second one builds the constant-voltage regulation. One of the two feedback paths sets the primary peak current into the transformer. During startup phase, however, the peak current is controlled by the soft-start. Zero Current Detection The NCP1365 integrates a quasi-resonant (QR) flyback controller. The power switch turn-off of a QR converter is determined by the peak current whose value depends on the feedback loop. The switch restart event is determined by the transformer demagnetization end. The demagnetization end ZCD QR multi-mode Valley lockout & Valley Switching & VCO management Rs1 Rs2 VZCD(TH) Blanking Tblank_ZCD Timeout (toutSS or tout) Figure 50. Valley Lockout Detection Circuitry internal Schematic www.onsemi.com 22 S Q R DRV (Internal) NCP1360, NCP1365 * Valley #1: the timeout delay must run twice so that the Timeout The ZCD block actually detects falling edges of the auxiliary winding voltage applied to the ZCD pin. At start-up or during other transient phases, the ZCD comparator may be unable to detect such an event. Also, in the case of extremely damped oscillations, the system may not succeed in detecting all the valleys required by valley lockout operation (VLO, see next section). In this condition, the NCP1365 ensures continued operation by incorporating a maximum timeout period that resets itself when a demagnetization phase is properly detected. In case the ringing signal is too weak or heavily damped, the timeout signal supersedes the ZCD signal for the valley counter. Figure 50 shows the timeout period generator circuit schematic. The timeout duration, tout , is set to 5.5 ms (typ.). During startup, the output voltage is still low, leading to long demagnetization phase, difficult to detect since the auxiliary winding voltage is small as well. In this condition, the tout timeout is generally shorter than the inductor demagnetization period and if used to restart a switching cycle, it can cause continuous current mode (CCM) operation for a few cycles until the voltage on the ZCD pin is high enough for proper valleys detection. A longer timeout period, toutSS , (typically 44 ms) is therefore set during soft-start to prevent CCM operation. In VLO operation, the timeout occurrences are counted instead of valleys when the drain-source voltage oscillations are too damped to be detected. For instance, assume the circuit must turn on at the third valley and the ZCD ringing only enables the detection of: * Valleys #1 to #2: the circuit generates a DRV pulse tout (steady-state timeout delay) after valley #2 detection. circuit generates a DRV pulse 10 ms (2*tout typ.) after valley #1 detection. Valley LockOut (VLO) and Frequency Foldback (FF) The operating frequency of a traditional Quasi-Resonant (QR) flyback controller is inversely proportional to the system load. In other words, a load reduction increases the operating frequency. A maximum frequency clamp can be useful to limit the operating frequency range. However, when associated with a valley-switching circuit, instabilities can arise because of the discrete frequency jumps. The controller tends to hesitate between two valleys and audible noise can be generated To avoid this issue, the NCP1360/65 incorporates a proprietary valley lockout circuitry which prevents so-called valley jumping. Once a valley is selected, the controller stays locked in this valley until the input level or output power changes significantly. This technique extends QR operation over a wider output power range while maintaining good efficiency and naturally limiting the maximum operating frequency. The operating valley (from 1st to 4th valley) is determined by the internal feedback level (FB node on Figure 4). As FB voltage level decreases or increases, the valley comparators toggle one after another to select the proper valley. The decimal counter increases each time a valley is detected. The activation of an "n" valley comparator blanks the "n-1" or "n+1" valley comparator output depending if VFB decreases or increases, respectively. Figure 51 shows a typical frequency characteristic obtained at low line in a 10 W charger. Figure 51. Typical Switching Frequency versus Output Power Relationship in a 10 W Adapter www.onsemi.com 23 NCP1360, NCP1365 When an "n" valley is asserted by the valley selection circuitry, the controller locks in this valley until the FB voltage decreases to the lower threshold ("n+1" valley activates) or increases to the "n valley threshold" + 600 mV ("n-1" valley activates). The regulation loop adjusts the peak current to deliver the necessary output power at the valley operating point. Each valley selection comparator features a 600 mV hysteresis that helps stabilize operation despite the FB voltage swing produced by the regulation loop. Table 1. VALLEY FB THRESHOLD ON CONSTANT VOLTAGE REGULATION FB Falling FB Rising 1st to 2nd valley 2.5 V FF mode to 4th 2.5 V 2nd to 3rd valley 2.3 V 4th to 3rd valley 2.7 V 2.1 V 3rd 1.9 V 2nd 3rd 4th to 4th valley to FF mode Frequency Foldback (FF) to 2nd valley 2.9 V to 1st valley 3.1 V efficiency benefit inherent to the QR operation, the controller turns on again with the next valley after the dead time has ended. As a result, the controller will still run in valley switching mode even when the FF is enabled. This dead-time increases when the FB voltage decays. There is no discontinuity when the system transitions from VLO to FF and the frequency smoothly reduces as FB goes below 1.9 V. The dead-time is selected to generate a 2 ms dead-time when VComp is decreasing and crossing VHVCOD (1.9 V typ.). At this moment, it can linearly go down to the minimal frequency limit (fVCO(min) = 200, 600 or 1200 Hz version are available). The generated dead-time is 1ms when VComp is increasing and crossing VHVCOI (2.5 V typ.). As the output current decreases (FB voltage decreases), the valleys are incremented from 1 to 4. In case the fourth valley is reached, the FB voltage further decreases below 1.9 V and the controller enters the frequency foldback mode (FF). The current setpoint being internally forced to remain above 0.12 V (setpoint corresponding to VComp = 1.9 V), the controller regulates the power delivery by modulating the switching frequency. When an output current increase causes FB to exceed the 2.5 V FF upper threshold (600-mV hysteresis), the circuit recovers VLO operation. In frequency foldback mode, the system reduces the switching frequency by adding some dead-time after the 4th valley is detected. However, in order to keep the high Figure 52. Valley Lockout Threshold Current Setpoint starting from the frozen peak current (VCS(VCO) = 120 mV typ.) to VILIM (0.8 V typ.) within 4 ms (tss ). However, this internal FB value is also limited by the following functions: A minimum setpoint is forced that equals VCS(VCO) (0.12 V, typ.) In addition, a second OCP comparator ensures that in any case the current setpoint is limited to VILIM . As explained in this operating description, the current setpoint is affected by several functions. Figure 53 summarizes these interactions. As shown by this figure, the current setpoint is the output of the control law divided by Kcomp (4 typ.). This current setpoint is clamped by the soft-start slope as long as the peak current requested by the FB_CV or FB_CC level are higher. The softstart clamp is www.onsemi.com 24 NCP1360, NCP1365 This ensures the MOSFET current setpoint remains limited to VILIM in a fault condition. Peak current Freeze SoftStart Control Law For Primary Peak Current Control FB_CV FB_CC PWM Comp 1/Kcomp FB Reset CS OCP Comp LEB1 RCS Rsense PWM Latch Reset Max_Ipk reset CCS Count VILIM OCP OCP Timer Reset Timer POReset DbleHiccup Short Circuit Comp LEB2 Reset Counter 4 clk Counter SCP VCS(Stop) Figure 53. Current Setpoint A 2nd Over-Current Comparator for Abnormal Overcurrent Fault Detection sequence or if the power supply is unplugged with a new startup sequence after the initial power on reset. A severe fault like a winding short-circuit can cause the switch current to increase very rapidly during the on-time. The current sense signal significantly exceeds VILIM . But, because the current sense signal is blanked by the LEB circuit during the switch turn on, the power switch current can abnormally increase, possibly causing system damages. The NCP1360/65 protects against this dangerous mode by adding an additional comparator for abnormal overcurrent fault detection or short-circuit condition. The current sense signal is blanked with a shorter LEB duration, tLEB2 , typically 120 ns, before applying it to the short-circuit comparator. The voltage threshold of this extra comparator, VCS(stop) , is typically 1.2 V, set 50% higher than VILIM . This is to avoid interference with normal operation. Four consecutive abnormal overcurrent faults cause the controller to enter in auto-recovery mode. The count to 4 provides noise immunity during surge testing. The counter is reset each time a DRV pulse occurs without activating the fault overcurrent comparator or after double hiccup Standby Power Optimization Assuming the no-load standby power is a critical parameter, the NCP1360/65 is optimized to reach an ultra low standby power. When the controller enters standby mode, a part of the internal circuitry has been disabled in order to minimize its supply current. When the STBY mode is enabled, the consumption is only 200 mA (ICC4 ) with the 200 Hz minimal frequency option. Cable Drop Compensation NCP1360/65 integrates an internal cable drop compensation. This circuitry compensates the drop due to the cable connected between the PCB output of the charger and the final equipment. As the drop is linearly varying with the output current level, this level can be compensated by accounting for the load output current. Figure 54 illustrates the practical implementation of the cable compensation with the NCP1360/65 controller. Sampled Vout CC Control FB_CC Vref_CV2 CBC OTA Vref_CV1 Figure 54. Cable Compensation Implementation www.onsemi.com 25 Comp NCP1360, NCP1365 The end of output cable voltage level could be written as follows: V out_cable_end(t) + V out_connector(t) * R cableI out(t) (eq. 13) (eq. 14) V out_cable_end(t) + V out ) V CBC(t) Thermal Shutdown: An internal thermal shutdown circuit monitors the junction temperature of the IC. The controller is disabled if the junction temperature exceeds the thermal shutdown threshold (TSHDN ), typically 150C. A continuous VCC hiccup is initiated after a thermal shutdown fault is detected. The controller restarts at the next VCC(on) once the IC temperature drops below TSHDN reduced by the thermal shutdown hysteresis (TSHDN(HYS)), typically 40C. The thermal shutdown is also cleared if VCC drops below VCC(reset). A new power up sequences commences at the next VCC(on) once all the faults are removed. Vout corresponds to the nominal output level at no-load. It is independent of the output current level. Then the cable compensation level could be determined as follow: V CBC(t) + CBC I out(t) (eq. 15) I out_nom Where: CBC corresponds to the cable compensation option selected (No comp, 150, 300 or 450 mV) Iout (t) corresponds to the output current currently sunk by the load estimated on by the controller on the primary side. Iout_nom the nominal output current level of the power supply. Driver The NCP1365 maximum supply voltage, VCC(max), is 28 V. Typical high-voltage MOSFETs have a maximum gate voltage rating of 20 V. The DRV pin incorporates an active voltage clamp which limits the gate voltage on the external mosfet. The DRV voltage clamp, VDRV(high) is set to 13 V maximum. Fault mode and Protection Vs/ZCD pin: after sending the first drive pulse the controller checks the correct wiring of Vs/ZCD pin: after the ZCD blanking time, if there is an open or short conditions, the controller enters in double hiccup mode. CS pin: at each startup, a 55 mA (ICS ) current source pulls up the CS pin to disable the controller if the pin is left open or grounded. Then the controller enters in a double hiccup mode. TABLE OF AVAILABLE OPTIONS Function Options Fault Mode VCC_OVP Latched / Full Autorecovery / Vout_UVP latched Cable drop Compensation No/150/300/450 mV Minimum operating frequency in VCO 200 Hz / 600 Hz / 1.2 kHz / 23 kHz Frequency Clamp or Maximum operating frequency No Clamp / 80 kHz / 110 kHz ORDERING TABLE OPTION HV Startup 5 OPN # NCP136_ _ _ _ _ Yes NCP1365AABCY X NCP1365BABCY X NCP1365CABCY X NCP1365BAAAY X NCP1365ACBAX X 0 Fault Mode A B Frequency Clamp Min Operating Fsw (STBY) C A B C D No Vcc_OVP Full Vout_UVP 200Hz 600Hz 1.2kHz 23kHz Latched Autorecovery Latched X X X X E No min NCP1360BABCY X NCP1360CABCY X NCP1360BBCCY X X NCP1360BCCCY X X NCP1360BACCY X X X X A B C D X Y X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X www.onsemi.com 26 Z No 80kHz 110kHz No 150mV 300mV 450mV 120mV 160mV 200mV X X X C X X X B Frozen Peak Current VCS(VCO) X X NCP1360AABCY A Cable Compensation NCP1360, NCP1365 ORDERING INFORMATION Device Marking NCP1365AABCYDR2G 1365A1 NCP1365ACBAXDR2G 1365A3 NCP1365BABCYDR2G 1365B1 NCP1365BAAAYDR2G 1365B2 NCP1360AABCYSNT1G ADA NCP1360BABCYSNT1G ADC NCP1360BBCCYSNT1G AA2 NCP1360BCCCYSNT1G AA3 NCP1360BACCYSNT1G AA4 Package Shipping SOIC-7 (Pb-Free) 2500 / Tape & Reel TSOP-6 (Pb-Free) 3000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 27 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSOP-6 CASE 318G-02 ISSUE V 1 SCALE 2:1 D H EE EE 6 E1 1 NOTE 5 5 2 L2 4 GAUGE PLANE E 3 L b SEATING PLANE C DETAIL Z e DIM A A1 b c D E E1 e L L2 M c A 0.05 M DATE 12 JUN 2012 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. A1 DETAIL Z MIN 0.90 0.01 0.25 0.10 2.90 2.50 1.30 0.85 0.20 0 MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 2.75 3.00 1.50 1.70 0.95 1.05 0.40 0.60 0.25 BSC 10 - STYLE 1: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 2: PIN 1. EMITTER 2 2. BASE 1 3. COLLECTOR 1 4. EMITTER 1 5. BASE 2 6. COLLECTOR 2 STYLE 3: PIN 1. ENABLE 2. N/C 3. R BOOST 4. Vz 5. V in 6. V out STYLE 4: PIN 1. N/C 2. V in 3. NOT USED 4. GROUND 5. ENABLE 6. LOAD STYLE 5: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 6: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 7: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. N/C 5. COLLECTOR 6. EMITTER STYLE 8: PIN 1. Vbus 2. D(in) 3. D(in)+ 4. D(out)+ 5. D(out) 6. GND STYLE 9: PIN 1. LOW VOLTAGE GATE 2. DRAIN 3. SOURCE 4. DRAIN 5. DRAIN 6. HIGH VOLTAGE GATE STYLE 10: PIN 1. D(OUT)+ 2. GND 3. D(OUT)- 4. D(IN)- 5. VBUS 6. D(IN)+ STYLE 11: PIN 1. SOURCE 1 2. DRAIN 2 3. DRAIN 2 4. SOURCE 2 5. GATE 1 6. DRAIN 1/GATE 2 STYLE 12: PIN 1. I/O 2. GROUND 3. I/O 4. I/O 5. VCC 6. I/O STYLE 13: PIN 1. GATE 1 2. SOURCE 2 3. GATE 2 4. DRAIN 2 5. SOURCE 1 6. DRAIN 1 STYLE 14: PIN 1. ANODE 2. SOURCE 3. GATE 4. CATHODE/DRAIN 5. CATHODE/DRAIN 6. CATHODE/DRAIN STYLE 15: PIN 1. ANODE 2. SOURCE 3. GATE 4. DRAIN 5. N/C 6. CATHODE STYLE 16: PIN 1. ANODE/CATHODE 2. BASE 3. EMITTER 4. COLLECTOR 5. ANODE 6. CATHODE STYLE 17: PIN 1. EMITTER 2. BASE 3. ANODE/CATHODE 4. ANODE 5. CATHODE 6. COLLECTOR GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 6X 0.60 XXXAYWG G 1 6X 3.20 XXX A Y W G 0.95 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ASB14888C TSOP-6 1 IC 0.95 XXX MG G = Specific Device Code =Assembly Location = Year = Work Week = Pb-Free Package STANDARD XXX = Specific Device Code M = Date Code G = Pb-Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot " G", may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. (c) Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC-7 CASE 751U-01 ISSUE E DATE 20 OCT 2009 SCALE 1:1 -A- 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B ARE DATUMS AND T IS A DATUM SURFACE. 4. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 5. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5 -B- S 0.25 (0.010) B M M 1 4 G C R X 45 _ J -T- SEATING PLANE H 0.25 (0.010) K M D 7 PL M T B S A DIM A B C D G H J K M N S INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 S GENERIC MARKING DIAGRAM SOLDERING FOOTPRINT* 8 1.52 0.060 7.0 0.275 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 1 XXX A L Y W G 4.0 0.155 0.6 0.024 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot " G", may or may not be present. 1.270 0.050 SCALE 6:1 XXXXX ALYWX G mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: 98AON12199D DESCRIPTION: 7-LEAD SOIC Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. (c) Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC-7 CASE 751U-01 ISSUE E STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. 7. NOT USED 8. EMITTER DATE 20 OCT 2009 STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. NOT USED 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. NOT USED 8. SOURCE, #1 STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. 6. 7. NOT USED 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. 7. NOT USED 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. NOT USED 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR (DIE 1) 2. BASE (DIE 1) 3. BASE (DIE 2) 4. COLLECTOR (DIE 2) 5. COLLECTOR (DIE 2) 6. EMITTER (DIE 2) 7. NOT USED 8. COLLECTOR (DIE 1) STYLE 9: PIN 1. EMITTER (COMMON) 2. COLLECTOR (DIE 1) 3. COLLECTOR (DIE 2) 4. EMITTER (COMMON) 5. EMITTER (COMMON) 6. BASE (DIE 2) 7. NOT USED 8. EMITTER (COMMON) STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. NOT USED 8. GROUND STYLE 11: PIN 1. SOURCE (DIE 1) 2. GATE (DIE 1) 3. SOURCE (DIE 2) 4. GATE (DIE 2) 5. DRAIN (DIE 2) 6. DRAIN (DIE 2) 7. NOT USED 8. DRAIN (DIE 1) STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. NOT USED 8. COMMON CATHODE DOCUMENT NUMBER: 98AON12199D DESCRIPTION: 7-LEAD SOIC Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. (c) Semiconductor Components Industries, LLC, 2019 www.onsemi.com ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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