AD5668BRUZ-1REEL7 - Analog Devices, Inc.

Octal, 12-/14-/16-Bit SPI Voltage Output

denseDAC with 5 ppm/°C On-Chip Reference

Data Sheet AD5628/AD5648/AD5668

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Low power, small footprint, pin-compatible octal DACs

AD5668: 16 bits

AD5648: 14 bits

AD5628: 12 bits

14-lead/16-lead TSSOP, 16-lead LFCSP, and 16-lead WLCSP

On-chip 1.25 V/2.5 V, 5 ppm/°C reference

Power down to 400 nA @ 5 V, 200 nA @ 3 V

2.7 V to 5.5 V power supply

Guaranteed monotonic by design

Power-on reset to zero scale or midscale

3 power-down functions

Hardware LDAC and LDAC override function

CLR function to programmable code

Rail-to-rail operation

APPLICATIONS

Process control

Data acquisition systems

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Programmable attenuators

FUNCTIONAL BLOCK DIAGRAM

INTERFACE

LOGIC

INPUT

DIN

LDAC

GND

OUT

LDAC

REFIN

REFOUT

SYNC

SCLK

AD5628/AD5648/AD5668

CLR

RU-16 PACKAGE O NLY

1.25V/2.5V

REF

OUT

DAC

DAC A BUFFER

INPUT

DAC B BUFFER

INPUT

DAC C BUFFER

INPUT

DAC D BUFFER

INPUT

DAC E BUFFER

INPUT

DAC F BUFFER

INPUT

DAC G BUFFER

INPUT

DAC H BUFFER

POWER-DOWN

LOGIC

POWER-ON

RESET

05302-001

Figure 1.

GENERAL DESCRIPTION

The AD5628/AD5648/AD5668 devices are low power, octal,

12-/14-/16-bit, buffered voltage-output DACs. All devices

operate from a single 2.7 V to 5.5 V supply and are guaranteed

monotonic by design. The AD5668 and AD5628 are available in

both a 4 mm × 4 mm LFCSP and a 16-lead TSSOP, while the

AD5648 is available in both a 14-lead and 16-lead TSSOP.

The AD5628/AD5648/AD5668 have an on-chip reference with

an internal gain of 2. The AD5628-1/AD5648-1/AD5668-1 have

a 1.25 V 5 ppm/°C reference, giving a full-scale output range

of 2.5 V; the AD5628-2/AD5648-2/AD5668-2 and AD5668-3 have

a 2.5 V 5 ppm/°C reference, giving a full-scale output range of

5 V. The on-board reference is off at power-up, allowing the use

of an external reference. The internal reference is enabled via a

software write.

The part incorporates a power-on reset circuit that ensures that the

DAC output powers up to 0 V (AD5628-1/AD5648-1/AD5668-1,

AD5628-2/AD5648-2/AD5668-2) or midscale (AD5668-3) and

remains powered up at this level until a valid write takes place.

The part contains a power-down feature that reduces the current

consumption of the device to 400 nA at 5 V and provides software-

selectable output loads while in power-down mode for any or all

DAC channels. The outputs of all DACs can be updated simul-

taneously using the LDAC function, with the added functionality

of user-selectable DAC channels to simultaneously update. There

is also an asynchronous CLR that updates all DACs to a user-

programmable code—zero scale, midscale, or full scale.

The AD5628/AD5648/AD5668 utilize a versatile 3-wire serial

interface that operates at clock rates of up to 50 MHz and is

compatible with standard SPI®, QSPI™, MICROWIRE™, and

DSP interface standards. The on-chip precision output amplifier

enables rail-to-rail output swing.

PRODUCT HIGHLIGHTS

1. Octal, 12-/14-/16-bit DAC.

2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.

3. Available in 14-lead/16-lead TSSOP, 16-lead LFCSP, and

16-lead WLCSP.

4. Power-on reset to 0 V or midscale.

5. Power-down capability. When powered down, the DAC

typically consumes 200 nA at 3 V and 400 nA at 5 V.

AD5628/AD5648/AD5668 Data Sheet

Rev. F | Page 2 of 32

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Characteristics........................................................................ 6

Timing Characteristics ................................................................ 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configurations and Function Descriptions ........................... 9

Typical Performance Characteristics ........................................... 11

Terminology .................................................................................... 19

Theory of Operation ...................................................................... 21

D/A Section................................................................................. 21

Resistor String............................................................................. 21

Internal Reference ...................................................................... 21

Output Amplifier........................................................................ 22

Serial Interface............................................................................ 22

Input Shift Register .................................................................... 23

SYNC Interrupt .......................................................................... 23

Internal Reference Register....................................................... 24

Power-On Reset.......................................................................... 24

Power-Down Modes .................................................................. 24

Clear Code Register ................................................................... 24

LDAC Function .......................................................................... 26

Power Supply Bypassing and Grounding................................ 26

Outline Dimensions ....................................................................... 27

Ordering Guide .......................................................................... 29

REVISION HISTORY

8/11—Rev. E to Rev. F

Added 16-Lead WLCSP.....................................................Universal

Added Figure 6 and Table 7; Renumbered Sequentially ........... 10

Changes to Figure 32 and Figure 33............................................. 15

Updated Outline Dimensions....................................................... 26

Changes to Ordering Guide .......................................................... 28

1/11—Rev. D to Rev. E

Changes to AD5628 Relative Accuracy, Zero-Code Error, Offset

Error, and Reference TC Parameters, Table 1............................... 3

Changes to AD5628 Relative Accuracy, Zero-Code Error, Offset

Error, and Reference TC Parameters, Table 2............................... 5

Changes to Output Voltage Settling Time, Table 3 ...................... 6

Added Figure 53; Renumbered Sequentially .............................. 17

Change to Output Amplifier Section........................................... 21

Changes to Ordering Guide .......................................................... 28

9/10—Rev. C to Rev. D

Change to Title.................................................................................. 1

Added 16-Lead LFCSP Throughout ................................Universal

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 5

Changes to Table 3............................................................................ 6

Changes to Table 4.............................................................................7

Deleted SnPb from Table 5...............................................................8

Added Figure 5; Renumbered Sequentially ...................................9

Changes to Table 6.............................................................................9

Replaced Typical Performance Characteristics Section ............ 10

Changes to Power-On Reset Section ........................................... 23

Updated Outline Dimensions....................................................... 26

Changes to Ordering Guide.......................................................... 28

1/10—Rev. B to Rev. C

Changes to Figure 3........................................................................ 10

Changes to Ordering Guide.......................................................... 28

2/09—Rev. A to Rev. B

Changes to Reference Current Parameter, Table 1........................3

Changes to IDD (Normal Mode) Parameter, Table 1......................4

Changes to Reference Current Parameter, Table 2........................5

Changes to IDD (Normal Mode) Parameter, Table 2......................6

11/05—Rev. 0 to Rev. A

Change to Specifications ..................................................................3

10/05—Revision 0: Initial Version

Data Sheet AD5628/AD5648/AD5668

Rev. F | Page 3 of 32

SPECIFICATIONS

VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.

Table 1.

A Grade1 B Grade1

Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE2

AD5628

Resolution 12 12 Bits

Relative Accuracy ±0.5 ±4 ±0.5 ±1 LSB See Figure 9

Differential Nonlinearity ±0.25 ±0.25 LSB

Guaranteed monotonic by design

(see Figure 12)

AD5648

Resolution 14 14 Bits

Relative Accuracy ±2 ±8 ±2 ±4 LSB See Figure 8

Differential Nonlinearity ±0.5 ±0.5 LSB

Guaranteed monotonic by design

(see Figure 11)

AD5668

Resolution 16 16 Bits

Relative Accuracy ±8 ±32 ±8 ±16 LSB See Figure 7

Differential Nonlinearity ±1 ±1 LSB

Guaranteed monotonic by design

(see Figure 10)

Zero-Code Error 6 19 6 19 mV All 0s loaded to DAC register (see Figure 26)

Zero-Code Error Drift ±2 ±2 µV/°C

Full-Scale Error −0.2 −1 −0.2 −1 % FSR

All 1s loaded to DAC register

(see Figure 27)

Gain Error ±1 ±1 % FSR

Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C

Offset Error ±6 ±19 ±6 ±19 mV

DC Power Supply Rejection Ratio –80 –80 dB VDD ± 10%

DC Crosstalk

(External Reference)

10 10 µV

Due to full-scale output change,

RL = 2 kΩ to GND or VDD

5 5 µV/mA Due to load current change

10 10 µV Due to powering down (per channel)

DC Crosstalk

(Internal Reference)

25 25 µV

Due to full-scale output change,

RL = 2 kΩ to GND or VDD

10 10 µV/mA Due to load current change

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 VDD 0 VDD V

Capacitive Load Stability 2 2 nF RL = ∞

10 10 nF RL = 2 kΩ

DC Output Impedance 0.5 0.5 Ω

Short-Circuit Current 30 30 mA VDD = 5 V

Power-Up Time 4 4 µs Coming out of power-down mode, VDD = 5 V

REFERENCE INPUTS

Reference Current 40 55 40 55 µA VREF = VDD = 5.5 V (per DAC channel)

Reference Input Range 0 VDD 0 VDD V

Reference Input Impedance 14.6 14.6 kΩ

REFERENCE OUTPUT

Output Voltage

AD56x8-2, AD56x8-3 2.495 2.505 2.495 2.505 V At ambient

Reference TC3 5 10 5 10 ppm/°C TSSOP

15 5 10 ppm/°C LFCSP

Reference Output Impedance 7.5 7.5 kΩ

AD5628/AD5648/AD5668 Data Sheet

Rev. F | Page 4 of 32

A Grade1 B Grade1

Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

LOGIC INPUTS3

Input Current ±3 ±3 µA All digital inputs

Input Low Voltage, VINL 0.8 0.8 V VDD = 5 V

Input High Voltage, VINH 2 2 V VDD = 5 V

Pin Capacitance 3 3 pF

POWER REQUIREMENTS

VDD 4.5 5.5 4.5 5.5 V All digital inputs at 0 or VDD,

DAC active, excludes load current

IDD (Normal Mode)4 V

IH = VDD and VIL = GND

VDD = 4.5 V to 5.5 V 1.0 1.5 1.0 1.5 mA Internal reference off

VDD = 4.5 V to 5.5 V 1.8 2.25 1.7 2.25 mA Internal reference on

IDD (All Power-Down Modes)5

VDD = 4.5 V to 5.5 V 0.4 1 0.4 1 µA VIH = VDD and VIL = GND

1 Temperature range is −40°C to +105°C, typical at 25°C.

2 Linearity calculated using a reduced code range of AD5628 (Code 32 to Code 4064), AD5648 (Code 128 to Code 16,256), and AD5668 (Code 512 to 65,024). Output

unloaded.

3 Guaranteed by design and characterization; not production tested.

4 Interface inactive. All DACs active. DAC outputs unloaded.

5 All eight DACs powered down.

Data Sheet AD5628/AD5648/AD5668

Rev. F | Page 5 of 32

VDD = 2.7 V to 3.6 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.

Table 2.

A Grade1 B Grade1

Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE2

AD5628

Resolution 12 12 Bits

Relative Accuracy ±0.5 ±4 ±0.5 ±1 LSB See Figure 9

Differential Nonlinearity ±0.25 ±0.25 LSB

Guaranteed monotonic by design

(see Figure 12)

AD5648

Resolution 14 14 Bits

Relative Accuracy ±2 ±8 ±2 ±4 LSB See Figure 8

Differential Nonlinearity ±0.5 ±0.5 LSB

Guaranteed monotonic by design

(see Figure 11)

AD5668

Resolution 16 16 Bits

Relative Accuracy ±8 ±32 ±8 ±16 LSB See Figure 7

Differential Nonlinearity ±1 ±1 LSB

Guaranteed monotonic by design

(see Figure 10)

Zero-Code Error 6 19 6 19 mV All 0s loaded to DAC register (see Figure 26)

Zero-Code Error Drift ±2 ±2 µV/°C

Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (see Figure 27)

Gain Error ±1 ±1 % FSR

Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C

Offset Error ±6 ±19 ±6 ±19 mV

DC Power Supply Rejection

Ratio3

–80 –80 dB VDD ± 10%

DC Crosstalk 3

(External Reference)

10 10 µV

Due to full-scale output change,

RL = 2 kΩ to GND or VDD

5 5 µV/mA Due to load current change

10 10 µV Due to powering down (per channel)

DC Crosstalk 3

(Internal Reference)

25 25 µV

Due to full-scale output change,

RL = 2 kΩ to GND or VDD

10 10 µV/mA Due to load current change

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 VDD 0 VDD V

Capacitive Load Stability 2 2 nF RL = ∞

10 10 nF RL = 2 kΩ

DC Output Impedance 0.5 0.5 Ω

Short-Circuit Current 30 30 mA VDD = 3 V

Power-Up Time 4 4 µs Coming out of power-down mode, VDD = 3 V

REFERENCE INPUTS

Reference Current 40 55 40 55 µA VREF = VDD = 5.5 V (per DAC channel)

Reference Input Range 0 VDD 0 VDD

Reference Input Impedance 14.6 14.6 kΩ

REFERENCE OUTPUT

Output Voltage

AD5628/AD5648/AD5668-1 1.247 1.253 1.247 1.253 V At ambient

Reference TC3 5 15 5 15 ppm/°C TSSOP

15 5 15 ppm/°C LFCSP

Reference Output

Impedance

7.5 7.5 kΩ

AD5628/AD5648/AD5668 Data Sheet

Rev. F | Page 6 of 32

A Grade1 B Grade1

Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

LOGIC INPUTS3

Input Current ±3 ±3 µA All digital inputs

Input Low Voltage, VINL 0.8 0.8 V VDD = 3 V

Input High Voltage, VINH 2 2 V VDD = 3 V

Pin Capacitance 3 3 pF

POWER REQUIREMENTS

VDD 2.7 3.6 2.7 3.6 V All digital inputs at 0 or VDD,

DAC active, excludes load current

IDD (Normal Mode)4 V

IH = VDD and VIL = GND

VDD = 2.7 V to 3.6 V 1.0 1.5 1.0 1.5 mA Internal reference off

VDD = 2.7 V to 3.6 V 1.8 2.25 1.7 2.25 mA Internal reference on

IDD (All Power-Down Modes)5

VDD = 2.7 V to 3.6 V 0.2 1 0.2 1 µA VIH = VDD and VIL = GND

1 Temperature range is −40°C to +105°C, typical at 25°C.

2 Linearity calculated using a reduced code range of AD5628 (Code 32 to Code 4064), AD5648 (Code 128 to Code 16256), and AD5668 (Code 512 to 65024). Output

unloaded.

3 Guaranteed by design and characterization; not production tested.

4 Interface inactive. All DACs active. DAC outputs unloaded.

5 All eight DACs powered down.

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter1, 2 Min Typ Max Unit Conditions/Comments3

Output Voltage Settling Time 2.5 7 µs ¼ to ¾ scale settling to ±2 LSB (16-bit resolution)

Slew Rate 1.2 V/µs

Digital-to-Analog Glitch Impulse 4 nV-s 1 LSB(16-bit resolution) change around major carry

(see Figure 42)

19 nV-s From code 0xEA00 to code 0xE9FF (16-bit resolution)

Digital Feedthrough 0.1 nV-s

Digital Crosstalk 0.2 nV-s

Analog Crosstalk 0.4 nV-s

DAC-to-DAC Crosstalk 0.8 nV-s

Multiplying Bandwidth 320 kHz VREF = 2 V ± 0.2 V p-p

Total Harmonic Distortion −80 dB VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz

Output Noise Spectral Density 120 nV/√Hz DAC code = 0x8400(16-bit resolution), 1 kHz

100 nV/√Hz DAC code = 0x8400(16-bit resolution), 10 kHz

Output Noise 12 V p-p 0.1 Hz to 10 Hz, DAC code = 0x0000

1 Guaranteed by design and characterization; not production tested.

2 See the Terminology section.

3 Temperature range is −40°C to +105°C, typical at 25°C.

Data Sheet AD5628/AD5648/AD5668

Rev. F | Page 7 of 32

TIMING CHARACTERISTICS

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.

VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.

Table 4.

Limit at TMIN, TMAX

Parameter VDD = 2.7 V to 5.5 V Unit Conditions/Comments

t1 1 20 ns min SCLK cycle time

t2 8 ns min SCLK high time

t3 8 ns min SCLK low time

t4 13 ns min SYNC to SCLK falling edge set-up time

t5 4 ns min Data set-up time

t6 4 ns min Data hold time

t7 0 ns min SCLK falling edge to SYNC rising edge

t8 15 ns min Minimum SYNC high time

t9 13 ns min SYNC rising edge to SCLK fall ignore

t10 0 ns min SCLK falling edge to SYNC fall ignore

t11 10 ns min LDAC pulse width low

t12 15 ns min SCLK falling edge to LDAC rising edge

t13 5 ns min CLR pulse width low

t14 0 ns min SCLK falling edge to LDAC falling edge

t15 300 ns typ

CLR pulse activation time

1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.

05302-002

SCLK

SYNC

DIN

DB31

LDAC

ASYNCHRO NOUS L DAC UPDATE MODE.

SYNCHRO NOUS L DAC UPDATE MODE.

CLR

OUT

DB0

Figure 2. Serial Write Operation

AD5628/AD5648/AD5668 Data Sheet

Rev. F | Page 8 of 32

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to GND −0.3 V to +7 V

Digital Input Voltage to GND −0.3 V to VDD + 0.3 V

VOUT to GND −0.3 V to VDD + 0.3 V

VREFIN/VREFOUT to GND −0.3 V to VDD + 0.3 V

Operating Temperature Range

Industrial −40°C to +105°C

Storage Temperature Range −65°C to +150°C

Junction Temperature (TJ MAX) 150°C

TSSOP Package

Power Dissipation (TJ MAX − TA)/θJA

θJA Thermal Impedance 150.4°C/W

Reflow Soldering Peak Temperature

Pb Free 260°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

Data Sheet AD5628/AD5648/AD5668

Rev. F | Page 9 of 32

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

05302-003

AD5628/

AD5648/

OUT

REFIN

REFOUT

OUT

DIN

GND

OUT

SCLK

TOP V IEW

(No t to S cal e)

SYNC

Figure 3. 14-Lead TSSOP (RU-14)

05302-004

SYNC

OUT

LDAC

DIN

GND

OUT

REFIN

REFOUT

CLR

OUT

SCLK

AD5628/

AD5648/

AD5668

TOP VIEW

(Not to Scale)

Figure 4. 16-Lead TSSOP (RU-16)

05302-005

GND

OUT

REFIN

REFOUT

OUT

CLR

OUT

16 SYNC

15 LDAC

14 SCLK

13 DIN

TO P VIEW

(Not to Scale)

NOTES

1. EXPOSED PAD MUST BE TIED TO GND.

AD5628/AD5668

Figure 5. 16-Lead LFCSP(CP-16-17)

Table 6. Pin Function Descriptions

Pin No.

14-Lead

TSSOP

16-Lead

TSSOP

16-Lead

LFCSP Mnemonic

Description

N/A

1 15

LDAC

Pulsing this pin low allows any or all DAC registers to be updated if the input registers

have new data. This allows all DAC outputs to simultaneously update. Alternatively, this

pin can be tied permanently low.

1 2 16

SYNC Active Low Control Input. This is the frame synchronization signal for the input data.

When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift

high before the 32nd falling edge, the rising edge of SYNC acts as an interrupt and the

write sequence is ignored by the device.

2 3 1 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply

should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

3 4 2 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

11 13 11 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

4 5 3 VOUTC Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

10 12 10 VOUTD Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

7 8 6 VREFIN/

VREFOUT

The AD5628/AD5648/AD5668 have a common pin for reference input and reference

output. When using the internal reference, this is the reference output pin. When using

an external reference, this is the reference input pin. The default for this pin is as a

reference input.

N/A 9 7 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all

LDAC pulses are ignored. When CLR is activated, the input register and the DAC register

are updated with the data contained in the CLR code register—zero, midscale, or full

scale. Default setting clears the output to 0 V.

5 6 4 VOUTE Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.

9 11 9 VOUTF Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.

6 7 5 VOUTG Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.

8 10 8 VOUTH Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.

12 14 12 GND Ground Reference Point for All Circuitry on the Part.

13 15 13 DIN Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register

on the falling edge of the serial clock input.

14 16 14 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the

serial clock input. Data can be transferred at rates of up to 50 MHz.

EPAD EPAD It is recommended that the exposed paddle be soldered to the ground plane.

AD5628/AD5648/AD5668 Data Sheet

Rev. F | Page 10 of 32

TOP VIE W

(BALL SIDE DOWN)

Not to Scale

05302-006

234

BALL

INDICATOR

GND

OUT

DIN

OUT

REF

SYNC

OUT

SCL

LDAC

OUT

CLR

Figure 6. 16-Lead WLCSP

Table 7. 16-Lead WLCSP Pin Function Descriptions

Pin. No. Mnemonic Description

LDAC

Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows

all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low.

A4 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it

powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges

of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of SYNC acts as an

interrupt and the write sequence is ignored by the device.

B3 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a

10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

B4 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

B1 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

C4 VOUTC Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

C2 VOUTD Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

D3 VREFIN/VREFOUT The AD5628/AD5648/AD5668 have a common pin for reference input and reference output. When using the

internal reference, this is the reference output pin. When using an external reference, this is the reference input

pin. The default for this pin is as a reference input.

D2 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored.

When CLR is activated, the input register and the DAC register are updated with the data contained in the CLR

code register—zero, midscale, or full scale. Default setting clears the output to 0 V.

C3 VOUTE Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.

C1 VOUTF Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.

D4 VOUTG Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.

D1 VOUTH Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.

A1 GND Ground Reference Point for All Circuitry on the Part.

A3 DIN Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling edge of the

serial clock input.

A4 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can

be transferred at rates of up to 50 MHz.

Data Sheet AD5628/AD5648/AD5668

Rev. F | Page 11 of 32

TYPICAL PERFORMANCE CHARACTERISTICS

–2

–4

–6

–8

–10

INL (LSB)

VDD = 5V

EXT REF = 5V

TA = 25°C

05302-106

CODES

0 10k 20k 30k 40k 50k 60k 65535

Figure 7. INL AD5668—External Reference

05302-107

–2

–1

–3

–4

INL (LSB)

= 5V

EXT REF = 5V

= 25°C

0 5k 10k 15k 16384

CODES

Figure 8. INL AD5648—External Reference

1.0

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

0 500 1000 1500 2000 2500 3000 3500 4095

INL (LSB)

CODES

= 5V

EXT REF = 5V

= 25° C

05302-108

Figure 9. INL AD5628—External Reference

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

DNL (LSB)

= 5V

EXT REF = 5V

= 25°C

05302-109

CODES

0 10k 20k 30k 40k 50k 60k 65535

Figure 10. DNL AD5668—External Reference

05302-110

CODES

INL (LSB)

= 5V

EXT REF = 5V

= 25°C

0 5k 10k 15k 16384

0.5

0.3

0.2

0.1

0.4

–0.2

–0.1

–0.3

–0.5

–0.4

Figure 11. DNL AD5648—External Reference

05302-111

0 500 1000 1500 2000 2500 3000 3500 4095

DNL (LSB)

CODES

–0.05

–0.10

–0.15

–0.20

0.05

0.10

0.15

0.20 V

= 5V

EXT REF = 5V

= 25°C

Figure 12. DNL AD5628—External Reference

AD5628/AD5648/AD5668 Data Sheet

Rev. F | Page 12 of 32

–10

–5

0 10k 20k 30k 40k 50k 60k 65535

INL (LSB)

CODES

= 5V

INT REF = 2.5V

= 25°C

05302-112

Figure 13. INL AD5668-2/AD5668-3

CODES

INL (LSB)

–4

–3

–2

–1

= 5V

EXT REF = 5V

= 25°C

0 5k 10k 15k 16383

05302-113

Figure 14. INL AD5648-2

1.0

0.5

–0.5

–1.0 0 500 1000 1500 2000 2500 3000 3500 4095

INL (LSB)

CODES

= 5V

INT REF = 2.5V

= 25°C

05302-114

Figure 15. INL AD5628-2

1.0

0.5

–1.0

–0.5

0 10k 20k 30k 40k 50k 60k 65535

DNL (LSB)

CODES

= 5V

INT REF = 2.5V

= 25°C

05302-115

Figure 16. DNL AD5668-2/AD5668-3

05302-116

CODES

DNL (LSB)

= 5V

EXT REF = 2.5V

= 25°C

0 5k 10k 15k 16383

0.5

0.3

0.2

0.1

0.4

–0.2

–0.1

–0.3

–0.5

–0.4

Figure 17. DNL AD5648-2

–0.05

–0.10

–0.15

–0.20

0.05

0.10

0.15

0.20

0 500 1000 1500 2000 2500 3000 3500 4095

DNL (LSB)

CODES

= 5V

INT REF = 2.5V

= 25°C

05302-117

Figure 18. DNL AD5628-2

Data Sheet AD5628/AD5648/AD5668

Rev. F | Page 13 of 32

–10

–6

–8

–4

–2

0 10k 20k 30k 40k 50k 60k 65535

INL (LSB)

CODES

= 3V

INT REF = 1.25V

= 25°C

05302-118

Figure 19. INL AD5668-1

CODES

INL (LSB)

–4

–3

–2

–1

= 3V

EXT REF = 1.25V

= 25°C

0 5k 10k 15k 16383

05302-119

Figure 20. INL AD5648-1

0 500 1000 1500 2000 2500 3000 3500 4095

INL (LSB)

CODES

= 3V

INT REF = 1.25V

= 25°C

05302-120

1.0

0.5

–0.5

–1.0

Figure 21. INL AD5628-1

0 10k 20k 30k 40k 50k 60k 65535

DNL (LSB)

CODES

= 3V

INT REF = 1.25V

= 25°C

05302-121

1.0

0.5

–1.0

–0.5

Figure 22. DNL AD5668-1

05302-122

CODES

DNL (LSB)

= 3V

EXT REF = 1.25V

= 25°C

0 5k 10k 15k 16383

0.5

0.3

0.2

0.1

0.4

–0.2

–0.1

–0.3

–0.5

–0.4

Figure 23. DNL AD5648-1

0 500 1000 1500 2000 2500 3000 3500 4095

DNL (LSB)

CODES

05302-123

–0.05

–0.10

–0.15

–0.20

0.05

0.10

0.15

0.20 V

= 3V

INT REF = 1.25V

= 25°C

Figure 24. DNL AD5628-1

AD5628/AD5648/AD5668 Data Sheet

Rev. F | Page 14 of 32

–0.30

–0.25

–0.20

–0.15

–0.10

–0.05

–40 1251109580655035205–10–25

ERROR ( % F SR)

TEMPERAT URE ( °C)

FUL L-SCALE ERROR

GAIN ERROR

= 5V

05302-124

Figure 25. Gain Error and Full-Scale Error vs. Temperature

–40 1251109580655035205–10–25

ERROR (mV)

TEMPERAT URE ( °C)

ZERO-SCALE ERRO R

OF F SE T ERRO R

= 5V

05302-125

Figure 26. Zero-Scale Error and Offset Error vs. Temperature

–

0.16

–0.26

–0.25

–0.24

–0.23

–0.22

–0.21

–0.20

–0.19

–0.18

–0.17

2.7 5.55.14.74.33.93.53.1

ERROR ( % F SR)

(V)

FULL-SCALE ERROR

GAIN ERROR

= 25°C

05302-126

Figure 27. Gain Error and Full-Scale Error vs. Supply Voltage

1.95

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

2.7 5.55.14.74.33.93.53.1

ERROR (mV)

(V)

ZERO-SCALE ERROR

OFFSET ERROR

= 25°C

05302-127

Figure 28. Zero-Scale Error and Offset Error vs. Supply Voltage

05302-128

WI T H EXTERNAL REF E RENCE (m A)

NUMBER OF HI T S

0.85 0.90 0.95 1.00 1.05

Figure 29. IDD Histogram with External Reference

05302-129

WI TH I NTERNAL REFERENCE ( mA)

NUMBER OF HI T S

1.65 1.70 1.75 1.80 1.85 1.190

Figure 30. IDD Histogram with Internal Reference

Data Sheet AD5628/AD5648/AD5668

Rev. F | Page 15 of 32

0.4

–0.5

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

–10–8–6–4–20246810

ERROR V O LTAGE ( V )

SOURCE/S INK CURRENT (mA)

= 5V, INT RE F = 2.5V

= 3V, INT REF = 1.25V

= 25°C

05302-130

Figure 31. Headroom at Rails vs. Source and Sink

–1

–0.03 –0.02 –0.01 0 0.01 0.02 0.03

OUT

(V)

CURRENT ( A)

ZE RO SCAL E

FUL L SCALE

MIDSCALE

1/4 S CALE

3/4 S CALE

= 5V

INT REF = 2.5V

= 25°C

05302-131

Figure 32. AD5668-2/AD5668-3 Source and Sink Capability

4.0

–1.0

–0.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

–0.03 –0.02 –0.01 0 0.01 0.02 0.03

OUT

(V)

CURRENT ( A)

ZERO S CAL E

FUL L SCALE

MIDSCALE

1/4 SCALE

3/4 S CALE

= 3V

INT REF = 1.25V

= 25°C

05302-132

Figure 33. AD5668-1 Source and Sink Capability

1.8

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

0 10k 20k 30k 40k 50k 60k

(mA)

DIG IT AL CODE S ( Decimal)

= 25° C

05302-133

= 5V

= 3V

Figure 34. Supply Current vs. Code

2.0

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

–40 –25 –10 5 20 35 50 65 80 95 110 125

(mA)

TEMPERAT URE ( °C)

05302-134

= 3. 6V

= 5. 5V

Figure 35. Supply Current vs. Temperature

1.48

1.34

1.36

1.38

1.40

1.42

1.44

1.46

2.7 5.55.14.74.33.93.53.1

IDD (mA)

VDD (V)

TA = 25°C

05302-135

Figure 36. Supply Current vs. Supply Voltage

AD5628/AD5648/AD5668 Data Sheet

Rev. F | Page 16 of 32

2.3

2.1

1.9

1.7

1.5

1.3

1.1

0.9

0.7 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

IDD (mA)

VLOGIC (V)

TA = 25°C

05302-136

VDD =5V

VDD =3V

Figure 37. Supply Current vs. Logic Input Voltage

0–2 86420

OUT

(V)

TIME (µs)

VDD = 5V

EXT REF = 5V

TA = 25°C

05302-137

Figure 38. Full-Scale Settling Time, 5 V

5.5

4.5

3.5

2.5

1.5

0.5

5.0

4.0

3.0

2.0

1.0

–0.5

–0.0010 0.00100.00060.0002–0.0002–0.0006

VOLTAGE (V)

TIME (s)

VOUTA

VDD

VDD = 5V

EXT REF = 5V

TA = 25°C

05302-138

Figure 39. Power-On Reset to 0 V

5.5

4.5

3.5

2.5

1.5

0.5

5.0

4.0

3.0

2.0

1.0

–0.5

–0.0010 0.00100.00060.0002–0.0002–0.0006

VOLTAGE (V)

TIME (s)

VOUTA

VDD

VDD = 5V

EXT REF = 5V

TA = 25°C

05302-139

Figure 40. Power-On Reset to Midscale

5.5

4.5

3.5

2.5

1.5

0.5

5.0

4.0

3.0

2.0

1.0

–0.5

–10 1050–5

VOLTAGE (V)

TIME (µs)

VOUTA

24TH CLK RI S ING E DGE

VDD = 5V

EXT REF = 5V

TA = 25°C

05302-140

Figure 41. Exiting Power-Down to Midscale

CH3 10.0mV

CH4 5.0V M400ns A CH4 1.50V

T 17.0%

05302-141

= 5V

EXT REF = 5V

= 25°C

OUT

CLK RI S ING EDGE

Figure 42. Digital-to-Analog Glitch Impulse (Negative)

Data Sheet AD5628/AD5648/AD5668

Rev. F | Page 17 of 32

0.0010

–0.0015

–0.0010

–0.0005

0.0005

0987654321

GLIT CH AM P LI TUDE (V )

TIME (µs)

05302-142

= 5V

EXT REF = 5V

= 25°C

Figure 43. Analog Crosstalk

0.0020

–0.0015

–0.0010

–0.0005

0.0010

0.0015

0.0005

087654321

GLIT CH AM P LI TUDE (V )

TIME (µs)

05302-143

= 5V

EXT REF = 5V

= 25°C

Figure 44. DAC-to-DAC Crosstalk

0.06

–0.08

–0.06

–0.04

–0.02

0.02

0.04

01897654321

OUTPUT VOLTAGE (V)

TIME (s) 0

EXT REF = 5V

05302-144

Figure 45. 0.1 Hz to 10 Hz Output Noise Plot, External Reference

0.20

–0.20

–0.15

–0.10

–0.05

0.10

0.15

0.05

01897654321

OUT P UT NOISE ( V )

TIME (s) 0

EXT REF = 2.5V

05302-145

Figure 46. 0.1 Hz to 10 Hz Output Noise Plot, External Reference

0.20

–0.20

–0.15

–0.10

–0.05

0.10

0.15

0.05

01897654321

OUT P UT NOISE ( V )

TIME (s) 0

INT REF = 1.25V

05302-146

Figure 47. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference

800

100

200

300

400

600

700

500

100 1M100k10k1k

OUTPUT NOISE (nV/ Hz)

FREQUENCY ( Hz)

REF

= 1.25V

REF

= 2. 5V

05302-147

Figure 48. Noise Spectral Density, Internal Reference

AD5628/AD5648/AD5668 Data Sheet

Rev. F | Page 18 of 32

–140

–120

–100

–80

–60

–40

–20

0 10,0008000600040002000

THD (dB)

FREQUENCY ( Hz)

05302-148

= 5. 5V

EXT REF = 5V

= 25°C

REF

= 2V ± 0 .1V p-p

FREQUENCY = 10kHz

Figure 49. Total Harmonic Distortion

010987654321

SETTLING TIME (µs)

CAPACITIVE LOAD (n F)

= EXTERNAL REFE RENCE = 5V

= EXTERNAL RE FERENCE = 3V

= 25°C

05302-149

Figure 50. Settling Time vs. Capacitive Load

5.5

–0.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

–10 1050–5

VOLTAGE (V)

TIME (µs)

OUT

CLR PULSE

EXT REF = 5V

05302-150

Figure 51. Hardware CLR

–80

–70

–60

–50

–40

–30

–20

–10

10 100M10M1M100k1k01k100

OUT

(dBm)

FREQUENCY ( Hz)

CH A

CH B

CH C

CH D

CH E

CH F

CH G

CH H

–3dB

05302-151

= 5.5V

EXT REF = 5V

= 25°C

REF

= 2V ± 0.2V p-p

Figure 52. Multiplying Bandwidth

1.2510

1.2490

1.2492

1.2494

1.2496

1.2498

1.2500

1.2502

1.2504

1.2506

1.2508

–40 25 105

REFE RE NCE ( ppm/°C)

TE MP ERAT URE ( ° C)

05302-152

= 5. 5V

Figure 53. 1.25 V Reference Temperature Coefficient vs. Temperature

05302-154

2.503

2.495

2.496

2.497

2.498

2.499

2.500

2.501

2.502

105 25 –40

REFE RE NCE (ppm/°C)

TEMPERATURE (°C)

Figure 54. 2.5 V Reference Temperature Coefficient vs. Temperature

Data Sheet AD5628/AD5648/AD5668

Rev. F | Page 19 of 32

TERMINOLOGY

Relative Accuracy

For the DAC, relative accuracy, or integral nonlinearity (INL), is

a measure of the maximum deviation in LSBs from a straight line

passing through the endpoints of the DAC transfer function.

Figure 7 to Figure 9, Figure 13 to Figure 15, and Figure 19 to

Figure 21 show plots of typical INL vs. code.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the

measured change and the ideal 1 LSB change between any two

adjacent codes. A specified differential nonlinearity of ±1 LSB

maximum ensures monotonicity. This DAC is guaranteed mono-

tonic by design. Figure 10 to Figure 12, Figure 16 to Figure 18,

and Figure 22 to Figure 24 show plots of typical DNL vs. code.

Offset Error

Offset error is a measure of the difference between the actual

VOUT and the ideal VOUT, expressed in millivolts in the linear

region of the transfer function. Offset error is measured on the

AD5668 with Code 512 loaded into the DAC register. It can be

negative or positive and is expressed in millivolts.

Zero-Code Error

Zero-code error is a measure of the output error when zero

code (0x0000) is loaded into the DAC register. Ideally, the

output should be 0 V. The zero-code error is always positive in

the AD5628/AD5648/AD5668, because the output of the DAC

cannot go below 0 V. It is due to a combination of the offset

errors in the DAC and output amplifier. Zero-code error is

expressed in millivolts. Figure 28 shows a plot of typical zero-

code error vs. temperature.

Gain Error

Gain error is a measure of the span error of the DAC. It is the

deviation in slope of the DAC transfer characteristic from the

ideal, expressed as a percentage of the full-scale range.

Zero-Code Error Drift

Zero-code error drift is a measure of the change in zero-code

error with a change in temperature. It is expressed in μV/°C.

Gain Error Drift

Gain error drift is a measure of the change in gain error with

changes in temperature. It is expressed in (ppm of full-scale

range)/°C.

Full-Scale Error

Full-scale error is a measure of the output error when full-scale

code (0xFFFF) is loaded into the DAC register. Ideally, the

output should be VDD – 1 LSB. Full-scale error is expressed as a

percentage of the full-scale range. Figure 25 shows a plot of

typical full-scale error vs. temperature.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

state. It is normally specified as the area of the glitch in nV-s and

is measured when the digital input code is changed by 1 LSB at

the major carry transition (0x7FFF to 0x8000). See Figure 42.

DC Power Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the DAC is affected by changes

in the supply voltage. PSRR is the ratio of the change in VOUT to

a change in VDD for full-scale output of the DAC. It is measured

in decibels. VREF is held at 2 V, and VDD is varied ±10%.

DC Crosstalk

DC crosstalk is the dc change in the output level of one DAC in

response to a change in the output of another DAC. It is measured

with a full-scale output change on one DAC (or soft power-down

and power-up) while monitoring another DAC kept at midscale.

It is expressed in microvolts.

DC crosstalk due to load current change is a measure of the

impact that a change in load current on one DAC has to another

DAC kept at midscale. It is expressed in microvolts per milliamp.

Reference Feedthrough

Reference feedthrough is the ratio of the amplitude of the signal

at the DAC output to the reference input when the DAC output

is not being updated (that is, LDAC is high). It is expressed in

decibels.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into

the analog output of a DAC from the digital input pins of the

device, but is measured when the DAC is not being written to

(SYNC held high). It is specified in nV-s and measured with a

full-scale change on the digital input pins, that is, from all 0s to

all 1s or vice versa.

Digital Crosstalk

Digital crosstalk is the glitch impulse transferred to the output

of one DAC at midscale in response to a full-scale code change

(all 0s to all 1s or vice versa) in the input register of another DAC.

It is measured in standalone mode and is expressed in nV-s.

Analog Crosstalk

Analog crosstalk is the glitch impulse transferred to the output

of one DAC due to a change in the output of another DAC. It is

measured by loading one of the input registers with a full-scale

code change (all 0s to all 1s or vice versa) while keeping LDAC

high, and then pulsing LDAC low and monitoring the output of

the DAC whose digital code has not changed. The area of the

glitch is expressed in nV-s.

AD5628/AD5648/AD5668 Data Sheet

Rev. F | Page 20 of 32

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse transferred to the

output of one DAC due to a digital code change and subsequent

output change of another DAC. This includes both digital and

analog crosstalk. It is measured by loading one of the DACs

with a full-scale code change (all 0s to all 1s or vice versa) with

LDAC low and monitoring the output of another DAC. The

energy of the glitch is expressed in nV-s.

Multiplying Bandwidth

The amplifiers within the DAC have a finite bandwidth. The

multiplying bandwidth is a measure of this. A sine wave on the

reference (with full-scale code loaded to the DAC) appears on

the output. The multiplying bandwidth is the frequency at

which the output amplitude falls to 3 dB below the input.

Total Harmonic Distortion (THD)

Total harmonic distortion is the difference between an ideal

sine wave and its attenuated version using the DAC. The sine

wave is used as the reference for the DAC, and the THD is a

measure of the harmonics present on the DAC output. It is

measured in decibels.

Data Sheet AD5628/AD5648/AD5668

Rev. F | Page 21 of 32

THEORY OF OPERATION

D/A SECTION

The AD5628/AD5648/AD5668 DACs are fabricated on a

CMOS process. The architecture consists of a string of DACs

followed by an output buffer amplifier. Each part includes an

internal 1.25 V/2.5 V, 5 ppm/°C reference with an internal gain

of 2. Figure 55 shows a block diagram of the DAC architecture.

05302-153

DAC

VREFIN

RESISTOR

STRING

REF

GND

OUTPUT

AMPLIFIER

(GAIN = ×2)

VOUT

Figure 55. DAC Architecture

Because the input coding to the DAC is straight binary, the ideal

output voltage when using an external reference is given by

⎟

⎠

⎞

⎜

⎝

⎛

×= N

REFIN

OUT

The ideal output voltage when using the internal reference is

given by

⎟

⎠

⎞

⎜

⎝

⎛

××= N

REFOUTOUT

where:

D = decimal equivalent of the binary code that is loaded to the

DAC register.

0 to 4095 for AD5628 (12 bits).

0 to 16,383 for AD5648 (14 bits).

0 to 65,535 for AD5668 (16 bits).

N = the DAC resolution.

RESISTOR STRING

The resistor string section is shown in Figure 56. It is simply a

string of resistors, each of value R. The code loaded into the

DAC register determines at which node on the string the

voltage is tapped off to be fed into the output amplifier. The

voltage is tapped off by closing one of the switches connecting

the string to the amplifier. Because it is a string of resistors, it is

guaranteed monotonic.

05302-053

TO O UTPUT

AMPLIFIER

Figure 56. Resistor String

INTERNAL REFERENCE

The AD5628/AD5648/AD5668 have an on-chip reference with

an internal gain of 2. The AD5628/AD5648/AD5668-1 have a

1.25 V, 5 ppm/°C reference, giving a full-scale output of 2.5 V;

the AD5628/AD5648/AD5668-2, -3 have a 2.5 V, 5 ppm/°C

reference, giving a full-scale output of 5 V. The on-board

reference is off at power-up, allowing the use of an external

reference. The internal reference is enabled via a write to the

control register (see Table 8).

The internal reference associated with each part is available at

the VREFOUT pin. A buffer is required if the reference output is

used to drive external loads. When using the internal reference,

it is recommended that a 100 nF capacitor be placed between

the reference output and GND for reference stability.

Individual channel power-down is not supported while using

the internal reference.

AD5628/AD5648/AD5668 Data Sheet

Rev. F | Page 22 of 32

OUTPUT AMPLIFIER

The output buffer amplifier can generate rail-to-rail voltages on

its output, which gives an output range of 0 V to VDD. The

amplifier is capable of driving a load of 2 kΩ in parallel with

200 pF to GND. The source and sink capabilities of the output

amplifier can be seen in Figure 32 and Figure 33. The slew rate

is 1.5 V/μs with a ¼ to ¾ scale settling time of 7 μs.

SERIAL INTERFACE

The AD5628/AD5648/AD5668 have a 3-wire serial interface

(SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and

MICROWIRE interface standards as well as most DSPs. See

for a timing diagram of a typical write sequence. Figure 2

The write sequence begins by bringing the SYNC line low. Data

from the DIN line is clocked into the 32-bit shift register on the

falling edge of SCLK. The serial clock frequency can be as high

as 50 MHz, making the AD5628/AD5648/AD5668 compatible

with high speed DSPs. On the 32nd falling clock edge, the last

data bit is clocked in and the programmed function is executed,

that is, a change in DAC register contents and/or a change in

the mode of operation. At this stage, the SYNC line can be kept

low or be brought high. In either case, it must be brought high

for a minimum of 15 ns before the next write sequence so that a

falling edge of SYNC can initiate the next write sequence. SYNC

should be idled low between write sequences for even lower

power operation of the part. As is mentioned previously,

however, SYNC must be brought high again just before the next

write sequence.

Table 8. Command Definitions

Command

C3 C2 C1 C0 Description

0 0 0 0 Write to Input Register n

0 0 0 1 Update DAC Register n

0 0 1 0 Write to Input Register n, update all

(software LDAC)

0 0 1 1 Write to and update DAC Channel n

0 1 0 0 Power down/power up DAC

0 1 0 1 Load clear code register

0 1 1 0 Load LDAC register

0 1 1 1 Reset (power-on reset)

1 0 0 0 Set up internal REF register

1 0 0 1 Reserved

– – – – Reserved

1 1 1 1 Reserved

Table 9. Address Commands

Address (n)

A3 A2 A1 A0 Selected DAC Channel

0 0 0 0 DAC A

0 0 0 1 DAC B

0 0 1 0 DAC C

0 0 1 1 DAC D

0 1 0 0 DAC E

0 1 0 1 DAC F

0 1 1 0 DAC G

0 1 1 1 DAC H

1 1 1 1 All DACs

Data Sheet AD5628/AD5648/AD5668

Rev. F | Page 23 of 32

INPUT SHIFT REGISTER

The input shift register is 32 bits wide. The first four bits are

don’t cares. The next four bits are the command bits, C3 to C0

(see Tabl e 8 ), followed by the 4-bit DAC address, A3 to A0 (see

Tabl e 9) and finally the 16-/14-/12-bit data-word. The data-

word comprises the 16-/14-/12-bit input code followed by four,

six, or eight don’t care bits for the AD5668, AD5648, and

AD5628, respectively (see Figure 57 through Figure 59). These

data bits are transferred to the DAC register on the 32nd falling

edge of SCLK.

SYNC INTERRUPT

In a normal write sequence, the SYNC line is kept low for

32 falling edges of SCLK, and the DAC is updated on the 32nd

falling edge and rising edge of SYNC. However, if SYNC is brought

high before the 32nd falling edge, this acts as an interrupt to the

write sequence. The shift register is reset, and the write sequence

is seen as invalid. Neither an update of the DAC register contents

nor a change in the operating mode occurs (see ). Figure 60

05302-054

ADDRESS BITSCOMMAND BITS

C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

XXXX

DB31 (MSB) DB0 (LSB)

DATA BITS

Figure 57. AD5668 Input Register Contents

05302-055

ADDRESS BITSCOMMAND BITS

C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X

XXXX

DB31 (MSB) DB0 (LSB)

DATA BITS

Figure 58. AD5648 Input Register Contents

05302-056

ADDRESS BITSCOMMAND BITS

C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X

XXXX

DB31 (MSB) DB0 (LSB)

DATA BITS

Figure 59. AD5628 Input Register Contents

05302-057

SCLK

DIN DB31 DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 32ND FALLING EDGE VALID WRIT E S E QUENCE, OUT PUT UPDATES

ON THE 32ND FALLING EDGE

DB31 DB0

SYNC

Figure 60. SYNC Interrupt Facility

AD5628/AD5648/AD5668 Data Sheet

Rev. F | Page 24 of 32

INTERNAL REFERENCE REGISTER

The on-board reference is off at power-up by default. This allows

the use of an external reference if the application requires it. The

on-board reference can be turned on or off by a user-program-

mable internal REF register by setting Bit DB0 high or low (see

Tabl e 10). Command 1000 is reserved for setting the internal

REF register (see Table 8). Table 12 shows how the state of the

bits in the input shift register corresponds to the mode of

operation of the device.

POWER-ON RESET

The AD5628/AD5648/AD5668 family contains a power-on

reset circuit that controls the output voltage during power-up.

The AD5628/AD5648/AD5668-1, -2 DAC output powers up to

0 V, and the AD5668-3 DAC output powers up to midscale. The

output remains powered up at this level until a valid write

sequence is made to the DAC. This is useful in applications

where it is important to know the state of the output of the DAC

while it is in the process of powering up. There is also a software

executable reset function that resets the DAC to the power-on

reset code. Command 0111 is reserved for this reset function

(see Tabl e 8 ). Any events on LDAC or CLR during power-on

reset are ignored.

POWER-DOWN MODES

The AD5628/AD5648/AD5668 contain four separate modes

of operation. Command 0100 is reserved for the power-down

function (see Tabl e 8 ). These modes are software-programmable

by setting two bits, Bit DB9 and Bit DB8, in the control register.

Tabl e 12 shows how the state of the bits corresponds to the

mode of operation of the device. Any or all DACs (DAC H to

DAC A) can be powered down to the selected mode by setting

the corresponding eight bits (DB7 to DB0) to 1. See Tabl e 1 3 for

the contents of the input shift register during power-down/power-

up operation. When using the internal reference, only all channel

power-down to the selected modes is supported.

When both bits are set to 0, the part works normally with its

normal power consumption of 1.3 mA at 5 V. However, for the

three power-down modes, the supply current falls to 0.4 μA at

5 V (0.2 μA at 3 V). Not only does the supply current fall, but

the output stage is also internally switched from the output of

the amplifier to a resistor network of known values. This has the

advantage that the output impedance of the part is known while

the part is in power-down mode. There are three different

options. The output is connected internally to GND through

either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited

(three-state). The output stage is illustrated in Figure 61.

The bias generator of the selected DAC(s), output amplifier,

resistor string, and other associated linear circuitry are shut

down when the power-down mode is activated. The internal

reference is powered down only when all channels are powered

down. However, the contents of the DAC register are unaffected

when in power-down. The time to exit power-down is typically

4 μs for VDD = 5 V and for VDD = 3 V. See Figure 41 for a plot.

Any combination of DACs can be powered up by setting PD1

and PD0 to 0 (normal operation). The output powers up to the

value in the input register (LDAC low) or to the value in the

DAC register before powering down (LDAC high).

CLEAR CODE REGISTER

The AD5628/AD5648/AD5668 have a hardware CLR pin that

is an asynchronous clear input. The CLR input is falling edge

sensitive. Bringing the CLR line low clears the contents of the

input register and the DAC registers to the data contained in

the user-configurable CLR register and sets the analog outputs

accordingly. This function can be used in system calibration to load

zero scale, midscale, or full scale to all channels together. These

clear code values are user-programmable by setting two bits,

Bit DB1 and Bit DB0, in the CLR control register (see ).

The default setting clears the outputs to 0 V. Command 0101 is

reserved for loading the clear code register (see ).

Table 14

Table 8

The part exits clear code mode on the 32nd falling edge of the next

write to the part. If CLR is activated during a write sequence, the

write is aborted.

The CLR pulse activation time—the falling edge of CLR to

when the output starts to change—is typically 280 ns. However, if

outside the DAC linear region, it typically takes 520 ns after

executing CLR for the output to start changing (see ). Figure 51

See Table 15 for contents of the input shift register during the

loading clear code register operation.

Data Sheet AD5628/AD5648/AD5668

Rev. F | Page 25 of 32

Table 10. Internal Reference Register

Internal REF Register (DB0) Action

0 Reference off (default)

1 Reference on

Table 11. 32-Bit Input Shift Register Contents for Reference Set-Up Command

MSB LSB

DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 to DB1 DB0

X 1 0 0 0 X X X X X 1/0

Don’t cares Command bits (C3 to C0) Address bits (A3 to A0)—don’t cares Don’t cares Internal REF

Table 12. Power-Down Modes of Operation

DB9 DB8 Operating Mode

0 0 Normal operation

Power-down modes

0 1 1 kΩ to GND

1 0 100 kΩ to GND

1 1 Three-state

Table 13. 32-Bit Input Shift Register Contents for Power-Down/Power-Up Function

MSB LSB

DB31

DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20

DB19

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

X 0 1 0 0 X X X X X PD1 PD0 DAC

DAC

Don’t

cares

Command bits (C3 to C0) Address bits (A3 to A0)—

don’t cares

Don’t

cares

Power-

down mode

Power-down/power-up channel selection—set bit to 1 to select

RESISTOR

NETWORK

OUT

RESISTOR

STRING DAC

05302-058

POWER-DOWN

CIRCUITRY

AMPLIFIER

Figure 61. Output Stage During Power-Down

Table 14. Clear Code Register

Clear Code Register

DB1 DB0

CR1 CR0 Clears to Code

0 0 0x0000

0 1 0x8000

1 0 0xFFFF

1 1 No operation

Table 15. 32-Bit Input Shift Register Contents for Clear Code Function

MSB LSB

DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 to DB2 DB1 DB0

X 0 1 0 1 X X X X X CR1 CR0

Don’t cares Command bits (C3 to C0) Address bits (A3 to A0)—don’t cares Don’t cares Clear code register

AD5628/AD5648/AD5668 Data Sheet

Rev. F | Page 26 of 32

LDAC FUNCTION

The outputs of all DACs can be updated simultaneously using

the hardware LDAC pin.

Synchronous LDAC: After new data is read, the DAC registers

are updated on the falling edge of the 32nd SCLK pulse. LDAC

can be permanently low or pulsed as in . Figure 2

Asynchronous LDAC: The outputs are not updated at the same

time that the input registers are written to. When LDAC goes

low, the DAC registers are updated with the contents of the

input register.

Alternatively, the outputs of all DACs can be updated simulta-

neously using the software LDAC function by writing to Input

reserved for this software LDAC function.

An LDAC register gives the user extra flexibility and control

over the hardware LDAC pin. This register allows the user to

select which combination of channels to simultaneously update

when the hardware LDAC pin is executed. Setting the LDAC bit

is controlled by the LDAC pin. If this bit is set to 1, this channel

updates synchronously; that is, the DAC register is updated

after new data is read, regardless of the state of the LDAC pin. It

effectively sees the LDAC pin as being tied low. (See

for the

Table 16

LDAC register mode of operation.) This flexibility is

useful in applications where the user wants to simultaneously

update select channels while the rest of the channels are

synchronously updating.

Writing to the DAC using command 0110 loads the 8-bit LDAC

the LDAC pin works normally. Setting the bits to 1 means the

DAC channel is updated regardless of the state of the LDAC

pin. See for the contents of the input shift register

during the load

Tabl e 17

LDAC register mode of operation.

POWER SUPPLY BYPASSING AND GROUNDING

When accuracy is important in a circuit, it is helpful to carefully

consider the power supply and ground return layout on the board.

The printed circuit board containing the AD5628/AD5648/

AD5668 should have separate analog and digital sections. If the

AD5628/AD5648/AD5668 are in a system where other devices

require an AGND-to-DGND connection, the connection should

be made at one point only. This ground point should be as close

as possible to the AD5628/AD5648/AD5668.

The power supply to the AD5628/AD5648/AD5668 should be

bypassed with 10 μF and 0.1 μF capacitors. The capacitors

should physically be as close as possible to the device, with the

0.1 μF capacitor ideally right up against the device. The 10 μF

capacitors are the tantalum bead type. It is important that the

0.1 μF capacitor has low effective series resistance (ESR) and

low effective series inductance (ESI), such as is typical of

common ceramic types of capacitors. This 0.1 μF capacitor

provides a low impedance path to ground for high frequencies

caused by transient currents due to internal logic switching.

The power supply line should have as large a trace as possible to

provide a low impedance path and reduce glitch effects on the

supply line. Clocks and other fast switching digital signals should

be shielded from other parts of the board by digital ground. Avoid

crossover of digital and analog signals if possible. When traces

cross on opposite sides of the board, ensure that they run at right

angles to each other to reduce feedthrough effects through the

board. The best board layout technique is the microstrip technique,

where the component side of the board is dedicated to the ground

plane only and the signal traces are placed on the solder side.

However, this is not always possible with a 2-layer board.

Table 16. LDAC Register

Load DAC Register

LDAC Bits (DB7 to DB0) LDAC Pin LDAC Operation

0 1/0

Determined by LDAC pin.

1 X—don’t care

DAC channels update, overriding the LDAC pin. DAC channels see LDAC as 0.

Table 17. 32-Bit Input Shift Register Contents for LDAC Register Function

MSB LSB

DB31

DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20

DB19

DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

X 0 1 1 0 X X X X X DAC

DAC

Don’t

cares

Command bits (C3 to C0) Address bits (A3 to A0)—

don’t cares

Don’t

cares

Setting LDAC bit to 1 overrides LDAC pin

Data Sheet AD5628/AD5648/AD5668

Rev. F | Page 27 of 32

OUTLINE DIMENSIONS

COMP LI ANT TO JEDEC STANDARDS M O-153-AB- 1

061908-A

8°

0°

4.50

4.40

4.30

14 8

6.40

BSC

PIN 1

5.10

5.00

4.90

0.65 BS C

0.15

0.05 0.30

0.19

1.20

MAX

1.05

1.00

0.80 0.20

0.09 0.75

0.60

0.45

COPLANARITY

0.10

SEATING

PLANE

Figure 62. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

16 9

PIN 1

SEATING

PLANE

8°

0°

4.50

4.40

4.30

6.40

BSC

5.10

5.00

4.90

0.65

BSC

0.15

0.05

1.20

MAX 0.20

0.09 0.75

0.60

0.45

0.30

0.19

COPLANARITY

0.10

COM PLI ANT TO JEDEC STANDARDS MO-153 - AB

Figure 63. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

AD5628/AD5648/AD5668 Data Sheet

Rev. F | Page 28 of 32

2.70

2.60 SQ

2.50

COMPLIANT

JEDEC STANDARDS MO-220-WGGC.

0.65

BSC

BOTTOM VIEWTOP VIEW

12 13

EXPOSED

PAD

PIN1

INDICATOR

4.10

4.00 SQ

3.90

0.45

0.40

0.35

EATING

PLANE

0.80

0.75

0.70 0.05 MAX

0.02 NOM

0.20 REF

0.20 MIN

COPLANARITY

0.08

PIN 1

INDICATOR

0.35

0.30

0.25

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

08-16-2010-C

Figure 64. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm Body, Very Very Thin Quad

(CP-16-17)

Dimensions shown in millimeters

08-16-2011-A

0.650

0.595

0.540

SIDE VIEW

0.270

0.240

0.210

0.340

0.320

0.300

COPLANARITY

0.05

SEATING

PLANE

BOT TO M VIEW

(BAL L S IDE UP)

TOP VIEW

( BALL SIDE DOWN)

BALL A1

IDENTIFIER

0.50

REF

1.50

REF

2.645

2.60 5 S Q

2.565

Figure 65. 16-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-16-16)

Dimensions shown in millimeters

Data Sheet AD5628/AD5648/AD5668

Rev. F | Page 29 of 32

ORDERING GUIDE

Model1 Temperature Range Package Description

Package

Option

Power-On

Reset to Code Accuracy

Internal

Reference

AD5628BRUZ-1 −40°C to +105°C 14-Lead TSSOP RU-14 Zero ±1 LSB INL 1.25 V

AD5628BRUZ-1REEL7 −40°C to +105°C 14-Lead TSSOP RU-14 Zero ±1 LSB INL 1.25 V

AD5628BRUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±1 LSB INL 2.5 V

AD5628BRUZ-2REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±1 LSB INL 2.5 V

AD5628ARUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±2 LSB INL 2.5 V

AD5628ARUZ-2REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±2 LSB INL 2.5 V

AD5628ACPZ-1-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±2 LSB INL 1.25 V

AD5628ACPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±2 LSB INL 2.5 V

AD5628BCPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±1 LSB INL 2.5 V

AD5628BCBZ-1-RL7 −40°C to +105°C 16-Lead WLCSP CB-16-16 Zero ±1 LSB INL 1.25 V

AD5648BRUZ-1 −40°C to +105°C 14-Lead TSSOP RU-14 Zero ±4 LSB INL 1.25 V

AD5648BRUZ-1REEL7 −40°C to +105°C 14-Lead TSSOP RU-14 Zero ±4 LSB INL 1.25 V

AD5648BRUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±4 LSB INL 2.5 V

AD5648BRUZ-2REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±4 LSB INL 2.5 V

AD5648ARUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±8 LSB INL 2.5 V

AD5648ARUZ-2REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±8 LSB INL 2.5 V

AD5668BRUZ-1 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±16 LSB INL 1.25 V

AD5668BRUZ-1REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±16 LSB INL 1.25 V

AD5668BRUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±16 LSB INL 2.5 V

AD5668BRUZ-2REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±16 LSB INL 2.5 V

AD5668BRUZ-3 −40°C to +105°C 16-Lead TSSOP RU-16 Midscale ±16 LSB INL 2.5 V

AD5668BRUZ-3REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Midscale ±16 LSB INL 2.5 V

AD5668ARUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±32 LSB INL 2.5 V

AD5668ARUZ-2REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±32 LSB INL 2.5 V

AD5668ARUZ-3 −40°C to +105°C 16-Lead TSSOP RU-16 Midscale ±32 LSB INL 2.5 V

AD5668ARUZ-3REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Midscale ±32 LSB INL 2.5 V

AD5668BCPZ-1-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±16 LSB INL 1.25 V

AD5668BCPZ-1500RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±16 LSB INL 1.25 V

AD5668BCPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±16 LSB INL 2.5 V

AD5668BCPZ-2500RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±16 LSB INL 2.5 V

AD5668ACPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±32 LSB INL 2.5 V

AD5668ACPZ-3-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Midscale ±32 LSB INL 2.5 V

AD5668BCBZ-1-RL7 −40°C to +105°C 16-Lead WLCSP CB-16-16 Zero ±1 LSB INL 1.25 V

EVAL-AD5668SDCZ LFCSP Evaluation Board

EVAL-AD5668SDRZ TSSOP Evaluation Board

1 Z = RoHS Compliant Part.

AD5628/AD5648/AD5668 Data Sheet

Rev. F | Page 30 of 32

NOTES

Data Sheet AD5628/AD5648/AD5668

Rev. F | Page 31 of 32

NOTES

AD5628/AD5648/AD5668 Data Sheet

Rev. F | Page 32 of 32

NOTES

registered trademarks are the property of their respective owners.

D05302-0-8/11(F)