DS028 (v1.2) November 5, 2001 www.xilinx.com 1
Preliminary Product Specification 1-800-255-7778
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
•0.22 µm 5-layer epitaxial process
•QML certified
• Radiation hard ened FPGA s for spa ce and satellite
applications
• Guaranteed total ionizing dose to 100K Rad(si)
• Latch-up immune to LET = 125 M eV cm 2/mg
• SEU immunity achievable with recommen ded
redundanc y implementat ion
• Guaranteed over the full m ilit ary tem perat ure range
(–55°C to +125°C)
• Fast, high-density Field-Programm able Gate Arrays
- Densities from 100k to 1M system gates
- System performance up to 200 MHz
- Hot-swappab le for Compact PCI
• Multi-standard SelectI/O™ interfaces
- 16 high-performance interface standards
- Connec ts directly to ZBTRAM devices
• Built-in clock-man agem ent circuitry
- Four dedicated delay-locked loops (DLLs) for
advanced clock con trol
- Four primary low-skew g lobal clock distribution
nets, plu s 24 secondary global nets
• Hierarchical memor y system
- LUTs conf igurable as 16-bit RAM, 32-bit RAM,
16-bit dual-ported RAM, or 16-bit Shift Register
- Conf igurable synchronous dual-port ed 4k-bit
RAMs
- Fast interfaces to external high-perf ormance RAMs
• Flexible architecture that balances speed and density
- Dedicated carry logic for high-speed arithmetic
- Dedicat ed multiplier support
- Cas cade chain for wide-input functions
- A bundant registers/latches with clock enable, and
dual synchronous/ asynch ronous se t and reset
- Internal 3-state bussing
- IEEE 1 149 .1 boundary-scan logic
- Die-tem perature sensing device
• Supported by FPGA F oundation™ and Alliance
De v e lopment Systems
- Complete support f or Uni fied Libraries, Relationally
Placed Macros, and Design Manager
- Wide selection of PC and workstat ion platfor m s
• S RA M -based in-system configuration
- Unlimited reprogrammability
- Four programming modes
• Av ailable to Standard Microcircuit Drawings. Contact
Defense Su pply Center Columbus (DSCC) for more
inform ation at http://www.d scc. dla.mil
- 5962-99572 f or XQVR300
- 5962-99573 f or XQVR600
- 5962-99574 f or XQVR1000
Description
The QPro™ Virtex™ FPGA family delivers high-perfor-
mance, high-capacity programmable logic solutions. Dra-
matic increases in silicon efficiency result from optimizing
the new architecture for place-and-route efficiency and
explo iting an aggressive 5-layer-metal 0.22 µm CM OS pro-
cess. These advances make QPro Virtex FPGAs powerful
and flexible alternatives to mask-programmed gate arrays.
The Virtex radiation hardened family comprises the three
members shown in Table 1.
Building on experience gained from previous generations of
FPGAs, the Virtex family represents a revolutionary step
forward in programmable logic design. Combining a wide
variety of programmable sy stem f eatures, a rich hierarchy of
fast, flexibl e interconnect resources, and advanced process
technology, the QPro Virtex family delivers a high-speed
and high-capacity programmable logic solution that
enhances design fle xibility while reducing time-to-market.
Refer to the “Virtex™ 2.5V Field Programmable Gate
Arrays” commercial data sheet for more information on
device architecture and timing specifications.
0QPro Virtex 2.5V Radiation
Hardened FPGAs
DS028 (v1.2) November 5, 2001 02Preliminary Product Speci fication
R