SCALE™-2 2SC0435T2E0-17
Prelim i nary Dat a Shee t
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5) An extended output power range is specified in the output power section for maximum ambient
temperatures of 70°C. In that case, the absolute maximum rating for the operating temperature
changes to (–40°C - 70°C) and the absolute m aximum output power rating changes to 6W.
6) The delay time is measured between 50% of the input signal and 10% voltage swing of the
corresp o nding out put. The delay time is independent of the output lo ading.
7) Output rise and fall ti mes are meas ured betwee n 10% and 90% of the nomi nal output swing w ith an
output load of 4.7Ω and 270nF. The values are given for the driver side of the gate resistors. The time
constant of the output load in conjunction wit h the present ga te resistors lea ds to an additio nal delay
at the load side of the gate resistors.
8) External blocking capacitors are to be placed between VISOx and VEx as well as VEx and COMx for
gate charges exceeding 3µC. Ceramic capacitors are recommended. A minimum external blocking
capacitance of 3µF is recommended for every 1µC of gate charge beyond 3µC. Insufficient external
blocking can lead to reduced driver efficiency and thus to therm al over load.
9) The minimum response time given is valid for the circuit given in the description and application
manual (Fig. 7) with the values of table 1 (Cax=0pF, Rthx=43kΩ).
10) The blocking time sets a minimum time span between the end of any fault state and the start of
normal operation (remove fault from pin SOx). The value of the blocking time can be adjusted at pin
TB. The specified blocking time is valid if TB is connected to GND.
11) This spe cification guara ntees that the drive in formation will be tra nsferred reliabl y even at a high DC-
link voltage and with ultra-fast switching operations.
12) Undervoltage monitoring of the primary-side supply voltage (VCC to GND). If the voltage drops below
this limit, a fault is transmitted t o both SOx outputs and the power semiconductors ar e switched off.
13) Unde rvolta ge monitor ing of the seco ndary-side suppl y voltage (VI SOx to VEx and VEx to COMx w hich
correspond with the approximate turn-on and turn-off gate-emitter voltages). If the corresponding
voltage drops below this limit, t he IGBT is switched off and a fault is transmitted t o the corresponding
SOx output.
14) Transmission delay of fault state from the secondary side to the corresp onding primar y status output.
15) HiPot testing (= dielectric testing) must generally be restricted to suitable components. This gate
driver is suited for HiPot te sting. Nevertheless, it is st rongly recommended to limi t the testing time to
1s slots as stipulated by EN 50178. Excessive HiPot testing at voltages much higher than 1200V AC(eff)
may lead to insulation degradation. No degradation has been observed over 1min. testing at
5000VAC(eff). Ever y production sample s hipped to customers has u ndergone 100% t esting at the given
value for 1s.
16) Partial discharge measurement is performed in accordance with IEC 60270 and isolation coordination
specified in E N 50178. The par tial discharge extincti on voltage bet ween primary and e ither secondary
side is coordinated for safe isolat ion to EN 50178.
17) Jitter measurements are performed with input signals INx switching between 0V and 5V referred to
GND, with a corresponding rise time and fall time of 15ns.