54AC16374, 74AC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS123B – MARCH 1990 – REVISED APRIL 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
Family
D
3-State True Outputs
D
Full Parallel Access for Loading
D
Flow-Through Architecture Optimizes
PCB Layout
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
500-mA Typical Latch-Up Immunity at
125°C
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The ’AC16374 are 16-bit edge-triggered D-type
flip-flops with 3-state outputs designed
specifically for driving highly capacitive or
relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The ’AC16374 can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock
(CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly.
OE does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The 74AC16374 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54AC16374 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74AC16374 is characterized for operation from –40°C to 85°C.
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1CLK
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2CLK
54AC16374 . . . WD PACKAGE
74AC16374 . . . DL PACKAGE
(TOP VIEW)
54AC16374, 74AC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS123B – MARCH 1990 – REVISED APRIL 1996
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS OUTPUT
OE CLK DQ
L↑H H
L↑LL
LXX Q
0
L↓XQ
0
H X X Z
logic symbol†
1OE
2OE
1EN
1
48
1CLK
1D
47
1D1 46
1D2 44
1D3 43
1D4
1Q1
2
1Q2
3
1Q3
5
1Q4
6
1
41
1D5 40
1D6 38
1D7 37
1D8
1Q5
8
1Q6
9
1Q7
11
1Q8
12
2D
36
2D1 35
2D2 33
2D3 32
2D4
2Q1
13
2Q2
14
2Q3
16
2Q4
17
30
2D5 29
2D6 27
2D7 26
2D8
2Q5
19
2Q6
20
2Q7
22
2Q8
23
2
2EN
24
25
2CLK
C1
C2
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
54AC16374, 74AC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS123B – MARCH 1990 – REVISED APRIL 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1OE
1CLK
1D1
To Seven Other Channels
1Q1
2OE
2CLK
2D1 2Q1
To Seven Other Channels
1
48
47
24
25
36 C1
1D 132
C1
1D
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±400 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power package dissipation at TA = 55°C (in still air)(see Note 2): DL package 1.2 W. . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
54AC16374, 74AC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS123B – MARCH 1990 – REVISED APRIL 1996
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
54AC16374 74AC16374
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 3 5 5.5 3 5 5.5 V
VCC = 3 V 2.1 2.1
VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V
VCC = 5.5 V 3.85 3.85
VCC = 3 V 0.9 0.9
VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 V
VCC = 5.5 V 1.65 1.65
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
VCC = 3 V –4 –4
IOH High-level output current VCC = 4.5 V –24 –24 mA
VCC = 5.5 V –24 –24
VCC = 3 V 12 12
IOL Low-level output current VCC = 4.5 V 24 24 mA
VCC = 5.5 V 24 24
∆t/∆vInput transition rise or fall rate 0 10 0 10 ns/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C 54AC16374 74AC16374
UNIT
PARAMETER
TEST
CONDITIONS
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
3 V 2.9 2.9 2.9
IOH = –50 µA4.5 V 4.4 4.4 4.4
5.5 V 5.4 5.4 5.4
VOH IOH = –4 mA 3 V 2.58 2.48 2.48 V
I24A
4.5 V 3.94 3.8 3.8
IOL = –24 mA 5.5 V 4.94 4.8 4.8
IOH = –75 mA†5.5 V 3.85 3.85
3 V 0.1 0.1 0.1
IOL = 50 µA4.5 V 0.1 0.1 0.1
5.5 V 0.1 0.1 0.1
VOL IOL = 12 mA 3 V 0.36 0.44 0.44 V
IOL =24mA
4.5 V 0.36 0.44 0.44
I
OL =
24
mA
5.5 V 0.36 0.44 0.44
IOL = 75 mA†5.5 V 1.65 1.65
IIVI = VCC or GND 5.5 V ±0.1 ±1±1µA
IOZ VO = VCC or GND 5.5 V ±0.5 ±5±5µA
ICC VI = VCC or GND, IO = 0 5.5 V 8 80 80 µA
CiVI = VCC or GND 5 V 3 pF
CoVO = VCC or GND 5 V 11 pF
†Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
54AC16374, 74AC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS123B – MARCH 1990 – REVISED APRIL 1996
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C 54AC16374 74AC16374
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
fclock Clock frequency 0 60 0 60 0 60 MHz
twPulse duration CLK high or low 8.3 8.3 8.3 ns
tsu Setup time, data before CLK↑7.5 7.5 7.5 ns
thHold time, data after CLK↑0 0 0 ns
timing requirements over recommended operating free-air temperature range
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C 54AC16374 74AC16374
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
fclock Clock frequency 0 100 0 100 0 100 MHz
twPulse duration CLK high or low 5 5 5 ns
tsu Setup time, data before CLK↑5 5 5 ns
thHold time, data after CLK↑0 0 0 ns
switching characteristics over recommended operating free-air temperature range
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO TA = 25°C 54AC16374 74AC16374
UNIT
PARAMETER
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
UNIT
fmax 60 60 60 MHz
tPLH
CLK
Q
4.9 12.2 15 4.9 17 4.9 17
ns
tPHL
CLK
Q
4.8 11.9 14.3 4.8 15.7 4.8 15.7
ns
tPZH
OE
Q
4.3 11.9 14.7 4.3 16.8 4.3 16.8
ns
tPZL
OE
Q
5.3 15.5 18.7 5.3 21.2 5.3 21.2
ns
tPHZ
OE
Q
4 7.3 9 4 9.8 4 9.8
ns
tPLZ
OE
Q
3.8 7.1 8.8 3.8 9.4 3.8 9.4
ns
switching characteristics over recommended operating free-air temperature range
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO TA = 25°C 54AC16374 74AC16374
UNIT
PARAMETER
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
UNIT
fmax 100 100 100 MHz
tPLH
CLK
Q
3.8 7.6 9.5 3.8 10.8 3.8 10.8
ns
tPHL
CLK
Q
3.8 7.6 9.5 3.8 10.6 3.8 10.6
ns
tPZH
OE
Q
3.2 7.2 9 3.2 10.2 3.2 10.2
ns
tPZL
OE
Q
3.8 8.7 10.7 3.8 12.1 3.8 12.1
ns
tPHZ
OE
Q
3.7 6 7.5 3.7 8.2 3.7 8.2
ns
tPLZ
OE
Q
3.5 5.8 7.3 3.5 7.9 3.5 7.9
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cd
Power dissi
p
ation ca
p
acitance
p
er fli
p
flo
pOutputs enabled
CL=50
p
F
f=1MHz
49 p
F
C
pd
Po
w
er
dissipation
capacitance
per
flip
-
flop
Outputs disabled
C
L =
50
pF
,
f
=
1
MH
z32
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
54AC16374, 74AC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS123B – MARCH 1990 – REVISED APRIL 1996
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
50%
50%
50%
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
50% 50% VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2 × VCC
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
50%
50%
[
VCC
0 V
50% VCC 20% VCC
50% VCC 80% VCC
[
0 V
VCC
GND
Open
VOLTAGE WAVEFORMS
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
VCC
0 V
50% 50%
tw
VOLTAGE WAVEFORMS
Input
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
74AC16374DL ACTIVE SSOP DL 48 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74AC16374DLG4 ACTIVE SSOP DL 48 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74AC16374DLR ACTIVE SSOP DL 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74AC16374DLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Feb-2006
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
74AC16374DLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
74AC16374DLR SSOP DL 48 1000 346.0 346.0 49.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 2
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040048/E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
4828
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0°–ā8°
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
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