SCE5784 - Infineon Technologies - Datasheet.Directory



2001 OSRAM Opto Semiconductors Inc.• San Jose, CA

www.inﬁneon.com/opto • 408-456-4000

OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany

www.osram-os.com • +49-941-202-7178 1 August 1, 2001-18

FEATURES

• Eight 0.180" (4.57 mm) 5 x 7 Dot Matrix

Characters in Red, Yellow, High Efﬁciency Red,

Green, High Efﬁciency Green, Soft Orange, or

InGaAlP Red

• ROMless Serial Input, Dot Addressable Display

Ideal for User Deﬁned Characters

• Built-in Decoders, Multiplexers and LED Drivers

• Readable from 8 Feet (2.5 meters)

• Programmable Features:

– Clear Function

– Eight Dimming Levels

– Peak Current Select

– (12.5% or Full Peak Current)

– Prescaler Function

(External Oscillator Divided by 16 or 1)

– Internal or External Clock

DESCRIPTION

The SCE5780 (red), SCE5781 (yellow), SCE5782 (HER), SCE5783

(green), SCE5784 (HEG), SCE5785 (orange), and SCE5786 (InGaAlP

red) are eight digit, dot addressable 5x7 dot matrix, serial input, Intelli-

gent Display devices. The eight 0.180" (4.57 mm) high digits are pack-

aged in a rugged, high quality, optically transparent, plastic 26 pin DIP

with 0.3" pin spacing.

The on-board CMOS has a 280 bit RAM, one bit associated with one

LED, each to generate User Deﬁned Characters.

The SCE578X is designed to work with the serial port of most com-

mon microprocessors. Data is transferred into the display through the

Serial Data Input (DATA), clocked by the Serial Data Clock (SDCLK),

and enabled by the Load Input (LOAD).

1.690 (42.93)

Max.

.105 (2.68) .211

(5.36)

.100 (2.54)

.450 (11.43) Max.

.090 (2.29)

Pin 1

Identifier

Pin 1

.020 (0.51)

.210

(5.33)

.158 (4.01)

Typ.

.018 (0.46)

Typ.

.010

(0.25)

.300

(7.62)

.225

(5.71)

0 1 2 3

4 5 6 7 L

C

L

C

L

C

L

CPin 13

.400

(10.16) Pin 14

SCE578X

OSRAM YYWW Z

Date code Intensity code

Tolerance: ±0.010 inches (0.25 mm)

unless otherwise speciﬁed

.180

(4.57)

.100±.005 Typ .

(2.54±0.13)

(Tol. non accum.)

.012

(0.30)

Typ.

Dimensions in Inches (mm)

RED

SCE5780

YELLOW

SCE5781

HIGH EFFICIENCY RED

SCE5782

GREEN

SCE5783

HIGH EFFICIENCY GREEN

SCE5784

SOFT ORANGE

SCE5785

InGaAlP RED

SCE5786

0.180" 8-Character 5 x 7 Dot Matrix

Serial Input Dot Addressable Intelligent Display

®

Devices



2001 OSRAM Opto Semiconductors Inc.• San Jose, CA SCE5780/1/2/3/4/5/6

www.inﬁneon.com/opto • 408-456-4000

OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany

www.osram-os.com • +49-941-202-7178 2 August 1, 2001-18

DESCRIPTION (continued)

The Clock I/O (CLK I/O) and Clock Select (CLKSEL) pins offer

the user the capability to supply a high speed external multiplex

clock. This feature can minimize audio in-band interference for

portable communication equipment or eliminate the visual syn-

chronization effects found in high vibration environments such

as avionic equipment. The prescaler function allows for a higher

speed external multiplex clock when set to divide by 16.

Maximum Ratings

V

CC

, Logic Supply Voltage (non-operating) ....... –0.5 to +7.0 Vdc

V

LL

, LED Supply Voltage (non-operating)............ –0.5 to 5.5 Vdc

Input Voltage Levels Relative

to Ground............................................... –0.5 to

V

CC

+0.5 Vdc

Operating Temperature

(1)

................................. –40

°

C to +85

°

C

Storage Temperature....................................... –40

°

C to +100

°

C

Maximum Solder Temperature 0.063"

below Seating Plane, t<5 s............................................260

°

C

Relative Humidity at 85

°

C ...................................................85%

Maximum Power Dissipation

70

°

C ...............................................................................1.7 W

85

°

C .............................................................................1.25 W

ESD (100 pF, 1.5 k

Ω

) ........................................................ 2.0 kV

Maximum Input Current ...............................................±100 mA

Note:

1)

For operation at high temperature, see Thermal Considerations.

Switching Speciﬁcations

(over operating temperature range and

V

CC

=4.5 V to 5.5 V)

Note:

T

SDCW

is the minimum time the SDCLK may be low or high.

The SDCLK period must be a minimum of 200 ns.

Symbol Description Min. Units

T

RC

Reset Active Time 600 ns

T

LDS

Load Setup Time 50 ns

T

DS

Data Setup Time 50 ns

T

SDCLK

Clock Period 200 ns

T

SDCW

Clock Width 70 ns

T

LDH

Load Hold Time 0 ns

T

DH

Data Hold Time 25 ns

T

WR

Total Write Time 2.2

µ

s

T

BL

Time Between Loads 600 ns



2001 OSRAM Opto Semiconductors Inc.• San Jose, CA SCE5780/1/2/3/4/5/6

www.inﬁneon.com/opto • 408-456-4000

OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany

www.osram-os.com • +49-941-202-7178 3 August 1, 2001-18

Figure 1. Timing Diagram—Data Write Cycle

Figure 2. Timing Diagram—Instruction Cycle

SDCLK

T

SDCW

T

DATA

LOAD

D0

DS

T

LDS

T

TDH

D7

LDH

T

LOAD

DATA

SDCLK

D0 D1 D2 D3 D4 D5 D6 D7

D0

BL

T

WR

T

OR



2001 OSRAM Opto Semiconductors Inc.• San Jose, CA SCE5780/1/2/3/4/5/6

www.inﬁneon.com/opto • 408-456-4000

OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany

www.osram-os.com • +49-941-202-7178 4 August 1, 2001-18

Electrical Characteristics

(over operating temperature)

Notes:

1)

Peak current=1.87 x

I

LL

x

I

LL

varies with

V

LL

Normalized curve, Figure 12.

2)

Unused inputs must be tied high.

3)

Mux rate=[OSC Frequency/(64 x 7)].

4)

External oscillator must be stopped during power down mode for minimum current.

Input/Output Circuits

Figures 3 and 4 show the input and output resistor/diode

networks used for ESD protection and to eliminate substrate

latch-up caused by input voltage over/under shoot.

Figure 3. Inputs Figure 4. Clock I/O

Optical Characteristics at 25

°

C

(

V

LL

=

V

CC

=5.0 V at 100% brightness level, viewing angle: X

axis ±55

°

, Y axis ±65

°

)

Parameter Min. Typ. Max. Units Conditions

V

CC

4.5 5.0 5.5 V —

V

LL

3.0 — 5.5 V —

I

CC

(PWR DWN)

(4)

— — 100

µ

A

V

CC

=

V

LL

=5.0 V, all inputs=0 V or

V

CC

I

LL

(PWR DWN)

(4)

——50

µ

A—

I

CC

— — 2.0 mA

V

CC

=5.0 V

I

LL

(20 dots/char)

(1)(2)

— 240 345 mA

V

CC

=

V

LL

=5.0 V, “#” displayed in 8 digits,

brightness=100%,

I

P

=100% at 25

°

C

I

IL

— — –10

µ

A

V

CC

=5.0 V, all inputs=0 V

I

IH

——10

µ

A

V

CC

=

V

IN

=5.0 V (all inputs)

V

IH

3.5 — — V

V

CC

=4.5 V to 5.5 V

V

IL

— — 1.5 V

V

CC

=4.5 V to 5.5 V

I

OH

(CLK I/O) — –8.9 — mA

V

CC

=4.5 V,

V

OH

=2.4 V

IOL (CLK I/O) — 1.6 — mA VCC=4.5 V, VOH=0.4 V

θJC-pin —34—°C/W —

Internal OSC Frequency 120 — 347 kHz VCC=5.0 V, CLKSEL=1, Prescale=÷1

External OSC Frequency 120 — 347 kHz VCC=5.0 V, CLKSEL=0, Prescale=÷1

External OSC Frequency with

Prescale

1.92 — 5.55 MHz VCC=5.0 V, CLKSEL=0, Prescale=÷16

Mux Frequency(3) 375 768 1086 Hz —

VCC

1 kΩ

GND

input

VCC

1 kΩ

GND

input/output

 2001 OSRAM Opto Semiconductors Inc.• San Jose, CA SCE5780/1/2/3/4/5/6

www.inﬁneon.com/opto • 408-456-4000

OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany

www.osram-os.com • +49-941-202-7178 5 August 1, 2001-18

Red SCE5780

Yellow SCE5781

High Efﬁciency Red SCE5782

Green SCE5783

High Efﬁciency Green SCE5784

Soft Orange SCE5785

InGaAlP Red SCE5786

Notes:

1. Dot to dot intensity matching at 100% brightness is 1.8:1.

2. Display are binned for hue at 2.0 nm intervals for yellow, green, and high efﬁciency green.

3. Displays within a given intensity category have an intensity matching of 1.5:1 (max.)

Description Symbol Min. Typ. Units

Luminous Intensity IV37.5 90.0 µcd/dot

Peak Wavelength λpeak —660 nm

Dominant Wavelength λdom —639 nm

Description Symbol Min. Typ. Units

Luminous Intensity IV75 110 µcd/dot

Peak Wavelength λpeak —585 nm

Dominant Wavelength λdom —583 nm

Description Symbol Min. Typ. Units

Luminous Intensity IV75 190 µcd/dot

Peak Wavelength λpeak —630 nm

Dominant Wavelength λdom —626 nm

Description Symbol Min. Typ. Units

Luminous Intensity IV75 150 µcd/dot

Peak Wavelength λpeak —565 nm

Dominant Wavelength λdom —570 nm

Description Symbol Min. Typ. Units

Luminous Intensity IV120 215 µcd/dot

Peak Wavelength λpeak —568 nm

Dominant Wavelength λdom —574 nm

Description Symbol Min. Typ. Units

Luminous Intensity IV120 150 µcd/dot

Peak Wavelength λpeak —610 nm

Dominant Wavelength λdom —605 nm

Description Symbol Min. Typ. Units

Luminous Intensity IV375 950 µcd/dot

Peak Wavelength λpeak —645 nm

Dominant Wavelength λdom —632 nm

 2001 OSRAM Opto Semiconductors Inc.• San Jose, CA SCE5780/1/2/3/4/5/6

www.inﬁneon.com/opto • 408-456-4000

OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany

www.osram-os.com • +49-941-202-7178 6 August 1, 2001-18

Figure 5. Top View

Pin Assignment

Figure 6. Dot Matrix Format

Pin Deﬁnitions

Display Column and Row Format

Pin Function Pin Function

1 CLKSEL 14 Serial Data

2VCC (Logic) 15 No connect

3VLL (LED) 16 Serial CLK

4 No pin 17 No pin

5 No pin 18 No pin

6 No pin 19 No pin

7 No pin 20 No pin

8 No pin 21 No pin

9 No pin 22 No pin

10 No pin 23 No pin

11 Load 24 Reset

12 GND 25 CLK I/O

13 GND 26 No connect

0 1 2 3

4 5 6 7

0.100

(2.54)

0.028

(.72)

typ.

0.022

(.57) typ.

0.180

(4.57)

R1

C0 C1 C2 C3 C4R0

R2

R3

R4

R5

R6

Pin Function Deﬁnitions

1 CLKSEL H=internal clock, L=external clock

2VCC (Logic) Logic power supply

3VLL (LED) LED power supply

4–10 No pin No pins in these positions

11 Load Low input enables data clocking

into the 8-bit serial shift register.

When Load goes high, the con-

tents of the 8-bit serial shift regis-

ter will be decoded.

12,13 GND Power supply ground

14 Serial Data Serial data input

15 No connect Pin has no function

16 Serial CLK For loading data into the 8-bit

serial register on a low to high

transition

17–23 No pin No pins in these positions

24 Reset Asynchronous input, when low

will clear the Multiplex Counter,

User RAM, and Data Register.

Control Word Register is set to

100% brightness, maximum peak

current, and oscillator divided by

1. The display blanked.

25 CLK I/O Outputs master clock or input

external clock for display multi-

plexing.

26 No connect Pin has no function

C0 C1 C2 C3 C4

Row 0 11111

Row 1 00100

Row 2 00100

Row 3 00100

Row 4 00100

Row 5 00100

Row 6 00100

1=Display dot “On”

0=Display dot “Off”

 2001 OSRAM Opto Semiconductors Inc.• San Jose, CA SCE5780/1/2/3/4/5/6

www.inﬁneon.com/opto • 408-456-4000

OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany

www.osram-os.com • +49-941-202-7178 7 August 1, 2001-18

Column Data Ranges

Figure 7. Block Diagram

Operation of the SCE578X

The SCE578X display consists of two CMOS ICs containing

control logic and drivers for eight 5 x 7 characters. The ﬁrst IC

controls characters 0 through 3 and the second IC controls

characters 4 through 7. These components are assembled in

a compact plastic package.

Individual LED dot addressability allows the user great free-

dom in creating special characters or mini-icons.

The serial data interface provides a highly efﬁcient intercon-

nection between the display and the mother board. The

SCE578X requires a minimum three input lines as compared

to fourteen for an equivalent eight character parallel input part.

The on-board CMOS IC is the electronic heart of the display.

Each IC accepts serially formatted data, which is stored in the

internal RAM. The IC accepts data based on the character

address selected. The ﬁrst IC is selected when addressing

characters 0 through 3, the second IC is selected when

addressing characters 4 though 7, and both ICs are selected

when the Control Word is addressed.

Asynchronously the RAM is read by the character multiplexer

at a strobe rate that results in a ﬂicker free display. Figure 7

shows the three functional areas of the IC. These include:

the input serial data register and control logic, a 140 bit two

port RAM, and an internal multiplexer/display driver. The sec-

ond IC is identical except characters 4 though 7 are driven.

The following explains how to format the serial data to be

loaded into the display. The user supplies a string of bit

mapped decoded characters. The contents of this string is

shown in Figure 8a. Figure 8b shows that each character con-

sist of eight 8 bit words. The ﬁrst word encodes the display

Row 0 00H to 1FH

Row 1 00H to 1FH

Row 2 00H to 1FH

Row 3 00H to 1FH

Row 4 00H to 1FH

Row 5 00H to 1FH

Row 6 00H to 1FH

SD CLK

SData

Load

Serial Data

Register

Reset

CLKSEL

CLK I/O Counter Chain

& Timing Logic

Oscillator

Y Address Decode

Display Multiplexer

Row Decoder

& Driver

0123 4567

140 Bit RAM

Write 28 X 5

Read 7 X 20

IC 1

IC 2

4 – 5 X 7

Characters

4 – 5 X 7

Characters

Column

Drivers

Digits

0 To 3

X Address Decode

3 Bit Address

Register

6 Bit Control

Word Register

Control Word Logic

VDIM Controls

MUX

Rate

The second IC has the same

function diagram as IC 1

IC 2 controls characters 4 To 7

 2001 OSRAM Opto Semiconductors Inc.• San Jose, CA SCE5780/1/2/3/4/5/6

www.inﬁneon.com/opto • 408-456-4000

OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany

www.osram-os.com • +49-941-202-7178 8 August 1, 2001-18

character location and the succeeding seven bytes are row data.

The row data represents the status (On, Off) of individual col-

umn LEDs. Figure 8c shows that each 8 bit word is formatted to

represent Character Address, or Column Data.

Figure 8d shows the sequence for loading the bytes of data.

Bringing the LOAD line low enables the serial register to accept

data. The shift action occurs on the low to high transition of the

serial data clock (SDCLK). The least signiﬁcant bit (D0) is loaded

ﬁrst. After eight clock pulses the LOAD line is brought high.

With this transition the OPCODE is decoded. The decoded

OPCODE directs D4–D0 to be latched in the Character Address

register, stored in the RAM as Column data, or latched in the

Control Word register. The control IC requires a minimum 600

ns delay between successive byte loads. As indicated in Figure

8a, a total of 512 bits of data are required to load all eight char-

acters into the display.

The Character Address Register selects the character address

that the row and column data will be written to. See Table 2 for

opcode and character addressing. After loading the Character

Address Register, the next seven bytes load the column data,

one row at a time, starting with row 0 (top row) and ending with

row 6 (bottom row). Each character address has a 7 x 5 bit User

RAM formatted as seven rows, each containing ﬁve column

data bits. The three most signiﬁcant bits, D7–D5 represent the

opcode for the row data and the least signiﬁcant ﬁve bits, D4–

D0 represent the column data. See Table 3 for the column data

format. If an address is loaded before all seven rows are written,

the next column data will be loaded into Row 0 of the new

address. The remaining rows of the old address are not changed.

Table 1 shows the Row Address for the example character,

“D.” Column data is written and read asynchronously from the

280 bit RAM. Once loaded, the internal oscillator and character

multiplexer reads the data from the RAM. These characters are

row strobed with column data as shown in Figures 9 and 10.

The character strobe rate is determined by the internal or user

supplied external MUX Clock and the ICs÷ 320 counter.

Table 1. Character “D”

Figure 8. Loading Serial Character Data

Op code

D 7 D 6 D 5

Column Data

D4 D3 D2 D1 D0

C0 C1 C2 C3 C4

Hex

Row 0 0 0 0 1 1 1 1 0 1E

Row 1 0 0 0 1 0 0 0 1 11

Row 2 0 0 0 1 0 0 0 1 11

Row 3 0 0 0 1 0 0 0 1 11

Row 4 0 0 0 1 0 0 0 1 11

Row 5 0 0 0 1 0 0 0 1 11

Row 6 0 0 0 1 1 1 1 0 1E

Character 0 Character 1 Character 2 Character 3 Character 4 Character 5 Character 6 Character 7

Example: Serial Clock=5.0 MHz, Clock Period=200 ns

Time between LOADS

LOAD

Serial

Clock

DATA

Clock

Period

t0

D0 D1 D2 D3 D4 D5 D6 D7

11 Clock Cycles, 2.2 µs

Time

Between

Loads

600 ns(min)

Character Address OPCODEOPCODE Column Data

D0

D D1

D D2

D D3

D D4

D

11 Clock Cycles, 2.2 µs

Character 0

Address Row 0 Column

Data

88 Clock Cycles, 17.6 µs

704 Clock Cycles, 140.8 µs

Row 1 Column

Data Row 2 Column

Data Row 3 Column

Data Row 4 Column

Data

D0

0 D1

0 D2

0 D3

0 D4

0 D5

1 D6

0 D7

1

a.

b.

c.

d.

Row 5 Column

Data Row 6 Column

Data

D5

0D6

0 D7

0

Time

Between

Loads

600 ns(min)

OPCODE

 2001 OSRAM Opto Semiconductors Inc.• San Jose, CA SCE5780/1/2/3/4/5/6

www.inﬁneon.com/opto • 408-456-4000

OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany

www.osram-os.com • +49-941-202-7178 9 August 1, 2001-18

Table 2. Load Character Address

Table 3. Load Column Data

The user can activate four Control functions. These include:

LED Brightness Level, IC Power Down, Prescaler, or Display

Clear. OPCODEs and six bit words are used to initiate these

functions. The OPCODEs and Control Words for the Character

Address and Loading Column Data are shown in Tables 2 and 3.

The user can select eight speciﬁc LED brightness levels, Tables

4 and 5. Depending on how D3 is selected either one (1) for

maximum peak current or zero (0) for 12.5% of maximum peak

current in the control word per Table 4 and 5, the user can

select 16 speciﬁc LED brightness levels. These brightness lev-

els (in percentages of full brightness of the display) depending

on how the user selects D3 can be one (1) or zero (0) are as fol-

lows: 100% (E0HEX or E8HEX), 53% (E1HEX or E9HEX), 40%

(E2HEX or EAHEX), 27% (E3HEX or EBHEX), 20% (E4HEX or

ECHEX), 13% (E5HEX or EDHEX), and 6.6% (E6HEX or EEHEX),

0.0% (E7HEX or EFHEX). The brightness levels are controlled by

changing the duty factor of the row strobe pulse.

The SCE578X offers a unique Display Power Down feature

which reduces ICC to less than 150 µA total. When EFHEX is

loaded (Table 6) the display is set to 0% brightness. When in

the Power Down mode data may still be written into the RAM.

The display is reactivated by loading a new brightness Level

Control Word into the display.

Table 4. Display Brightness

Table 5. Display Brightness

Table 6. Power Down

Figure 9. Row and Column Locations for a Character “D”

Op code

D 7 D 6 D 5

Character Address

D4 D3 D2 D1 D0

Hex Operation

Load

1 0 1 0 0 0 0 0 A0 Character 0

1 0 1 0 0 0 0 1 A1 Character 1

1 0 1 0 0 0 1 0 A2 Character 2

1 0 1 0 0 0 1 1 A3 Character 3

1 0 1 0 0 1 0 0 A4 Character 4

1 0 1 0 0 1 0 1 A5 Character 5

1 0 1 0 0 1 1 0 A6 Character 6

1 0 1 0 0 1 1 1 A7 Character 7

Op code

D 7 D 6 D 5

Column Data

D4 D3 D2 D1 D0

Operation Load

0 0 0 C0 C1 C2 C3 C4 Row 0

0 0 0 C0 C1 C2 C3 C4 Row 1

0 0 0 C0 C1 C2 C3 C4 Row 2

0 0 0 C0 C1 C2 C3 C4 Row 3

0 0 0 C0 C1 C2 C3 C4 Row 4

0 0 0 C0 C1 C2 C3 C4 Row 5

0 0 0 C0 C1 C2 C3 C4 Row 6

Op code

D7 D6 D5

Control Word

D4 D3 D2 D1 D0

Hex Operation

Level

1 1 1 0 0 0 0 0 E0 100%

111 00001 E1 53%

111 00010 E2 40%

111 00011 E3 27%

111 00100 E4 20%

111 00101 E5 13%

1 1 1 0 0 1 1 0 E6 6.6%

1 1 1 0 0 1 1 1 E7 0.0%

Op code

D7 D6 D5

Control Word

D4 D3 D2 D1 D0

Hex Operation

Level

1 1 1 0 1 0 0 0 E8 100%

111 01001 E9 53%

111 01010 EA 40%

111 01011 EB 27%

111 01100 EC 20%

111 01101 ED 13%

1 1 1 0 1 1 1 0 EE 6.6%

1 1 1 0 1 1 1 1 EF 0.0%

Op code

D7 D6 D5

Control Word

D4 D3 D2 D1 D0

Hex Operation

Level

111 01111 EF 0%

brightness

off LED

on LED

Row 0

Row 1

Row 2

Row 3

Row 4

Row 5

Row 6

Previously “on” LED

0 1 2 3 4

Columns

 2001 OSRAM Opto Semiconductors Inc.• San Jose, CA SCE5780/1/2/3/4/5/6

www.inﬁneon.com/opto • 408-456-4000

OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany

www.osram-os.com • +49-941-202-7178 10 August 1, 2001-18

Figure 10. Row Strobing

The SCE578X allows a high frequency external oscillator

source to drive the display. Data bit, D4, in the control word

format controls the prescaler function. The prescaler allows

the oscillator source to be divided by 16 by setting D4=1.

However, the prescaler should not be used, i.e., when using

the internal oscillator source.

The Software Clear (C0HEX), given in Table 7, clears the

Address Register and the RAM. The display is blanked and the

Character Address Register will be set to Character 0. The

internal counter and the Control Word Register are unaffected.

The Software Clear will remain active until the next data input

cycle is initiated.

Table 7. Software Clear

Multiplexer and Display Driver

The eight characters are row multiplexed with RAM resident

column data. The strobe rate is established by the internal or

external MUX Clock rate. The MUX Clock frequency is divided

by a 320 counter chain. This results in a typical strobe rate of

768 Hz. By pulling the Clock SEL line low, the display can be

operated from an external MUX Clock. The external clock is

attached to the CLK I/O connection.

An asynchronous hardware Reset (pin 24) is also provided.

Bringing this pin low will clear the Character Address Register,

Control Word Register, RAM, and blanks the display. This

action leaves the display set at Character Address 0, and the

Brightness Level set at 100%, prescaler ÷1.

Electrical and Mechanical Considerations

Thermal Considerations

The display’s power usage may need to be reduced to operate

at high ambient temperatures. The power may be reduced by

lowering the brightness level, reducing the total number of

LEDs illuminated, or lowering VLED. The VCC supply, relative to

the VLED supply, has little effect on the power dissipation of

the display and is not considered when determining the

power dissipation.

To determine the power deration with a given ambient temper-

ature, use the following formula:

where: Tjmax=maximum IC junction temperature

PD=power dissipated by the ICs

θja=thermal resistance, junction to ambient

To determine the power dissipation of the display, use the fol-

lowing formula:

where: N=number of LEDs on

ILL/140=average current for a single LED

RB=relative brightness level

A typical thermal resistance value (qja) for this display is

50°C/W when mounted in a socket soldered on a 0.062" thick

PCB with 0.020", 1 ounce copper traces and the display cov-

ered by a plastic ﬁlter. The display’s maximum IC junction tem-

perature is 125°C. Power Deration Curve is based on these

typical values.

Figure 11. Power Deration Curve (θja=50°C/W)

VCC and VLL are two separate power supplies sharing a com-

mon ground. VCC supplies power for all the display logic. VLL

supplies the power for the LEDs. By separating the two sup-

plies, VCC and VLL can be varied independently and keeps the

logic supply clean.

VLL can be varied between 3.0 volts and 5.5 volts. The LED

drive current will vary with changes in VLL. See Figure 12 for

ILL variance.

Row 0

Row 1

Row 2

Row 3

Row 4

Row 5

Row 6 0 1 2 3 4

Columns

Row 0

Row 1

Row 2

Row 3

Row 4

Row 5

Row 6 0 1 2 3 4

Columns

Row 0

Row 1

Row 2

Row 3

Row 4

Row 5

Row 6 0 1 2 3 4

Columns

Row 0

Row 1

Row 2

Row 3

Row 4

Row 5

Row 6 0 1 2 3 4

Columns

Row 0

Row 1

Row 2

Row 3

Row 4

Row 5

Row 6 0 1 2 3 4

Columns

ROW LOAD LOAD ROW 0 LOAD ROW 1 LOAD ROW 2 LOAD ROW 3 LOAD ROW 4 LOAD ROW 5 LOAD ROW 6

Row 0

Row 1

Row 2

Row 3

Row 4

Row 5

Row 6 0 1 2 3 4

Columns

Row 0

Row 1

Row 2

Row 3

Row 4

Row 5

Row 6 0 1 2 3 4

Columns

Op code

D7 D6

Control Word

D5 D4 D3 D2 D1 D0

Hex Operation

11 000000 C0 CLEAR

Tjmax TAPDθja

⋅+=

PD N ILL 140 RB⋅⁄⋅=

Temperature

Watts

0.0

0.5

1.0

1.5

2.0

2.5

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100

 2001 OSRAM Opto Semiconductors Inc.• San Jose, CA SCE5780/1/2/3/4/5/6

www.inﬁneon.com/opto • 408-456-4000

OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany

www.osram-os.com • +49-941-202-7178 11 August 1, 2001-18

Figure 12. ILL Variance

VCC can vary between 4.5 volts and 5.5 volts. Operation below

4.5 volts will change the timing and switching levels of the

inputs.

Interconnect Considerations

Optimum product performance can be had when the following

electrical and mechanical recommendations are adopted. The

SCE578X’s IC is constructed in a high speed CMOS process;

consequently high speed noise on the SERIAL DATA, SERIAL

DATA CLOCK, LOAD and RESET lines may cause incorrect data

to be written into the serial shift register. Adhere to transmis-

sion line termination procedures when using fast line drivers

and long cables (>10 cm).

Good ground and power supply decoupling will insure that ICC

(<800 mA peak) switching currents do not generate localized

ground bounce. Therefore it is recommended that each display

package use a 0.1 µF and 20 µF tantulum capacitor between

VCC and ground.

When the internal MUX Clock is being used connect the

CLKSEL pin to VCC. In those applications where RESET will not

be connected to the system’s reset control, it is recommended

that this pin be connected to the center node of a series 0.1 µF

and 100 kΩ RC network. Thus upon initial power up the RESET

will be held low for 10 ms allowing adequate time for the sys-

tem power supply to stabilize.

ESD Protection

The input protection structure of the SCE578X provides signiﬁ-

cant protection against ESD damage. It is capable of withstand-

ing discharges greater than 2.0 kV. Take all the standard

precautions, normal for CMOS components. These include

properly grounding personnel, tools, tables, and transport carri-

ers that come in contact with unshielded parts. If these condi-

tions are not, or cannot be met, keep the leads of the device

shorted together or the parts in antistatic packaging.

Soldering Considerations

The SCE578X can be hand soldered with SN63 solder using a

grounded iron set to 260°C.

Wave soldering is also possible following these conditions: Pre-

heat that does not exceed 93°C on the solder side of the PC

board or a package surface temperature of 85°C. Water soluble

organic acid ﬂux (except carboxylic acid) or resin-based RMA

ﬂux without alcohol can be used.

Wave temperature of 245°C ±5°C with a dwell between 1.5

sec. to 3.0 sec. Exposure to the wave should not exceed

temperatures above 260°C for ﬁve seconds at 0.063" below

the seating plane. The packages should not be immersed in

the wave.

Post Solder Cleaning Procedures

The least offensive cleaning solution is hot D.I. water (60°C) for

less than 15 minutes. Addition of mild saponiﬁers is acceptable.

Do not use commercial dishwasher detergents.

For faster cleaning, solvents may be used. Exercise care in

choosing solvents as some may chemically attack the nylon

package. For further information refer to Appnotes 18 and 19.

An alternative to soldering and cleaning the display modules is

to use sockets. Naturally, 14 pin DIP sockets .300" wide with

.100" centers work well for single displays. Multiple display

assemblies are best handled by longer SIP sockets or DIP sock-

ets when available for uniform package alignment. Socket man-

ufacturers are Aries Electronics, Inc., Frenchtown, NJ; Garry

Manufacturing, New Brunswick, NJ; Robinson-Nugent, New

Albany, IN; and Samtec Electronic Hardward, New Albany, IN.

For further information refer to Appnote 22.

Optical Considerations

The 0.180" high character of the SCE578X gives readability up

to ﬁve feet. Proper ﬁlter selection enhances readability over

this distance.

Using ﬁlters emphasizes the contrast ratio between a lit LED

and the character background. This will increase the discrimina-

tion of different characters. The only limitation is cost. Take into

consideration the ambient lighting environment for the best

cost/beneﬁt ratio for ﬁlters.

Incandescent (with almost no green) or ﬂuorescent (with

almost no red) lights do not have the ﬂat spectral response of

sunlight. Plastic band-pass ﬁlters are an inexpensive and effec-

tive way to strengthen contrast ratios. The SCE5780 is a red

display and should be used with long wavelength pass ﬁlter

having a sharp cut-off in the 600 nm to 620 nm range. The

SCE5782 is a high efﬁciency red display and should be used

with long wavelength pass ﬁlter having a sharp cut-off in the

570 nm to 600 nm range. The SCE5784 is a high efﬁciency

green display and should be used with long wavelength pass

ﬁlter that peaks at 565 nm. The SCE5785 is a soft orange dis-

play and should be used with long wavelength pass ﬁlter that

peaks at 610 nm. The SCE5786 is an InGaAlP red display and

should be used with long wavelength pass ﬁlter that peaks at

645 nm.

VLL

ILL

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50

 2001 OSRAM Opto Semiconductors Inc.• San Jose, CA SCE5780/1/2/3/4/5/6

www.inﬁneon.com/opto • 408-456-4000

OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany

www.osram-os.com • +49-941-202-7178 12 August 1, 2001-18

Additional contrast enhancement is gained by shading the dis-

plays. Plastic band-pass ﬁlters with built-in louvers offer the

next step up in contrast improvement. Plastic ﬁlters can be

improved further with anti-reﬂective coatings to reduce glare.

The trade-off is fuzzy characters. Mounting the ﬁlters close to

the display reduces this effect. Take care not to overheat the

plastic ﬁlter by allowing for proper air ﬂow.

Optimal ﬁlter enhancements are gained by using circular

polarized, anti-reﬂective, band-pass ﬁlters. The circular polariz-

ing further enhances contrast by reducing the light that travels

through the ﬁlter and reﬂects back off the display to less than

1.0%.

Several ﬁlter manufacturers supply quality ﬁlter materials.

Some of them are: Panelgraphic Corporation, W. Caldwell, NJ;

SGL Homalite, Wilmington, DE; 3M Company, Visual Products

Division, St. Paul, MN; Polaroid Corporation, St. Paul, MN;

Polaroid Corporation, Polarizer Division, Cambridge, MA; Marks

Polarized Corporation, Deer Park, NY, Hoya Optics, Inc., Fre-

mont, CA.

One last note on mounting ﬁlters: recessing displays and

bezel assemblies is an inexpensive way to provide a shading

effect in overhead lighting situations. Several Bezel manufac-

turers are: R.M.F. Products, Batavia, IL; Nobex Components,

Grifﬁth Plastic Corp., Burlingame, CA; Photo Chemical Prod-

ucts of California, Santa Monica, CA; I.E.E.-Atlas, Van Nuys,

CA.

Microprocessor Interface

The microprocessor interface is through the serial port, SPI port

or one out of eight data bits on the eight bit parallel port and

also control lines SDCLK and LOAD.

Power Up Sequence

Upon power up display will come on at random. Thus the dis-

play should be reset at power-up. The reset will set the

Address Register to Digit 0, User RAM is set to 0 (display

blank) the Control Word is set to 0 (100% brightness) and the

internal counters are reset.

Loading Data into the Display

Use following procedure to load data into the display:

1. Power up the display.

2. Bring RST low (600 ns duration minimum) to clear the Multi-

plex Counter, Address Register, Control Word Register, User

Ram and Data Register. The display will be blank. Display

brightness is set to 100%.

3. If a different brightness is desired, load the proper bright-

ness opcode into the Control Word Register.

4. Load the Digit Address into the display.

5. Load display row and column data for the selected digit.

6. Repeat steps 4 and 5 for all digits.

Data Contents for the Word “ABCDEFGH”

Step D7 D6 D5 D4 D3 D2 D1 D0 Function

A

B

1 1 0

1 1 1

00 0 0 0

CLEAR

100% BRIGHTNESS

1

2

3

4

5

6

7

8

1 0 1

00 0

0 0 0

00 0 0 0

00100

01 0 1 0

10 0 0 1

11 1 1 1

10001

10 0 0 1

DIGIT D0 SELECT

ROW 0 (A)

ROW 1 (A)

ROW 2 (A)

ROW 3 (A)

ROW 4 (A)

ROW 5 (A)

ROW 6 (A)

9

10

11

12

13

14

15

16

10 1

00 0

0 0 0

00001

11111

10001

10 0 0 1

1 1 1 1 0

10 0 0 1

11 1 1 1

DIGIT D1 SELECT

ROW 0 (B)

ROW 1 (B)

ROW 2 (B)

ROW 3 (B)

ROW 4 (B)

ROW 5 (B)

ROW 6 (B)

17

18

19

20

21

22

23

24

1 0 1

0 0 0

00 0 1 0

00111

01000

10 0 0 0

10000

01 0 0 0

00 1 1 1

DIGIT D2 SELECT

ROW 0 (C)

ROW 1 (C)

ROW 2 (C)

ROW 3 (C)

ROW 4 (C)

ROW 5 (C)

ROW 6 (C)

25

26

27

28

29

30

31

32

1 0 1

0 0 0

00011

11 1 1 0

10 0 0 1

10001

10 0 0 1

10001

11110

DIGIT D3 SELECT

ROW 0 (D)

ROW 1 (D)

ROW 2 (D)

ROW 3 (D)

ROW 4 (D)

ROW 5 (D)

ROW 6 (D)

33

34

35

36

37

38

39

40

1 0 1

0 0 0

00100

11 1 1 1

10 0 0 0

10000

11 1 1 0

10 0 0 0

10000

11111

DIGIT D4 SELECT

ROW 0 (E)

ROW 1 (E)

ROW 2 (E)

ROW 3 (E)

ROW 4 (E)

ROW 5 (E)

ROW 6 (E)

41

42

43

44

45

46

47

48

1 0 1

0 0 0

00101

11 1 1 1

10 0 0 0

10000

11 1 1 0

10 0 0 0

10000

DIGIT D5 SELECT

ROW 0 (F)

ROW 1 (F)

ROW 2 (F)

ROW 3 (F)

ROW 4 (F)

ROW 5 (F)

ROW 6 (F)

49

50

51

52

53

54

55

56

1 0 1

0 0 0

00110

01 1 1 0

10 0 0 1

10000

10 0 0 0

10 0 1 1

10001

01110

DIGIT D6 SELECT

ROW 0 (G)

ROW 1 (G)

ROW 2 (G)

ROW 3 (G)

ROW 4 (G)

ROW 5 (G)

ROW 6 (G)

57

58

59

60

61

62

63

1 0 1

0 0 0

00111

10 0 0 1

10001

11 1 1 1

10 0 0 1

10001

DIGIT D7 SELECT

ROW 0 (H)

ROW 1 (H)

ROW 2 (H)

ROW 3 (H)

ROW 4 (H)

ROW 5 (H)

ROW 6 (H)

 2001 OSRAM Opto Semiconductors Inc.• San Jose, CA SCE5780/1/2/3/4/5/6

www.inﬁneon.com/opto • 408-456-4000

OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany

www.osram-os.com • +49-941-202-7178 13 August 1, 2001-18

Figure 13. Display Interface to Siemens/Intel 8031

Microprocessor (using serial port in mode 0)

Figure 14. Display Interface to Siemens/Intel 8031

Microprocessor (using one bit of parallel port as serial port)

Figure 15. Display Interface with Motorola 68HC05C4

Microprocessor (using SPI port)

Figure 16. Cascading Multiple Displays

VCC

U1

8031

9RST

18

19

XTAL2

XTAL1

40

RXD

TXD

10

11

22 µf

TAN

.01 µf

P3.7 17

P3.3 13

P3.4 14

GND

DATA

VCC

CLKSEL

CLK I/O

SDCLK

LD

RST

GND

ID +

VCC

U1

8031

1

9

20

RST

P1.0

18

19

XTAL2

XTAL1

40 P3.0

P3.1

P3.6

P0.0

10

11

16

39

VCC

22 µF

TAN

.01 µF

GND

DATA

VCC

CLKSEL

CLK I/O

SDCLK

LD

RST

GND

ID +

VCC

VCC U1

68HC05C4

1

9

20

RST

PA2

38

39

OSC1

OSC2

40 PA0

PA1

SCLK

MOSI

11

10

33

32

VCC

22 µF

TAN

.01 µF

GND

DATA

VCC

CS

CLK I/O

SDCLK

LD

RST

GND

ID +

DATA SDCLK LOAD

14 more displays

in between

RST CLK I/O CLK SELRST CLK I/O CLK SEL

DATA SDCLK LOAD

Address

Decoder

Chip

0

15

Address Decode 1–14

V

CC

RST

DATA

SDCLK

A0

A1

A2

A3

LD

Intelligent Display Intelligent Display

CE

Multiple displays can be cascaded using the CLKSEL

and CLK I/O pins (Figure 16). The display designated as

the MasterClock source should have its CLKSEL pin tied

high and the slaves should have their CLKSEL pins tied

low. All CLK I/O pins should be tied together. One dis-

play CLK I/O can drive 15 slave CLK I/Os. Use RST to

synchronize all display counters.

 2001 OSRAM Opto Semiconductors Inc.• San Jose, CA SCE5780/1/2/3/4/5/6

www.inﬁneon.com/opto • 408-456-4000

OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany

www.osram-os.com • +49-941-202-7178 14 August 1, 2001-18

Figure 17. Character Set

0E

11

1F

11

1E

11

1E

11

1E

0E

11

10

11

0E

1E

11

1E

01

11

0E

11

12

14

18

14

12

11

10

1F

11

1B

15

11

1F

10

1E

10

1F

10

1E

10

0E

11

10

13

11

0E

11

19

15

13

11

0E

11

0E

1E

11

1E

10

11

1F

11

07

04

07

0E

11

15

12

0D

1E

11

1E

14

12

11

0E

11

10

0E

01

11

0E

1F

04

11

0E

11

0A

04

00

0E

12

0D

10

16

19

11

1E

00

0E

10

11

0E

01

0D

13

11

0F

02

00

06

02

12

0C

10

12

14

18

14

12

0C

04

0E

00

0A

15

11

15

1B

11

0A

04

0A

11

0A

04

1F

01

02

04

08

10

1F

00

0E

11

1E

10

0E

04

0A

08

1C

08

00

0F

11

0F

01

06

10

16

19

11

00

16

19

11

00

0E

11

0E

00

1E

11

19

16

10

00

0F

11

13

0D

01

00

04

00

0C

04

0E

00

0B

0C

08

00

0E

10

0E

01

1E

08

1C

08

0A

04

00

11

13

0D

00

11

0A

04

00

11

15

0A

00

11

0A

04

0A

11

00

11

0A

04

08

00

1F

02

04

08

1F

02

06

0E

1E

0E

06

02

04

00

04

08

11

0E

1F

00

11

0A

04

0A

11

1F

00

11

19

15

13

11

1F

00

16

19

11

00

01

0E

14

04

00

04

0E

15

0E

04

0E

11

0A

1B

04

00

0E

11

1F

11

04

00

0E

12

0D

00

04

00

04

0A

00

0A

1F

0A

1F

0A

04

0F

14

0E

05

1E

04

00

0D

12

0D

0C

12

16

11

16

10

06

08

04

0E

11

0E

00

04

0A

11

1F

00

10

1C

12

02

01

0A

00

0E

11

1F

11

0A

00

0E

12

0D

0A

0E

11

0E

0A

00

0E

11

0E

0A

00

11

0E

18

19

02

04

08

13

03

08

14

08

15

12

0D

0C

04

08

00

02

04

02

08

04

08

0E

11

1F

11

0E

00

10

08

04

0A

11

00

09

0E

10

00

01

0E

1A

0A

00

0F

12

0C

00

0A

00

11

0E

00

04

02

1F

02

04

00

0F

08

18

08

0C

12

04

08

1E

00

06

09

08

1C

08

1F

00

0A

04

1F

04

0A

00

04

1F

04

00

18

08

10

00

1F

00

0C

1F

08

04

02

04

08

1F

11

0A

04

0E

04

00

01

02

04

08

10

00

0E

11

17

15

17

10

0E

11

13

15

19

11

0E

04

0C

04

0E

11

01

06

08

10

1F

0E

11

01

0E

01

11

0E

02

06

0A

12

1F

02

1F

10

1E

01

1E

06

08

10

1E

11

0E

1F

01

02

04

08

0E

11

0E

11

0E

11

0F

01

02

0C

00

0C

00

0C

00

0C

00

0C

04

08

01

02

04

08

04

02

01

00

1F

00

1F

00

10

08

04

02

04

08

10

0E

11

01

02

04

00

04

00

1F

04

0E

15

04

07

04

07

00

10

08

04

02

01

00

1C

04

1C

0C

08

04

00

02

04

08

04

02

04

00

04

18

04

02

04

08

00

08

15

02

00

0A

15

0A

15

0A

15

0A

HEX

CODE

HEX

CODE

HEX

CODE

HEX

CODE

HEX

CODE

HEX

CODE

HEX

CODE

HEX

CODE