1. General description
The TDA4865J and TDA4865AJ are deflection boosters for use in vertical deflection
systems for frame frequencies up to 200 Hz.
The TDA4865J needs a separate flyback supply voltage, so the supply voltages are
independently adjustable to optimize power consumption and flyback time.
For the TDA4865AJ the flyback supply voltage will be generated internally by doubling the
supply voltage and therefore a separate flyback supply voltage is not needed.
Both circuits provide differential input stages.
2. Features
nPower amplifier with differential inputs
nOutput current up to 3.8 A (p-p)
nHigh vertical deflection frequency up to 200 Hz
nHigh linear sawtooth signal amplification
nFlyback generator:
uTDA4865J: separate adjustable flyback supply voltage up to 70 V
uTDA4865AJ: internally doubled supply voltage (two supply voltages only for
DC-coupled outputs)
3. Quick reference data
TDA4865J; TDA4865AJ
Vertical deflection booster
Rev. 02 — 3 November 2006 Product data sheet
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VP1 supply voltage 1 9 - 35 V
VP2 supply voltage 2 VP1 −1 - 70 V
VFB flyback supply voltage of
TDA4865J VP1 −1 - 70 V
VP3 flyback generator output
voltage of TDA4865AJ IVOUT =−1.9 A 0 - VP1 + 2.2 V
Vi(INN) input voltage on pin INN 1.6 - VP1 −0.5 V
Vi(INP) input voltage on pin INP 1.6 - VP1 −0.5 V
IP1 supply current 1 during scan - 6 10 mA
TDA4865J_TDA4865AJ_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 3 November 2006 2 of 18
NXP Semiconductors TDA4865J; TDA4865AJ
Vertical deflection booster
4. Ordering information
5. Block diagram
IP2 quiescent supply
current 2 IVOUT =0 - 25 60 mA
IVOUT(p-p) vertical deflection output
current
(peak-to-peak value)
- - 3.8 A
Tamb ambient temperature −20 - +75 °C
Table 1. Quick reference data
…continued
Symbol Parameter Conditions Min Typ Max Unit
Table 2. Ordering information
Type
number Package
Name Description Version
TDA4865J DBS7P plastic DIL-bent-SIL power package; 7 leads
(lead length 12/11 mm); exposed die pad SOT524-1
TDA4865AJ
Fig 1. Block diagram of TDA4865J
001aad296
RS1 CS1
RP
C1
D1
TDA4865J
R3
R2 R1
C2C4
R4
7
INP INN
deflection
coil
from
deflection controller
VOUT GND VP2
VNVFVP
VP1
VFB
6543 21
DIFFERENTIAL
INPUT
STAGE
VERTICAL
OUTPUT FLYBACK
GENERATOR REFERENCE
CIRCUIT
THERMAL
PROTECTION
TDA4865J_TDA4865AJ_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 3 November 2006 3 of 18
NXP Semiconductors TDA4865J; TDA4865AJ
Vertical deflection booster
6. Pinning information
6.1 Pinning
Fig 2. Block diagram of TDA4865AJ
001aad297
RS1 CS1 CF
RP
C1
R5
D1
TDA4865AJ
R3
R2 R1
R6
C2
7
INP INN
deflection
coil
from
deflection controller
VOUT GND VP2
VNVP
VP1
VP3
65432 1
DIFFERENTIAL
INPUT
STAGE
VERTICAL
OUTPUT FLYBACK
GENERATOR REFERENCE
CIRCUIT
THERMAL
PROTECTION
Fig 3. Pin configuration for DBS7P
(TDA4865J) Fig 4. Pin configuration for DBS7P
(TDA4865AJ)
TDA4865J
VP1
VFB
VP2
GND
VOUT
INN
INP
001aad298
1
2
3
4
5
6
7
TDA4865AJ
VP1
VP3
VP2
GND
VOUT
INN
INP
001aad299
1
2
3
4
5
6
7
TDA4865J_TDA4865AJ_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 3 November 2006 4 of 18
NXP Semiconductors TDA4865J; TDA4865AJ
Vertical deflection booster
6.2 Pin description
7. Functional description
Both the TDA4865J and TDA4865AJ consist of a differential input stage, a vertical output
stage, a flyback generator, a reference circuit and a thermal protection circuit.
The TDA4865J operates with a separate flyback supply voltage (see Figure 1) while the
TDA4865AJ generates the flyback voltage internally by doubling the supply voltage
(see Figure 2).
7.1 Differential input stage
The differential sawtooth input current signal (from the deflection controller) is connected
to the inputs (inverted signal to pin INN and non-inverted signal to pin INP). The vertical
feedback signal is superimposed on the inverted signal on pin INN.
7.2 Vertical output and thermal protection
The vertical output stage is a quasi-complementary class-B amplifier with a high linearity.
The output stage is protected against thermal overshoots. For a junction temperature of
Tj> 150 °C the protection will be activated and will reduce the deflection current (IVOUT).
7.3 Flyback generator
The flyback generator supplies the vertical output stage during flyback.
The TDA4865J is used with a separate flyback supply voltage to achieve a short flyback
time with minimized power dissipation.
The TDA4865AJ needs a capacitor (CF) connected between pins VP3 and VP2 (see
Figure 2). Capacitor CF is charged during scan, using the external diode D1 and resistor
R5. During flyback the cathode of capacitor CFis connected to the positive supply voltage
and the flyback voltage is then twice the supply voltage. For the TDA4865AJ the
resistor R6 in the positive supply line can be used to reduce the power consumption.
Table 3. Pin description
Symbol Pin Description
TDA4865J TDA4865AJ
VP1 1 1 positive supply voltage 1
VFB 2 - flyback supply voltage
VP3 - 2 flyback generator output
VP2 3 3 supply voltage 2 for vertical output
GND 4 4 ground or negative supply voltage
VOUT 5 5 vertical output
INN 6 6 inverted input of differential input stage
INP 7 7 non-inverted input of differential input stage
TDA4865J_TDA4865AJ_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 3 November 2006 5 of 18
NXP Semiconductors TDA4865J; TDA4865AJ
Vertical deflection booster
In parallel with the deflection coil a damping resistor RP and an RC combination
(RS1 = 5.6 Ω and CS1 = 100 nF) are needed. Furthermore, another additional
RC combination (RS2 = 5.6 Ω and CS2 = 47 nF to 150 nF) can be used to minimize the
noise effect and the flyback time (see Figure 7 and Figure 8).
8. Internal circuitry
Table 4. Internal circuits
Symbol Pin Equivalent circuit
TDA4865J
VP1 1
VFB 2
VP2 3
GND 4
VOUT 5
INN 6
INP 7
TDA4865AJ
VP1 1
VP3 2
VP2 3
GND 4
VOUT 5
INN 6
INP 7
001aad300
TDA4865J
7
INP INN VOUT GND VP2 VP1
VFB
654321
001aad301
TDA4865AJ
7
INP INN VOUT GND VP2 VP1
VP3
654321
TDA4865J_TDA4865AJ_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 3 November 2006 6 of 18
NXP Semiconductors TDA4865J; TDA4865AJ
Vertical deflection booster
9. Limiting values
[1] Internally limited by thermal protection; will be activated for Tj≥150 °C.
[2] Class C according to EIA/JESD22-A115-A.
[3] Class 3A according to JESD22-A114C.01.
10. Thermal characteristics
[1] To minimize the thermal resistance from mounting base to heat sink [Rth(mb-h)] follow the recommended mounting instruction: screw
mounting preferred; torque = 40 Ncm; use heat sink compound; isolation plate increases Rth(mb-h).
11. Characteristics
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages referenced to pin GND; unless otherwise
specified.
Symbol Parameter Conditions Min Max Unit
VP1 supply voltage 1 - 40 V
VP2 supply voltage 2 - 70 V
VFB flyback supply voltage of TDA4865J - 70 V
VP3 flyback generator output voltage of TDA4865AJ 0 VP1 +3 V
Vi(INN) input voltage on pin INN - VP1 V
Vi(INP) input voltage on pin INP - VP1 V
Vo(VOUT) output voltage on pin VOUT - 72 V
IP2 supply current 2 - ±2.0 A
Io(VOUT) output current on pin VOUT [1] -±2.0 A
IVFB current during flyback of TDA4865J - ±2.0 A
IVP3 current during flyback of TDA4865AJ - ±2.0 A
Tstg storage temperature −25 +150 °C
Tamb ambient temperature −20 +75 °C
Tjjunction temperature [1] - 150 °C
Vesd electrostatic discharge voltage machine model [2] −400 +400 V
human body model [3] −4000 +4000 V
Table 6. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-mb) thermal resistance from junction to mounting base [1] 4 K/W
Table 7. Characteristics
V
P1
= 25 V; T
amb
= 25
°
C; voltages referenced to pin GND; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VP1 supply voltage 1 9 - 35 V
VP2 supply voltage 2 VP1 −1 - 70 V
VFB flyback supply voltage of
TDA4865J VP1 −1 - 70 V
TDA4865J_TDA4865AJ_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 3 November 2006 7 of 18
NXP Semiconductors TDA4865J; TDA4865AJ
Vertical deflection booster
[1] Deviation of the output slope at a constant input slope.
VP3 flyback generator output voltage of
TDA4865AJ IVOUT =−1.9 A 0 - VP1 + 2.2 V
IP1 supply current 1 during scan - 6 10 mA
IP2 quiescent supply current 2 IVOUT =0 - 25 60 mA
Differential input stage
Vi(INN) input voltage on pin INN 1.6 - VP1 −0.5 V
Vi(INP) input voltage on pin INP 1.6 - VP1 −0.5 V
Iq(INN) input quiescent current on pin INN - −100 −500 nA
Iq(INP) input quiescent current on pin INP - −100 −500 nA
Flyback generator
IVFB current during flyback of
TDA4865J --±1.9 A
IVP3 current during flyback of
TDA4865AJ --±1.9 A
VVP2-VFB(r) reverse voltage drop during flyback
of TDA4865J IVOUT =−1A - −2- V
IVOUT =−1.25 A - −2.2 - V
IVOUT =−1.9 A - −2.7 - V
VVP2-VFB(f) forward voltage drop during flyback
of TDA4865J IVOUT =1A - 1.5 - V
IVOUT = 1.25 A - 1.7 - V
IVOUT = 1.9 A - 2.1 - V
VVP3-VP1(r) reverse voltage drop during flyback
of TDA4865AJ IVOUT =−1A - −2- V
IVOUT =−1.25 A - −2.2 - V
IVOUT =−1.9 A - −2.7 - V
VVP3-VP1(f) forward voltage drop during flyback
of TDA4865AJ IVOUT =1A - 1.5 - V
IVOUT = 1.25 A - 1.7 - V
IVOUT = 1.9 A - 2.1 - V
Vertical output stage; see Figure 5
IVOUT vertical deflection output current - - ±1.9 A
IVOUT(p-p) vertical deflection output current
(peak-to-peak value) - - 3.8 A
Vo(sat)n output saturation voltage to ground IVOUT = 1 A - 1.3 1.7 V
IVOUT = 1.25 A - 1.5 2.3 V
IVOUT = 1.9 A - 2.6 3.0 V
Vo(sat)p output saturation voltage to VP2 IVOUT =1A −2.3 −2.0 - V
IVOUT = 1.25 A −2.8 −2.2 - V
IVOUT = 1.9 A −3.5 −2.6 - V
LIN non-linearity of output signal [1] --1%
Table 7. Characteristics
…continued
V
P1
= 25 V; T
amb
= 25
°
C; voltages referenced to pin GND; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
TDA4865J_TDA4865AJ_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 3 November 2006 8 of 18
NXP Semiconductors TDA4865J; TDA4865AJ
Vertical deflection booster
12. Application information
(1) VFB for TDA4865J; 2VP1 for TDA4865AJ.
Fig 5. Timing diagram
t
input signal
on pin INN
t
input signal
on pin INP
t
output voltage
on pin VOUT
VFB(1)
VP1
GND
t
deflection current
through the coil
001aab327
Fig 6. Application diagram with TDA4865J for external guard signal generation
> 1 kΩ
3.3 kΩ2.2 Ω
vertical
output
signal
1N4448
VFB
BC548
BC556
guard output
HIGH = error
VOUT
220 kΩ22 µF
VFVP
001aad302
TDA4865J
TDA4865J_TDA4865AJ_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 3 November 2006 9 of 18
NXP Semiconductors TDA4865J; TDA4865AJ
Vertical deflection booster
Remark: the heat sink of the IC must be isolated against ground of the application (it is connected to pin GND).
(1) With CS2 (typical value between 47 nF and 150 nF) the flyback time and the noise behavior can be optimized.
Fig 7. Application diagram with TDA4865J
5.6 Ω
1.8 kΩ
1.8 kΩ
5.6 Ω270 Ω
0.5 Ω
(1 W)
4.3 Ω
100
nF
470 µF470 µF470 µF
001aad303
RS1
RS2
CS1
CS2(1) RP
D1
BYV27
TDA4865J
R3
R2 R1
7
INP INN
deflection
coil
from
deflection controller
VOUT GND VP2
VN
−8 V +50 V +9 V
VFVP
VP1
VFB
654321
DIFFERENTIAL
INPUT
STAGE
VERTICAL
OUTPUT FLYBACK
GENERATOR REFERENCE
CIRCUIT
THERMAL
PROTECTION
TDA4865J_TDA4865AJ_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 3 November 2006 10 of 18
NXP Semiconductors TDA4865J; TDA4865AJ
Vertical deflection booster
12.1 Example for both TDA4865J and TDA4865AJ
[1] Flyback voltage measured against 0 V; for TDA4865J only.
Remark: the heat sink of the IC must be isolated against ground of the application (it is connected to pin GND).
(1) With CS2 (typical value between 47 nF and 150 nF) the flyback time and the noise behavior can be optimized.
(2) With R5 capacitor CFwill be charged during scan and the value (typical value between 150 Ωand 270 Ω) depends on Idefl,
tflb and CF.
(3) R6 reduces the power dissipation of the IC. The maximum possible value depends on the application.
Fig 8. Application diagram with TDA4865AJ
001aad304
3.9 Ω
(2 W)
240 Ω (2 W)
100 µF
470 µF
CF
R5(2)
D1
TDA4865AJ
R6(3)
7
INP INN VOUT GND VP2 VP1
VP3
654321
DIFFERENTIAL
INPUT
STAGE
VERTICAL
OUTPUT FLYBACK
GENERATOR REFERENCE
CIRCUIT
THERMAL
PROTECTION
BYV27 470 µF
+12.5 V−12.5 V VP
VN
5.6 Ω
1.8 kΩ
1.8 kΩ
5.6 Ω270 Ω
0.5 Ω
(1 W)
100
nF
RS1
RS2
CS1
CS2(1) RP
R3
R2 R1
deflection
coil
from
deflection controller
Table 8. Values given from application
Symbol Value Unit
Idefl(max)(M) 1.6 (peak value) A
Ldeflcoil 10 mH
Rdeflcoil 4Ω
RP270 Ω
R1 0.5 Ω
R2 1.8 kΩ
R3 1.8 kΩ
VF[1] 50 V
Tamb 50 °C
Tdeflcoil 75 °C
Rth(j-mb) 4 K/W
Rth(mb-h) 0.5 K/W
Rth(h-a) 2 K/W
TDA4865J_TDA4865AJ_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 3 November 2006 11 of 18
NXP Semiconductors TDA4865J; TDA4865AJ
Vertical deflection booster
[1] With a heat sink of 2 K/W.
VP1,V
N and VFB are referenced to ground of application; voltages are calculated with
+10 % tolerances.
The calculation formulae for supply voltages are as follows:
(1)
(2)
where:
U’L=L
deflcoil ×2Idefl(max) ×fv
fv= vertical deflection frequency
UD1 = forward voltage drop across D1
The calculation formulae for power consumption is:
(3)
(4)
(5)
where:
PIC = power dissipation of the IC
Ptot = total power dissipation
Pdefl = power dissipation of the deflection coil
Calculation formulae for maximum required thermal resistance for the heat sink at
Tj(max) = 110 °C:
(6)
(7)
Table 9. Calculated values
Symbol Value Unit
TDA4865J TDA4865AJ
VP1 815V
VN−13 −15 V
Ptot 8.5 12.1 W
Pdefl 3.85 3.85 W
PIC 4.65 8.25 W
Rth(tot)(max) 12.9 7.27 K/W
Tj(max)[1] 93 103.6 °C
tflb 650 720 µs
VP1 Vosat()p
–R1 Rdeflcoil
+()Idefl max()
U'LUD1
+–×+=
VNVosat()nR1 Rdeflcoil
+()Idefl max()
U'L
+×+=
PIC Ptot Pdefl
–=
Ptot VP1 UD1
–()
Idefl max()
4
---------------------- VNIdefl max()
4
---------------------- VP1 VN
+()0.01 0.2+×+×+×=
Pdefl Rdeflcoil R1+
3
---------------------------------Idefl max()
2
×=
Rth tot() Rth j-mb()
Rth mb-h()
Rth h-a()
++=
Rth h-a() Tjmax()
Tamb
–
PIC
------------------------------------ Rth j-mb()
–Rth mb-h()
–=
TDA4865J_TDA4865AJ_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 3 November 2006 12 of 18
NXP Semiconductors TDA4865J; TDA4865AJ
Vertical deflection booster
Calculation formulae for flyback time (for TDA4865J only):
(8)
where:
VF measured against 0 V
12.2 Application example for different driver circuits
tflb Ldeflcoil
Rdeflcoil R1+
---------------------------------VFRdeflcoil R1+()Idefl max()
×+
VFRdeflcoil R1+()Idefl max()
×–
--------------------------------------------------------------------------------
ln×=
Fig 9. Application for single-ended driver currents with inverting amplifier
001aad305
TDA4865J or
TDA4865AJ
7
INP INN VOUT
65
5.6 Ω270 Ω
R1
1 Ω
RS2
CS2 RP
R3
R2a
deflection
coil
R2b
Vref
5.6 Ω100
nF
RS1 CS1
GND
4
Iv(drv)
t
Iv(drv)
Iv(drv)(max)
Iv(drv)(min)
t
Idefl
Idefl(max)(P)
Idefl(max)(N)
Idefl
Fig 10. Application for single-ended driver currents with non-inverting amplifier
t
Iv(drv)
Iv(drv)(max)
Iv(drv)(min)
001aad306
t
Idefl
Idefl(max)(P)
Idefl(max)(N)
TDA4865J or
TDA4865AJ
7
INP INN VOUT
65
5.6 Ω270 Ω
R1
1 Ω
RS2
CS2 RP
R3b
deflection
coil
R2
Iv(drv)
5.6 Ω100
nF
RS1 CS1
GND
4
Idefl
Vref R3a
TDA4865J_TDA4865AJ_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 3 November 2006 13 of 18
NXP Semiconductors TDA4865J; TDA4865AJ
Vertical deflection booster
Fig 11. Application for single-ended driver voltage output with non-inverting amplifier
001aad307
t
Idefl
Idefl(max)(P)
Idefl(max)(N)
Idefl
TDA4865J or
TDA4865AJ
7
INP INN VOUT
65
5.6 Ω270 Ω
R1
1 Ω
RS2
CS2 RP
R3b
deflection
coil
Vdrv 5.6 Ω100
nF
RS1 CS1
GND
4
t
Vdrv
Vdrv(max)
Vdrv(min)
Vref R3a
TDA4865J_TDA4865AJ_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 3 November 2006 14 of 18
NXP Semiconductors TDA4865J; TDA4865AJ
Vertical deflection booster
13. Package outline
Fig 12. Package outline SOT524-1 (DBS7P)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
2. Plastic surface within circle area D1 may protrude 0.04 mm maximum.
SOT524-1
0 10 mm5
scale
wM
bp
Dh
q1
Z
17
e
e1
me2
x
A2
non-concave
D1
D
P
kq2
L3
L2
L
Qc
E
00-07-03
03-03-12
DBS7P: plastic DIL-bent-SIL power package; 7 leads (lead length 12/11 mm); exposed die pad SOT524-1
view B: mounting base side
B
UNIT bpL1
cD
(1) DhLq
2
mm 2.7
2.3
A2(2)
0.80
0.65 0.58
0.48 13.2
12.8
D1(2)
6.2
5.8 3.5
Eh
3.5
e
2.54
e1
1.27
e2
5.08 4.85
QE(1)
14.7
14.3
Z(1)
2.92
2.37
11.4
10.0
L2
6.7
5.5
L3
4.5
3.7 3.4
3.1 1.15
0.85
q
17.5
16.3
q1
2.8
m
0.8
v
3.8
3.6
3
212.4
11.0
Pk
0.02
x
0.3
w
Eh
L1
q
vM
TDA4865J_TDA4865AJ_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 3 November 2006 15 of 18
NXP Semiconductors TDA4865J; TDA4865AJ
Vertical deflection booster
14. Soldering
14.1 Introduction to soldering through-hole mount packages
This text gives a brief insight to wave, dip and manual soldering.
Wave soldering is the preferred method for mounting of through-hole mount IC packages
on a printed-circuit board.
14.2 Soldering by dipping or by solder wave
Driven by legislation and environmental forces the worldwide use of lead-free solder
pastes is increasing. Typical dwell time of the leads in the wave ranges from
3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb
or Pb-free respectively.
The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic
body must not exceed the specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling may be necessary immediately
after soldering to keep the temperature within the permissible limit.
14.3 Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is
less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is
between 300 °C and 400 °C, contact may be up to 5 seconds.
14.4 Package related soldering information
[1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit
board.
[2] For PMFP packages hot bar soldering or manual soldering is suitable.
Table 10. Suitability of through-hole mount IC packages for dipping and wave soldering
Package Soldering method
Dipping Wave
CPGA, HCPGA - suitable
DBS, DIP, HDIP, RDBS, SDIP, SIL suitable suitable[1]
PMFP[2] - not suitable
TDA4865J_TDA4865AJ_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 3 November 2006 16 of 18
NXP Semiconductors TDA4865J; TDA4865AJ
Vertical deflection booster
15. Revision history
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
TDA4865J_TDA4865AJ_2 20061103 Product data sheet - TDA4865_1
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors
•Legal texts have been adapted to the new company name where appropriate
TDA4865_1 19921208 Preliminary specification - -
TDA4865J_TDA4865AJ_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 3 November 2006 17 of 18
NXP Semiconductors TDA4865J; TDA4865AJ
Vertical deflection booster
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors TDA4865J; TDA4865AJ
Vertical deflection booster
© NXP B.V. 2006. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 November 2006
Document identifier: TDA4865J_TDA4865AJ_2
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Functional description . . . . . . . . . . . . . . . . . . . 4
7.1 Differential input stage . . . . . . . . . . . . . . . . . . . 4
7.2 Vertical output and thermal protection . . . . . . . 4
7.3 Flyback generator. . . . . . . . . . . . . . . . . . . . . . . 4
8 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
10 Thermal characteristics. . . . . . . . . . . . . . . . . . . 6
11 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 6
12 Application information. . . . . . . . . . . . . . . . . . . 8
12.1 Example for both TDA4865J and TDA4865AJ 10
12.2 Application example for different driver circuits 12
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
14 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
14.1 Introduction to soldering through-hole mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
14.2 Soldering by dipping or by solder wave . . . . . 15
14.3 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 15
14.4 Package related soldering information . . . . . . 15
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
17 Contact information. . . . . . . . . . . . . . . . . . . . . 17
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
