© 2002 Fairchild Semiconductor Corporation DS500632 www.fairchildsemi.com
September 2001
Revised February 2002
74ALVCH162244 Low Voltage 16-Bit Buffer/Line Driver with Bushold and 26
Ω
Series Resistor in Outputs
74ALVCH162244
Low Voltage 16-Bit Buffer/Line Driver with Bushold
and 26Ω Series Resistor in Outputs
General Description
The ALVCH162244 contains sixteen non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inpu ts whic h ca n be sh ort ed
together for full 16-bit operation.
The ALVCH1622 44 data in puts include act ive bushold c ir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level
The 74ALVCH162244 is also designed with 26Ω series
resistors in the outputs. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
The 74ALVCH162244 is designed for low voltage (1.65V to
3.6V) VCC applications with output capability up to 3.6V.
The 74ALVCH162244 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining low CMOS power dissipation.
Features
■1.65V to 3.6V VCC supply operation
■3.6V tolerant control inputs and outputs
■Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
■26Ω series resistors in outputs
■tPD
4.2 ns max for 3.0V to 3.6V VCC
4.9 ns max for 2.3V to 2.7V VCC
7.6 ns max for 1.65V to 1.95V VCC
■Uses patente d noise /E MI reducti o n circuitr y
■Latch-up conforms to JEDEC JED78
■ESD performa nce :
Human body model > 2000V
Machine model > 200V
Ordering Code:
Devices also available in Tape and R eel. Speci fy by append ing suffix lette r “X” to the ordering co de.
Logic Symbol Pin Descriptions
Order Number Package
Number Package Description
74ALVCH162244T MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OEnOutput Enable Input (Active LOW)
I0–I15 Bushold Inputs
O0–O15 Outputs
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74ALVCH162244
Connection Diagram Truth Tables
H = HIGH Voltage Lev el
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
Functional Description
The 74ALVCH162244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled
with ea ch nibbl e funct ioning i denticall y, b ut indep endent of each ot her. The control pi ns may b e shorted tog ether to obtai n
full 16- bit ope ration .The 3-S TAT E outpu ts are cont rolle d by an Outpu t Enable (OEn) inpu t. When OEn is LOW, th e outputs
are in the 2-s tate mo de. When OEn is HIGH , th e sta nd ard out put s are i n th e hig h imp ed ance mo de but this do es not inter-
fere with entering new data into the inputs.
Logic Diagram
Inputs Outputs
OE1I0–I3O0–O3
LL L
LH H
HX Z
Inputs Outputs
OE2I4–I7O4–O7
LLL
LHH
HXZ
Inputs Outputs
OE3I8–I11 O8–O11
LLL
LHH
HXZ
Inputs Outputs
OE4I12–I15 O12–O15
LLL
LHH
HXZ
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74ALVCH162244
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions (N o te 3)
Note 1: The Absolute Maximum Ratings are those values beyond which
the saf ety of the device cannot be gu aranteed. Th e device shou ld not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tio ns f or actu al device op eration.
Note 2: IO Absolute Maximum Rating must be observed.
Note 3: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
Supply Voltage (VCC)−0.5V to +4.6V
DC Input Voltage (VI)−0.5V to 4.6V
Output Voltage (VO) (Note 2) −0.5V to VCC +0.5V
DC Input Diode Current (IIK)
VI < 0V −50 mA
DC Output Diode Current (IOK)
VO < 0V −50 mA
DC Output Source/Sink Current
(IOH/IOL)±50 mA
DC VCC or GND Current per
Supply Pin (ICC or GND) ±100 mA
Stora ge Temperature Range (TSTG)−65°C to +150°C
Power Supply
Operating 1.65V to 3.6V
Input Voltage 0V to VCC
Output Voltage (VO)0V to V
CC
Free Air Operating Temperature (TA)−40°C to +85°C
Minimum Input Edge Rate (∆t/∆V)
VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V
Symbol Parameter Conditions VCC Min Max Units
(V)
VIH HIGH Level Input Voltage 1.65 - 1.95 0.65 x VCC V2.3 - 2.7 1.7
2.7 - 3.6 2.0
VIL LOW Level Input Voltage 1.65 - 1.95 0.35 x VCC V2.3 - 2.7 0.7
2.7 - 3.6 0 .8
VOH HIGH Level Output Voltage IOH = −100 µA 1.65 - 3.6 VCC - 0.2
V
IOH = −2 mA 1.65 1.2
IOH = −4 mA 2.3 1.9
IOH = −6 mA 2.3 1.7
32.4
IOH = −8 mA 2.7 2
IOH = −12 mA 3.0 2
VOL LOW Level Output Voltage IOL = 100 µA 1.65 - 3.6 0.2
V
IOL = 2 mA 1.65 0.45
IOL = 4 mA 2.3 0.4
IOL = 6 mA 2.3 0.55
30.55
IOL = 8 mA 2.7 0.6
IOL = 12 mA 3 0.8
IIInput Leakage Current 0 ≤ VI ≤ 3.6V 3.6 ±5.0 µA
II(HOLD) Bushold Input Minimum VIN = 0.58V 1.65 25
µA
Drive Hold Current VIN = 1.07V 1.65 −25
VIN = 0.7V 2.3 45
VIN = 1.7V 2.3 −45
VIN = 0.8V 3.0 75
VIN = 2.0V 3.0 −75
0 < VO ≤ 3.6V 3 .6 ±500
IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 3.6V 3.6 ±10 µA
ICC Quiescent Supply Current VI = VCC or GND, IO = 0 3.6 40 µA
∆ICC Increase in ICC per Input VIH = VCC − 0.6V 3 - 3.6 750 µA
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74ALVCH162244
AC Electrical Characteristics
Capacitance
Symbo l Parame t e r
TA = −40°C to +85°C, RL = 500Ω
Units
CL = 50 pF CL = 30 pF
VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5V ± 0.2V VCC = 1.8V ± 0.15V
Min Max Min Max Min Max Min Max
tPHL, tPLH Propagation Delay 1.0 4.2 4.7 1.0 4.9 1.5 7.6 ns
tPZL, tPZH Output Enable Time 1.0 5.6 6.7 1.0 6.8 1.5 9.8 ns
tPLZ, tPHZ Output Disable Time 1.0 5.5 5.7 1 .0 6.3 1.5 7.2 ns
Symbol Parameter Conditions TA = +25°C Units
VCC Typical
CIN Input Capacitance Control VI = 0V or VCC 3.3 3 pF
Data VI = 0V or VCC 3.3 6
COUT Output Capacitance VI = 0V or VCC 3.3 7 pF
CPD Power Dissipation Capacitance Outputs Enabled f = 10 MHz, CL = 50 pF 3.3 19
pF
2.5 16
Outputs Disabled f = 10 MHz, CL = 50 pF 3.3 5
2.5 4
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74ALVCH162244
AC Loading and Waveforms
FIGURE 1. AC Test Circuit
TABLE 1. Values for Figure 1
TABLE 2. Variable Matrix
(Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50Ω)
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
TEST SWITCH
tPLH, tPHL Open
tPZL, tPLZ VL
tPZH, tPHZ GND
Sym bol VCC
3.3V ± 0.3V 2.7V 2.5V ± 0.2V 1.8V ± 0.1 5V
Vmi 1.5V 1.5V VCC/2 VCC/2
Vmo 1.5V 1.5V VCC/2 VCC/2
VXVOL + 0.3V VOL + 0.3V VOL + 0.15V VOL + 0.15V
VYVOH − 0.3 V VOH − 0.3V VOH − 0.15V VOH − 0.15V
VL6V 6V VCC*2 VCC*2
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74ALVCH162244 Low Voltage 16-Bit Buffer/Line Driver with Bushold and 26
Ω
Series Resistor in O utputs
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-, 6.1mm Wide
Package Number MTD48
Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syste ms are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical compon ent i n any compon ent of a lif e supp ort
device or system whose failure to perform can be rea-
sonabl y ex pect ed to ca use the fa ilu re of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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