Total-AceXtreme
Ultra-Small, Ultra-Low Power
MIL-STD-1553 Single Package Solution
Data Sheet
© 2011 Data Device Corporation. All trademarks are the property of their respective owners.
Model: BU-67301B
For more information: www.ddc-web.com/BU-67301B
Small, Fully Integrated 1553 Terminal with
Transformers Inside:
- 16 x 16 x 4.7 mm (0.63 x 0.63 x 0.185 in.)
- Protocol, RAM, Transceivers and Transformers in a
Single Package
- 324 Ball JEDEC Design Guide 4.5 Standard Size
Fine Pitch Ball Grid Array with 0.8 mm Ball Pitch
Ultra Low Transceiver Power
Comprehensive Built-in Self Test
Versatile User Selectable High-Speed Backend for
PCI or CPU Interface
- Access Time as low as 12.5ns
- DMA Engine with 264MB/sec Burst Transfer Rate
1 Dual Redundant MIL-STD-1553 Channel
- BC or Multi-RT with Concurrent Bus Monitor
- Supports MIL-STD-1553 A/B and MIL-STD-1760
- 2 Mb (64K x 36) RAM
- Tx Inhibit Ball for MT Only Applications
- BC Disable Ball for RT Only Applications
- 48-bit/100ns Time Stamp
- IRIG-106 Chapter 10 MT Support
Supports JTAG Boundary Scan
IRIG-B Input
8 Digital Discrete I/O
Hardware/Software Development Kit with PCI
Evaluation Board and Reference Design Artifacts
Features
World's smallest, ultra low power, fully integrated MIL-STD-1553 BGA package, complete with 1553 protocol, 2
Mb (64K x 36) RAM, transceivers, and isolation transformers inside a single package — saves board space and simpli-
fies 1553 design and layout. Available with development kit to ease integration.
DDC's Data Networking Solutions
MIL-STD-1553 | ARINC 429 | Fibre Channel
As the leading global supplier of data bus components, cards, and software solutions for the military, commercial,
and aerospace markets, DDC’s data bus networking solutions encompass the full range of data interface
protocols from MIL-STD-1553 and ARINC 429 to USB, and Fibre Channel, for applications utilizing a spectrum of
form-factors including PMC, PCI, Compact PCI, PC/104, ISA, and VME/VXI.
DDC has developed its line of high-speed Fibre Channel and Extended 1553 products to support the real-time
processing of field-critical data networking netween sensors, compute notes, data storage displays, and weapons
for air, sea, and ground military vehicles.
Whether employed in increased bandwidth, high-speed serial communications, or traditional avionics and ground
support applications, DDC's data solutions fufill the expanse of military requirements including reliability,
determinism, low CPU utilization, real-time performance, and ruggedness within harsh environments. Out use of
in-house intellectual property ensures superior mutli-generational support, independent of the life cycles of
commercial devices. Moreover, we maintain software compatibility between product generations to protect our
customers' investments in software development, system testing, and end-product qualification.
DDC provides an assortment of quality MIL-STD-1553 commercial, military, and COTS grade cards and
components to meet your data conversion and data interface needs. DDC supplies MIL-STD-1553 board level
products in a variety of form factors including AMC, USB, PCI, cPCI, PCI-104, PCMCIA, PMC, PC/104, PC/104-
Plus, VME/VXI, and ISAbus cards. Our 1553 data bus board solutions are integral elements of military, aerospace,
and industrial applications. Our extensive line of military and space grade components provide MIL-STD-1553
interface solutions for microprocessors, PCI buses, and simple systems. Our 1553 data bus solutions are
designed into a global network of aircraft, helicopter, and missle programs.
DDC also has a wide assortment of quality ARINC-429 commercial, military, and COTS grade cards and
components, which will meet your data conversion and data interface needs. DDC supplies ARINC-429 board
level products in a variety of form factors including AMC, USB, PCI, PMC, PCI-104, PC/104 Plus, and PCMCIA
boards. DDC's ARINC 429 components ensure the accurate and reliable transfer of flight-critical data. Our 429
interfaces support data bus development, validation, and the transfer of flight-critical data aboard commercial
aerospace platforms.
MIL-STD-1553
ARINC 429
DDC has developed its line of high-speed Fibre Channel network access controllers and switches to support the
real-time processing demands of field-critical data networking between sensors, computer nodes, data storage,
displays, and weapons, for air, sea, and ground military vehicles. Fibre Channel's architecture is optimized to
meet the performance,reliability, and demanding environmental requirements of embedded, real time, military
applications, and designed to endure the multi-decade life cycle demands of military/aerospace programs.
Fibre Channel
DATA DEVICE CORPORATION
Data Device Corporation DS-BU-67301B-E
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i
ULTRA-SMALL, ULTRA-LOW POWER MIL-STD-1553
SINGLE PACKAGE SOLUTION
BU-67301B DATA SHEET
The information provided in this Data Sheet is believed to be accurate; however, no
responsibility is assumed by Data Device Corporation for its use, and no license or rights
are granted by implication or otherwise connection therewith.
Specifications are subject to change without notice.
Please visit our Web site at http://www.ddc-web.com/ for the latest information.
All rights reserved. No part of this Data Sheet may be reproduced or transmitted in any
form or by any mean, electronic, mechanical photocopying recording, or otherwise,
without the prior written permission of Data Device Corporation.
105 Wilbur Place
Bohemia, New York 11716-2426
Tel: (631) 567-5600, Fax: (631) 567-7358
World Wide Web - http://www.ddc-web.com
For Technical Support - 1-800-DDC-5757 ext. 7771
United Kingdom - Tel: +4 4-(0)1635-811140, Fax: +44-(0)1635-32264
France - Tel: +33-(0)1-41-16-3424, Fax : +33-(0)1-41-16-3425
Germany - Tel: +49-(0)89-15 00 12-11, Fax: +49-(0)89-15 00 12-22
Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689
Asia - Tel: +65-6489-4801 © 2010 Data Devic e Corp.
RECORD OF CHANGE
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ii
Revision Date Pages Description
Pre Rev A Sept., 2010 All Preliminary release
Rev. A Sept., 2011 All Initial Release
Rev. B Dec., 2011 6, 7, 9, 38, 113,
25-93, 95, 101-
115
Table 1: removed part numbers from Supply Voltage
section, changed Storage Temperature Max. from:
+150°C to: +125°C., added Ramp Rate specs, added
Junction Temperature (TJ)
Table 7: Changed Tah min from 2ns to 7ns.
Table 25: removed redundant B1 listing in NC section.
Section 6: changed heading to Host Interface.
Added Secti on 7: Power Inputs
Tables 15 - 22: Added Pullup/Pulldown column and
values
Rev. C Dec., 2011 10, 15, 96-97, 99,
100, 115
Table 1: Eliminated reference to “(Hottest Die)”.
Figure 5: Eliminat ed “MT 1 00 µs Timer (16-bit)” block.
Added Figure 56, Timing of CLK_IN, Logic_VDDIO,
PLL_+1.8V, and Core_+1.8V.
Figure 58: Made corr ec tions
Figure 59: Made corr ec tions
Table 22: Changed second column signal description
for nSINGEND(I).
Rev. D January, 2012
7, 36-39, 55-58,
89. 96-98, 104,
107-108, 110,
122, 125
Figure 2: Added nPO R and PLL_LOCKED
Figures 7-10 and Figures 19-22: Add ed nPOR ,
supervisor circuit, and PLL_LOCKED, modifed use of
nMSTCLR
Figure 48: Added nPOR and PLL_LOCKED
Paragraph 7.2: upd at e d power -up sequence, modified
Figure 56
Table 15: Added nPOR and PLL_LOCKED
Table 18: Modified RST#
Table 19: Modified nMSTCLR
Table 26: Added nPOR and PLL_LOCKED
Figure 61: Added nPOR and PLL_LOCKED
Rev. E Feb., 2012 98 Updated Figure 56
TABLE OF CONTENTS
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1 PREFACE ............................................................................................................. 1
1.1 Standard Definitions .................................................................................................... 1
1.2 Trademarks ................................................................................................................. 1
1.3 Technical Support ....................................................................................................... 2
2 OVERVIEW .......................................................................................................... 3
2.1 Features ...................................................................................................................... 3
2.2 Specifications .............................................................................................................. 8
2.3 Additional Support Documents .................................................................................. 12
2.4 Total-AceXtreme™ Development Kit ......................................................................... 13
3 MIL-STD-155 3 MODES AND ARCHITECTURE ................................................ 14
3.1 Bus Controller Mode.................................................................................................. 14
3.2 Remote Terminal Operation ...................................................................................... 15
3.3 Monitor Mode Operation ............................................................................................ 17
3.4 Advanced Data Handler (ADH) ................................................................................. 19
4 GLOBAL FEATURE S ........................................................................................ 21
4.1 Transceivers and Isolation Transformers ................................................................... 21
4.2 Time Tags ................................................................................................................. 21
4.3 Local Timer ............................................................................................................... 21
4.4 DMA Contro ller .......................................................................................................... 22
4.5 Digital I/O .................................................................................................................. 23
5 BUILT-IN TEST .................................................................................................. 24
5.1 Total-AceXtreme™ Self-Test ..................................................................................... 24
5.2 JTAG Boundary Scan ................................................................................................ 24
6 HOST INTERF ACE ............................................................................................ 26
6.1 Host Interface Configuration Options ......................................................................... 26
6.2 Parallel CPU Interface ............................................................................................... 26
6.3 Asynchronous Interface Mode ................................................................................... 34
6.4 Synchronous Host Processor Interface ..................................................................... 50
6.5 PCI Interface ............................................................................................................. 87
7 POWER INPUTS ................................................................................................ 96
7.1 Decoupling Capacitors .............................................................................................. 96
7.2 Power Sequencing .................................................................................................... 96
8 MIL-STD-155 3 TRANSCEIVER OPTIONS ........................................................ 99
8.1 Using the Internal Transceivers ................................................................................. 99
8.2 Connection to External Transceivers ....................................................................... 100
8.3 Using External Fiber Optic Transceivers ................................................................. 101
TABLE OF CONTENTS
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9 REGISTER AND MEMORY ADDRESSING ..................................................... 103
9.1 Memory Address Space .......................................................................................... 103
9.2 Register Address Space .......................................................................................... 103
10 TOTAL-ACEXTREME™ SIGNALS .................................................................. 104
10.1 Signal Descriptions and Pinout by Functional Groups ............................................. 104
10.2 Host Interface Signals ............................................................................................. 106
10.3 Pinout Table ............................................................................................................ 120
10.4 Total-AceXtreme™ Pin Diagram ............................................................................. 124
11 MECHANICAL OUTLINE ................................................................................. 125
12 ORDERING INFORMATION ............................................................................ 126
LIST OF FIGURES
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Figure 1. BU-67301B Total-AceXtreme™ .................................................................................6
Figure 2. Total-AceXtreme™ Block Diagram .............................................................................7
Figure 3. Bus Controller Block Diagram .................................................................................. 15
Figure 4. Remote Terminal Block Diagram .............................................................................. 17
Figure 5. Monitor Block Diagram ............................................................................................. 18
Figure 6. PCI DMA Block Diagram .......................................................................................... 22
Figure 7. 32-bit, Non-Multiplexed Address, Asynchronous Interface ....................................... 36
Figure 8. 32-bit, Multiplexed Address, Asynchronous Interface ............................................... 37
Figure 9. 16-bit, Non-Multiplexed Address, Asynchronous Interface ....................................... 38
Figure 10. 16-bit, Multiplexed Address, Asynchronous Interface ............................................. 39
Figure 11. Asynchronous Non-Multiplexed Address 32-bit Read Timing ................................. 42
Figure 12. Asynchronous Non-Multiplexed Address 32-bit Write Timing ................................. 43
Figure 13. Asynchronous Non-Multiplexed Address 16-bit Read Timing ................................. 44
Figure 14. Asynchronous Non-Multiplexed Address 16-bit Write T iming ................................. 45
Figure 15. Asynchronous Multiplexed Address 32-bit Read Timing ........................................ 46
Figure 16. Asynchronous Multiplexed Address 32-bit Write Timing ......................................... 47
Figure 17. Asynchronous Multiplexed Address 16-bit Read Timing ........................................ 48
Figure 18. Asynchronous Multiplexed Address 16-bit Write Timing ......................................... 49
Figure 19. 32-bit, Non-Multiplexed Address, Synchronous Interface ....................................... 55
Figure 20. 32-bit, Multiplexed Address, Synchronous Interface .............................................. 56
Figure 21. 16-bit, Non-Multiplexed Address, Synchronous Interface ....................................... 57
Figure 22. 16-bit, Multiplexed Address, Synchronous Interface .............................................. 58
Figure 23. Synchronous, Non-Multiplexed Address ................................................................. 62
Figure 24. Synchronous, Non-Multiplexed Address ................................................................. 63
Figure 25. Synchronous, Non-Multiplexed Address ................................................................. 64
Figure 26. Synchronous, Non-Multiplexed Address 16-bit ....................................................... 65
Figure 27. Synchronous, Non-Multiplexed Address 16-bit ....................................................... 66
Figure 28. Synchronous, Non-Multiplexed Address ................................................................. 67
Figure 29. Synchronous, Non-Multiplexed Address ................................................................. 68
Figure 30. Synchronous, Multiplexed Address 32-bit .............................................................. 69
Figure 31. Synchronous, Multiplexed Address 32-bit .............................................................. 70
Figure 32. Synchronous, Multiplexed Address 32-bit Single-Word Wr i te Tim i ng ..................... 71
Figure 33. Synchronous, Multiplexed Address 16-bit .............................................................. 72
Figure 34. Synchronous, Multiplexed Address 16-bit Single-Word Register Read Timing ...... 73
Figure 35. Synchronous, Multiplexed Address 16-bit Single-Word Memory Write Timing ....... 74
Figure 36. Synchronous, Multi pl ex ed Addr ess 16-bit Single-Word Register Write Timing ...... 75
Figure 37. Synchronous, Non-Mul ti plexed Addr es s, 32-bit ...................................................... 76
Figure 38. Synchronous, Non-Multiplexed Address ................................................................. 77
Figure 39. Synchronous, Non-Multiplexed Address 32-bit ....................................................... 78
Figure 40. Synchronous, Non-Multiplexed Address ................................................................. 79
Figure 41. Synchronous, Non-Multiplexed Address ................................................................. 80
Figure 42. Synchronous, Non-Multiplexed Address ................................................................. 81
Figure 43. Synchronous, Multiplexed Address ........................................................................ 82
Figure 44. Synchronous, Multiplexed Address ........................................................................ 83
Figure 45. Synchronous, Multiplexed Address ........................................................................ 84
LIST OF FIGURES
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Figure 46. Synchronous, Multiplexed Address ........................................................................ 85
Figure 47. Timing for Assertion of CPU_nSTOP ..................................................................... 86
Figure 48. Interface Between Host PCI Bus and Total-AceXtreme™ ...................................... 89
Figure 49. PCI Parametric Timing ........................................................................................... 92
Figure 50. PCI Slave Burst Write ............................................................................................. 92
Figure 51. PCI Slave Burst Read ............................................................................................. 93
Figure 52. PCI DMA Start Delay .............................................................................................. 94
Figure 53. PCI DMA Burst Write .............................................................................................. 94
Figure 54. PCI DMA Burst Read .............................................................................................. 95
Figure 55. Recommended +1.8V_PLL Filter Network ............................................................. 96
Figure 56. Power-Up Initialization Sequence Timing ............................................................... 98
Figure 57. Total-AceXtreme™ Internal Transceiver and Isolation Transformer Connection to
MIL-STD-1553 Bus ............................................................................................................ 99
Figure 58. Mandatory Connections for Integrated Transceivers ............................................ 100
Figure 59. Total-AceXtreme Interface to External McAir Transceiver .................................... 101
Figure 60. Total-AceXtreme™ Interface to Fiber Optic Transceivers .................................... 102
Figure 61. Total-AceXtreme™ Pin Diagram .......................................................................... 124
Figure 62. Total-AceXtreme™ Mechanical Outline Drawing ................................................. 125
LIST OF TABLES
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Table 1. Total-AceXtreme™ Seri es Sp ec i fi cati ons ....................................................................8
Table 2. Supported JTAG Functions ....................................................................................... 25
Table 3. Total-AceXtreme™ Host Interf ac e Conf igur ation Options ......................................... 27
Table 4. Summary of the Operation of the nDATA_RDY Output Signal for Synchronous
Single-Word Memory and Register Accesses ................................................................... 32
Table 5. Asynchronous 16-bit Mode Configuration Options .................................................... 35
Table 6. Asynchronous Transfers ............................................................................................ 40
Table 7. Asynchronous Timing Information ............................................................................. 40
Table 8. Synchronous 16-bit Mode Configuration Options ...................................................... 54
Table 9. Single-Word Synchr o nous Transf er s ......................................................................... 59
Table 10. Synchronous Burst Transfers .................................................................................. 59
Table 11. Synchronous Timing Parameters............................................................................. 60
Table 12. Total-AceXtreme™ PC I Inter f ac e C har act er is ti cs .................................................... 87
Table 13. PCI Bus Interface Signals ........................................................................................ 90
Table 14. PCI Timing Information ............................................................................................ 91
Table 15. Protocol Configuration ........................................................................................... 104
Table 16. JTAG Test ............................................................................................................. 105
Table 17. General Purpose Discrete I/O ................................................................................ 105
Table 18. PCI Signals ............................................................................................................ 106
Table 19. CPU Data Bus ....................................................................................................... 108
Table 20. RT Address Signals ............................................................................................... 113
Table 21. Miscellaneous Signals ........................................................................................... 113
Table 22. Additional Connections & Interface to External Transceiver .................................. 116
Table 23. MIL-STD-1553 Interface ........................................................................................ 118
Table 24. Power and G round Connecti o ns ............................................................................ 118
Table 25. No User Connections ............................................................................................. 119
Table 26. Signal Pinout by Ball Location ............................................................................... 120
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1 PREFACE
This section will define the acronyms used in the rest of the document.
1.1 Standard Definit ions
E2MA Extended Enhanced Mini-ACE®
EMACE Enhanced Mini-ACE®
BC MIL-STD-1553 Bus Co ntr ol l er
MT MIL-STD-1553 Monitor Terminal
RT MIL-STD-1553 Remote Terminal
Multi-RT MIL-STD-1553 Multiple Remote Terminals
ADH DDC Advanced Data Handler
Host Controller connected to the Host Interface
PCI Peripheral Component Interconnect
Rx Receive by RT
Tx Transmit by RT
Bcst Broadcast
MC Mode Code
BIT Built-In Test
PCB Printed Circui t Boar d
FGPI Flexible Generic Processor Interface
1.2 Trademarks
All trademarks are the property of their respective owners.
PREFACE
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1.3 Technical Support
In the event that problems arise beyond the scope of this manual, you can contact In
the event that problems arise beyond the scope of this manual, you can contact DDC
by the following:
US Toll Free Technical Support: 1-800-DDC-5757, ext. 7771
Outside of the US Technical Support: 1-631-567-5600, ext. 7771
Fax: 1-631-567-5758, to the attention of DATA BUS Applications
DDC Website : www.ddc-web.com/ContactUs/TechSupport.aspx
Please note that the latest revisions of Software and Documentation are available for
download at DDC’s Web Site, www.ddc-web.com.
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2 OVERVIEW
The Total-AceXtreme™ provides a complete, compact solution for providing MIL-
STD-1553 interfaces for embedded systems. It provides the required isolation
trans formers, MIL-STD-1553 transceivers, protocol, and 64K x 36 of internal memory
within a single BGA device. It is ideal for extended temperature range applications
where PCB space is at a premium, due to its very small size of just 16 mm x 16 mm,
and its low power dissipation.
The Host interface can be configured as either a flexible generic processor interface
(FGPI), or as a PCI initiator/target interface. The FGPI allows direct connection with
little or no glue logic to a variety of 16-, and 32-bit processors. The PCI interface
allows for a direct connection to a 32-bit PCI bus and supports PCI clock speeds up
to 66 MHz. The PCI Initiator interface provides DMA, allowing host software to
initialize arbitrary sized read or write bursts between the Total-AceXtreme’s shared
memor y and PCI host spac e.
The device provides a dual redundant MIL-STD-1553 channel with very low power,
less than 1 W maximum dissipation. It includes an IEEE 1149.1 compliant JTAG test
interface to support boundary scan testing of circuit assemblies, a digital IRIG-B
input, and 8 digital discrete I/O lines. The IRIG-B input can be used to create a
common time tag reference for the 1553 messages.
The Total-AceXtreme can be used as a MIL-STD-1553 Bus Controller (BC), single
Remote Terminals (RT), multiple (up to 32) Remote Terminals, a Bus Monito r (MT ),
combined BC/Monitor, or combined single RT /M oni tor , or Mul ti -RT/Monitor.
2.1 Features
Small Integrated BGA with Transformers Inside:
- 324 Ball BGA 16 mm x 16 mm x 4.7 m m (0.63 in. x 0.63 in. x 0.185 in.)
- Protocol, RAM, Transceivers and Transformers in a single package
Ultra Low Power, under 1 Watt dissipation at 100% duty cycle
Configurable Host Interface
- 16-bit and 32-bit Options for Parallel CPU Interface
Synchronous and Asynchronous Options
Asynchronous Access Time 70 ns to read, 40 ns to write
Synchronous Access Time for first word as low as 125 ns to read,
50 ns to write
Synchronous Word Bursts at Host Clock Rate, up to 80 MHz
OVERVIEW
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- 32-bit PCI Target/Initiator Interface
Operates at up to 66 MHz
Target single-word reads as low as 125 ns for reads, and 60 ns for
writes
Target Word Bur s ts at PC I Clock Rate
PCI Initiator with built-in DMA Engine with 264MB/sec Burst Transfer
Rate for reduced host resources.
1 Dual Redundant MIL-STD-1553 Channel
- BC or Mu lti-RT with Concurrent Bus Monitor
- Support of MIL-STD-1553 A/B, STANAG-3838, and MIL-STD-1760
- 2 Mb (64K x 36) RAM
- Transmit Inhibit Ball for Monitor-only Appli c a ti ons
- BC Disable Ball for RT-only Applications
- 48-bit/100ns Time Stamp
- IRIG-106 Chapter 10 Monitor
1553 Bus Controller (BC)
- Highly Autonomous Controller, with 32-Instruction Set
- Streami ng an d Minor/Major Frame Scheduling of Messages
- High and Low Priority Asynchronous Message Insertion
- Modify Messages or Data while BC is running
1553 Remote Terminal (RT)
- Emulate up to 31 RT Addr es ses Si m ult an eo u s l y
- Multiple Buffering Techniques
- Programmable Command Illegalization
- Program m able Bus y by Sub-address
- RT Auto -Boot Option for MIL-STD-1760
1553 Bus Monitor (MT)
- IRIG-106 Chapter 10 Compatibility
- Filter Based on RT Address, T/R bit, Sub-Address
- Advanced Bit Level Error Detection to Isolate Bus Failures
Advanced Data Handler (ADH)
- For BC, RT, and Multi-RT modes, Option to Combine Control/Status and
Data Structures into Consolidated Structures for each Message.
OVERVIEW
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- Options for Transferring based on transmit and/or received messages.
- Transfer co ntr ol/ status str uctur es and /or data w or ds .
- For RT, can Filter based on RT Address/T-R bit/Subaddress.
- Filter on Valid and/or Invalid Messages.
- Host Interrupts Based on Time, Number of Messages, or Number of Words.
- Can work in Conjunction with DMA Controller and PCI Initiator Interface.
Autonomous Built-In Self-Test
- Host Initiated Protocol & RAM Self-Test
- Automatic Power On Self-Test
- Online Loo pb ac k Test
- Capability for Channel A-to-B Wraparound Test
- Capability to Test Transmitter Timeout Function
Provides JTAG Bou ndary S can
IRIG-B Input
8 Digita l Dis c rete I/O
High-Level C Software Development Kits with Drivers for Windows®, Linux®, and
VxWorks®
Optional Hardware/Software Development Kit with PCI Evaluation Board and
Design Artifacts (see section 2.4)
- PCI Evaluation Board with Cable
- 1 Total-AceXtreme™ Component
- BusTrACEr™ with Application Code Generation for Software Development
- Drivers for Windows®, Linux®, and VxWorks®
- Thermal Model, IBIS Model and Schematic Symbols
- PCI Card Reference Design Schematic
Extended Industrial Temperature Range, -40°C to +100°C
Thermal Balls for Improved Heatsinking
Leaded and RoHS Versions Available
Total-AceXtreme Architectural Reference Guide. This document, which DDC can
provide under an NDA, includes detailed information about the Total-AceXtreme
architecture. This includes register bit maps and definitions, and detailed information
about the AceXtreme’s data structures and operations for BC, Multi-RT, and Monitor
modes.
OVERVIEW
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Figure 1. BU-67301B Total-AceXtreme™
OVERVIEW
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Figure 2. Total-AceXtreme™ Block Di agram
OVERVIEW
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2.2 Specifications
Table 1. Total-AceXtreme™ Series Specifications
PARAMETER MIN TYP MAX UNITS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Note 11)
Logic +3.3V (VDDIO) -0.3 4.0 V
Core +1.8V -0.3 2.0 V
PLL +1.8V -0.3 2.0 V
Transceivers +3.3V (during transmit)
DC Input or Output Logic Voltage -0.3
-0.3
4.5
VDDIO +0.3, or
4.0 (which ever
is less)
V
V
Logic
3.3V Logic Input or Output Range -0.3 VDDIO +0.3, or
4.0 (which ever
is less)
V
RECEIVER
Differential Input Impedance (Notes 1 6)
• +3.3V Transformer Coupled 1.0 KΩ
Input Voltage Range
Threshol d Voltage ( Transformer Coupled) 0.86
0.200
14.0
0.860 VPK-PK
VPK-PK
Common Mode Voltage ±10 Vpeak
TRANSMITTER
Differential Output Voltage
Transformer Coupled Across 70
, Measured on Bus (Note 9)
20 21.5 27 VPK-PK
Output Noise, Differential 14 mVRMS
Output Offset Voltage, Transformer Coupled Across 70 -250 250 mVPK
Rise/Fall T im e 100 150 300 ns
LOGIC
VIH
All signals except for CLK/PCI_CLK and CLK_IN 0.5*VDDIO VDDIO + 0.3 V
HOST_CLK/PCI_CLK and CLK_IN 2.0 VDDIO + 0.3 V
VIL
All signals except for HOST_CLK/PCI_CLK and CLK_IN -0.3 0.3*VDDIO V
CLK_IN -0.3 0.8 V
OVERVIEW
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Table 1. Total-AceXtreme™ Series Specifications
PARAMETER MIN TYP MAX UNITS
LOGIC (Con’t)
Schmidt Hysteresis
HOST_CLK/PCI_CLK and CLK_IN 0.4 0.7 V
IIH, IIL
All signals except CLK_IN
IIH (Vcc = TBDV, VIN = TBDV) -10 +10 µA
IIL (Vcc = TBDV, VIN = TBDV) -10 +10 µA
CLK_IN
IIH 37 114 µA
IIL 38 97 µA
VOH (Vcc = TBDV, VIH = TBDV, VIL = TBDV, IOH = max) 0.9*VDDIO V
VOL (Vcc = TBDV, VIH = TBDV, VIL = 0.2V, IOH = max) 0.1*VDDIO V
IOL (Vcc = TBDV) 500 µA mA
IOH (Vcc = TBDV) -1.5 mA mA
CI (Input Capacitance) All signals except for
HOST_CLK/PCI_CLK, CLK_IN, and IDSEL 10 pF
CCLK (HOST_CLK and CLK_IN pin capacitance)
Pin inductance 5 12
20 pF
nH
PCI LOGIC (see PCI spec 3.3V signaling environment)
C
I
(Input Capacitance) all PCI except PCI_CLK/HOST_CLK
& IDSEL
10 pF
CI (Input Capacitance) PCI_CLK/HOST_CLK 5 12 pF
CI (Input Capacitance) IDSEL 20 pF
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
• Logic +3.3V (VDDIO)
• Logic +3.3V (VDDIO) Ramp Rate 3.0
3.3
3.6
1.85 V
V/µs
• Core and PLL +1.8V (VCORE and VPLL)
• Core and PLL +1.8V (VCORE and VPLL) Ramp Rate 1.65
1.8
1.95
1.85 V
V/µs
Transceivers +3.3V 3.135 3.3 3.465 V
Current Drain (Total Hybrid) (Note 10)
3.3V (I/O and transceiver) (Note 10):
• Idle
40
mA
• 25% Duty Transmitter Cycle 214 mA
• 50% Duty Transmitter Cycle 344 mA
• 100% Duty Transmitter Cycle
1.8V (logic core) (Note 10)
624
160 mA
mA
OVERVIEW
Data Device Corporation DS-BU-67301B-E
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Table 1. Total-AceXtreme™ Series Specifications
PARAMETER MIN TYP MAX UNITS
POWER DISSIPATION: TOTAL HYBRID (Note 10)
• Idle 0.42 W
• 25% Duty Transmitter Cycle 0.58 W
• 50% Duty Transmitter Cycle 0.70 W
• 100% Duty Transmitter Cycle 0.90 W
POWER DISSIPATION: TRANSCEIVER CHIP (Note 10)
• Idle 0.09 W
• 25% Duty Transmitter Cycle 0.23 W
• 50% Duty Transmitter Cycle 0.33 W
• 100% Duty Transmitter Cycle 0.50 W
CLOCK INPUTS
PCI CLOCK INPUT FREQUENCY 0 66 MHz
HOST_CLK (CPU) CLOCK INPUT FREQUENCY 0 80 MHz
CLOCK_IN (MIL-STD-1553) FREQUENCY
• Nominal Value 40 MHz
Long Term Tolerance
• 1553A Compliance 0.01 -0.01 %
• 1553B Compliance 0.10 -0.10 %
Short Term Tolerance, 1 second
• 1553A Compliance -0.001
0.001 %
• 1553B Compliance -0.01
0.001 %
Duty Cycle 40
60 %
Jitter Tolerance
100 Ps
1553 MESSAGE TIMING
BC Intermessage Gap (Note 7) 10 µs
BC/RT/MT No-Response Timeout mid-parity-to-mid-sync
programmable range (Note 8)
4 511.5 µs
RT Response Time (mid-parity to mid-sync) 4 7 µs
Transmitter Watchdog Timeout 660.5 µs
THERMAL
TOTAL-ACEXTREME BGA 324-BALL BGA PACKAGE
(See Thermal Management Section)
Active Transceiver
• Junction Temperature (TJ)
• Junction-to-Ambient (θJA via simul atio n) 150
°C
- Per JESD 51-2 standard at 25°C
θJA in Still Air 68.8 °C/W
OVERVIEW
Data Device Corporation DS-BU-67301B-E
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Table 1. Total-AceXtreme™ Series Specifications
PARAMETER MIN TYP MAX UNITS
THERMAL (Con’t)
- Per JESD 51-6 standard at 25°C
θJA @ 1M/S 52.9 °C/W
θJA @ 2M/S 47.1 °C/W
θJA @ 3M/S 43.6 °C/W
• Junct ion-to-case (θJC via simulation)
- Per JESD 51-12 standard at 25°C
θJC 24.5 °C/W
• Junction-to-board (θJB via simulation)
- Per JESD 51-8
θJB 46.9 °C/W
ALL PACKAGES
Operating Case Temperature
- EXX -40 +100 °C
Storage Temperature -65 +125 °C
SOLDERING
324-BALL BGA PACKAGE
The reflow profile detailed in IPC/JEDEC J-STD-020 is applicable for both the leaded and lead-free versions of Total-
AceXtreme.
PHYSICAL CHARACTERISTICS
Package Body Size
324-ball BGA
• BU-67301B0TXL-E02 0.630 x 0.630 x 0.185 in
(16 x 16 x 4.7) (mm)
PHYSICAL CHARACTERISTICS (con’t)
Moisture and ESD Sensitivity
• Moisture Sensitivity Level MSL-3
• Electrostatic Discharge Sensitivity ESD Class 0
Weight
324-ball BGA 0.105 oz
(3) (g)
OVERVIEW
Data Device Corporation DS-BU-67301B-E
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Table 1. Total-AceXtreme™ Series Specifications
PARAMETER MIN TYP MAX UNITS
Notes:
Notes 1 through 6 are applicable to the Receiver Differential Input Impedance specifications:
1. Specifications include contributions from the transformer, transmitter, and receiver.
2. Impedance parameters are specified directly between pins CHA(B)_1553 and CHA(B)_1553_L of the Total-
AceXtreme hybrid.
3. It is assumed that all power and ground inputs to the package are connected.
4. The specifications are applicable for both unpowered and powered conditions.
5. The specifications assume a 2 volt rms balanced, differential, sinusoidal input. The applicable frequency range is 75
KHz to 1 MHz.
6. Minimum resistance and maximum
capacitance parameters are guaranteed over the operating range, but are not
tested.
7. Typical value for minimum Intermessage gap time. Under software control, this may be lengthened (to 65,535 µs -
message time) in increments of 1 μs.
8. In 0.5 μS increments with a resolution of ±12 μS.9. Measured from mid-parity crossing of Command Word to mid-
sync crossing of RT's Status Word.
9. MIL-STD-1760 requires a 20 VPK-PK minimum output on the stub connection.
10.
Power supply currents and power dissipation assume nominal supply voltages, 1.8V and 3.3V. Power Dissipation is
the input power consumption minus the power delivered to the 1553 fault isolation resistors, bus termination
resistors, and the c
opper losses in the bus coupling transformer. This power is assumed to be approximately 1.5
Watts when the Total-AceXtreme is transmitting.
2.3 Additi ona l Support Docume nt s
This data sheet has been written to address the implementation of the Total-
AceXtreme device on a PC board and specify the device operational and functional
modes. Additional information about MIL-STD-1553, the MIL-STD-1553 core
(AceXtreme), and/or internal register/memory information is available, including the
following:
The DDC MIL -STD-1553 Designer’s Guide
MIL-STD-1553B Specification
MIL-STD-1553 Handbook
IRIG 106 Chapter 10 Specification
DDC BGA User’s Guide
BU-69092SX AceXtreme C SDK Software Reference Manual
BU-69092SX AceXtreme C SDK Software User's Manual
Total-AceXtreme™ IBIS Model
Total-AceXtreme JTAG/BSDL File
Total-AceXtreme OrCad Schem at ic Sym bol
Total-AceXtreme CAD Drawing/Layout Footprint for PADS
Total-AceXtreme CAD Drawing/Layout Footprint for Allegro
MTBF Prediction Report
OVERVIEW
Data Device Corporation DS-BU-67301B-E
www.ddc-web.com 2/12
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BC Validation Test Report
RT Validation Test Report
AceXtreme Architectural Manual (Contact Factory)
2.4 Total-AceXtreme™ Developm ent Kit
DDC offers a Development Kit for the BU-67301 Total-AceXtreme component. This
kit contains a PCI Evaluation Card to allow easy integration of the BU-67301
component into a standard desktop personal computer. The Evaluation Card brings
the various configuration, control, and other I/O signals of the Total-AceXtreme to
switches, headers, and LEDs, as appropriate to allow the user to experiment with the
various features that the component offers. The Development Kit also includes
various reference data to aid in designing systems around the Total-AceXtreme
component.
Contents:
Total-AceXtreme PCI evaluation car d.
BU-69092S Sof tware Dev elopm ent Kit (SDK)
BU-69066S0 BusTrACEr Software
Searchable PDF Schematic Reference and Layout Information
FloTherm Thermal Model
IBIS Model
JTAG/B SDL File
OrCad Schematic Symbol
CAD Drawing/Layout Footprint for PADS
CAD Drawing/Layout Footprint for Allegro
MTBF Prediction Report
BC Valid ation Test Report
RT Validation Test Report
Product Brief
Data Sheet
SDK Usage Document
SDK Manual
Evaluation Card Quick Start Guide
Evaluation Card Hardware Manual
Data Device Corporation 14 DS-BU-67301B-E
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3 MIL-STD-1553 MODES AND ARCHITECTURE
3.1 Bus Control ler Mode
The Total-AceXtreme’s MIL-STD-1553 Bus Controller (BC) is based on the 32-bit
architecture of DDC’s AceXtreme 1553 Bus Contr ol ler .
Total-AceXtreme’s BC architecture retains much of the previous generation
(Enhanced Mini-ACE, Mini-A CE Mark 3, Mi c ro-ACE (TE), and Total-ACE) 1553 Bus
Controller architecture. However, it expands upon it in specific areas to provide
improved capabilities. The top-level BC design, shown in Fig ur e 3, includes the
Command Interpreter, Low and High Priority Queues (LPQ and HPQ respectively),
1553 Protoc ol engine, and Gener al Pur pose Q ueu e (GPQ) .
The Total-AceXtreme™ BC architec tur e is b as ed on a built-in command interpreter
with a set of 32 instructions. The command interpreter is a message sequence
control engine that provides a high degree of flexibility for implementing 1553
Message lists, including major and minor frame scheduling. It separates 1553
message data from control/status data for the purposes of implementing different
data block handling schemes, performing bulk data transfers, and implementing
automatic message retries. It also includes the capability for automatic bus
switchover for failed messages and reporting of various error and status conditions to
the host proces sor by means of five user-defined interrupts and a general-purpose
queue.
Two Asynchronous queues are also included, to improve the Bus Controller’s
efficiency and flexibility. The High Priority Queue (HPQ) enables the user to easily
insert asynchronous messages into a running Message list, causing it to operate on
the new message immediately. The Low Priority Queue (LPQ) enables the user to
insert asynchronous messages which will only be processed when there’s sufficient
“dead-time” available on the bus at the end of a minor frame.
The Total-AceXtreme’s BC Engine implements all MIL-STD-1553B m es sage
formats. Message format is programmable on a message-by-message basis.
Automatic retries and interrupt requests may be enabled or disabled for each
individual messages. The BC performs all error checking required by MIL-STD-
1553B. This includes validation of response time, sync type and sync encoding,
Manchester II encoding, parity, bit count, word count, Status Word RT Address field,
and various RT-to-RT transfer errors. The BC No-Response timeout v al ue is als o
programmable to enable operation over long buses or through repeaters.
MIL-STD-1553 MODES AND ARCHITECTURE
Data Device Corporation DS-BU-67301B-E
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15
Figure 3. Bus Controll er Block Diagram
3.2 Remote Terminal Operation
The Total-AceXtreme™ RT architecture builds upon the single-RT architecture of
Enhanced Mini-ACE, Mini-ACE Mark 3, Micro-ACE(TE), and Total-ACE.
One of the major new features of Total-AceXtreme is its Multi-RT capability. That is,
the Total-AceXtreme provides the cap abil i ty to implement up to 31 independent
Remote Terminals (up to 32 RTs if Broadcast is disabled).
The Total-AceXtreme -RT engine can also be configured to operate in a Single-RT
legacy mode of operation. Single-RT operation supports hardware control of the RT
address and automatic boot, allowing the Total-AceXtreme to respond to c om m ands
with Status with its Busy bit set immediately following power turn-on without requiring
configuration by the host.
For RT (and/or Monitor) applications, where the possibility of BC operation must be
absolutely prohibited, the Total-AceXtreme includes a DISABLE_BC input signal. In
BC Block
Shared RAM (Applicable Logical Areas Highlighted)
Command Interpreter
LP Queue
Controller
HP Queue
Controller
BC Registers
1553 BC
Protocol
Engine
Instruction
List
(ICL)
Message
Blocks
(MB)
Data
Blocks
(DB)
HP Queue
(HPQ)LP Queue
(LPQ)
General
Purpose Flags
(GPF)
General
Purpose
Queue
(GPQ)
1553_IN_A
1553_IN_B
1553_OUT_A
1553_OUT_B
REG Interface
Memory Bus (32-Bit)
ICL
GPQ
HPQ
LPQ
MB/DB
MEM Interface
EXT_TRIG
GPQ Controller
Message Timer (16 bits)
1us
Delay Timer (16 bits)
1us
MIL-STD-1553 MODES AND ARCHITECTURE
Data Device Corporation DS-BU-67301B-E
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addition to single-RT and Multi-RT operat ion, the Total-AceXtreme™ includes the
followin g capabilities:
Meets MIL-STD-1553A, MIL-STD-1553B, MIL-STD-1760, and STANAG
3838 standards.
Multiple Data Handling Modes:
- Single Buff er Mod e
- Double Buff er Mod e
- Circular Buffer Mode
- Global Circular Buffer
Command Illegalization by Subaddress/Word Count, and Mode Codes
Program m able Bus y by Subaddr es s
Flexible Interrupt Conditions, Including 50% and 100% Rollover Interrupts
for Circular Buffers
Interrupt Status Queue with Programmable Filtering
Time Tagging Options for Sync hroni z e M ode C odes
Option for RT Auto-Boot with Busy bit Set