SN54LV574A, SN74LV574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS412I − APRIL 1998 − REVISED APRIL 2005
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D2-V to 5.5-V VCC Operation
DMax tpd of 10 ns at 5 V
DTypical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
DTypical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
DSupport Mixed-Mode Voltage Operation on
All Ports
DIoff Supports Partial-Power-Down Mode
Operation
DLatch-Up Performance Exceeds 250 mA Per
JESD 17
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN54LV574A . . . FK PACKAGE
(TOP VIEW)
SN54LV574A ...J OR W PACKAGE
SN74LV574A . . . DB, DGV, DW, NS,
OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
3212019
910111213
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2D
1D
OE
8Q
7Q 1Q
8D
GND
CLK
VCC
SN74LV574A . . . RGY PACKAGE
(TOP VIEW)
120
10 11
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1D
2D
3D
4D
5D
6D
7D
8D
OE
CLK V
GND
CC
description/ordering information
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN − RGY Reel of 1000 SN74LV574ARGYR LV574A
SOIC DW
Tube of 25 SN74LV574ADW
LV574A
SOIC − DW Reel of 2000 SN74LV574ADWR LV574A
SOP − NS Reel of 2000 SN74LV574ANSR 74LV574A
40°Cto85°C
SSOP − DB Reel of 2000 SN74LV574ADBR LV574A
−40°C to 85°CTube of 70 SN74LV574APW
TSSOP − PW Reel of 2000 SN74LV574APWR LV574A
TSSOP
PW
Reel of 250 SN74LV574APWT
LV574A
TVSOP − DGV Reel of 2000 SN74LV574ADGVR LV574A
VFBGA − GQN Reel of 1000 SN74LV574AGQNR LV574A
CDIP − J Tube of 20 SNJ54LV574AJ SNJ54LV574AJ
−55°C to 125°CCFP − W Tube of 85 SNJ54LV574AW SNJ54LV574AW
LCCC − FK Tube of 55 SNJ54LV574AFK SNJ54LV574AFK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright © 2005, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LV574A, SN74LV574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS412I − APRIL 1998 − REVISED APRIL 2005
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
The ’LV574A devices are octal edge-triggered D-type flip-flops designed for 2-V to 5.5-V VCC operation.
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data
(D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
terminal assignments
1234
A1D OE VCC 1Q
B3D 3Q 2D 2Q
C5D 4D 5Q 4Q
D7D 7Q 6D 6Q
EGND 8D CLK 8Q
FUNCTION TABLE
(each flip-flop)
INPUTS OUTPUT
OE CLK D
OUTPUT
Q
L↑H H
L↑LL
LH or L X Q0
H X X Z
GQN PACKAGE
(TOP VIEW)
1234
A
B
C
D
E
SN54LV574A, SN74LV574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS412I − APRIL 1998 − REVISED APRIL 2005
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
OE
CLK
1D
1Q
To Seven Other Channels
C1
1
11
2
19
1D
Pin numbers shown are for the DB, DGV, DW, FK, J, NS, PW, RGY, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range applied in the high or low state, VO (see Notes 1 and 2) −0.5 V to VCC + 0.5 V. . . . . .
Input clamp current, IIK (VI < 0) −20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): DGV package 92°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): GQN package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 4): RGY package 37°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
SN54LV574A, SN74LV574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS412I − APRIL 1998 − REVISED APRIL 2005
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 5)
SN54LV574A SN74LV574A
UNIT
MIN MAX MIN MAX UNIT
VCC Supply voltage 2 5.5 2 5.5 V
VCC = 2 V 1.5 1.5
V
High level input voltage
VCC = 2.3 V to 2.7 V VCC ×0.7 VCC ×0.7
V
VIH High-level input voltage VCC = 3 V to 3.6 V VCC ×0.7 VCC ×0.7 V
VCC = 4.5 V to 5.5 V VCC ×0.7 VCC ×0.7
VCC = 2 V 0.5 0.5
V
Low level input voltage
VCC = 2.3 V to 2.7 V VCC ×0.3 VCC ×0.3
V
VIL Low-level input voltage VCC = 3 V to 3.6 V VCC ×0.3 VCC ×0.3 V
VCC = 4.5 V to 5.5 V VCC ×0.3 VCC ×0.3
VIInput voltage 0 5.5 0 5.5 V
V
Output voltage
High or low state 0 VCC 0 VCC
V
VOOutput voltage 3-state 0 5.5 0 5.5 V
VCC = 2 V −50 −50 μA
I
High level output current
VCC = 2.3 V to 2.7 V −2 −2
IOH High-level output current VCC = 3 V to 3.6 V −8 −8 mA
VCC = 4.5 V to 5.5 V −16 −16
mA
VCC = 2 V 50 50 μA
I
Low level output current
VCC = 2.3 V to 2.7 V 2 2
IOL Low-level output current VCC = 3 V to 3.6 V 8 8 mA
VCC = 4.5 V to 5.5 V 16 16
mA
VCC = 2.3 V to 2.7 V 200 200
Δt/ΔvInput transition rise or fall rate VCC = 3 V to 3.6 V 100 100 ns/V
Δt/Δv
Input
transition
rise
or
fall
rate
VCC = 4.5 V to 5.5 V 20 20
ns/V
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
SN54LV574A SN74LV574A
UNIT
PARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN TYP MAX UNIT
IOH = −50 μA2 V to 5.5 V VCC−0.1 VCC−0.1
V
IOH = −2 mA 2.3 V 2 2
V
VOH IOH = −8 mA 3 V 2.48 2.48 V
IOH = −16 mA 4.5 V 3.8 3.8
IOL = 50 μA2 V to 5.5 V 0.1 0.1
V
IOL = 2 mA 2.3 V 0.4 0.4
V
VOL IOL = 8 mA 3 V 0.44 0.44 V
IOL = 16 mA 4.5 V 0.55 0.55
IIVI = 5.5 V or GND 0 to 5.5 V ±1±1μA
IOZ VO = VCC or GND 5.5 V ±5±5μA
ICC VI = VCC or GND, IO = 0 5.5 V 20 20 μA
Ioff VI or VO = 0 to 5.5 V 0 5 5 μA
CiVI = VCC or GND 3.3 V 1.8 1.8 pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV574A, SN74LV574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS412I − APRIL 1998 − REVISED APRIL 2005
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ±0.2 V
(unless otherwise noted) (see Figure 1)
PARAMETER
TA = 25°C SN54LV574A SN74LV574A
UNIT
PARAMETER MIN MAX MIN MAX MIN MAX UNIT
twPulse duration CLK high or low 7 7 7 ns
tsu Setup time High or low before CLK↑5.5 5.5 5.5 ns
thHold time Data after CLK↑2 2 2 ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ±0.3 V
(unless otherwise noted) (see Figure 1)
PARAMETER
TA = 25°C SN54LV574A SN74LV574A
UNIT
PARAMETER MIN MAX MIN MAX MIN MAX UNIT
twPulse duration CLK high or low 5 5 5 ns
tsu Setup time High or low before CLK↑3.5 3.5 3.5 ns
thHold time Data after CLK↑1.5 1.5 1.5 ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ±0.5 V
(unless otherwise noted) (see Figure 1)
PARAMETER
TA = 25°C SN54LV574A SN74LV574A
UNIT
PARAMETER MIN MAX MIN MAX MIN MAX UNIT
twPulse duration CLK high or low 5 5 5 ns
tsu Setup time High or low before CLK↑3.5 3.5 3.5 ns
thHold time Data after CLK↑1.5 1.5 1.5 ns
switching characteristics over recommended operating free-air temperature range,
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO LOAD TA = 25°C SN54LV574A SN74LV574A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE MIN TYP MAX MIN MAX MIN MAX UNIT
f
CL = 15 pF 60* 100* 50* 50
MHz
fmax CL = 50 pF 50 85 40 40 MHz
tpd CLK Q9.6* 16.6* 1* 20* 1 20
ten OE QCL = 15 pF 9.2* 16.1* 1* 19* 1 19 ns
tdis OE Q
CL
15
pF
6.5* 12.8* 1* 15* 1 15
tpd CLK Q11.6 19.6 1 23 1 23
ten OE Q
C50 pF
10.9 19 1 22 1 22
ns
tdis OE QCL = 50 pF 8.4 17.5 1 20 1 20 ns
tsk(o) 2 2
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV574A, SN74LV574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS412I − APRIL 1998 − REVISED APRIL 2005
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO LOAD TA = 25°C SN54LV574A SN74LV574A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE MIN TYP MAX MIN MAX MIN MAX UNIT
f
CL = 15 pF 80* 145* 65* 65
MHz
fmax CL = 50 pF 50 120 45 45 MHz
tpd CLK Q6.8* 13.2* 1* 15.5* 1 15.5
ten OE QCL = 15 pF 6.4* 12.8* 1* 15* 1 15 ns
tdis OE Q
CL
15
pF
4.8* 13* 1* 15* 1 15
tpd CLK Q8.1 16.7 1 19 1 19
ten OE Q
C50 pF
7.7 16.3 1 18.5 1 18.5
ns
tdis OE QCL = 50 pF 6.1 15 1 17 1 17 ns
tsk(o) 1.5 1.5
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO LOAD TA = 25°C SN54LV574A SN74LV574A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE MIN TYP MAX MIN MAX MIN MAX UNIT
f
CL = 15 pF 130* 205* 110* 110
MHz
fmax CL = 50 pF 85 175 75 75 MHz
tpd CLK Q4.8* 8.6* 1* 10* 1 10
ten OE QCL = 15 pF 4.6* 9* 1* 10.5* 1 10.5 ns
tdis OE Q
CL
15
pF
3.5* 9* 1* 10.5* 1 10.5
tpd CLK Q5.7 10.6 1 12 1 12
ten OE Q
C50 pF
5.5 11 1 12.5 1 12.5
ns
tdis OE QCL = 50 pF 4.1 10.1 1 11.5 1 11.5 ns
tsk(o) 1 1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 6)
PARAMETER
SN74LV574A
UNIT
PARAMETER MIN TYP MAX UNIT
VOL(P) Quiet output, maximum dynamic VOL 0.7 0.8 V
VOL(V) Quiet output, minimum dynamic VOL −0.6 −0.8 V
VOH(V) Quiet output, minimum dynamic VOH 2.8 V
VIH(D) High-level dynamic input voltage 2.31 V
VIL(D) Low-level dynamic input voltage 0.99 V
NOTE 6: Characteristics are for surface-mount packages only.
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
C
Power dissipation capacitance
Outputs enabled
C=50pF
f = 10 MHz
3.3 V 20.4
pF
Cpd Power dissipation capacitance Outputs enabled CL = 50 pF, f = 10 MHz 5 V 23.8 pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV574A, SN74LV574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS412I − APRIL 1998 − REVISED APRIL 2005
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VCC
0 V
50% VCC VOL + 0.3 V
50% VCC ≈0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST S1
VCC
0 V
50% VCC
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1
VCC
RL = 1 kΩ
GND
From Output
Under Test
CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
50% VCC
50% VCC 50% VCC
50% VCC
50% VCC 50% VCC
50% VCC 50% VCC
VOH − 0.3 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 1-Aug-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74LV574ADBR ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574ADBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574ADBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574ADGVRE4 ACTIVE TVSOP DGV 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574ADGVRG4 ACTIVE TVSOP DGV 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574ADW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574ADWE4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574ADWR ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574ADWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574AGQNR OBSOLETE BGA
MICROSTAR
JUNIOR
GQN 20 TBD Call TI Call TI
SN74LV574ANSR ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574ANSRE4 ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574ANSRG4 ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 1-Aug-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74LV574APW ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574APWE4 ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574APWR ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574APWT ACTIVE TSSOP PW 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574APWTE4 ACTIVE TSSOP PW 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574APWTG4 ACTIVE TSSOP PW 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV574ARGYR ACTIVE VQFN RGY 20 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74LV574ARGYRG4 ACTIVE VQFN RGY 20 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74LV574AZQNR ACTIVE BGA
MICROSTAR
JUNIOR
ZQN 20 1000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PACKAGE OPTION ADDENDUM
www.ti.com 1-Aug-2011
Addendum-Page 3
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LV574ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74LV574ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV574ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
SN74LV574ANSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1
SN74LV574APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74LV574APWT TSSOP PW 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74LV574ARGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1
SN74LV574AZQNR BGA MI
CROSTA
R JUNI
OR
ZQN 20 1000 330.0 12.4 3.3 4.3 1.5 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jul-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LV574ADBR SSOP DB 20 2000 346.0 346.0 33.0
SN74LV574ADGVR TVSOP DGV 20 2000 346.0 346.0 29.0
SN74LV574ADWR SOIC DW 20 2000 346.0 346.0 41.0
SN74LV574ANSR SO NS 20 2000 346.0 346.0 41.0
SN74LV574APWR TSSOP PW 20 2000 346.0 346.0 33.0
SN74LV574APWT TSSOP PW 20 250 346.0 346.0 33.0
SN74LV574ARGYR VQFN RGY 20 3000 346.0 346.0 29.0
SN74LV574AZQNR BGA MICROSTAR
JUNIOR ZQN 20 1000 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jul-2011
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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