Integrated Circuit Systems, Inc. ICS9148-60 Pentium/ProTM System Clock Chip General Description Features The ICS9148-60 is part of a reduced pin count two-chip clock solution for designs using an Intel BX style chipset. Companion SDRAM buffers are ICS9179-11 and 12. There are two PLLs, with the first PLL capable of spread spectrum operation. Spread spectrum typically reduces system EMI by 8-10dB. The second PLL provides support for USB (48MHz) and 24MHz requirements. CPU frequencies up to 100MHz are supported. The I2C interface allows stop clock programming, frequency selection, and spread spectrum operation to be programmed. Clock outputs include two CPU (2.5V or 3.3V), seven PCI (3.3V), one REF (3.3V), one IOAPIC (2.5V or 3.3V), one 48MHz, and one selectable 48_24MHz. Generates system clocks for CPU, PCI, IOAPIC , 14.314 MHz, 48 and 24MHz. Supports single or dual processor systems Skew from CPU (earlier) to PCI clock 1 to 4ns Separate 2.5V and 3.3V supply pins 2.5V outputs: CPU, IOAPIC 3.3V outputs: PCI, REF No power supply sequence requirements 28 pin SOIC and SSOP Spread Spectrum operation optional for PLL1 CPU frequencies to 100MHz are supported. Pin Configuration Block Diagram 28 pin SOIC and SSOP Power Groups VDD = Supply for PLL core VDD1 = REF0, X1, X2 VDD2 = PCICLK_F, PCICLK (0:5) VDD3 = 48MHz VDDL = CPUCLK (0:1) VDDL1=IOAPIC Ground Groups GND = Ground Source Core GND1 = REF0, X1, X2 GND2 = PCICLK_F, PCICLK (0:5) GND3=48MHz GNDL = CPUCLK (0:1) Pentium is a trademark on Intel Corporation. 9148-60 Rev D 10/19/99 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9148-60 Pin Descriptions PIN NUMBER PIN NAME TYPE 1 X1 IN 2 3 4 5, 6, 7, 8, 10, 11 6, 9 12 13 X2 GND2 PCICLK_F PCICLK (0:5) VDD2 VDD3 48MHz OUT PWR OUT OUT PWR PWR OUT 14 24_48MHz OUT 15 GND3 PWR 16 SEL100/66.6# IN 17 18 19 20 21, 22 23 24 25 26 SCLK SDATA GND VDD CPUCLK (1:0) VDDL IOAPIC VDDL VDD1 REF0 SEL48# GND1 IN IN PWR PWR OUT PWR OUT PWR PWR OUT IN PWR 27 28 DESCRIPTION XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap and feed back resistor from X2 XTAL_OUT Crystal output, has internal load cap 33pF Ground for PCI outputs Free Running PCI output PCI clock outputs. TTL compatible 3.3V Power for PCICLK outputs, nominally 3.3V Poer for 48MHz Fixed CLK output @ 48MHz Fixed CLK output; 24MHz if pin 27 =1 at power up, 48MHz if pin 27=0 at power up. Ground for 48MHz Select pin for enabling 100MHz or 66.6MHz H=100MHz, L=66.6MHz (PCI always synchronous 33.3MHz) Clock input for I2 C input Data input for I2 C input Ground for CPUCLK (0:1) Power for PLL core CPU and Host clock outputs nominally 2.5V Power for CPU outputs, nominally 2.5V IOAPIC clock output 14.318MHz. Power for IOAPIC Power for REF outputs. 14.318MHz clock . Output/Latched input at power up. When low, pin 14 is 48MHz Ground for REF outputs, X1, X2. 2 ICS9148-60 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Byte 6 Byte 6 Stop Bit Notes: 1. 2. 3. 4. 5. 6. ICS (Slave/Receiver) The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 3 ICS9148-60 Serial Bitmap Byte 3: Functionality & Frequency Select & Spread Slect Register Bit Description 0: Center Spread (0.25) 7 1: Down Spread (0 to -0.6%) Bit CPU PCI 654 34.25 68.5 000 37.5 75.0 001 41.6 83.3 010 6:4 33.3 66.6 011 34.3 103 100 37.3 112 101 44.43 133.3 110 33.33 100 111 0 - Frequency is selected by 3 hardware select SEL100/66.6# 1 - Frequency is selected by 6:4 above 2 (Reserved) 00 - Normal operation 01 - Test mode 10 10 - Spread sprectrum ON 11 - Tristate all outputs Byte 5: PWD 0 0 0 Bit Pin# Pin Name PWD 7 4 PCICLK_F 1 6 11 PCICLK5 1 5 10 PCICLK4 1 4 - - 0 3 8 PCICLK3 1 2 7 PCICLK2 1 1 6 PCICLK1 1 0 5 PCICLK0 1 Description Bit Value = 0 Bit Value = 1 Disabled Enabled (low) Disabled Enabled (low) Disabled Enabled (low) (Reserved) (Reserved) Disabled Enabled (low) Disabled Enabled (low) Disabled Enabled (low) Disabled Enabled (low) Notes: 1 = Enabled; 0 = Disabled, outputs held low 00 Notes: 1 = Enabled; 0 = Disabled, outputs held low Byte 4: Byte 6: Bit Pin# Pin Name PWD 7 6 5 4 3 - - - 2 21 CPUCLK1 1 1 - - 0 0 22 CPUCLK0 1 Description Bit Value = 0 Bit Value = 1 (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Disabled Enabled (low) (Reserved) (Reserved) (Disabled) Enabled (low) Notes: 1 = Enabled; 0 = Disabled, outputs held low Bit Pin# Pin Name PWD 7 6 - - 0 0 5 24 IOAPIC 1 4 3 2 - - 0 0 0 1 27 REF0 1 0 27 REF0 1 Description Bit Value = 0 Bit Value = 1 (Reserved) (Reserved) (Reserved) (Reserved) Disabled Enabled (low) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Disabled) Enabled (low) (Disabled) Enabled (low) Notes: 1 = Enabled; 0 = Disabled, outputs held low Note: PWD = Power-Up Default For pin 27, there are 2 output stages together for 1 pin. These 2 latches must be both 0 or 1 simultaneously or there will be a short to ground if one is disabled and the other is running. 4 ICS9148-60 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 7.0 V GND 0.5 V to VDD +0.5 V 0C to +70C 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL Input High Voltage VIH Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency VIL IIH IIL1 IIL2 Input Capacitance 1 1 Transition Time Settling Time 1 Clk Stabilization 1 Skew1 1 IDD3.3OP66 IDD3.3OP100 IDD3.3PD Fi C IN C INX Ttrans Ts TSTAB T AGP-PCI1 CONDITIONS VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors C L = 0 pF; Select @ 66MHz C L = 0 pF; Select @ 100MHz MIN TYP MAX UNITS 2 VDD+0.3 V VSS-0.3 0.8 5 -5 -200 C L = 0 pF; With input address to Vdd or GND VDD = 3.3 V; Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. VT = 1.5 V; 0.1 2.0 -100 60 66 170 170 V A A A mA mA 3 650 A 14.318 27 36 5 45 3 5 1 3.5 3 4 MHz pF pF ms ms ms ns Guaranteed by design, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current Power Down Supply Current 1 Skew 1 SYMBOL IDD2.5OP 66 IDD2.5OP 100 CONDITIONS CL = 0 pF; Select @ 66.8 MHz CL = 0 pF; Select @ 100 MHz IDD2.5PD CL = 0 pF; With input address to Vdd or GND tCP U-AGP tCP U-P CI2 VT = 1.5 V; VTL = 1.25 V MIN 0 1 Guaranteed by design, not 100% tested in production. 5 TYP 16 23 MAX 72 100 UNITS mA mA 10 100 A 0.5 2.6 1 4 ns ns ICS9148-60 Electrical Characteristics - CPUCLK TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time SYMBOL VOH2B VOL2B IOH2B IOL2B Fall Time tf2B1 VOH = 2.0 V, VOL = 0.4 V Duty Cycle d t2B1 tsk2B1 VT = 1.25 V tjcyc-cyc2B1 tj1s2B1 tjabs2B1 Skew Jitter, Cycle-to-cycle Jitter, One Sigma Jitter, Absolute 1 tr2B 1 CONDITIONS IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V MIN 2 19 TYP 2.3 0.2 -41 37 1.25 MAX UNITS V 0.4 V -19 mA mA 1.6 ns 1 1.6 ns 48 55 % VT = 1.25 V 30 175 ps VT = 1.25 V 150 250 ps VT = 1.25 V 40 150 ps -250 140 +250 ps MIN 2.4 TYP 3.1 0.1 -62 57 1.5 1.1 50 140 17 70 45 VT = 1.25 V Guaranteed by design, not 100% tested in production. Electrical Characteristics - PCICLK TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current 1 Rise Time Fall Time1 Duty Cycle1 Skew1 Jitter, One Sigma1 Jitter, Absolute1 1 SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tsk1 tj1s1 tjabs1 CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V Guaranteed by design, not 100% tested in production. 6 16 45 -500 MAX UNITS V 0.4 V -22 mA mA 2 ns 2 ns 55 % 500 ps 150 ps 500 ps ICS9148-60 Electrical Characteristics - IOAPIC TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current CONDITIONS IOH = -18 mA IOL = 18 mA VOH = 1.7 V VOL = 0.7 V MIN 2 29 TYP 2.2 0.33 -41 37 MAX UNITS V 0.4 V -28 mA mA 1 Tr4B VOL = 0.4 V, VOH = 2.0 V 1.3 1.6 ns 1 Tf4B VOH = 2.0 V, VOL = 0.4 V 1.1 1.6 ns Dt4B VT = 1.25 V 54 55 % tsk4B1 VT = 1.25 V 60 250 ps Jitter, One Sigma Tj1s4B VT = 1.25 V 1 3 % 1 Tjabs4B VT = 1.25 V 5 % Rise Time Fall Time Duty Cycle Skew1 1 1 Jitter, Absolute 1 SYMBOL VOH4B VOL4B IOH4B IOL4B 45 -5 Guaranteed by design, not 100% tested in production. Electrical Characteristics - REF TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 Jitter, One Sigma Jitter, Absolute 1 1 1 SYMBOL VOH5 VOL5 IOH5 IOL5 CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V MIN 2.6 29 TYP 3.1 0.17 -44 42 MAX UNITS V 0.4 V -22 mA mA tr5 VOL = 0.4 V, VOH = 2.4 V 1.4 2 ns tf5 VOH = 2.4 V, VOL = 0.4 V 1.1 2 ns d t5 VT = 1.5 V 54 57 % tj1s5 VT = 1.5 V 1 3 % tjabs5 VT = 1.5 V 3 5 % 47 Guaranteed by design, not 100% tested in production. 7 ICS9148-60 Electrical Characteristics - 48, 24 MHz TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V MIN 2.6 16 TYP 3 0.14 -44 42 MAX UNITS V 0.4 V -22 mA mA 1 tr5 VOL = 0.4 V, VOH = 2.4 V 1.2 4 ns 1 tf5 VOH = 2.4 V, VOL = 0.4 V 1.2 4 ns dt5 VT = 1.5 V 52 55 % tj1s5 VT = 1.5 V 1 3 % tjabs5 VT = 1.5 V 3 5 % Rise Time Fall Time Duty Cycle 1 Jitter, One Sigma Jitter, Absolute 1 SYMBOL VOH5 VOL5 IOH5 IOL5 1 1 45 Guaranteed by design, not 100% tested in production. 8 ICS9148-60 SOIC Package LEAD COUNT 28L DIMENSION L 0.704 Ordering Information ICS9148yM-60 Example: ICS XXXX y M - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type M = SOIC Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 9 ICS9148-60 COMMON DIMENSIONS SYMBOL D VARIATIONS MIN. NOM. MAX. N MIN. NOM. MAX. A 0.068 0.073 0.078 14 0.239 0.244 0.249 A1 0.002 0.005 0.008 16 0.239 0.244 0.249 A2 0.066 0.068 0.070 20 0.278 0.284 0.289 b 0.010 0.012 0.015 24 0.318 0.323 0.328 c 0.004 0.006 0.008 28 0.397 0.402 0.407 30 0.397 0.402 0.407 D E See Variations 0.205 e 0.209 0.212 0.0256 BSC H 0.301 0.307 0.311 L 0.025 0.030 0.037 N SSOP Package Dimensions in inches See Variations 0 4 8 Ordering Information ICS9148yF-60 Example: ICS XXXX y F - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 10 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.