1. General description
The PCA9542A is a 1-of-2 bidirectional translating multiplexer, controlled via the I2C-bus.
The SCL/SDA upstream pair fans out to two SCx/SDx downstream pairs, or channels.
Only one SCx/SDx channel is selected at a time, determined by the contents of the
programmable control register. Two interrupt inputs, INT0 and INT1, one for each of the
SCx/SDx downstream pairs, are provided. One interrupt output, INT, which acts as an
AND of the two interrupt inputs, is provided.
A power-on rese t function puts the r egisters in their default state and initializes the I2C-bus
state machine with no channels selected.
The pass gates of the multiplexer are constructed such that the VDD pin can be used to
limit the maximum high voltage which will be passed by the PCA9542A. This allows the
use of dif ferent bus volt ages on each SCx/SDx pair, so tha t 1.8 V, 2.5 V, or 3.3 V p arts ca n
communicate with 5 V parts without any addition al pr ot ec tion . Exte rn a l pull-up res isto rs
pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
2. Features and benefits
1-of-2 bidirectional translating multiplexer
I2C-bus interface logic; compatible with SMBus
2 active LOW interrupt inputs (INT0, INT1)
Active LOW interrupt output (INT)
3 address pins allowing up to 8 devices on the I2C-bus
Channel selection via I2C-bus
Powers up with all multiplexer channe ls deselected
Low Ron switches
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
No glitch on power-up
Supports hot insertion
Low standby current
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: SO14, TSSOP14
PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
Rev. 5.1 — 15 July 2015 Product data sheet
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Product data sheet Rev. 5.1 — 15 July 2015 2 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
3. Ordering information
3.1 Ordering options
Table 1. Ordering information
Type number Topside
marking Package
Name Description Version
PCA9542AD PCA9542AD SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
PCA9542APW PA9542A TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm SOT402-1
Table 2. Ordering options
Type number Orderable
part number Package Packing method Minimum
order
quantity
Temperature range
PCA9542AD PCA9542AD,112 SO14 Standard marking
*IC’s tube - DSC bulk pack 1140 Tamb = 40 C to +85 C
PCA9542AD,118 SO14 Reel 13” Q1/T1
*Standard mark SMD 2500 Tamb = 40 C to +85 C
PCA9542APW PCA9542APW,112 TSSOP14 Standard marking
*IC’s tube - DSC bulk pack 2400 Tamb = 40 C to +85 C
PCA9542APW,118 TSSOP14 Reel 13” Q1/T1
*Standard mark SMD 2500 Tamb = 40 C to +85 C
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Product data sheet Rev. 5.1 — 15 July 2015 3 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
4. Block diagram
Fig 1. Block diagram of PCA9542A
SWITCH CONTROL LOGIC
PCA9542A
POWER-ON
RESET
002aae303
SD1
VSS
VDD
I2C-BUS
CONTROL
INPUT
FILTER
SCL
SDA
A0
A1
A2
SD0
SC1
SC0
INTERRUPT LOGIC
INT[1:0] INT
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Product data sheet Rev. 5.1 — 15 July 2015 4 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 2. Pin configuration for SO14 Fig 3. Pin configuration for TSSOP14
PCA9542AD
A0 VDD
A1 SDA
A2 SCL
INT0 INT
SD0 SC1
SC0 SD1
VSS INT1
002aae301
1
2
3
4
5
6
7 8
10
9
12
11
14
13
PCA9542APW
A0 V
DD
A1 SDA
A2 SCL
INT0 INT
SD0 SC1
SC0 SD1
V
SS
INT1
002aae302
1
2
3
4
5
6
78
10
9
12
11
14
13
Table 3. Pin description
Symbol Pin Description
A0 1 address input 0
A1 2 address input 1
A2 3 address input 2
INT0 4 active LOW interrupt input 0
SD0 5 serial data 0
SC0 6 serial clock 0
VSS 7 supply ground
INT1 8 active LOW interrupt input 1
SD1 9 serial data 1
SC1 10 serial clock 1
INT 11 active LOW interrupt output
SCL 12 serial clock line
SDA 13 serial data line
VDD 14 supply voltage
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Product data sheet Rev. 5.1 — 15 July 2015 5 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
6. Functional description
Refer to Figure 1 “Block diagram of PCA9542A”.
6.1 Device addressing
Following a START condition the bus master must output the address of the slave it is
accessing. The address of the PCA9542A is shown in Figure 4. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
6.2 Control register
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9542A which will be stored in the control register. If multiple bytes are
received by the PCA9542A, it will save the last byte received. This register can be written
and read via the I2C-bus.
6.2.1 Control register definition
A SCx/SDx downstream pair, or channel, is selected by the contents of the control
register. This register is written af ter the PCA9542A has been addressed. The 3 LSBs of
the control byte are used to determine which channel is to be selected. Wh en a channel is
selected, it will become active after a STOP condition has been placed on the I2C-bus.
This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made
active, so that no false conditions are generated at the time of connection.
Bits INT0, INT1, D6 and D7 are all writable, but will read the chip status. INT0 and INT1
indicate the state of the corresponding interrupt input. D7 and D6 always read 0.
See Section 6.3.
Fig 4. Slave address
002aab189
1 1 1 0 A2 A1 A0 R/W
fixed hardware
selectable
Fig 5. Control register
002aae304
X X INT1 INT0 X B2 B1 B0
interrupt bits
(read only) channel selection bits
(read/write)
76543210bit
enable bit
writable,
but always read 0
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Product data sheet Rev. 5.1 — 15 July 2015 6 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
6.3 Interrupt handling
The PCA9542A provides 2 interrupt inputs, one for each channel and one open-drain
interrupt output. When an interrupt is generated by any device, it will be detected by the
PCA9542A and the interrupt output will be driven LOW. The channel need not be active
for detection of the interrupt. A bit is also set in the control byte.
Bits 5:4 of the control byte correspond to channel 1, channel 0 of the PCA9542A,
respectively. Therefore, if an interrupt is generated by any device connected to channel 1,
the state of the interrupt inputs is loaded into th e control register when a read is
accomplished. Likewise, an interrupt on any device connected to channel 0 would cause
bit 4 of the control register to be set on the read. The master can then address the
PCA9542A and read the content s of the contro l byte to de termine which cha nnel cont ains
the device generating the interrupt. The master can then reconfigure the PCA9542A to
select this channel, and locate the device generating the interrupt and clear it.
It should be noted that more than one device can be providing an interrupt on a channel,
so it is up to the master to ensure that all devices on a channel are interro gated for an
interrupt.
The interrupt inputs may be used as general purpose inp uts if the interrupt function is not
required.
If unused, interrupt input(s) must be connected to VDD thro ug h a pu ll-u p resis tor.
Remark: The two interrupts can be active at the same time. D6 and D7 always read 0.
6.4 Power-on reset
When power is applied to VDD, an internal Power-On Rese t (POR) holds the PCA9542A in
a reset condition until VDD has reached VPOR. At this po int, the reset condition is rel eased
and the PCA9542A registers and I2C-bus state machine are initialized to their default
states (all zeroes), causing all the channels to be deselected. Thereafter, VDD must be
lowered below 0.2 V for at least 5 s in order to reset the device.
Table 4. Control register: Write—channel selection; Read—channel status
D7 D6 INT1 INT0 D3 B2 B1 B0 Command
X X X X X 0 X X no ch annel selected
X X X X X 1 0 0 channel 0 enabled
X X X X X 1 0 1 channel 1 enabled
X X X X X 1 1 X no channel selected
0 0 0 0 0 0 0 0 no channel selected;
power-up defa u l t state
Table 5. Control register read — interru pt
D7 D6 INT1 INT0 D3 B2 B1 B0 Command
00X0XXXX
no interrupt on channel 0
1 interrupt on channel 0
000XXXXX
no interrupt on channel 1
1 interrupt on channel 1
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Product data sheet Rev. 5.1 — 15 July 2015 7 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
6.5 Voltage translation
The pass gate tra nsistors of the PCA9542A are constructed such that the VDD volt age can
be used to limit the maximum voltage that will be passed from one I2C-bus to another.
Figure 6 shows the volt age characteristics of the p ass gate transistors (note that the graph
was generated using the data specified in Section 12 “ Dynamic charac teristics” of this
data sh e et) . In or de r for the P CA9 54 2A to act as a voltage translator, the Vo(sw) voltage
should be equal to, or lower than the lowest bus voltage. For examp le, if the main bus was
running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be
equal to or below 2.7 V to effectively clamp the downstream bus voltages. Lo ok ing at
Figure 6, we see that Vo(sw)(max) will be at 2.7 V when the PCA9542A supply voltage is
3.5 V or lower so the PCA9542A supply voltage could be set to 3.3 V. Pull-up resistors
can then be used to bring the bus voltages to their appropriate levels (see Figure 13).
More Information can be found in Application Note AN262, PCA954X family of I2C/SMBus
multiplexers and switches.
(1) maximum
(2) typical
(3) minimum
Fig 6. Pass gate voltage versus supply voltage
VDD (V)
2.0 5.54.53.0 4.0
002aaa964
3.0
2.0
4.0
5.0
Vo(sw)
(V)
1.0 3.5 5.02.5
(1)
(2)
(3)
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Product data sheet Rev. 5.1 — 15 July 2015 8 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
7. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line co mmunication between dif ferent ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Dat a transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data b it is transferred durin g each clock pulse . The data on th e SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 7).
7.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line wh ile the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 8).
7.3 System configuration
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 9).
Fig 7. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 8. Definition of START and STOP conditions
mba608
SDA
SCL P
STOP condition
S
START condition
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Product data sheet Rev. 5.1 — 15 July 2015 9 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
7.4 Acknowledge
The number of data bytes transferred between the START and th e STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bi t is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addresse d must gener ate an acknowledg e af ter the reception of
each byte. Also, a master must generate an acknowle dge after the reception of each byte
that has been clocke d ou t of th e sla v e tr ansmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leav e th e da ta line HIGH to enable the master to generate a STOP
condition.
Fig 9. Syste m co nfi gura t io n
002aaa966
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
I2C-BUS
MULTIPLEXER
SLAVE
Fig 10. Acknowledgement on the I2C-bus
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Product data sheet Rev. 5.1 — 15 July 2015 10 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
7.5 Bus transactions
8. Application design-in information
Fig 11. Write control register
Fig 12. Read control register
002aae299
XXXXXB2B1B01 1 0 A2 A1 A0 0 AS 1 A P
slave address
START condition R/W acknowledge
from slave acknowledge
from slave
control register
SDA
STOP condition
002aae305
XX
INT
1INT
0X B2B1B0
1 1 0 A2 A1 A0 1 AS 1 NA P
slave address
START condition R/W acknowledge
from slave no acknowledge
from master
control register
SDA
STOP condition
last byte
(1) If the device generating the interrupt has an open-drain output structure or can be 3-stated,
a pull-up resistor is required.
If the device generating the interrupt has a totem pole output structure and cannot be 3-stated,
a pull-up resistor is not required.
The interrupt inputs should not be left floating.
Fig 13. Typical application
PCA9542A
SD0
SC0
A1
A0
VSS
SDA
SCL
INT
VDD = 3.3 V
VDD = 2.7 V to 5.5 V
I2C-bus/SMBus master
002aae306
SDA
SCL channel 0
V = 2.7 V to 5.5 V
A2
INT0
(1)
SD1
SC1 channel 1
V = 2.7 V to 5.5 V
INT1
(1)
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Product data sheet Rev. 5.1 — 15 July 2015 11 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
9. Limiting values
[1] The performance capability of a high-perfo rmance integrated circuit in conjunction with its thermal
environment can create junction temperatures which ar e detrimental to reliability. The maximum junction
temperature of this integrated circuit should not exceed 125 C.
10. Thermal characteristics
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to ground (VSS = 0 V).[1]
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +7.0 V
VIinput voltage 0.5 +7.0 V
IIinput current - 20 mA
IOoutput current - 25 mA
IDD supply current - 100 mA
ISS ground supply curren t - 100 mA
Ptot total power dissipation - 400 mW
Tj(max) maximum junction temperature [1] -125C
Tstg storage temperature 60 +150 C
Tamb ambient temperature operating 40 +85 C
Table 7. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction
to ambient SO14 package 127 C/W
TSSOP14 package 175 C/W
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Product data sheet Rev. 5.1 — 15 July 2015 12 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
11. Static characteristics
[1] For operation between published voltage ranges, refer to worst case parameter in both ranges.
[2] VDD must be lowered to 0.2 V for at least 5 s in order to reset part.
Table 8. Static characteristics at VDD =2.3V to 3.6V
VSS =0V; T
amb =
40
C to +85
C; unless otherwise specified. See Table 9 for VDD = 4.5 V to 5.5 V.[1]
Symbol Parameter Conditions Min Typ Max Unit
Supply
VDD supply voltage 2.3 - 3.6 V
IDD supply current operating mode; VDD =3.6V;
no load; VI=V
DD or VSS;
fSCL = 100 kHz
-1030A
Istb standby current standby mode; VDD = 3.6 V; no load;
VI=V
DD or VSS; fSCL = 0 kHz -0.11 A
VPOR power-on reset voltage no load; VI=V
DD or VSS [2] -1.62.1V
Input SCL; input/outpu t S DA
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD -6 V
IOL LOW-level output current VOL =0.4V 3 7 - mA
VOL =0.6V 6 10 - mA
ILleakage current V I=V
DD or VSS 1- +1 A
Ciinput capacitance VI=V
SS -910pF
Select inputs A0, A1, A2, INT0, INT1
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD -6 V
ILI input leakage curren t VI=V
DD or VSS 1- +1 A
Ciinput capacitance VI=V
SS -1.63 pF
Pass gate
Ron ON-state resistance VDD = 3.0 V to 3.6 V; VO=0.4V;
IO=15mA 51130
VDD = 2.3 V to 2.7 V; VO=0.4V;
IO=10mA 71655
Vo(sw) switch output voltage Vi(sw) =V
DD = 3.3 V; Io(sw) =100 A- 1.9- V
Vi(sw) =V
DD = 3.0 V to 3.6 V;
Io(sw) =100 A1.6 - 2.8 V
Vi(sw) =V
DD = 2.5 V; Io(sw) =100 A- 1.5- V
Vi(sw) =V
DD = 2.3 V to 2.7 V;
Io(sw) =100 A1.1 - 2.0 V
ILleakage current V I=V
DD or VSS 1- +1 A
Cio input/output capacitance VI=V
SS -35 pF
INT output
IOL LOW-level output current VOL =0.4V 3 - - mA
IOH HIGH-level output current - - +10 A
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Product data sheet Rev. 5.1 — 15 July 2015 13 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
[1] For operation between published voltage ranges, refer to worst case parameter in both ranges.
[2] VDD must be lowered to 0.2 V for at least 5 s in order to reset part.
Table 9. Static characteristics at VDD =4.5V to 5.5V
VSS =0V; T
amb =
40
C to +85
C; unless otherwise specified. See Table 8 for VDD = 2.3 V to 3.6 V.[1]
Symbol Parameter Conditions Min Typ Max Unit
Supply
VDD supply voltage 4.5 - 5.5 V
IDD supply current operating mode; VDD =5.5V;
no load; VI=V
DD or VSS;
fSCL = 100 kHz
-25100A
Istb standby current standby mode; VDD = 5.5 V; no load;
VI=V
DD or VSS; fSCL = 0 kHz -0.31 A
VPOR power-on reset voltage no load; VI=V
DD or VSS [2] -1.72.1V
Input SCL; input/outpu t S DA
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD -6 V
IOL LOW-level output current VOL =0.4V 3 - - mA
VOL =0.6V 6 - - mA
ILleakage current V I=V
DD or VSS 1- +1 A
Ciinput capacitance VI=V
SS -910pF
Select inputs A0, A1, A2, INT0, INT1
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD -6 V
ILI input leakage curren t VI=V
DD or VSS 1- +1 A
Ciinput capacitance VI=V
SS -25 pF
Pass gate
Ron ON-state resistance VDD = 4.5 V to 5.5 V; VO=0.4V;
IO=15mA 4924
Vo(sw) switch output voltage Vi(sw) =V
DD = 5.0 V; Io(sw) =100 A- 3.6- V
Vi(sw) =V
DD = 4.5 V to 5.5 V;
Io(sw) =100 A2.6 - 4.5 V
ILleakage current V I=V
DD or VSS 1- +1 A
Cio input/output capacitance VI=V
SS -35 pF
INT output
IOL LOW-level output current VOL =0.4V 3 - - mA
IOH HIGH-level output current - - +10 A
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Product data sheet Rev. 5.1 — 15 July 2015 14 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
12. Dynamic characteristics
[1] Pass gate propagation delay is calculated from the 20 typical Ron and the 15 pF load capacitance.
[2] After this period, the first clock pulse is gener ated.
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
[4] Cb= total capacitance of one bus line in pF.
[5] Measurements taken with 1 k pull-up resistor and 50 pF load.
Table 10. Dy namic characteristics
Symbol Parameter Conditions Standard-mode
I2C-bus Fast-mode I2C-bus Unit
Min Max Min Max
tPD propagation delay from SDA to SDx,
or SCL to SCx -0.3
[1] -0.3
[1] ns
fSCL SCL clock frequency 0 100 0 400 kHz
tBUF bus free time between a STOP and
START condition 4.7 - 1.3 - s
tHD;STA hold time (repeated ) START
condition [2] 4.0 - 0.6 - s
tLOW LOW period of the SCL clock 4.7 - 1.3 - s
tHIGH HIGH period of the SCL clock 4.0 - 0.6 - s
tSU;STA set-up time for a repeated START
condition 4.7 - 0.6 - s
tSU;STO set-up time for STOP condition 4.0 - 0.6 - s
tHD;DAT data hold time 0[3] 3.45 0[3] 0.9 s
tSU;DAT data set-up time 250 - 100 - ns
trrise time of both SDA and SCL
signals - 1000 20 + 0.1Cb[4] 300 ns
tffall time of both SDA and SCL
signals -30020+0.1C
b[4] 300 ns
Cbcapacitive load for each bus line - 400 - 400 pF
tSP pulse width of spikes that must be
suppressed by the input filter -50 - 50ns
tVD;DAT data valid time HIGH-to-LOW [5] -1 - 1s
LOW-to-HIGH [5] -0.6 - 0.6s
tVD;ACK data valid acknowledge ti me - 1 - 1 s
INT
tv(INTnN-INTN) valid time from INTn to INT signal [5] -4 - 4s
td(INTnN-INTN) delay time from INTn to INT inactive [5] -2 - 2s
tw(rej)L LOW-leve l re je ct io n time IN Tn inputs [5] 1- 1 -s
tw(rej)H HIGH-level rejection time INTn inputs [5] 0.5 - 0.5 - s
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Product data sheet Rev. 5.1 — 15 July 2015 15 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
Fig 14. Definition of timing on the I2C-bus
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Product data sheet Rev. 5.1 — 15 July 2015 16 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
13. Package outline
Fig 15. Package outline SOT108-1 (SO14)
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PCA9542A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 5.1 — 15 July 2015 17 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
Fig 16. Package outline SOT402-1 (TSSOP14)
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PCA9542A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 5.1 — 15 July 2015 18 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on on e printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
W ave soldering is a joining te chnology in which the joints are m ade by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
•Through-hole components
•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solde r lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads ha ving a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature pr ofile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•Board specifications, including the board finish, solder masks and vias
•Package footprints, including solder thieves and orientation
•The moisture sensitivity level of the packages
•Package placement
•Inspection and repair
•Lead-free soldering ve rsus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
•Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
•Solder bath specifications, including temperature and impurities
PCA9542A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 5.1 — 15 July 2015 19 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
14.4 Reflow soldering
Key characteristics in reflow soldering are :
•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to
higher minimum peak temperatures (see Figure 17) than a SnPb process, thus
reducing the process window
•Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
•Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) an d cooling down. It is imperative that the peak
temperature is high enoug h for the solder to make reliable solder joint s (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The pe ak temperature of the package
depends on p ackage thickness and volume and is classified in accordan ce with
Table 11 and 12
Moisture sensitivity precautions, as indicated on the packing, must be respe cted at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 17.
Table 11. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350
< 2.5 235 220
2.5 220 220
Table 12. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
PCA9542A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 5.1 — 15 July 2015 20 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
For further informa tion on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
MSL: Moisture Sensitivity Level
Fig 17. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
PCA9542A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 5.1 — 15 July 2015 21 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
15. Soldering: PCB footprints
Fig 18. PCB footprint for SOT108-1 (SO14); reflow soldering
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PCA9542A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 5.1 — 15 July 2015 22 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
Fig 19. P CB footprint for SOT402-1 (TSSOP14); reflow soldering
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PCA9542A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 5.1 — 15 July 2015 23 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
16. Abbreviations
Table 13. Abbreviations
Acronym Description
CDM Charged-Device Model
ESD ElectroStatic Discharge
HBM Human Body Model
I/O Input/Output
I2C-bus Inter-Integrated Circuit bus
LSB Least Significant Bit
POR Power-On Reset
SMBus System Management Bus
PCA9542A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 5.1 — 15 July 2015 24 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
17. Revision history
Table 14. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PCA9542A v.5.1 20150715 Product data sheet - PCA9542A v.5
Modifications: •Table 14 “Revision history”, corrected phrase “for at least 5 ms” to “for at least 5 s” for Table 8
and Table 9 modifications
PCA9542A v.5 20140407 Product data sheet - PCA9542A v.4
Modifications: •Section 2 “Features and benefits”, 16th bullet item: deleted phrase “200 V MM per JESD22-A115”
•Table 1 “Ordering information”: added column “Topside marking” (moved from Table 2)
•Table 2 “Ordering options”:
–deleted column “Topside mark” (moved to Table 1)
–added columns “Orderable part number”, “Package”, “Packing method”, and “Minimum order
quantity”
•Figure 5 “Control register” updated: added notation ‘writable, but always read 0’
•Section 6.2. 1 “ Control register definition”: added second paragraph
•Section 6.3 “Interrupt handling”, “Remark” paragraph (following Table 5): added second sentence
•Section 6.4 “Power-on reset”: first para graph, third sentence: corrected from “VDD must be
lowered below 0.2 V to reset the device” to “VDD must be lowered below 0.2 V for at least 5 s in
order to reset the device”
•Table 6 “Limiting values”: added limiting values for “Tj(max)”
•Added Section 10 “Thermal characteristics”
•Table 8 “Static characteristics at VDD = 2.3 V to 3.6 V”,
–Table note [2]: inserted phrase “for at least 5 s”
–sub-section “Select inputs A0, A1, A2, INT0, IN T1 ”: Max value for VIH corrected
from “VDD + 0.5 V” to “6 V”
•Table 9 “Static characteristics at VDD = 4.5 V to 5.5 V”,
–Table note [2]: inserted phrase “for at least 5 s”
–sub-section “Select inputs A0, A1, A2, INT0, IN T1 ”: Max value for VIH corrected
from “VDD + 0.5 V” to “6 V”
•Added Section 15 “Soldering: PCB footprints”
PCA9542A v.4 20090615 Product data sheet - PCA9542A v.3
PCA9542A v.3 20081124 Product data sheet - PCA9542A v.2
PCA9542A v.2
(9397 750 13955) 20040929 Product data sheet - PCA9542A v.1
PCA9542A v.1
(9397 750 13307) 20040727 Objective data sheet - -
PCA9542A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 5.1 — 15 July 2015 25 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
18. Legal information
18.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The prod uct sta tus of device (s) descri bed in this d ocument may have change d since this d ocument was p ublished and may dif fer in case of multiple devices. The latest product st atus
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semicond uctors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
18.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for t he customer’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Custo mers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability rela ted to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the applica tion or use by customer’s
third party custo mer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contain s data from the objective specification for product development .
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
PCA9542A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 5.1 — 15 July 2015 26 of 27
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a pri or
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qua lified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standards, custome r
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such au tomotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y
liability, damages or failed product claims result ing from customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a docume nt is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
18.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
I2C-bus — logo is a trademark of NXP Semi conductors N.V.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
© NXP Semiconductors N.V. 2015. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 July 2015
Document identifier: PCA9542A
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
20. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
6.1 Device addressing . . . . . . . . . . . . . . . . . . . . . . 5
6.2 Control register. . . . . . . . . . . . . . . . . . . . . . . . . 5
6.2.1 Control register definition . . . . . . . . . . . . . . . . . 5
6.3 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . 6
6.4 Power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . 6
6.5 Voltage translation . . . . . . . . . . . . . . . . . . . . . . 7
7 Characteristics of the I2C-bus . . . . . . . . . . . . . 8
7.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.2 START and STOP conditions . . . . . . . . . . . . . . 8
7.3 System configuration . . . . . . . . . . . . . . . . . . . . 8
7.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7.5 Bus transactions. . . . . . . . . . . . . . . . . . . . . . . 10
8 Application design-in information . . . . . . . . . 10
9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11
10 Thermal characteristics . . . . . . . . . . . . . . . . . 11
11 Static characteristics. . . . . . . . . . . . . . . . . . . . 12
12 Dynamic characteristics . . . . . . . . . . . . . . . . . 14
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
14 Soldering of SMD packages . . . . . . . . . . . . . . 18
14.1 Introduction to soldering . . . . . . . . . . . . . . . . . 18
14.2 Wave and reflow soldering . . . . . . . . . . . . . . . 18
14.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 18
14.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 19
15 Soldering: PCB footprints. . . . . . . . . . . . . . . . 21
16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 23
17 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24
18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 25
18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25
18.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
18.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
19 Contact information. . . . . . . . . . . . . . . . . . . . . 26
20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27