Dual 12-/14-/16-Bit,
1 GSPS, Digital-to-Analog Converters
AD9776/AD9778/AD9779
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved.
FEATURES
Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS,
full operating conditions
SFDR = 78 dBc to fOUT = 100 MHz
Single carrier WCDMA ACLR = 79 dBc @ 80 MHz IF
Analog output: adjustable 8.7 mA to 31.7 mA,
RL = 25 Ω to 50 Ω
Novel 2×, 4×, and 8× interpolator/coarse complex modulator
allows carrier placement anywhere in DAC bandwidth
Auxiliary DACs allow control of external VGA and offset control
Multiple chip synchronization interface
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
100-lead, exposed paddle TQFP package
APPLICATIONS
Wireless infrastructure
WCDMA, CDMA2000, TD-SCDMA, WiMax, GSM
Digital high or low IF synthesis
Internal digital upconversion capability
Transmit diversity
Wideband communications: LMDS/MMDS, point-to-point
GENERAL DESCRIPTION
The AD9776/AD9778/AD9779 are dual, 12-/14-/16-bit, high
dynamic range, digital-to-analog converters (DACs) that pro-
vide a sample rate of 1 GSPS, permitting multicarrier generation
up to the Nyquist frequency. They include features optimized
for direct conversion transmit applications, including complex
digital modulation, and gain and offset compensation. The DAC
outputs are optimized to interface seamlessly with analog quad-
rature modulators such as the AD8349. A serial peripheral interface
(SPI®) provides for programming/readback of many internal
parameters. Full-scale output current can be programmed over a
range of 10 mA to 30 mA. The devices are manufactured on an
advanced 0.18 m CMOS process and operate on 1.8 V and
3.3 V supplies for a total power consumption of 1.0 W. They are
enclosed in 100-lead TQFP packages.
PRODUCT HIGHLIGHTS
1. Ultralow noise and intermodulation distortion (IMD)
enable high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
2. A proprietary DAC output switching technique enhances
dynamic performance.
3. The current outputs are easily configured for various
single-ended or differential circuit topologies.
4. CMOS data input interface with adjustable set up and hold.
5. Novel 2×, 4×, and 8× interpolator/coarse complex
modulator allows carrier placement anywhere in DAC
bandwidth.
TYPICAL SIGNAL CHAIN
05361-114
FPGA/ASIC/DSP
DC
COMPLEX I AND Q
DC LO
QUADRATURE
MODULATOR/
MIXER/
AMPLIFIER
I DAC
Q DAC
DIGITAL INTERPOLATION FILTERS
AD9779
POST DAC
ANALOG FILTER
A
Figure 1.
AD9776/AD9778/AD9779
Rev. A | Page 2 of 56
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Typical Signal Chain......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
Digital Specifications ................................................................... 6
Digital Input Data Timing Specifications ................................. 7
AC Specifications.......................................................................... 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 15
Ter mi nol og y .................................................................................... 24
Theory of Operation ...................................................................... 25
Serial Peripheral Interface ......................................................... 25
MSB/LSB Transfers..................................................................... 26
SPI Register Map ............................................................................ 27
Interpolation Filter Architecture .................................................. 31
Interpolation Filter Minimum and Maximum Bandwidth
Specifications .............................................................................. 35
Driving the REFCLK Input....................................................... 35
Internal PLL Clock Multiplier/Clock Distribution................ 36
Full-Scale Current Generation ................................................. 38
Power Dissipation....................................................................... 39
Power-Down and Sleep Modes................................................. 41
Interleaved Data Mode .............................................................. 41
Timing Information ................................................................... 41
Synchronization of Input Data to DATACLK
Output (Pin 37)........................................................................... 43
Synchronization of Input Data to the REFCLK Input (Pin 5
and Pin 6) with PLL Enabled or Disabled............................... 43
Evaluation Board Operation ......................................................... 46
Modifying the Evaluation Board to Use the AD8349 On-
Board Quadrature Modulator................................................... 48
Evaluation Board Schematics ................................................... 49
Outline Dimensions ....................................................................... 56
Ordering Guide .......................................................................... 56
REVISION HISTORY
3/07—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Changes to Applications .................................................................. 1
Changes to General Product Highlights........................................ 1
Added Figure 1, Renumbered Figures Sequentially..................... 1
Changes to Table 1............................................................................ 4
Changes to Table 2............................................................................ 5
Changes to Table 3............................................................................ 5
Changes to Figure 53 and Figure 54............................................. 26
Changes to Table 12........................................................................ 29
Changes to Power Dissipation Section ........................................ 39
Added Table 19, Renumbered Tables Sequentially.................... 41
Changes to Figure 92 and Figure 93............................................. 42
Changes to Figure 94...................................................................... 42
Added New Figure 95, Renumbered Figures Sequentially ....... 42
Changes to Synchronization of Input Data to the REFCLK Input
(Pin 5 and Pin 6) with PLL Enabled or Disabled Section ......... 43
Added New Figure 96, Renumbered Figures Sequentially ....... 43
Changes to Figure 106 ................................................................... 51
7/05—Revision 0: Initial Version
AD9776/AD9778/AD9779
Rev. A | Page 3 of 56
FUNCTIONAL BLOCK DIAGRAM
10
10
10
10
CLOCK GENERATION/DISTRIBUTION
DATA
ASSEMBLER
DIGITAL CONTROLLER
2× 2×
SYNC
1
CLOCK
MULTIPLIER
2×/4×/8×
16-BIT
IDAC
CLK+
CLK–
IOUT1_P
IOUT1_N
AUX1_P
AUX1_N
AUX2_P
AUX2_N
IOUT2_P
IOUT2_N
GAIN
GAIN
GAIN
GAIN
16-BIT
QDAC
2×
SYNC
1
I
LATCH
DELAY
LINE
Q
LATCH
P2D(15:0)
P1D(15:0)
SYNC_O
SYNC_I
DATACLK_OUT
2× 2× 2×
n ×
f
DAC
/8
n = 0, 1, 2 ... 7
POWER-ON
RESET
SDO
SDIO
SCL
K
CSB
SERIAL
PERIPHERAL
INTERFACE
COMPLEX
MODULATOR
REFERENCE
AND BIAS
VREF
I120
DELAY
LINE
0
5361-001
Figure 2. Functional Block Diagram
AD9776/AD9778/AD9779
Rev. A | Page 4 of 56
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 =1.8 V, = 20 mA, maximum sample rate, unless
otherwise noted.
S
OUTF
I
Table 1. AD9776, AD9778, and AD9779 DC Specifications
AD9776 AD9778 AD9779
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION 12 14 16 Bits
ACCURACY
Differential Nonlinearity (DNL) ±0.1 ±0.65 ±2.1 LSB
Integral Nonlinearity (INL) ±0.6 ±1 ±3.7 LSB
MAIN DAC OUTPUTS
Offset Error −0.001 0 +0.001 −0.001 0 +0.001 −0.001 0 +0.001 % FSR
Gain Error (with Internal
Reference)
±2 ±2 ±2 % FSR
Full-Scale Output Current18.66 20.2 31.66 8.66 20.2 31.66 8.66 20.2 31.66 mA
Output Compliance Range −1.0 +1.0 −1.0 +1.0 −1.0 +1.0 V
Output Resistance 10 10 10 MΩ
Gain DAC Monotonicity Guaranteed Guaranteed Guaranteed
MAIN DAC TEMPERATURE DRIFT
Offset 0.04 0.04 0.04 ppm/°C
Gain 100 100 100 ppm/°C
Reference Voltage 30 30 30 ppm/°C
AUX DAC OUTPUTS
Resolution 10 10 10 Bits
Full-Scale Output Current1−1.998 +1.998 −1.998 +1.998 −1.998 +1.998 mA
Output Compliance Range
(Source)
0 1.6 0 1.6 0 1.6 V
Output Compliance Range
(Sink)
0.8 1.6 0.8 1.6 0.8 1.6 V
Output Resistance 1 1 1 MΩ
Aux DAC Monotonicity
Guaranteed
REFERENCE
Internal Reference Voltage 1.2 1.2 1.2 V
Output Resistance 5 5 5 kΩ
ANALOG SUPPLY VOLTAGES
AVDD33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V
CVDD18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 V
DIGITAL SUPPLY VOLTAGES
DVDD33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V
DVDD18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 V
POWER CONSUMPTION
1× Mode, fDAC = 100 MSPS,
IF = 1 MHz
250 300 250 300 250 300 mW
2× Mode, fDAC = 320 MSPS,
IF = 16 MHz, PLL Off
498 498 498 mW
2× Mode, fDAC = 320 MSPS,
IF = 16 MHz, PLL On
588 588 588 mW
4× Mode, fDAC/4 Modulation,
fDAC = 500 MSPS,
IF = 137.5 MHz, Q DAC Off
572 572 572 mW
AD9776/AD9778/AD9779
Rev. A | Page 5 of 56
AD9776 AD9778 AD9779
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
8× Mode, fDAC/4 Modulation,
fDAC = 1 GSPS, IF = 262.5 MHz
980 980 980 mW
Power-Down Mode 2 3.7 2 3.7 2 3.7 mW
Power Supply Rejection Ratio,
AVDD33
−0.3 +0.3 −0.3 +0.3 −0.3 +0.3 % FSR/V
OPERATING RANGE −40 +25 +85 −40 +25 +85 −40 +25 +85 °C
1 Based on a 10 k external resistor.
AD9776/AD9778/AD9779
Rev. A | Page 6 of 56
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, = 20 mA, maximum sample rate, unless
otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted.
S
OUTF
I
Table 2. AD9776, AD9778, and AD9779 Digital Specifications
Parameter Conditions Min Typ Max Unit
CMOS INPUT LOGIC LEVEL
Input VIN Logic High 2.0 V
Input VIN Logic Low 0.8 V
Maximum Input Data Rate at Interpolation
1× 300 MSPS
2× 250 MSPS
4× 200 MSPS
8× 125 MSPS
CMOS OUTPUT LOGIC LEVEL (DATACLK, PIN 37)1
Output VOUT Logic High 2.4 V
Output VOUT Logic Low 0.4 V
LVDS RECEIVER INPUTS (SYNC_I+, SYNC_I−) SYNC_I+ = VIA, SYNC_I− = VIB
Input Voltage Range, VIA or VIB 825 1575 mV
Input Differential Threshold, VIDTH −100 +100 mV
Input Differential Hysteresis, VIDTHH − VIDTHL 20 mV
Receiver Differential Input Impedance, RIN2 80 120 Ω
LVDS Input Rate 125 MSPS
Set-Up Time, SYNC_I to DAC Clock −0.2 ns
Hold Time, SYNC_I to DAC Clock 1 ns
LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−) SYNC_O+ = VOA, SYNC_O− = VOB, 100 Ω termination
Output Voltage High, VOA or VOB 825 1575 mV
Output Voltage Low, VOA or VOB 1025 mV
Output Differential Voltage, |VOD| 150 200 250 mV
Output Offset Voltage, VOS 1150 1250 mV
Output Impedance, ROSingle-ended 80 100 120 Ω
Maximum Clock Rate 1 GHz
DAC CLOCK INPUT (CLK+, CLK−)
Differential Peak-to-Peak Voltage (CLK+, CLK−)3 400 800 2000 mV
Common-Mode Voltage 300 400 500 mV
Maximum Clock Rate4 1 GSPS
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK) 40 MHz
Minimum Pulse Width High 12.5 ns
Minimum Pulse Width Low 12.5 ns
1 Specification is at a DATACLK frequency of 100 MHz into a 1 kΩ load; maximum drive capability of 8 mA. At higher speeds or greater loads, best practice suggests
using an external buffer for this signal.
2 Guaranteed at 25°C. Can drift above 120 Ω at temperatures above 25°C.
3 When using the PLL, a differential swing of 2 V p-p is recommended.
4 Typical maximum clock rate when DVDD18 = CVDD18 = 1.9 V.
AD9776/AD9778/AD9779
Rev. A | Page 7 of 56
DIGITAL INPUT DATA TIMING SPECIFICATIONS
Table 3. AD9776, AD9778, and AD9779 Digital Input Data Timing Specifications
Parameter Min Typ Max Unit
INPUT DATA (ALL MODES, −40°C to +85°C)1
Set-Up Time, Input Data to DATACLK +2.5 ns
Hold Time, Input Data to DATACLK −0.4 ns
Set-Up Time, Input Data to REFCLK −0.8 ns
Hold Time, Input Data to REFCLK +2.9 ns
1 Timing vs. temperature and data valid keep out windows are delineated in Table 19.
AC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, = 20 mA, maximum sample rate, unless
otherwise noted.
S
OUTF
I
Table 4. AD9776, AD9778, and AD9779 AC Specifications
AD9776 AD9778 AD9779
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
SPURIOUS FREE DYNAMIC RANGE (SFDR)
fDAC = 100 MSPS, fOUT = 20 MHz 82 82 82 dBc
fDAC = 200 MSPS, fOUT = 50 MHz 81 81 82 dBc
fDAC = 400 MSPS, fOUT = 70 MHz 80 80 80 dBc
fDAC = 800 MSPS, fOUT = 70 MHz 85 85 87 dBc
TWO-TONE INTERMODULATION DISTORTION
(IMD)
fDAC = 200 MSPS, fOUT = 50 MHz 87 87 91 dBc
fDAC = 400 MSPS, fOUT = 60 MHz 80 85 85 dBc
fDAC = 400 MSPS, fOUT = 80 MHz 75 81 81 dBc
fDAC = 800 MSPS, fOUT = 100 MHz 75 80 81 dBc
NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE,
500 kHz TONE SPACING
fDAC = 200 MSPS, fOUT = 80 MHz −152 −155 −158 dBm/Hz
fDAC = 400 MSPS, fOUT = 80 MHz −155 −159 −160 dBm/Hz
fDAC = 800 MSPS, fOUT = 80 MHz −157.5 −160 −161 dBm/Hz
WCDMA ADJACENT CHANNEL LEAKAGE
RATIO (ACLR), SINGLE CARRIER
fDAC = 491.52 MSPS, fOUT = 100 MHz 76 78 79 dBc
fDAC = 491.52 MSPS, fOUT = 200 MHz 69 73 74 dBc
WCDMA SECOND ADJACENT CHANNEL
LEAKAGE RATIO (ACLR), SINGLE CARRIER
fDAC = 491.52 MSPS, fOUT = 100 MHz 77.5 80 81 dBc
fDAC = 491.52 MSPS, fOUT = 200 MHz 76 78 78 dBc
AD9776/AD9778/AD9779
Rev. A | Page 8 of 56
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
With
Respect
To Rating
AVDD33, DVDD33 AGND,
DGND,
CGND
−0.3 V to +3.6 V
DVDD18, CVDD18 AGND,
DGND,
CGND
−0.3 V to +1.98 V
AGND DGND,
CGND
−0.3 V to +0.3 V
DGND AGND,
CGND
−0.3 V to +0.3 V
CGND AGND,
DGND
−0.3 V to +0.3 V
I120, VREF, IPTAT AGND −0.3 V to AVDD33 + 0.3 V
IOUT1-P, IOUT1-N, IOUT2-P,
IOUT2-N, Aux1-P, Aux1-N,
Aux2-P, Aux2-N
AGND −1.0 V to AVDD33 + 0.3 V
P1D15 to P1D0,
P2D15 to P2D0
DGND −0.3 V to DVDD33 + 0.3 V
DATACLK, TXENABLE DGND −0.3 V to DVDD33 + 0.3 V
CLK+, CLK− CGND −0.3 V to CVDD18 + 0.3 V
RESET, IRQ, PLL_LOCK,
SYNC_O+, SYNC_O−,
SYNC_I+, SYNC_I−,
CSB, SCLK, SDIO, SDO
DGND −0.3 V to DVDD33 + 0.3 V
Junction Temperature +125°C
Storage Temperature
Range
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
100-lead, thermally enhanced TQFP_EP package, θJA = 19.1°C/W
with the bottom EPAD soldered to the PCB. With the bottom
EPAD not soldered to the PCB, θJA = 27.4°C/W. These
specifications are valid with no airflow movement.
ESD CAUTION
AD9776/AD9778/AD9779
Rev. A | Page 9 of 56
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
74
VREF
73
IPTAT
72
AGND
69
CSB
70
RESET
71
IRQ
75
I120
68
SCLK
67
SDIO
66
SDO
64
DGND
63
SYNC_O+
62
SYNC_O–
61
DVDD33
60
DVDD18
59
NC
58
NC
57
NC
56
NC
55
P2D<0>
54
DGND
53
DVDD18
52
P2D<1>
51
P2D<2>
65
PLL_LOCK
PIN 1
100
AVDD33
99
AGND
98
AVDD33
97
AGND
96
AVDD33
95
AGND
94
AGND
93
OUT1_P
92
OUT1_N
91
AGND
90
AUX1_P
89
AUX1_N
88
AGND
87
AUX2_N
86
AUX2_P
85
AGND
84
OUT2_N
83
OUT2_P
82
AGND
81
AGND
80
AVDD33
79
AGND
78
AVDD33
77
AGND
76
AVDD33
26
P1D<4>
27
P1D<3>
28
P1D<2>
29
P1D<1>
30
P1D<0>
31
NC
32
DGND
33
DVDD18
34
NC
35
NC
36
NC
37
DATACLK
38
DVDD33
39
TXENABLE
40
P2D<11>
41
P2D<10>
42
P2D<9>
43
DVDD18
44
DGND
45
P2D<8>
46
P2D<7>
47
P2D<6>
48
P2D<5>
49
P2D<4>
50
P2D<3>
2
CVDD18
3
CGND
4
CGND
7
CGND
6
CLK–
5
CLK+
1
CVDD18
8
CGND
9
CVDD18
10
CVDD18
12
AGND
13
SYNC_I+
14
SYNC_I–
15
DGND
16
DVDD18
17
P1D<11>
18
P1D<10>
19
P1D<9>
20
P1D<8>
21
P1D<7>
22
DGND
23
DVDD18
24
P1D<6>
25
P1D<5>
11
CGND
AD9776
TOP VIEW
(Not to Scale)
ANALOG DOMAIN
DIGITAL DOMAIN
NC = NO CONNECT
05361-002
Figure 3. AD9776 Pin Configuration
Table 6. AD9776 Pin Function Descriptions
Pin
No. Mnemonic Description
1 CVDD18 1.8 V Clock Supply.
2 CVDD18 1.8 V Clock Supply.
3 CGND Clock Common.
4 CGND Clock Common.
5 CLK+1Differential Clock Input.
6 CLK−1Differential Clock Input.
7 CGND Clock Common.
8 CGND Clock Common.
9 CVDD18 1.8 V Clock Supply.
10 CVDD18 1.8 V Clock Supply.
11 CGND Clock Common.
12 AGND Analog Common.
13 SYNC_I+ Differential Synchronization Input.
14 SYNC_I− Differential Synchronization Input.
15 DGND Digital Common.
16 DVDD18 1.8 V Digital Supply.
17 P1D<11> Port 1, Data Input D11 (MSB).
18 P1D<10> Port 1, Data Input D10.
19 P1D<9> Port 1, Data Input D9.
Pin
No. Mnemonic Description
20 P1D<8> Port 1, Data Input D8.
21 P1D<7> Port 1, Data Input D7.
22 DGND Digital Common.
23 DVDD18 1.8 V Digital Supply.
24 P1D<6> Port 1, Data Input D6.
25 P1D<5> Port 1, Data Input D5.
26 P1D<4> Port 1, Data Input D4.
27 P1D<3> Port 1, Data Input D3.
28 P1D<2> Port 1, Data Input D2.
29 P1D<1> Port 1, Data Input D1.
30 P1D<0> Port 1, Data Input D0 (LSB).
31 NC No Connect.
32 DGND Digital Common.
33 DVDD18 1.8 V Digital Supply.
34 NC No Connect.
35 NC No Connect.
36 NC No Connect.
37 DATACLK Data Clock Output.
38 DVDD33 3.3 V Digital Supply.
AD9776/AD9778/AD9779
Rev. A | Page 10 of 56
Pin
No. Mnemonic Description
39 TXENABLE Transmit Enable.
40 P2D<11> Port 2, Data Input D11 (MSB).
41 P2D<10> Port 2, Data Input D10.
42 P2D<9> Port 2, Data Input D9.
43 DVDD18 1.8 V Digital Supply.
44 DGND Digital Common.
45 P2D<8> Port 2, Data Input D8.
46 P2D<7> Port 2, Data Input D7.
47 P2D<6> Port 2, Data Input D6.
48 P2D<5> Port 2, Data Input D5.
49 P2D<4> Port 2, Data Input D4.
50 P2D<3> Port 2, Data Input D3.
51 P2D<2> Port 2, Data Input D2.
52 P2D<1> Port 2, Data Input D1.
53 DVDD18 1.8 V Digital Supply.
54 DGND Digital Common.
55 P2D<0> Port 2, Data Input D0 (LSB).
56 NC No Connect.
57 NC No Connect.
58 NC No Connect.
59 NC No Connect.
60 DVDD18 1.8 V Digital Supply.
61 DVDD33 3.3 V Digital Supply.
62 SYNC_O− Differential Synchronization Output.
63 SYNC_O+ Differential Synchronization Output
64 DGND Digital Common
65 PLL_LOCK PLL Lock Indicator
66 SDO SPI Port Data Output
67 SDIO SPI Port Data Input/Output
68 SCLK SPI Port Clock
69 CSB SPI Port Chip Select Bar.
70 RESET Reset, Active High.
71 IRQ Interrupt Request.
72 AGND Analog Common.
Pin
No. Mnemonic Description
73 IPTAT Factory Test Pin. Output current is
proportional to absolute temperature,
approximately 10 μA at 25°C with
approximately 20 nA/°C slope. This pin
should remain floating.
74 VREF Voltage Reference Output.
75 I120 120 μA Reference Current.
76 AVDD33 3.3 V Analog Supply.
77 AGND Analog Common.
78 AVDD33 3.3 V Analog Supply.
79 AGND Analog Common.
80 AVDD33 3.3 V Analog Supply.
81 AGND Analog Common.
82 AGND Analog Common.
83 OUT2_P Differential DAC Current Output, Channel 2.
84 OUT2_N Differential DAC Current Output, Channel 2.
85 AGND Analog Common.
86 AUX2_P Auxiliary DAC Current Output, Channel 2.
87 AUX2_N Auxiliary DAC Current Output, Channel 2.
88 AGND Analog Common.
89 AUX1_N Auxiliary DAC Current Output, Channel 1.
90 AUX1_P Auxiliary DAC Current Output, Channel 1.
91 AGND Analog Common.
92 OUT1_N Differential DAC Current Output, Channel 1.
93 OUT1_P Differential DAC Current Output, Channel 1.
94 AGND Analog Common.
95 AGND Analog Common.
96 AVDD33 3.3 V Analog Supply.
97 AGND Analog Common.
98 AVDD33 3.3 V Analog Supply.
99 AGND Analog Common.
100 AVDD33 3.3 V Analog Supply.
1 The combined differential clock input at the CLK+ and CLK– pins are referred
to as REFCLK.
AD9776/AD9778/AD9779
Rev. A | Page 11 of 56
74
VREF
73
IPTAT
72
AGND
69
CSB
70
RESET
71
IRQ
75
I120
68
SCLK
67
SDIO
66
SDO
64
DGND
63
SYNC_O+
62
SYNC_O–
61
DVDD33
60
DVDD18
59
NC
58
NC
57
P2D<0>
56
P2D<1>
55
P2D<2>
54
DGND
53
DVDD18
52
P2D<3>
51
P2D<4>
65
PLL_LOCK
PIN 1
100
AVDD33
99
AGND
98
AVDD33
97
AGND
96
AVDD33
95
AGND
94
AGND
93
OUT1_P
92
OUT1_N
91
AGND
90
AUX1_P
89
AUX1_N
88
AGND
87
AUX2_N
86
AUX2_P
85
AGND
84
OUT2_N
83
OUT2_P
82
AGND
81
AGND
80
AVDD33
79
AGND
78
AVDD33
77
AGND
76
AVDD33
26
P1D<6>
27
P1D<5>
28
P1D<4>
29
P1D<3>
30
P1D<2>
31
P1D<1>
32
DGND
33
DVDD18
34
P1D<0>
35
NC
36
NC
37
DATACLK
38
DVDD33
39
TXENABLE
40
P2D<13>
41
P2D<12>
42
P2D<11>
43
DVDD18
44
DGND
45
P2D<10>
46
P2D<9>
47
P2D<8>
48
P2D<7>
49
P2D<6>
50
P2D<5>
2
CVDD18
3
CGND
4
CGND
7
CGND
6
CLK–
5
CLK+
1
CVDD18
8
CGND
9
CVDD18
10
CVDD18
12
AGND
13
SYNC_I+
14
SYNC_I–
15
DGND
16
DVDD18
17
P1D<13>
18
P1D<12>
19
P1D<11>
20
P1D<10>
21
P1D<9>
22
DGND
23
DVDD18
24
P1D<8>
25
P1D<7>
11
CGND
AD9778
TOP VIEW
(Not to Scale)
ANALOG DOMAIN
DIGITAL DOMAIN
NC = NO CONNECT
05361-003
Figure 4. AD9778 Pin Configuration
Table 7. AD9778 Pin Function Description
Pin
No. Mnemonic Description
1 CVDD18 1.8 V Clock Supply.
2 CVDD18 1.8 V Clock Supply.
3 CGND Clock Common.
4 CGND Clock Common.
5 CLK+1Differential Clock Input.
6 CLK−1Differential Clock Input.
7 CGND Clock Common.
8 CGND Clock Common.
9 CVDD18 1.8 V Clock Supply.
10 CVDD18 1.8 V Clock Supply.
11 CGND Clock Common.
12 AGND Analog Common.
13 SYNC_I+ Differential Synchronization Input.
14 SYNC_I− Differential Synchronization Input.
15 DGND Digital Common.
16 DVDD18 1.8 V Digital Supply.
17 P1D<13> Port 1, Data Input D13 (MSB).
18 P1D<12> Port 1, Data Input D12.
19 P1D<11> Port 1, Data Input D11.
20 P1D<10> Port 1, Data Input D10.
Pin
No. Mnemonic Description
21 P1D<9> Port 1, Data Input D9.
22 DGND Digital Common.
23 DVDD18 1.8 V Digital Supply.
24 P1D<8> Port 1, Data Input D8.
25 P1D<7> Port 1, Data Input D7.
26 P1D<6> Port 1, Data Input D6.
27 P1D<5> Port 1, Data Input D5.
28 P1D<4> Port 1, Data Input D4.
29 P1D<3> Port 1, Data Input D3.
30 P1D<2> Port 1, Data Input D2.
31 P1D<1> Port 1, Data Input D1.
32 DGND Digital Common.
33 DVDD18 1.8 V Digital Supply.
34 P1D<0> Port 1, Data Input D0 (LSB).
35 NC No Connect.
36 NC No Connect.
37 DATACLK Data Clock Output.
38 DVDD33 3.3 V Digital Supply.
39 TXENABLE Transmit Enable.
40 P2D<13> Port 2, Data Input D13 (MSB).
AD9776/AD9778/AD9779
Rev. A | Page 12 of 56
Pin
No. Mnemonic Description
41 P2D<12> Port 2, Data Input D12.
42 P2D<11> Port 2, Data Input D11.
43 DVDD18 1.8 V Digital Supply.
44 DGND Digital Common.
45 P2D<10> Port 2, Data Input D10.
46 P2D<9> Port 2, Data Input D9.
47 P2D<8> Port 2, Data Input D8.
48 P2D<7> Port 2, Data Input D7.
49 P2D<6> Port 2, Data Input D6.
50 P2D<5> Port 2, Data Input D5.
51 P2D<4> Port 2, Data Input D4.
52 P2D<3> Port 2, Data Input D3.
53 DVDD18 1.8 V Digital Supply.
54 DGND Digital Common.
55 P2D<2> Port 2, Data Input D2.
56 P2D<1> Port 2, Data Input D1.
57 P2D<0> Port 2, Data Input D0 (LSB).
58 NC No Connect.
59 NC No Connect.
60 DVDD18 1.8 V Digital Supply.
61 DVDD33 3.3 V Digital Supply.
62 SYNC_O− Differential Synchronization Output.
63 SYNC_O+ Differential Synchronization Output.
64 DGND Digital Common.
65 PLL_LOCK PLL Lock Indicator.
66 SDO SPI Port Data Output.
67 SDIO SPI Port Data Input/Output.
68 SCLK SPI Port Clock.
69 CSB SPI Port Chip Select Bar.
70 RESET Reset, Active High.
71 IRQ Interrupt Request.
72 AGND Analog Common.
73 IPTAT Factory Test Pin. Output current is
proportional to absolute temperature,
approximately 10 μA at 25°C with
approximately 20 nA/°C slope. This
pin should remain floating.
Pin
No. Mnemonic Description
74 VREF Voltage Reference Output.
75 I120 120 μA Reference Current.
76 AVDD33 3.3 V Analog Supply.
77 AGND Analog Common.
78 AVDD33 3.3 V Analog Supply.
79 AGND Analog Common.
80 AVDD33 3.3 V Analog Supply.
81 AGND Analog Common.
82 AGND Analog Common.
83 OUT2_P Differential DAC Current Output,
Channel 2.
84 OUT2_N Differential DAC Current Output,
Channel 2.
85 AGND Analog Common.
86 AUX2_P Auxiliary DAC Current Output,
Channel 2.
87 AUX2_N Auxiliary DAC Current Output,
Channel 2.
88 AGND Analog Common.
89 AUX1_N Auxiliary DAC Current Output,
Channel 1.
90 AUX1_P Auxiliary DAC Current Output,
Channel 1.
91 AGND Analog Common.
92 OUT1_N Differential DAC Current Output,
Channel 1.
93 OUT1_P Differential DAC Current Output,
Channel 1.
94 AGND Analog Common.
95 AGND Analog Common.
96 AVDD33 3.3 V Analog Supply.
97 AGND Analog Common.
98 AVDD33 3.3 V Analog Supply.
99 AGND Analog Common.
100 AVDD33 3.3 V Analog Supply.
1 The combined differential clock input at the CLK+ and CLK– pins are referred
to as REFCLK.
AD9776/AD9778/AD9779
Rev. A | Page 13 of 56
74
VREF
73
IPTAT
72
AGND
69
CSB
70
RESET
71
IRQ
75
I120
68
SCLK
67
SDIO
66
SDO
64
DGND
63
SYNC_O+
62
SYNC_O–
61
DVDD33
60
DVDD18
59
P2D<0>
58
P2D<1>
57
P2D<2>
56
P2D<3>
55
P2D<4>
54
DGND
53
DVDD18
52
P2D<5>
51
P2D<6>
65
PLL_LOCK
PIN 1
100
AVDD33
99
AGND
98
AVDD33
97
AGND
96
AVDD33
95
AGND
94
AGND
93
OUT1_P
92
OUT1_N
91
AGND
90
AUX1_P
89
AUX1_N
88
AGND
87
AUX2_N
86
AUX2_P
85
AGND
84
OUT2_N
83
OUT2_P
82
AGND
81
AGND
80
AVDD33
79
AGND
78
AVDD33
77
AGND
76
AVDD33
26
P1D<8>
27
P1D<7>
28
P1D<6>
29
P1D<5>
30
P1D<4>
31
P1D<3>
32
DGND
33
DVDD18
34
P1D<2>
35
P1D<1>
36
P1D<0>
37
DATACLK
38
DVDD33
39
TXENABLE
40
P2D<15>
41
P2D<14>
42
P2D<13>
43
DVDD18
44
DGND
45
P2D<12>
46
P2D<11>
47
P2D<10>
48
P2D<9>
49
P2D<8>
50
P2D<7>
2
CVDD18
3
CGND
4
CGND
7
CGND
6
CLK–
5
CLK+
1
CVDD18
8
CGND
9
CVDD18
10
CVDD18
12
AGND
13
SYNC_I+
14
SYNC_I–
15
DGND
16
DVDD18
17
P1D<15>
18
P1D<14>
19
P1D<13>
20
P1D<12>
21
P1D<11>
22
DGND
23
DVDD18
24
P1D<10>
25
P1D<9>
11
CGND
AD9779
TOP VIEW
(Not to Scale)
ANALOG DOMAIN
DIGITAL DOMAIN
05361-004
Figure 5. AD9779 Pin Configuration
Table 8. AD9779 Pin Function Descriptions
Pin
No. Mnemonic Description
1 CVDD18 1.8 V Clock Supply.
2 CVDD18 1.8 V Clock Supply.
3 CGND Clock Common.
4 CGND Clock Common.
5 CLK+1Differential Clock Input.
6 CLK−1Differential Clock Input.
7 CGND Clock Common.
8 CGND Clock Common.
9 CVDD18 1.8 V Clock Supply.
10 CVDD18 1.8 V Clock Supply.
11 CGND Clock Common.
12 AGND Analog Common.
13 SYNC_I+ Differential Synchronization Input.
14 SYNC_I− Differential Synchronization Input.
15 DGND Digital Common.
16 DVDD18 1.8 V Digital Supply.
17 P1D<15> Port 1, Data Input D15 (MSB).
18 P1D<14> Port 1, Data Input D14.
19 P1D<13> Port 1, Data Input D13.
20 P1D<12> Port 1, Data Input D12.
21 P1D<11> Port 1, Data Input D11.
Pin
No. Mnemonic Description
22 DGND Digital Common.
23 DVDD18 1.8 V Digital Supply.
24 P1D<10> Port 1, Data Input D10.
25 P1D<9> Port 1, Data Input D9.
26 P1D<8> Port 1, Data Input D8.
27 P1D<7> Port 1, Data Input D7.
28 P1D<6> Port 1, Data Input D6.
29 P1D<5> Port 1, Data Input D5.
30 P1D<4> Port 1, Data Input D4.
31 P1D<3> Port 1, Data Input D3.
32 DGND Digital Common.
33 DVDD18 1.8 V Digital Supply.
34 P1D<2> Port 1, Data Input D2.
35 P1D<1> Port 1, Data Input D1.
36 P1D<0> Port 1, Data Input D0 (LSB).
37 DATACLK Data Clock Output.
38 DVDD33 3.3 V Digital Supply.
39 TXENABLE Transmit Enable.
40 P2D<15> Port 2, Data Input D15 (MSB).
41 P2D<14> Port 2, Data Input D14.
42 P2D<13> Port 2, Data Input D13.
AD9776/AD9778/AD9779
Rev. A | Page 14 of 56
Pin
No. Mnemonic Description
43 DVDD18 1.8 V Digital Supply.
44 DGND Digital Common.
45 P2D<12> Port 2, Data Input D12.
46 P2D<11> Port 2, Data Input D11.
47 P2D<10> Port 2, Data Input D10.
48 P2D<9> Port 2, Data Input D9.
49 P2D<8> Port 2, Data Input D8.
50 P2D<7> Port 2, Data Input D7.
51 P2D<6> Port 2, Data Input D6.
52 P2D<5> Port 2, Data Input D5.
53 DVDD18 1.8 V Digital Supply.
54 DGND Digital Common.
55 P2D<4> Port 2, Data Input D4.
56 P2D<3> Port 2, Data Input D3.
57 P2D<2> Port 2, Data Input D2.
58 P2D<1> Port 2, Data Input D1.
59 P2D<0> Port 2, Data Input D0 (LSB).
60 DVDD18 1.8 V Digital Supply.
61 DVDD33 3.3 V Digital Supply.
62 SYNC_O− Differential Synchronization Output.
63 SYNC_O+ Differential Synchronization Output.
64 DGND Digital Common.
65 PLL_LOCK PLL Lock Indicator.
66 SPI_SDO SPI Port Data Output.
67 SPI_SDIO SPI Port Data Input/Output.
68 SCLK SPI Port Clock.
69 SPI_CSB SPI Port Chip Select Bar.
70 RESET Reset, Active High.
71 IRQ Interrupt Request.
72 AGND Analog Common.
73 IPTAT Factory Test Pin. Output current is
proportional to absolute temperature,
approximately 10 μA at 25°C with
approximately 20 nA/°C slope. This pin
should remain floating.
Pin
No. Mnemonic Description
74 VREF Voltage Reference Output.
75 I120 120 μA Reference Current.
76 AVDD33 3.3 V Analog Supply.
77 AGND Analog Common.
78 AVDD33 3.3 V Analog Supply.
79 AGND Analog Common.
80 AVDD33 3.3 V Analog Supply.
81 AGND Analog Common.
82 AGND Analog Common.
83 OUT2_P Differential DAC Current Output,
Channel 2.
84 OUT2_N Differential DAC Current Output,
Channel 2.
85 AGND Analog Common.
86 AUX2_P Auxiliary DAC Current Output, Channel 2.
87 AUX2_N Auxiliary DAC Current Output, Channel 2.
88 AGND Analog Common.
89 AUX1_N Auxiliary DAC Current Output, Channel 1.
90 AUX1_P Auxiliary DAC Current Output, Channel 1.
91 AGND Analog Common.
92 OUT1_N Differential DAC Current Output,
Channel 1.
93 OUT1_P Differential DAC Current Output,
Channel 1.
94 AGND Analog Common.
95 AGND Analog Common.
96 AVDD33 3.3 V Analog Supply.
97 AGND Analog Common.
98 AVDD33 3.3 V Analog Supply.
99 AGND Analog Common.
100 AVDD33 3.3 V Analog Supply.
1 The combined differential clock input at the CLK+ and CLK– pins are referred
to as REFCLK.
AD9776/AD9778/AD9779
Rev. A | Page 15 of 56
TYPICAL PERFORMANCE CHARACTERISTICS
4
–6
0
CODE
INL (16-BIT LSB)
3
2
1
0
–1
–2
–3
–4
–5
10k 20k 30k 60k50k40k
05361-005
Figure 6. AD9779 Typical INL
1.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
060k50k40k30k20k10k
CODE
DNL (16-BIT LSB)
05361-006
Figure 7. AD9779 Typical DNL
100
50
0 100
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
20 40 60 80
f
DATA
= 160MSPS
f
DATA
= 200MSPS
f
DATA
= 250MSPS
05361-007
Figure 8. AD9779 In-Band SFDR vs. fOUT, 1x Interpolation
100
50
0 100
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
20 40 60 80
f
DATA
= 160MSPS
f
DATA
= 200MSPS
f
DATA
= 250MSPS
05361-008
Figure 9. AD9779 In-Band SFDR vs. fOUT, 2× Interpolation
100
50
0 100
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
20 40 60 80
f
DATA
= 100MSPS
f
DATA
= 200MSPS
f
DATA
= 150MSPS
05361-009
Figure 10. AD9779 In-Band SFDR vs. fOUT, 4× Interpolation
100
50
0
50
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
10 20 30 40
f
DATA
= 50MSPS
f
DATA
= 100MSPS
f
DATA
= 125MSPS
05361-010
Figure 11. AD9779 In-Band SFDR vs. fOUT, 8× Interpolation
AD9776/AD9778/AD9779
Rev. A | Page 16 of 56
100
50
0
100
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
20 40 60 80
f
DATA
= 200MSPS
f
DATA
= 160MSPS
f
DATA
= 250MSPS
05361-011
Figure 12. AD9779 Out-of-Band SFDR vs. fOUT, 2× Interpolation
100
50
0
100
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
20 40 60 80
f
DATA
= 150MSPS
f
DATA
= 100MSPS
f
DATA
= 200MSPS
05361-012
Figure 13. AD9779 Out-of-Band SFDR vs. fOUT, 4× Interpolation
100
50
0
50
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
10 20 30 40
f
DATA
= 50MSPS
f
DATA
= 100MSPS
f
DATA
= 125MSPS
05361-013
Figure 14. AD9779 Out-of-Band SFDR vs. fOUT, 8× Interpolation
100
50
04
f
OUT
(MHz)
SFDR (dBc)
0
90
80
70
60
10 20 30
PLL OFF
PLL ON
05361-014
Figure 15. AD9779 In-Band SFDR, 4× Interpolation,
fDATA = 100 MSPS, PLL On/Off
100
50
08
f
OUT
(MHz)
SFDR (dBc)
0
90
80
70
60
20 40 60
–3dBFS
0dBFS
–6dBFS
05361-015
Figure 16. AD9779 In-Band SFDR vs. Digital Full-Scale Input
100
50
08
f
OUT
(MHz)
SFDR (dBc)
0
90
80
70
60
20 40 60
10mA
20mA
30mA
05361-016
Figure 17. AD9779 In-Band SFDR vs. Output Full-Scale Current
AD9776/AD9778/AD9779
Rev. A | Page 17 of 56
100
50
0 120
f
OUT
(MHz)
IMD (dBc)
90
80
70
60
20 40 60 80 100
f
DATA
= 200MSPS
f
DATA
= 250MSPS
f
DATA
= 160MSPS
05361-017
Figure 18. AD9779 Third-Order IMD vs. fOUT, 1× Interpolation
100
50
0 20 40 60 80 100 120 140 160 180 200 220
fOUT (MHz)
IMD (dBc)
90
80
70
60
fDATA = 160MSPS
fDATA = 250MSPS
fDATA = 200MSPS
05361-018
Figure 19. AD9779 Third-Order IMD vs. fOUT, 2× Interpolation
100
50
0 400
fOUT (MHz)
IMD (dBc)
90
80
70
60
40 80 120 160 200 240 280 320 360
fDATA = 150MSPS
fDATA = 200MSPS
fDATA = 100MSPS
05361-019
Figure 20. AD9779 Third-Order IMD vs. fOUT, 4× Interpolation
fOUT
(MHz)
IMD (dBc)
fDATA
= 75MSPS
fDATA
= 125MSPS
fDATA
= 100MSPS
90
100
80
70
60
50
450
425
400
375
350
325
300
275
250
225
200
175
150
125
100
75
50
25
0
fDATA
= 50MSPS
05361-020
Figure 21. AD9779 Third-Order IMD vs. fOUT, 8× Interpolation
100
50
0 200
fOUT
(MHz)
IMD (dBc)
90
80
70
60
100
20 40 60 80 120 140 160 180
PLL OFF
PLL ON
05361-021
Figure 22. AD9779 Third-Order IMD vs. fOUT, 4× Interpolation,
fDATA = 100 MSPS, PLL On vs. PLL Off
100
95
50
55
0 400360
fOUT
(MHz)
IMD (dBc)
90
80
85
70
75
60
65
40 80 120 160 200 240 280 320
05361-022
Figure 23. AD9779 Third-Order IMD vs. fOUT, over 50 Parts,4× Interpolation,
fDATA = 200 MSPS
AD9776/AD9778/AD9779
Rev. A | Page 18 of 56
100
50
55
60
65
70
75
80
85
90
95
0400
fOUT
(MHz)
IMD (dBc)
80 160 240 36032040 120 200 280
05361-117
0dBFS
–3dBFS
–6dBFS
Figure 24. IMD Performance vs. Digital Full-Scale Input, 4× Interpolation,
fDATA = 200 MSPS
100
50
55
60
65
70
75
80
85
90
95
0400
fOUT
(MHz)
IMD (dBc)
80 160 240 36032040 120 200 280
05361-118
20mA
10mA
30mA
Figure 25. IMD Performance vs. Full-Scale Output Current, 4× Interpolation,
fDATA = 200 MSPS
STOP 400.0MHz
SWEEP 1.203s (601 pts)VBW 20kHz
START 1.0MHz
*RES BW 20kHz
REF 0dBm
*PEAK
Log
10dB/
LGAV
51
W1
S3
£(f):
FTUN
SWP
S2
FC
AA
*ATTEN 20dB
EXT REF
DC COUPLED
05361-023
Figure 26. AD9779 Single Tone, 4× Interpolation, fDATA = 100 MSPS,
fOUT = 30 MHz
STOP 400.0MHz
SWEEP 1.203s (601 pts)VBW 20kHz
START 1.0MHz
*RES BW 20kHz
REF 0dBm
*PEAK
Log
10dB/
LGAV
51
W1
S3
£(f):
FTUN
SWP
S2
FC
AA
*ATTEN 20dB
EXT REF
DC COUPLED
05361-024
Figure 27. AD9779 Two-Tone Spectrum, 4× Interpolation,
fDATA = 100 MSPS, fOUT = 30 MHz, 35 MHz
–142
–146
–150
–154
–158
–162
–166
–170
0
f
OUT (MHz)
NSD (dBm/Hz)
20 40 60 80
0dBFS
–3dBFS
–6dBFS
05361-025
Figure 28. AD9779 Noise Spectral Density vs. Digital Full-Scale of Single-Tone
Input, fDATA = 200 MSPS, 2× Interpolation
–150
–170
0 100
f
OUT (MHz)
NSD (dBm/Hz)
–154
–158
–162
–166
20 40 60 80
f
DAC = 800MSPS
f
DAC = 400MSPS
f
DAC = 200MSPS
05361-026
Figure 29. AD9779 Noise Spectral Density vs. fDAC, Eight-Tone Input
with 500 kHz Spacing, fDATA = 200 MSPS
AD9776/AD9778/AD9779
Rev. A | Page 19 of 56
–150
–170
0 100
f
OUT (MHz)
NSD (dBm/Hz)
–154
–158
–162
–166
20 40 60 80
f
DAC = 800MSPS
f
DAC = 400MSPS
f
DAC = 200MSPS
05361-027
Figure 30. AD9779 Noise Spectral Density vs. fDAC,
Single-Tone Input at −6 dBFS
–55
–90
0 260
f
OUT (MHz)
ACLR (dBc)
–60
–65
–70
–75
–80
–85
20 40 60 80 100 120 140 160 180 200 220 240
–6dBFS
–3dBFS
0dBFS – PLL ON
0dBFS
05361-028
Figure 31. AD9779 ACLR for First Adjacent Band WCDMA, 4× Interpolation,
fDATA = 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF
–55
–90
0 260
f
OUT (MHz)
ACLR (dBc)
–60
–65
–70
–75
–80
–85
20 40 60 80 100 120 140 160 180 200 220 240
–6dBFS
–3dBFS
0dBFS – PLL ON
0dBFS
05361-029
Figure 32. AD9779 ACLR for Second Adjacent Band WCDMA, 4×
Interpolation, fDATA = 122.88 MSPS. On-Chip Modulation Translates
Baseband Signal to IF
–55
–90
0 260
f
OUT (MHz)
ACLR (dBc)
–60
–65
–70
–75
–80
–85
20 40 60 80 100 120 140 160 180 200 220 240
–6dBFS
–3dBFS
0dBFS – PLL ON
0dBFS
05361-030
Figure 33. AD9779 ACLR for Third Adjacent Band WCDMA, 4× Interpolation,
fDATA = 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF
AD9776/AD9778/AD9779
Rev. A | Page 20 of 56
SPAN 50MHz
SWEEP 162.2ms (601 pts)VBW 300kHz
CENTER 143.88MHz
*RES BW 30kHz
RMS RESULTS
CARRIER POWER
–12.49dBm/
3.84000MHz
FREQ OFFSET
5.000MHz
10.00MHz
15.00MHz
REF BW
3.840MHz
3.840MHz
3.840MHz
dBc
–76.75
–80.94
–79.95
dBm
–89.23
–93.43
–92.44
LOWER
dBc
–77.42
–80.47
–78.96
dBm
–89.91
–92.96
–91.45
UPPER
REF –25.28dBm
*AVG
Log
10dB/
PAVG
10
W1 S2
*ATTEN 4dB
EXT REF
05361-031
Figure 34. AD9779 WCDMA Signal, 4× Interpolation,
fDATA =122.88 MSPS, fDAC/4 Modulation
SPAN 50MHz
SWEEP 162.2ms (601 pts)VBW 300kHz
CENTER 151.38MHz
*RES BW 30kHz
1 –17.87dBm
2 –20.65dBm
3 –18.26dBm
4 –18.23dBm
TOTAL CARRIER POWER –12.61dBm/15.3600MHz
REF CARRIER POWER –17.87dBm/3.84000MHz
FREQ OFFSET
5.000MHz
10.00MHz
15.00MHz
INTEG BW
3.840MHz
3.840MHz
3.840MHz
dBc
–67.70
–70.00
–71.65
dBm
–85.57
–97.87
–99.52
LOWER
dBc
–67.70
–69.32
–71.00
dBm
–85.57
–87.19
–88.88
UPPER
REF –30.28dBm
*AVG
Log
10dB/
PAVG
10
W1 S2
*ATTEN 4dB
EXT REF
05361-032
Figure 35. AD9779 Multicarrier WCDMA Signal, 4× Interpolation,
fDAC =122.88 MSPS, fDAC/4 Modulation
1.5
0
CODE
INL (14-BIT LSB)
10k
1.0
0.5
0
–0.5
–1.0
–1.5
2k 4k 6k 8k
05361-033
Figure 36. AD9778 Typical INL
0.6
0
CODE
DNL (14-BIT LSB)
–0.2
–1.0
16k14k12k10k8k6k4k2k
0.4
0.2
0
–0.4
–0.6
–0.8
05361-034
Figure 37. AD9778 Typical DNL
AD9776/AD9778/AD9779
Rev. A | Page 21 of 56
100
50
0 400
f
OUT
(MHz)
IMD (dBc)
90
80
70
60
40 80 120 160 200 240 280 320 360
4× 200MSPS
4× 150MSPS
4× 100MSPS
05361-035
Figure 38. AD9778 IMD, 4× Interpolation
100
50
0 100
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
20 40 60 80
f
DATA
= 250MSPS
f
DATA
= 200MSPS
f
DATA
= 160MSPS
05361-036
Figure 39. AD9778 In-Band SFDR, 2× Interpolation
–90
0250
fOUT
(MHz)
ACLR (dBc)
–70
–80
–60
25 50 75 100 125 150 175 200 225
1ST ADJ CHAN
2ND ADJ CHAN
3RD ADJ CHAN
05361-037
Figure 40. AD9778 ACLR, Single-Carrier WCDMA, 4× Interpolation,
fDATA = 122.88 MSPS, Amplitude = −3 dBFS
SPAN 50MHz
SWEEP 162.2ms (601 pts)VBW 300kHz
CENTER 143.88MHz
*RES BW 30kHz
RMS RESULTS
CARRIER POWER
–12.74dBm/
3.84000MHz
FREQ OFFSET
5.000MHz
10.00MHz
15.00MHz
REF BW
3.884MHz
3.840MHz
3.840MHz
dBc
–76.49
–80.13
–80.90
dBm
–89.23
–92.87
–93.64
LOWER
dBc
–76.89
–80.02
–79.53
dBm
–89.63
–92.76
–92.27
UPPER
REF –25.39dBm
*AVG
Log
10dB/
PAVG
10
W1 S2
*ATTEN 4dB
05361-038
Figure 41. AD9778 ACLR, fDATA = 122.88 MSPS, 4× Interpolation,
fDAC/4 Modulation
–150
–170
0 100
fOUT
(MHz)
NSD (dBm/Hz)
–154
–158
–162
–166
20 40 60 80
fDAC
= 800MSPS
fDAC
= 400MSPS
fDAC
= 200MSPS
05361-039
Figure 42. AD9778 Noise Spectral Density vs. fDAC Eight-Tone Input
with 500 kHz Spacing, fDATA = 200 MSPS
–150
–170
0 100
fOUT
(MHz)
NSD (dBm/Hz)
–154
–158
–162
–166
20 40 60 80
fDAC
= 800MSPS
fDAC
= 400MSPS
fDAC
= 200MSPS
05361-040
Figure 43. AD9778 Noise Spectral Density vs. fDAC Single-Tone Input
at −6 dBFS, fDATA = 200 MSPS
AD9776/AD9778/AD9779
Rev. A | Page 22 of 56
0.4
0 4096
CODE
INL (12-BIT LSB)
–0.4
512 1024 256020481536 3072 3584
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
05361-041
Figure 44. AD9776 Typical INL
0.20
0 4096
CODE
DNL (12-BIT LSB)
2048
–0.20
512 1024 1536 2560 3072 3584
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
05361-042
Figure 45. AD9776 Typical DNL
100
50
0 400
f
OUT
(MHz)
IMD (dBc)
40 80 120 160 200 240 280 320 360
4× 200MSPS
4× 100MSPS
4× 150MSPS
95
90
85
80
75
70
65
60
55
05361-043
Figure 46. AD9776 IMD, 4× Interpolation
100
50
0 100
f
OUT
(MHz)
SFDR (dBc)
90
80
70
60
20 40 60 80
f
DATA
= 250MSPS
f
DATA
= 200MSPS
f
DATA
= 160MSPS
05361-044
Figure 47. AD9776 In-Band SFDR, 2× Interpolation
–90
0250
F
OUT
(MHz)
ACLR (dBc)
–55
25 50 75 100 125 150 175 200 225
1ST ADJ CHAN
2ND ADJ CHAN
3RD ADJ CHAN
–60
–65
–70
–75
–80
–85
05361-045
Figure 48. AD9776 ACLR, fDATA = 122.88 MSPS, 4× Interpolation,
fDAC/4 Modulation
SPAN 50MHz
SWEEP 162.2ms (601 pts)VBW 300kHz
CENTER 143.88MHz
*RES BW 30kHz
RMS RESULTS
CARRIER POWER
–12.67dBm/
3.84000MHz
FREQ OFFSET
5.000MHz
10.00MHz
15.00MHz
REF BW
3.884MHz
3.840MHz
3.840MHz
dBc
–75.00
–78.05
–77.73
dBm
–87.67
–90.73
–90.41
LOWER
dBc
–75.30
–77.99
–77.50
dBm
–87.97
–90.66
–90.17
UPPER
REF –25.29dBm
*AVG
Log
10dB/
PAVG
10
W1 S2
*ATTEN 4dB
05361-046
Figure 49. AD9776, Single Carrier WCDMA, 4× Interpolation,
fDATA = 122.88 MSPS, Amplitude = −3 dBFS
AD9776/AD9778/AD9779
Rev. A | Page 23 of 56
–150
–170
0 100
f
OUT
(MHz)
NSD (dBm/Hz)
–154
–158
–162
–166
20 40 60 80
f
DAC
= 800MSPS
f
DAC
= 400MSPS
f
DAC
= 200MSPS
10 30 50 70 90
05361-047
Figure 50. AD9776 Noise Spectral Density vs. fDAC, Eight-Tone Input
with 500 kHz Spacing, fDATA = 200 MSPS
–150
–170
0 100
f
OUT
(MHz)
NSD (dBm/Hz)
–154
–158
–162
–166
20 40 60 80
f
DAC
= 800MSPS
f
DAC
= 400MSPS
f
DAC
= 200MSPS
10 30 50 70 90
05361-048
Figure 51. AD9776 Noise Spectral Density vs. fDAC,
Single-Tone Input at −6 dBFS, fDATA = 200 MSPS
AD9776/AD9778/AD9779
Rev. A | Page 24 of 56
TERMINOLOGY
Integral Nonlinearity (INL)
INL is defined as the maximum deviation of the actual analog
output from the ideal output, determined by a straight line
drawn from zero scale to full scale.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when the
inputs are all 0s. For IOUTB, 0 mA output is expected when all
inputs are set to 1.
B
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the difference between the output
when all inputs are set to 1 and the output when all inputs are
set to 0.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits can
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temper ature D r ift
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree Celsius. For reference drift, the drift is
reported in ppm per degree Celsius.
Power Supply Rejection (PSR)
The maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band around its final value, measured from the
start of the output transition.
In-Band Spurious Free Dynamic Range (SFDR)
The difference, in decibels, between the peak amplitude of the
output signal and the peak spurious signal between dc and the
frequency equal to half the input data rate.
Out-of-Band Spurious Free Dynamic Range (SFDR)
The difference, in decibels, between the peak amplitude of the
output signal and the peak spurious signal within the band that
starts at the frequency of the input data rate and ends at the
Nyquist frequency of the DAC output sample rate. Normally,
energy in this band is rejected by the interpolation filters. This
specification, therefore, defines how well the interpolation
filters work and the effect of other parasitic coupling paths to
the DAC output.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
Interpolation Filter
If the digital inputs to the DAC are sampled at a multiple rate of
fDATA (interpolation rate), a digital filter can be constructed that
has a sharp transition band near fDATA/2. Images that typically
appear around fDAC (output data rate) can be greatly suppressed.
Adjacent Channel Leakage Ratio (ACLR)
The ratio in dBc between the measured power within a channel
relative to its adjacent channel.
Complex Image Rejection
In a traditional two-part upconversion, two images are created
around the second IF frequency. These images have the effect of
wasting transmitter power and system bandwidth. By placing
the real part of a second complex modulator in series with the
first complex modulator, either the upper or lower frequency
image near the second IF can be rejected.
AD9776/AD9778/AD9779
Rev. A | Page 25 of 56
THEORY OF OPERATION
The AD9776/AD9778/AD9779 combine many features that
make them very attractive DACs for wired and wireless
communications systems. The dual digital signal path and
dual DAC structure allow an easy interface with common
quadrature modulators when designing single sideband
transmitters. The speed and performance of the parts allow
wider bandwidths and more carriers to be synthesized than
in previously available DACs. The digital engine uses a break-
through filter architecture that combines the interpolation with
a digital quadrature modulator. This allows the parts to conduct
digital quadrature frequency upconversion. They also have
features that allow simplified synchronization with incoming
data and between multiple parts.
The serial port configuration is controlled by Register 0x00,
Bits<6:7>. It is important to note that the configuration changes
immediately upon writing to the last bit of the byte. For multi-
byte transfers, writing to this register can occur during the
middle of a communication cycle. Care must be taken to
compensate for this new configuration for the remaining bytes
of the current communication cycle.
The same considerations apply to setting the software reset,
RESET (Register 0x00, Bit 5) or pulling the RESET pin (Pin 70)
high. All registers are set to their default values, except
Register 0x00 and Register 0x04, which remain unchanged.
Use of only single-byte transfers when changing serial port
configurations or initiating a software reset is recommended to
prevent unexpected device behavior.
As described in this section, all serial port data is transferred
to/from the device in synchronization to the SCLK pin. If
synchronization is lost, the device has the ability to asynchro-
nously terminate an I/O operation, putting the serial port
controller into a known state and, thereby, regaining
synchronization.
SERIAL PERIPHERAL INTERFACE
SPI_SDO
SPI
PORT
66
SPI_SDI
67
SPI_SCLK
68
SPI_CSB
69
05361-049
Figure 52. SPI Port
The serial port is a flexible, synchronous serial communications
port allowing easy interface to many industry-standard micro-
controllers and microprocessors. The serial I/O is compatible
with most synchronous transfer formats, including both the
Motorola SPI® and Intel® SSR protocols. The interface allows
read/write access to all registers that configure the AD9776/
AD9778/AD9779. Single or multiple byte transfers are sup-
ported, as well as MSB-first or LSB-first transfer formats. The
serial interface ports can be configured as a single pin I/O (SDIO)
or two unidirectional pins for input/output (SDIO/SDO).
General Operation of the Serial Interface
There are two phases to a communication cycle with the
AD977x. Phase 1 is the instruction cycle (the writing of an
instruction byte into the device), coincident with the first eight
SCLK rising edges. The instruction byte provides the serial port
controller with information regarding the data transfer cycle,
Phase 2 of the communication cycle. The Phase 1 instruction
byte defines whether the upcoming data transfer is a read or
write, the number of bytes in the data transfer, and the starting
register address for the first byte of the data transfer. The first
eight SCLK rising edges of each communication cycle are used
to write the instruction byte into the device.
A logic high on the CSB pin followed by a logic low resets the
SPI port timing to the initial state of the instruction cycle.
From this state, the next eight rising SCLK edges represent the
instruction bits of the current I/O operation, regardless of the
state of the internal registers or the other signal levels at the
inputs to the SPI port. If the SPI port is in an instruction cycle
or a data transfer cycle, none of the present data is written.
The remaining SCLK edges are for Phase 2 of the communica-
tion cycle. Phase 2 is the actual data transfer between the device
and the system controller. Phase 2 of the communication cycle
is a transfer of one, two, three, or four data bytes as determined
by the instruction byte. Using one multibyte transfer is preferred.
Single-byte data transfers are useful in reducing CPU overhead
when register access requires only one byte. Registers change
immediately upon writing to the last bit of each transfer byte.
Instruction Byte
The instruction byte contains the information shown in
Table 9 .
Table 9. SPI Instruction Byte
MSB LSB
I7 I6 I5 I4 I3 I2 I1 I0
R/WN1 N0 A4 A3 A2 A1 A0
R/W, Bit 7 of the instruction byte, determines whether a read or
a write data transfer occurs after the instruction byte write.
Logic high indicates a read operation. Logic 0 indicates a write
operation.
N1 and N0, Bit 6 and Bit 5 of the instruction byte, determine
the number of bytes to be transferred during the data transfer
cycle. The bit decodes are listed in Table 10.
A4, A3, A2, A1, and A0—Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0, respec-
tively, of the instruction byte determine the register that is accessed
during the data transfer portion of the communication cycle.
AD9776/AD9778/AD9779
Rev. A | Page 26 of 56
For multibyte transfers, this address is the starting byte address.
The remaining register addresses are generated by the device
based on the LSB-first bit (Register 0x00, Bit 6).
Table 10. Byte Transfer Count
N1 N0 Description
0 0 Transfer one byte
0 1 Transfer three bytes
1 0 Transfer two bytes
1 1 Transfer four bytes
Serial Interface Port Pin Descriptions
Serial Clock (SCLK)
The serial clock pin synchronizes data to and from the device
and to run the internal state machines. The maximum frequency
of SCLK is 40 MHz. All data input is registered on the rising
edge of SCLK. All data is driven out on the falling edge of SCLK.
Chip Select (CSB)
Active low input starts and gates a communication cycle. It
allows more than one device to be used on the same serial
communications lines. The SDO and SDIO pins go to a high
impedance state when this input is high. Chip select should
stay low during the entire communication cycle.
Serial Data I/O (SDIO)
Data is always written into the device on this pin. However, this
pin can be used as a bidirectional data line. The configuration
of this pin is controlled by Register 0x00, Bit 7. The default is
Logic 0, configuring the SDIO pin as unidirectional.
Serial Data Out (SDO)
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. In the case where the device
operates in a single bidirectional I/O mode, this pin does not
output data and is set to a high impedance state.
MSB/LSB TRANSFERS
The serial port can support both MSB-first and LSB-first data
formats. This functionality is controlled by Register Bit LSB_FIRST
(Register 0x00, Bit 6). The default is MSB-first (LSB-first = 0).
When LSB-first = 0 (MSB-first) the instruction and data bit
must be written from MSB to LSB. Multibyte data transfers in
MSB-first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent data
bytes should follow from high address to low address. In MSB-first
mode, the serial port internal byte address generator decrements
for each data byte of the multibyte communication cycle.
When LSB-first = 1 (LSB-first) the instruction and data bit
must be written from LSB to MSB. Multibyte data transfers in
LSB-first format start with an instruction byte that includes the
register address of the least significant data byte followed by mul-
tiple data bytes. The serial port internal byte address generator
increments for each byte of the multibyte communication cycle.
The serial port controller data address decrements from the
data address written toward 0x00 for multibyte I/O operations if
the MSB-first mode is active. The serial port controller address
increments from the data address written toward 0x1F for
multibyte I/O operations if the LSB-first mode is active.
R/W N1 N0 A4 A3 A2 A1 A0 D7 D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
D7 D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
INSTRUCTION CYCLE DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
05361-050
Figure 53. Serial Register Interface Timing MSB-First
A0 A1 A2 A3 A4 N0 N1 R/W D0
0
D1
0
D2
0
D7
N
D6
N
D5
N
D4
N
D0
0
D1
0
D2
0
D7
N
D6
N
D5
N
D4
N
INSTRUCTION CYCLE DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
05361-051
Figure 54. Serial Register Interface Timing LSB-First
INSTRUCTION BIT 6INSTRUCTION BIT 7
CSB
SCLK
SDIO
t
DS
t
DS
t
DH
t
PWH
t
PWL
t
SCLK
05361-052
Figure 55. Timing Diagram for SPI Register Write
DATA BIT n–1DATA BIT n
CSB
SCLK
SDIO
SDO
t
DV
05361-053
Figure 56. Timing Diagram for SPI Register Read
AD9776/AD9778/AD9779
Rev. A | Page 27 of 56
SPI REGISTER MAP
Table 11.
Register
Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Def.
Comm 0x00 00 SDIO
Bidirectional
LSB/MSB First Software
Reset
Power-
Down
Mode
Auto
Power-
Down
Enable
PLL Lock
Indicator
(Read
Only)
0x00
0x01 01 Filter Interpolation Factor<1:0> Filter Modulation Mode<3:0> Zero
Stuffing
Enable
0x00
Digital
Control
0x02 02 Data Format Dual/Interleaved
Data Bus Mode
Real Mode Data
Clock
Delay
Enable
Inverse
Sinc
Enable
DATACLK
Invert
TxEnable
Invert
Q First 0x00
Sync
Control
0x03 03 Data Clock Delay Mode<1:0> Data Clock Divide
Ratio<1:0>
Reserved 0x00
0x04 04 Data Clock Delay<3:0> Output Sync Pulse Divide<2:0> Sync Out
Delay<4>
0x00
0x05 05 Sync Out Delay<3:0> Input Sync Pulse Frequency Ratio<2:0> Sync Input
Delay<4>
0x00
0x06 06 Sync Input Delay<3:0> Input Sync Pulse Timing Error Tolerance<3:0> 0x00
0x07 07 Sync
Receiver
Enable
Sync Driver
Enable
Sync
Triggering
Edge
DAC Clock Offset<4:0> 0x00
PLL
Control
0x08 08 PLL Band Select<5:0> PLL VCO AGC
Gain<1:0>
0xCF
0x09 09 PLL Enable PLL VCO Divider Ratio<1:0> PLL Loop
Divide
Ratio<1:0>
PLL Bias Setting<2:0> 0x37
Misc
Control
0x0A 10 PLL Control Voltage Range<2:0> (Read Only) PLL Loop Bandwidth Adjustment<4:0> 0x38
0x0B 11 I DAC Gain Adjustment<7:0> 0xF9 I DAC
Control
Register 0x0C 12 I DAC Sleep I DAC Power
Down
I DAC Gain
Adjustment<9:8>
0x01
0x0D 13 Auxiliary DAC1 Data<7:0> 0x00 Aux DAC1
Control
Register 0x0E 14 Auxiliary
DAC1 Sign
Auxiliary DAC1
Current Direction
Auxiliary
DAC1
Power-
Down
Auxiliary DAC1
Data<9:8>
0x00
0x0F 15 Q DAC Gain Adjustment<7:0> 0xF9 Q DAC
Control
Register 0x10 16 Q DAC Sleep Q DAC Power-
Down
Q DAC Gain
Adjustment<9:8>
0x01
0x11 17 Auxiliary DAC2 Data<7:0> 0x00
0x12 18 Auxiliary
DAC2 Sign
Auxiliary DAC2
Current Direction
Auxiliary
DAC2
Power-
Down
Auxiliary DAC2
Data<9:8>
0x00
Aux DAC2
Control
Register
0x13
to
0x18
19 to 24 Reserved
0x19 25 Sync Delay IRQ Sync
Delay
IRQ
Enable
Internal
Sync
Loopback
0x00
Interrupt
Register
0x1A
to
0x1F
26 to 31 Reserved
AD9776/AD9778/AD9779
Rev. A | Page 28 of 56
Table 12. SPI Register Description
Address
Register Name Reg. No. Bits Description Function Default
Comm Register 00 7 SDIO bidirectional 0: use SDIO pin as input data only 0
1: use SDIO as both input and output data
00 6 LSB/MSB first 0: first bit of serial data is MSB of data byte 0
1: first bit of serial data is LSB of data byte
00 5 Software reset
Bit must be written with a 1, then 0 to soft
reset SPI register map
0
00 4 Power-down mode 0: all circuitry is active
1: disable all digital and analog circuitry,
only SPI port is active
00 3 Auto power-down enable Controls auto power-down mode, see the
Power-Down and Sleep Modes section
0
00 1 PLL lock (read only) 0: PLL is not locked
1: PLL is locked 0
Digital Control Register 01 7:6 Filter interpolation factor 00: 1× interpolation 00
01: 2× interpolation
10: 4× interpolation
11: 8× interpolation
01 5:2 Filter modulation mode See Table 21 for filter modes 0000
01 0 Zero stuffing 0: zero stuffing off 0
1: zero stuffing on
02 7 Data format 0: signed binary 0
1: unsigned binary
02 6 Dual/interleaved data bus mode 0: both input data ports receive data 0
1: Data Port 1 only receives data
02 5 Real mode 0: enable Q path for signal processing 0
1: disable Q path data (internal Q channel
clocks disabled, I and Q modulators
disabled)
02 4 DATACLK delay enable See the Using Data Delay to Meet Timing
Requirements section.
02 3 Inverse sinc enable 0: inverse sinc filter disabled 0
1: inverse sinc filter enabled
02 2 DATACLK invert
0: output DATACLK same phase as internal
capture clock
0
1: output DATACLK opposite phase as
internal capture clock
02 1 TxEnable invert
Inverts the function of TxEnable Pin 39, see
the Interleaved Data Mode section
0
02 0 Q first 0: first byte of data is always I data at
beginning of transmit
1: first byte of data is always Q data at
beginning of transmit
Sync Control Register 03 7:6 Data clock delay mode 00: manual 00
03 5:4 Extra data clock divide ratio Data clock output divider (see Table 22 for
divider ratio)
00
03 3:0 Reserved 000
04 7:4 Data clock delay Sets delay of REFCLK in to DATACLK out 0000
04 3:1 Output sync pulse divide Sets frequency of SYNC_O pulses 000
04 0 Sync out delay Sync output delay, Bit 4
05 7:4 Sync out delay Sync output delay, Bits<3:0> 0
05 3:1 Input sync pulse frequency Input sync pulse frequency divider, see the
AN-822 application note
000
05 0 Sync input delay Sync input delay, Bit 4 0
AD9776/AD9778/AD9779
Rev. A | Page 29 of 56
Address
Register Name Reg. No. Bits Description Function Default
Sync Control Register 06 7:4 Sync input delay See the Multiple DAC Synchronization
section for details on using these registers
to synchronize multiple DACs
0
06 3:0
Input sync pulse timing error
tolerance
0
07 7 Sync receiver enable 0
07 6 Sync driver enable 0
07 5 Sync triggering edge 0
07 4:0
SYNC_I to input data sampling
clock offset
0
PLL Control 08 7:2 PLL band select VCO frequency range vs. PLL band select
value (see Table 18)
111001
08 1:0 VCO AGC gain control Lower number (low gain) is generally better
for performance
11
09 7 PLL enable 0: PLL off, DAC rate clock supplied by
outside source
0
1: PLL on, DAC rate clock synthesized
internally from external reference clock via
PLL clock multiplier
09 6:5 PLL VCO divide ratio FVCO/fDAC
00 × 1
01 × 2
10 × 4
11 × 8
09 4:3 PLL loop divide ratio fDAC/fREF
00 × 2
01 × 4
10 × 8
11 × 16
09 2:0 PLL bias setting Always set to 010 010
0A 7:5 PLL control voltage range 000 to 111, proportional to voltage at PLL
loop filter output, readback only
Misc Control
0A 4:0 PLL loop bandwidth adjustment See PLL Loop Filter Bandwidth section for
details
I DAC Control Register 0B 7:0 I DAC gain adjustment (7:0) LSB slice of 10-bit gain setting word
for I DAC
11111001
0C 7 I DAC sleep 0: I DAC on 0
1: I DAC off
0C 6 I DAC power-down 0: I DAC on 0
1: I DAC off
0C 1:0 I DAC gain adjustment (9:8) MSB slice of 10-bit gain setting word
for I DAC
01
0D 7:0 Aux DAC1 gain adjustment (7:0) LSB slice of 10-bit gain setting word for
Aux DAC1
00000000
0E 7 Aux DAC1 sign 0: positive
1: negative
0E 6 Aux DAC1 current direction 0: source 0
1: sink
0E 5 Aux DAC1 power-down 0: Aux DAC1 on 0
1: Aux DAC1 off
Aux DAC1 Control
Register
0E 1:0 Aux DAC1 gain adjustment (9:8) MSB slice of 10-bit gain setting word
for Aux DAC1
00
AD9776/AD9778/AD9779
Rev. A | Page 30 of 56
Address
Register Name Reg. No. Bits Description Function Default
Q DAC Control Register 0F 7:0 Q DAC gain adjustment (7:0) LSB slice of 10-bit gain setting word for
Q DAC
11111001
10 7 Q DAC sleep 0: Q DAC on 0
1: Q DAC off
10 6 Q DAC power-down 0: Q DAC on 0
1: Q DAC off
10 1:0 Q DAC gain adjustment (9:8) MSB slice of 10-bit gain setting word
for Q DAC
11 7:0 Aux DAC2 gain adjustment (7:0) LSB slice of 10-bit gain setting word for
Aux DAC2
00000000
12 7 Aux DAC2 sign 0: positive
1: negative
12 6 Aux DAC2 current direction 0: source 0
1: sink
12 5 Aux DAC2 power-down 0: Aux DAC2 on 0
1: Aux DAC2 off
Aux DAC2 Control
Register
12 1:0 Aux DAC2 gain adjustment (9:8) MSB slice of 10-bit gain setting word
for Aux DAC2
00
Interrupt Register 19 7 0
19 6 Sync delay IRQ Readback, must write 0 to clear 0
19 5 0
19 3 0
19 2 Sync delay IRQ enable 0
19 1 0
19 0 Internal sync loopback 0
AD9776/AD9778/AD9779
Rev. A | Page 31 of 56
INTERPOLATION FILTER ARCHITECTURE
The AD9776/AD9778/AD9779 can provide up to 8× interpola-
tion, or the interpolation filters can be entirely disabled. It is
important to note that the input signal should be backed off by
approximately 0.01 dB from full scale to avoid overflowing the
interpolation filters. The coefficients of the low-pass filters and
the inverse sinc filter are given in Table 13, Table 1 4, Table 15,
and Table 1 6. Spectral plots for the filter responses are shown in
Figure 57, Figure 58, and Figure 59.
Table 13. Half-Band Filter 1
Lower Coefficient Upper Coefficient Integer Value
H(1) H(55) −4
H(2) H(54) 0
H(3) H(53) +13
H(4) H(52) 0
H(5) H(51) −34
H(6) H(50) 0
H(7) H(49) +72
H(8) H(48) 0
H(9) H(47) −138
H(10) H(46) 0
H(11) H(45) +245
H(12) H(44) 0
H(13) H(43) −408
H(14) H(42) 0
H(15) H(41) +650
H(16) H(40) 0
H(17) H(39) −1003
H(18) H(38) 0
H(19) H(37) +1521
H(20) H(36) 0
H(21) H(35) −2315
H(22) H(34) 0
H(23) H(33) +3671
H(24) H(32) 0
H(25) H(31) −6642
H(26) H(30) 0
H(27) H(29) +20,755
H(28) +32,768
Table 14. Half-Band Filter 2
Lower Coefficient Upper Coefficient Integer Value
H(1) H(23) −2
H(2) H(22) 0
H(3) H(21) +17
H(4) H(20) 0
H(5) H(19) −75
H(6) H(18) 0
H(7) H(17) +238
H(8) H(16) 0
H(9) H(15) −660
H(10) H(14) 0
H(11) H(13) +2530
H(12) +4096
Table 15. Half-Band Filter 3
Lower Coefficient Upper Coefficient Integer Value
H(1) H(15) −39
H(2) H(14) 0
H(3) H(13) +273
H(4) H(12) 0
H(5) H(11) −1102
H(6) H(10) 0
H(7) H(9) +4964
H(8) +8192
Table 16. Inverse Sinc Filter
Lower Coefficient Upper Coefficient Integer Value
H(1) H(9) +2
H(2) H(8) −4
H(3) H(7) +10
H(4) H(6) −35
H(5) +401
10
–100
–4 4
f
OUT
(×Input Data Rate)
ATTENUATION (dB)
–3–2–10123
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
05361-054
Figure 57. 2× Interpolation, Low-Pass Response to ±4× Input Data Rate
(Dotted Lines Indicate 1 dB Roll-Off)
10
–100
–4 4
f
OUT
(×Input Data Rate)
ATTENUATION (dB)
–3–2–10123
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
05361-055
Figure 58. 4× Interpolation, Low-Pass Response to ±4× Input Data Rate
(Dotted Lines Indicate 1 dB Roll-Off)
AD9776/AD9778/AD9779
Rev. A | Page 32 of 56
10
–100
–4 4
f
OUT
(×Input Data Rate)
ATTENUATION (dB)
–3–2–10123
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
05361-056
Figure 59. 8× Interpolation, Low-Pass Response to ±4× Input Data Rate
(Dotted Lines Indicate 1 dB Roll-Off)
With the interpolation filter and modulator combined, the
incoming signal can be placed anywhere within the Nyquist
region of the DAC output sample rate. When the input signal is
complex, this architecture allows modulation of the input signal
to positive or negative Nyquist regions (see Table 17).
The Nyquist regions of up to 4× the input data rate can be seen
in Figure 60.
–4×
–8
–3×
–6
–2×
–4
–1×
–2
DC
1
1×
3
2×
5
3×
7–7 –5 –3 –1 2 4 6 8
4×
05361-057
Figure 60. Nyquist Zones
Figure 57, Figure 58, and Figure 59 show the low-pass response
of the digital filters with no modulation. By turning on the
modulation feature, the response of the digital filters can be
tuned to anywhere within the DAC bandwidth. As an example,
Figure 61 to Figure 67 show the nonshifted mode filter responses
(refer to Table 17 for shifted/nonshifted mode filter responses).
10
–100
–4 4
–3–2–10123
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
f
OUT
(×Input Data Rate)
ATTENUATION (dB)
05361-058
Figure 61. Interpolation/Modulation Combination of 4 fDAC/8 Filter
10
–100
–4 4
–3–2–10123
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
f
OUT
(×Input Data Rate)
ATTENUATION (dB)
05361-059
Figure 62. Interpolation/Modulation Combination of −3 fDAC/8 Filter
10
–100
–4 4
–3–2–10123
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
f
OUT
(×Input Data Rate)
ATTENUATION (dB)
05361-060
Figure 63. Interpolation/Modulation Combination of −2 fDAC/8 Filter
10
–100
–4 4
–3–2–10123
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
f
OUT
(×Input Data Rate)
ATTENUATION (dB)
05361-061
Figure 64. Interpolation/Modulation Combination of −1 fDAC/8 Filter
AD9776/AD9778/AD9779
Rev. A | Page 33 of 56
10
–100
–4 4
–3–2–10123
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
f
OUT
(×Input Data Rate)
ATTENUATION (dB)
05361-062
Figure 65. Interpolation/Modulation Combination of fDAC/8 Filter
10
–100
–4 4
–3 –2 –1 0 1 2 3
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
f
OUT
(×Input Data Rate)
ATTENUATION (dB)
05361-063
Figure 66. Interpolation/Modulation Combination of
2 fDAC/8 Filter in Shifted Mode
10
–100
–4 4
–3–2–10123
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
f
OUT
(
×
Input Data Rate)
ATTENUATION (dB)
05361-064
Figure 67. Interpolation/Modulation Combination of
3 fDAC/8 Filter in Shifted Mode
Shifted mode filter responses allow the pass band to be centered
around ±0.5 fDATA, ±1.5 fDATA, ±2.5 fDATA, and ±3.5 fDATA. Switching
to the shifted mode response does not modulate the signal.
Instead, the pass band is simply shifted. For example, picture
the response shown in Figure 67 and assume the signal in-band
is a complex signal over the bandwidth 3.2 fDATA to 3.3 fDATA. If
the even mode filter response is then selected, the pass band
becomes centered at 3.5 fDATA. However, the signal remains at
the same place in the spectrum. The shifted mode capability
allows the filter pass band to be placed anywhere in the DAC
Nyquist bandwidth.
The AD9776/AD9778/AD9779 are dual DACs with internal
complex modulators built into the interpolating filter response.
In dual channel mode, the devices expect the real and the
imaginary components of a complex signal at Digital Input
Port 1 and Digital Input Port 2 (I and Q, respectively). The DAC
outputs then represent the real and imaginary components of
the input signal, modulated by the complex carrier fDAC/2,
fDAC/4, or fDAC/8.
With Register 2, Bit 6 set, the device accepts interleaved data on
Port 1 in the I, Q, I, Q . . . sequence. Note that in interleaved
mode, the channel data rate at the beginning of the I and the Q
data paths are now half the input data rate because of the inter-
leaving. The maximum input data rate is still subject to the
maximum specification of the device. This limits the synthesis
bandwidth available at the input in interleaved mode.
With Register 0x02, Bit 5 (real mode) set, the Q channel and the
internal I and Q digital modulation are turned off. The output
spectrum at the I DAC then represents the signal at Digital
Input Port 1, interpolated by 1×, 2×, 4×, or 8×.
The general recommendation is that if the desired signal is
within ±0.4 × fDATA, the odd filter mode should be used. Outside
of this, the even filter mode should be used. In any situation, the
total bandwidth of the signal should be less than 0.8 × fDATA.
AD9776/AD9778/AD9779
Rev. A | Page 34 of 56
Table 17. Interpolation Filter Modes, (Register 0x01, Bits<5:2>)
Interpolation
Factor <7:6>
Filter
Mode
<5:2> Modulation
Nyquist
Zone
Pass
Band F_Low1Center1F_High1Comments
8 0x00 DC 1 −0.05 0 +0.05
8 0x01 DC shifted 2 0.0125 0.0625 0.1125
8 0x02 F/8 3 0.075 0.125 0.175
8 0x03 F/8 shifted 4 0.1375 0.1875 0.2375
8 0x04 F/4 5 0.2 0.25 0.3
8 0x05 F/4 shifted 6 0.2625 0.3125 0.3625
8 0x06 3F/8 7 0.325 0.375 0.425
8 0x07 3F/8 shifted 8 0.3875 0.4375 0.4875
8 0x08 F/2 −8 −0.55 −0.5 −0.45
8 0x09 F/2 shifted −7 −0.4875 −0.4375 −0.3875
8 0x0A −3F/8 −6 −0.425 −0.375 −0.343
8 0x0B −3F/8 shifted −5 −0.3625 −0.3125 −0.2625
8 0x0C −F/4 −4 −0.3 −0.25 −0.2
8 0x0D −F/4 shifted −3 −0.2375 −0.1875 −0.1375
8 0x0E −F/8 −2 −0.175 −0.125 −0.075
8 0x0F −F/8 shifted −1 −0.1125 −0.0625 −0.0125
In 8× interpolation;
BW (min) = 0.0375 × fDAC
BW (max) = 0.1 × fDAC
4 0x00 DC 1 −0.1 0 +0.1
4 0x01 DC shifted 2 0.025 0.125 0.225
4 0x02 F/4 3 0.15 0.25 0.35
4 0x03 F/4 shifted 4 0.275 0.375 0.475
4 0x04 F/2 −4 −0.6 −0.5 −0.4
4 0x05 F/2 shifted −3 −0.475 −0.375 −0.275
4 0x06 −F/4 −2 −0.35 −0.25 −0.15
4 0x07 −F/4 shifted −1 −0.225 −0.125 −0.025
In 4× interpolation;
BW (min) = 0.075 × fDAC
BW (max) = 0.2 × fDAC
2 0x00 DC 1 −0.2 0 +0.2
2 0x01 DC shifted 2 0.05 0.25 0.45
2 0x02 F/2 −2 −0.7 −0.5 −0.3
2 0x03 F/2 shifted −1 −0.45 −0.25 −0.05
In 2× interpolation;
BW (min) = 0.15 × fDAC
BW (max) = 0.4 × fDAC
1 Frequency normalized to fDAC.
AD9776/AD9778/AD9779
Rev. A | Page 35 of 56
INTERPOLATION FILTER MINIMUM AND
MAXIMUM BANDWIDTH SPECIFICATIONS
The AD977x uses a novel interpolation filter architecture that
allows DAC IF frequencies to be generated anywhere in the
spectrum. Figure 68 shows the traditional choice of DAC IF
output bandwidth placement. Note that there are no possible
filter modes in which the carrier can be placed near 0.5 × fDATA,
1.5 × fDATA, 2.5 × fDATA, and so on.
10
–80
–4 4
fOUT
(×Input Data Rate),
ASSUMING 8× INTERPOLATION
ATTENUATION (dB)
0
–10
–20
–30
–40
–50
–60
–70
–3–2–10123
+
fDAC
/2
+
fDAC
/4
+
fDAC
/8
BASEBAND
–
fDAC
/8
–
fDAC
/4
–
fDAC
/2
05361-065
Figure 68. Traditional Bandwidth Options for TxDAC Output IF
The filter architecture not only allows the interpolation filter
pass bands to be centered in the middle of the input Nyquist
zones (as explained in this section), but also allows the possi-
bility of a 3 × fDAC/8 modulation mode. With all of these filter
combinations, a carrier of given bandwidth can be placed
anywhere in the spectrum and fall into a possible pass band of
the interpolation filters. The possible bandwidths accessible
with the filter architecture are shown in Figure 69 and
Figure 70. Note that the shifted and nonshifted filter modes
are all accessible by programming the filter mode for the
particular interpolation rate.
10
–80
–4 4
f
OUT
(×Input Data Rate),
ASSUMING 8× INTERPOLATION
ATTENUATION (dB)
0
–10
–20
–30
–40
–50
–60
–70
–3 –2 –1 0 1 2 3
–
f
DAC
/2
–3 ×
f
DAC
/8
–
f
DAC
/4
–
f
DAC
/8
BASEBAND
+
f
DAC
/8
+
f
DAC
/4
+3 ×
f
DAC
/8
+
f
DAC
/2
05361-066
Figure 69. Nonshifted Bandwidths Accessible with the Filter Architecture
10
–80
–4 4
f
OUT
(
×
Input Data Rate),
ASSUMING 8
×
INTERPOLATION
ATTENUATION (dB)
0
–10
–20
–30
–40
–50
–60
–70
–3 –2 –1 0 1 2 3
SHIFTED –3
×
f
DAC
/8
SHIFTED –
f
DAC
/4
SHIFTED –
f
DAC
/8
SHIFTED –DC
SHIFTED –DC
SHIFTED –
f
DAC
/8
SHIFTED –
f
DAC
/4
SHIFTED –3
×
f
DAC
/8
05361-067
Figure 70. Shifted Bandwidths Accessible with the Filter Architecture
With this filter architecture, a signal placed anywhere in the
spectrum is possible. However, the signal bandwidth is limited
by the input sample rate of the DAC and the specific placement
of the carrier in the spectrum. The bandwidth restriction
resulting from the combination of filter response and input
sample rate is often referred to as the synthesis bandwidth, since
this is the largest bandwidth that the DAC can synthesize.
The maximum bandwidth condition exists if the carrier is
placed directly in the center of one of the filter pass bands. In
this case, the total 0.1 dB bandwidth of the interpolation filters
is equal to 0.8 × fDATA. As Table 17 shows, the synthesis band-
width as a fraction of DAC output sample rate drops by a factor
of 2 for every doubling of interpolation rate. The minimum
bandwidth condition exists, for example, if a carrier is placed at
0.25 × fDATA. In this situation, if the nonshifted filter response is
enabled, the high end of the filter response cuts off at 0.4 × fDATA,
thus limiting the high end of the signal bandwidth. If the shifted
filter response is enabled instead, then the low end of the filter
response cuts off at 0.1 × fDATA, thus limiting the low end of the
signal bandwidth. The minimum bandwidth specification that
applies for a carrier at 0.25 × fDATA is therefore 0.3 × fDATA. The
minimum bandwidth behavior is repeated over the spectrum
for carriers placed at (±n ± 0.25) × fDATA, where n is any integer.
DRIVING THE REFCLK INPUT
The REFCLK input requires a low jitter differential drive signal.
It is a PMOS input differential pair powered from
the 1.8 V supply, therefore, it is important to maintain the
specified 400 mV input common-mode voltage. Each input
pin can safely swing from 200 mV p-p to 1 V p-p about the
400 mV common-mode voltage. While these input levels are
not directly LVDS-compatible, REFCLK can be driven by an
offset ac-coupled LVDS signal, as shown in Figure 71.
AD9776/AD9778/AD9779
Rev. A | Page 36 of 56
LVDS_P_IN CLK+
50Ω
50Ω
0.1μF
0.1μF
LVDS_N_IN CLK–
V
CM
= 400mV
05361-068
Figure 71. LVDS REFCLK Drive Circuit
If a clean sine clock is available, it can be transformer-coupled
to REFCLK, as shown in Figure 71. Use of a CMOS or TTL
clock is also acceptable for lower sample rates. It can be routed
through a CMOS to LVDS translator, then ac-coupled, as
described in this section. Alternatively, it can be transformer-
coupled and clamped, as shown in Figure 72.
50Ω
50Ω
TTL OR CMOS
CLK INPUT CLK+
CLK–
V
CM
= 400mV
BAV99ZXCT
HIGH SPEED
DUAL DIODE
0.1μF
05361-069
Figure 72. TTL or CMOS REFCLK Drive Circuit
A simple bias network for generating VCM is shown in
Figure 73. It is important to use CVDD18 and CGND for the
clock bias circuit. Any noise or other signal that is coupled onto
the clock is multiplied by the DAC digital input signal and can
degrade DAC performance.
0.1μF 1nF
1nF
V
CM
= 400mV
CVDD18
CGND
1kΩ
2
87Ω
05361-070
Figure 73. REFCLK VCM Generator Circuit
INTERNAL PLL CLOCK MULTIPLIER/CLOCK
DISTRIBUTION
The internal clock structure on the devices allows the user to
drive the differential clock inputs with a clock at 1× or an
integer multiple of the input data rate or at the DAC output
sample rate. An internal PLL provides input clock multiplication
and provides all the internal clocks required for the interpolation
filters and data synchronization.
The internal clock architecture is shown in Figure 74. The
reference clock is the differential clock at Pin 5 and Pin 6. This
clock input can be run differentially or singled-ended by
driving Pin 5 with a clock signal and biasing Pin 6 to the
midswing point of the signal at Pin 5. The clock architecture
can be run in the following configurations:
PLL Enabled (Register 0x09, Bit 7 = 1)
The PLL enable switch shown in Figure 74 is connected to the
junction of the N1 dividers (PLL VCO divide ratio) and N2
dividers (PLL loop divide ratio). Divider N3 determines the
interpolation rate of the DAC, and the ratio N3/N2 determines
the ratio of reference clock/input data rate. The VCO runs
optimally over the range of 1.0 GHz to 2.0 GHz, so that N1
keeps the speed of the VCO within this range, although the
DAC sample rate can be lower. The loop filter components are
entirely internal and no external compensation is necessary.
PLL Disabled (Register 0x09, Bit 7 = 0)
The PLL enable switch shown in Figure 74 is connected to the
reference clock input. The differential reference clock input is
the same as the DAC output sample rate. N3 determines the
interpolation rate.
ADC
PHASE
DETECTION VCO
DAC
INTERPOLATION
RATE
INTERNAL
LOOP
FILTER
0x0A (4:0)
LOOP FILTER
BANDWIDTH
REFERENCE CLOCK
(PINS 5 AND 6)
0x0A (7:5)
PLL CONTROL
VOLTAGE RANGE
0x08 (7:2)
VCO RANGE
0x09 (7)
PLL ENABLE
INTERNAL DAC SAMPLE
RATE CLOCK
DATACLK OUT (PIN 37)
0x01 (7:6)
0x09 (6:5)
PLL VCO
DIVIDE RATIO
0x09 (4:3)
PLL LOOP
DIVIDE RATIO
÷N3
÷N2 ÷N1
05361-071
Figure 74. Internal Clock Architecture
AD9776/AD9778/AD9779
Rev. A | Page 37 of 56
Table 18. VCO Frequency Range vs. PLL Band Select Value
Typical PLL Lock Ranges
VCO Frequency Range in MHz
Typ at 25°C Typ over Temp
PLL Band Select
fLOW fHIGH fLOW fHIGH
111111 (63) Auto mode Auto mode
111110 (62) 2056 2170 2105 2138
111101 (61) 2002 2113 2048 2081
111100 (60) 1982 2093 2029 2061
111011 (59) 1964 2075 2010 2043
111010 58) 1947 2057 1992 2026
111001 (57) 1927 2037 1971 2006
111000 (56) 1907 2016 1951 1986
110111 (55) 1894 2003 1936 1972
110110 (54) 1872 1981 1913 1952
110101 (53) 1852 1960 1892 1931
110100 (52) 1841 1948 1881 1920
110011 (51) 1816 1923 1855 1895
110010 (50) 1796 1903 1835 1874
110001 (49) 1789 1895 1828 1867
110000 (48) 1764 1871 1803 1844
101111 (47) 1746 1853 1784 1826
101110 (46) 1738 1842 1776 1815
101101 (45) 1714 1820 1752 1794
101100 (44) 1700 1804 1737 1779
101011 (43) 1689 1790 1726 1764
101010 (42) 1657 1757 1695 1734
101001 (41) 1641 1738 1679 1714
101000 (40) 1610 1707 1649 1684
100111 (39) 1597 1689 1635 1666
100110 (38) 1568 1661 1607 1639
100101 (37) 1553 1641 1592 1617
100100 (36) 1525 1613 1562 1592
100011 (35) 1511 1595 1548 1572
100010 (34) 1484 1570 1519 1549
100001 (33) 1470 1552 1506 1528
100000 (32) 1441 1525 1474 1504
011111 (31) 1429 1509 1463 1487
011110 (30) 1403 1485 1433 1464
011101 (29) 1390 1469 1422 1447
011100 (28) 1362 1443 1391 1423
011011 (27) 1352 1429 1380 1407
011010 (26) 1325 1405 1352 1385
011001 (25) 1314 1390 1340 1369
011000 (24) 1290 1368 1315 1350
010111 (23) 1276 1351 1302 1332
010110 (22) 1253 1331 1277 1313
010101 (21) 1239 1313 1264 1295
010100 (20) 1183 1255 1205 1240
010011 (19) 1204 1275 1227 1259
010010 (18) 1151 1221 1172 1207
010001 (17) 1171 1240 1193 1224
010000 (16) 1148 1218 1170 1204
001111 (15) 1137 1204 1159 1189
Typical PLL Lock Ranges
VCO Frequency Range in MHz
Typ at 25°C Typ over Temp
PLL Band Select
fLOW fHIGH fLOW fHIGH
001110 (14) 1116 1184 1137 1170
001101 (13) 1106 1171 1127 1157
001100 (12) 1086 1152 1106 1138
001011 (11) 1075 1138 1095 1124
001010 (10) 1055 1119 1075 1106
001001 (9) 1045 1107 1065 1093
001000 (8) 1027 1090 1047 1076
000111 (7) 1016 1076 1034 1062
000110 (6) 998 1059 1016 1046
000101 (5) 987 1046 1005 1032
000100 (4) 960 1017 977 1004
000011 (3) 933 989 949 976
000010 (2) 908 962 923 950
000001 (1) 883 936 898 925
000000 (0) 859 911 873 899
VCO Frequency Ranges
Because the PLL band covers greater than a 2× frequency range,
there can be two options for the PLL band select: one at the low
end of the range and one at the high end of the range. Under
these conditions, the VCO phase noise is optimal when the user
selects the band select value corresponding to the high end of the
frequency range. Figure 75 shows how the VCO bandwidth and
the optimal VCO frequency varies with the band select value.
VCO Frequency Ranges over Temperature
The specifications given over temperature in Table 1 8 are for a
single part in a single lot. Part-to-part, and lot-to-lot, these
specifications can exhibit a mean shift of several register
settings. Systems should be designed to take this potential shift
into account to maintain optimal PLL performance.
PLL Loop Filter Bandwidth
The loop filter bandwidth of the PLL is programmed via SPI
Register 0x0A, Bits<4:0>. Changing these values switches
capacitors on the internal loop filter. No external loop filter
components are required. This loop filter has a pole at 0 (P1),
and then a zero (Z1) pole (P2) combination. Z1 and P2 occur
within a decade of each other. The location of the zero pole is
determined by Bits<4:0>. For a setting of 00000, the zero pole
occurs near 10 MHz. By setting Bits<4:0> to 11111, the Z1/P2
combination can be lowered to approximately 1 MHz. The
relationship between Bits<4:0> and the position of the zero pole
between 1 MHz and 10 MHz is linear. The internal components
are not low tolerance, however, and can drift by as much as ±30%.
For optimal performance, the bandwidth adjustment
(Register 0x0A, Bits<4:0>) should be set to 11111 for all
operating modes with PLL enabled. The PLL bias settings
AD9776/AD9778/AD9779
Rev. A | Page 38 of 56
(Register 0x09, Bits<2:0>) should be set to 111. The PLL control
voltage (Register 0x0A, Bits<7:5>) is read back and is propor-
tional to the dc voltage at the internal loop filter output. With
the PLL bias settings given in this section, the readback from
the PLL control voltage should typically be 010, or possibly 001
or 011. Anything outside of this range indicates that the PLL is
not operating correctly.
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
850
2150
2050
1950
1850
1750
1650
1450
1550
1350
1250
1150
1050
950
F
VCO
(MHz)
PLL BAND
05361-072
Figure 75. Typical PLL Band Select vs. Frequency at 25°C
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
850
2150
2050
1950
1850
1750
1650
1450
1550
1350
1250
1150
1050
950
F
VCO
(MHz)
PLL BAND
05361-113
Figure 76. Typical PLL Band Select vs. Frequency over Temperature
The AD977x has an autosearch feature that determines the
optimal settings for the PLL. To enable the autosearch mode, set
Register 0x08, Bits<7:2> to 11111b, and read back the value
from Register 0x08, Bits<7:2>. Autosearch mode is intended to
find the optimal PLL settings only, after which the same settings
should be applied in manual mode. It is not recommended that
the PLL be set to autosearch mode during regular operation.
FULL-SCALE CURRENT GENERATION
Internal Reference
Full-scale current on the I DAC and Q DAC can be set from
8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is
used to set up a current in an external resistor connected to
I120 (Pin 75). A simplified block diagram of the reference
circuitry is shown in Figure 77. The recommended value for the
external resistor is 10 k, which sets up an IREFERENCE in the
resistor of 120 A, which in turn provides a DAC output full-
scale current of 20 mA. Because the gain error is a linear
function of this resistor, a high precision resistor improves gain
matching to the internal matching specification of the devices.
Internal current mirrors provide a current-gain scaling, where
I DAC or Q DAC gain is a 10-bit word in the SPI port register
(Register 0x0A, Register 0x0B, Register 0x0E, and Register 0x0F).
The default value for the DAC gain registers gives an IFS of
approximately 20 mA, where IFS is equal to
32
1024
6
12
27
V2.1 ×
⎟
⎠
⎞
⎜
⎝
⎛⎟
⎠
⎞
⎜
⎝
⎛×+× gainDAC
R
I DAC
DAC FULL-SCALE
REFERENCE
CURRENT
CURRENT
SCALING
I DAC GAIN
Q DAC GAIN
Q DAC
AD9779
VREF
10kΩ
1.2V BAND GAP
0.1μFI120
05361-073
Figure 77. Reference Circuitry
35
0
01000
DAC GAIN CODE
I
FS
(mA)
30
25
20
15
10
5
200 400 600 800
05361-074
Figure 78. IFS vs. DAC Gain Code
Application of Auxiliary DACs in Single Sideband
Transmitter
Two auxiliary DACs are provided on the AD977x. The full-scale
output current on these DACs is derived from the 1.2 V band
gap reference and external resistor. The gain scale from the ref-
erence amplifier current IREFERENCE to the auxiliary DAC reference
current is 16.67 with the auxiliary DAC gain set to full scale
(10-bit values, SPI Register 0x0D and SPI Register 0x11), this
gives a full-scale current of approximately 2 mA for auxiliary
DAC1 and auxiliary DAC2. The auxiliary DAC outputs are not
differential. Only one side of the auxiliary DAC (P or N) is
active at one time. The inactive side goes into a high impedance
state (>100 k). In addition, the P or N outputs can act as
current sources or sinks. The control of the P and N side for
both auxiliary DACs is via Register 0x0E and Register 0x10,
Bits<7:6>. When sourcing current, the output compliance
AD9776/AD9778/AD9779
Rev. A | Page 39 of 56
voltage is 0 V to 1.6 V. When sinking current, the output
compliance voltage is 0.8 V to 1.6 V.
The auxiliary DACs can be used for local oscillator (LO) cancella-
tion when the DAC output is followed by a quadrature modulator.
This LO feedthrough is caused by the input referred dc offset
voltage of the quadrature modulator (and the DAC output offset
voltage mismatch) and can degrade system performance. Typical
DAC-to-quadrature modulator interfaces are shown in Figure 79
and Figure 80. Often, the input common-mode voltage for the
modulator is much higher than the output compliance range of
the DAC, so that ac coupling or a dc level shift is necessary. If the
required common-mode input voltage on the quadrature
modulator matches that of the DAC, then the dc blocking
capacitors in Figure 79 can be removed. A low-pass or band-pass
passive filter is recommended when spurious signals from the
DAC (distortion and DAC images) at the quadrature modulator
inputs can affect the system performance. Placing the filter at the
location shown in Figure 79 and Figure 80 allows easy design of
the filter, as the source and load impedances can easily be
designed close to 50 Ω.
05361-115
AD9779
Q DAC
AD9779
AUX
DAC2
25ΩTO 50Ω
0.1μF
0.1μF
OPTIONAL
PASSIVE
FILTERING
QUADRATURE
MODULATOR V+
QUAD MOD
Q INPUTS
AD9779
I DAC
AD9779
AUX
DAC1
25ΩTO 50Ω
0.1μF
0.1μF
OPTIONAL
PASSIVE
FILTERING
QUADRATURE
MODULATOR V+
QUAD MOD
I INPUTS
Figure 79. Typical Use of Auxiliary DACs AC Coupling to
Quadrature Modulator
05361-116
AD9779
I OR Q DAC
AD9779
AUX
DAC1 OR 2
25ΩTO 50Ω25ΩTO 50Ω
OPTIONAL
PASSIVE
FILTERING
QUADRATURE
MODULATOR V+
QUAD MOD
I OR Q INPUTS
Figure 80. Typical Use of Auxiliary DACs DC Coupling to Quadrature
Modulator with DC Shift
POWER DISSIPATION
Figure 81 to Figure 89 show the power dissipation of the 1.8 V
and 3.3 V digital and clock supplies in single DAC and dual
DAC modes. In addition to this, the power dissipation/current
of the 3.3 V supply (mode and speed independent) in single
DAC mode is 102 mW/31 mA. In dual DAC mode, this is
182 mW/55 mA. Furthermore, when the PLL is enabled, it adds
90 mW/50 mA to the 1.8 V clock supply regardless of the mode
of the AD9779.
0
0 250
f
DATA
(MSPS)
POWER (W)
0.6
0.7
0.5
0.4
0.3
0.2
0.1
25 50 75 100 125 150 175 200 225
8
×
INTERPOLATION,
ZERO STUFFING
8
×
INTERPOLATION
4
×
INTERPOLATION
4
×
INTERPOLATION,
ZERO STUFFING
2
×
INTERPOLATION
1
×
INTERPOLATION
2
×
INTERPOLATION,
ZERO STUFFING
1
×
INTERPOLATION,
ZERO STUFFING
05361-076
Figure 81. Total Power Dissipation, I Data Only, Real Mode
0
0 250
f
DATA
(MSPS)
POWER (W)
0.4
25 50 75 100 125 150 175 200 225
8
×
INTERPOLATION 4
×
INTERPOLATION
2
×
INTERPOLATION
1
×
INTERPOLATION
0.3
0.2
0.1
05361-078
Figure 82. Power Dissipation, Digital 1.8 V Supply, I Data Only, Real Mode,
Does Not Include Zero Stuffing
0
0 250
f
DATA
(MSPS)
POWER (W)
0.08
25 50 75 100 125 150 175 200 225
8
×
INTERPOLATION 4
×
INTERPOLATION
2
×
INTERPOLATION
1
×
INTERPOLATION
0.06
0.04
0.02
05361-079
Figure 83. Power Dissipation, Clock 1.8 V Supply, I Data Only, Real Mode,
Includes Modulation Modes, Does Not Include Zero Stuffing
AD9776/AD9778/AD9779
Rev. A | Page 40 of 56
0
0 250
f
DATA
(MSPS)
POWER (W)
0.075
25 50 75 100 125 150 175 200 225
0.050
0.025
ALL INTERPOLATION MODES
05361-080
Figure 84. Digital 3.3 V Supply, I Data Only, Real Mode, Includes Modulation
Modes and Zero Stuffing
0
0 300250 275
f
DATA
(MSPS)
POWER (W)
0.6
1.0
0.7
0.8
0.9
0.5
0.4
0.3
0.2
0.1
25 50 75 100 125 150 175 200 225
05361-077
1× INTERPOLATION
1× INTERPOLATION,
ZERO STUFFING
2× INTERPOLATION,
ALL MODULATION MODES
2× INTERPOLATION,
ZERO STUFFING
4× INTERPOLATION,
ALL MODULATION
MODES
4× INTERPOLATION,
ZERO STUFFING
8× INTERPOLATION, ALL
MODULATION MODES
8× INTERPOLATION,
ZERO STUFFING
Figure 85. Total Power Dissipation, Dual DAC Mode
0
0250
f
DATA (MSPS)
POWER (W)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
25 50 75 100 125 150 175 200 225
2× INTERPOLATION
4× INTERPOLATION
1× INTERPOLATION,
NO MODULATION
8× INTERPOLATION, fDAC/8,
fDAC/4,
fDAC/2,
NO MODULATION
05361-081
Figure 86. Power Dissipation, Digital 1.8 V Supply, I and Q Data, Dual DAC
Mode, Does Not Include Zero Stuffing
0
0250
f
DATA (MSPS)
POWER (W)
0.125
25 50 75 100 125 150 175 200 225
2× INTERPOLATION
4× INTERPOLATION
1× INTERPOLATION,
NO MODULATION
8× INTERPOLATION, fDAC/8,
fDAC/4,
fDAC/2,
NO MODULATION
0.100
0.075
0.050
0.025
05361-082
Figure 87. Power Dissipation, Clock 1.8 V Supply, I and Q Data, Dual DAC
Mode, Does Not Include Zero Stuffing
0
0 250
f
DATA (MSPS)
POWER (W)
0.075
25 50 75 100 125 150 175 200 225
0.050
0.025
ALL INTERPOLATION MODES
05361-083
Figure 88. Digital 3.3 V Supply, I and Q Data, Dual DAC Mode
0.16
0
0 1200
f
DAC (MSPS)
POWER (W)
0.14
0.12
0.10
0.08
0.06
0.04
0.02
200 400 600 800 1000
05361-084
Figure 89. Power Dissipation of Inverse Sinc Filter
AD9776/AD9778/AD9779
Rev. A | Page 41 of 56
POWER-DOWN AND SLEEP MODES INTERLEAVED DATA MODE
The AD977x has a variety of power-down modes, so that the
digital engine, main TxDACs, or auxiliary DACs can be powered
down individually or together. Via the SPI port, the main TxDACs
can be placed in sleep or power-down mode. In sleep mode, the
TxDAC output is turned off, thus reducing power dissipation.
The reference remains powered on, however, so that recovery
from sleep mode is very fast. With the power-down mode bit
set (Register 0x00, Bit 4), all analog and digital circuitry, including
the reference, is powered down. The SPI port remains active in
this mode. This mode offers more substantial power savings
than sleep mode, but the turn-on time is much longer. The
auxiliary DACs also have the capability to be programmed into
sleep mode via the SPI port. The auto power-down enable bit
(Register 0x00, Bit 3) controls the power-down function for the
digital section of the devices. The auto power-down function
works in conjunction with the TXENABLE pin (Pin 39) according
to the following:
The TxEnable bit is dual function. In dual port mode, it is
simply used to power down the digital section of the devices. In
interleaved mode, the IQ data stream is synchronized to
TXENABLE. Therefore, to achieve IQ synchronization,
TXENABLE should be held low until an I data word is present at
the inputs to Data Port 1. If a DATACLK rising edge occurs
while TXENABLE is at a high logic level, IQ data becomes
synchronized to the DATACLK output. TXENABLE can remain
high and the input IQ data remains synchronized. To be
backwards-compatible with previous DACs from Analog
Devices, Inc. such as the AD9777 and AD9786, the user can
also toggle TXENABLE once during each data input cycle, thus
continually updating the synchronization. If TXENABLE is
brought low and held low for multiple REFCLK cycles, then the
devices flush the data in the interpolation filters, and shut down
the digital engine after the filters are flushed. The amount of
REFCLK cycles it takes to go into this power-down mode is
then a function of the length of the equivalent 2×, 4×, or 8×
interpolation filter. The timing of TXENABLE, I/Q select, filter
flush, and digital power-down are shown in Figure 91.
TXENABLE (Pin 39) =
0: autopower-down enable =
0: flush data path with 0s
1: flush data for multiple REFCLK cycles; then
automatically place the digital engine in power-down
state. DACs, reference, and SPI port are not affected.
INTERLEAVED
INPUT DATA
TxENABLE CAN REMAIN
HIGH OR TOGGLE FOR
I/Q SYNCHRONIZATION
I1 Q1 I2 Q2
TxENABLE
FLUSHING
INTERPOLATION
FILTERS
POWER
DOWN DIGITAL
SECTION
05361-085
or TXENABLE (Pin 39) =
1: normal operation
As shown in Figure 90, the power dissipation saved by using the
power down mode is nearly proportional to the duty cycle of
the signal at the TXENABLE pin.
Figure 91. TXENABLE Function
The TXENABLE function can be inverted by changing the
status of Register 0x02, Bit 1. The other bit that controls IQ
ordering is the Q-first bit (Register 0x02, Bit 0). With the Q-first
bit reset to the default of 0, the IQ pairing that is latched is the
I1Q1, I2Q2, and so on. With IQ first set to 1, the first I data is
discarded and the pairing is I2Q1, I3Q2, and so on. Note that
with IQ-first set, the I data is still routed to the internal I
channel, the Q data is routed to the internal Q channel, and
only the pairing changes.
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0 10080604020
DUTY CYCLE (%)
POWER SAVINGS
05361-119
2× INT fDATA = 50MSPS
8× INT fDATA = 50MSPS
2× INT fDATA = 200MSPS
4× INT fDATA = 50MSPS
4× INT fDATA = 200MSPS
8× INT fDATA = 200MSPS
TIMING INFORMATION
Figure 92 to Figure 95 show some of the various timing
possibilities when the PLL is enabled. The combination of the
settings of N2 and N3 from Figure 74 means that the reference
clock frequency can be a multiple of the actual input data rate.
Figure 92 to Figure 95 show, respectively, what the timing looks
like when N2/N3 = 1 and 2.
Figure 90. Power Savings Based on Duty Cycle of TxEnable
If the TxEnable invert bit (Register 0x02, Bit 1) is set, the
function of this TXENABLE pin is inverted. In interleaved mode, set-up and hold times of DATACLK out to
data in are the same as those shown in Figure 92 to Figure 95. It
is recommended that any toggling of TXENABLE occur
concurrently with the digital data input updating. In this way,
timing margins between DATACLK, TXENABLE, and digital
input data are optimized.
AD9776/AD9778/AD9779
Rev. A | Page 42 of 56
05361-120
REFERENCE
CLOCK IN
DATA
CLOCK OUT
INPUT
DATA
t
SREFCLK
t
HREFCLK
t
SDATACLK
t
HDATACLK
Figure 92. Timing Specifications, PLL Enabled or Disabled, Interpolation = 1×
REFERENCE
CLOCK IN
DATA
CLOCK OUT
SYNC_IN
t
S_SYNC
t
H_SYNC
05361-121
INPUT
DATA
t
SREFCLK
t
HREFCLK
t
SDATACLK
t
HDATACLK
Figure 93. Timing Specifications, PLL Enabled or Disabled, Interpolation = 2×
0
5361-122
REFERENCE
CLOCK IN
DATA
CLOCK OUT
INPUT
DATA
tSREFCLK tHREFCLK
tSDATACLK tHDATACLK
tS_SYNC
tH_SYNC
SYNC_IN
Figure 94. Timing Specifications, PLL Enabled or Disabled, Interpolation = 4×
REFERENCE
CLOCK IN
DATA
CLOCK OUT
05361-123
INPUT
DATA
tSREFCLK tHREFCLK
tSDATACLK tHDATACLK
SYNC_IN
tS_SYNC
tH_SYNC
Figure 95. Timing Specifications, PLL Enabled or Disabled, Interpolation = 8×
AD9776/AD9778/AD9779
Rev. A | Page 43 of 56
Specifications are given in Table 19 for the drift of input data set
up and hold time vs. temperature, as well as the data keep out
window (KOW). Note that although these specifications do
drift, the length of the keep out window, where input data is
invalid, changes very little over temperature.
Table 19. AD9779 Timing Specifications vs. Temperature
Timing
Parameter Temperature
Min
tS
(ns)
Min
tH
(ns)
Max
KOW
(ns)
REFCLK to DATA −40°C −0.8 +2.2 +1.3
+25°C −1.1 +2.5 +1.4
+85°C −1.3 +2.9 +1.5
DATACLK to DATA −40°C +1.8 −0.4 +1.3
+25°C +2.1 −0.7 +1.4
+85°C +2.5 −0.9 +1.5
SYNC_I to
REFCLK
−40°C to +85°C −0.2 +1.0 +0.8
SYNCHRONIZATION OF INPUT DATA TO DATACLK
OUTPUT (PIN 37)
Synchronizing the input data bus to the DATACLK out signal is
achieved by meeting the timing relationships between DATACLK
and DATA timing specified in Tabl e 19. If the user is synchro-
nizing the input data to the DATACLK out, the sync input
(SYNC_I) signal does not need to be applied and can be ignored
(connect to GND).
SYNCHRONIZATION OF INPUT DATA TO THE
REFCLK INPUT (PIN 5 AND PIN 6) WITH PLL
ENABLED OR DISABLED
Synchronizing the input data bus to the REFCLK input requires
the use of the SYNC_I input pins (Pin 13 and Pin 14). If the
SYNC_I input is not used, there is a phase ambiguity between
the DATACLK out and the REFCLK in. This ambiguity matches
the interpolation rate in which the AD9779, for example, is
currently operating. Because input data is latched on the rising
edge of DATACLK, it is impossible for the user to determine
onto which one of the multiple internal DACCLK edges (as an
example, one of four edges in 4× interpolation) the input data
actually latches. For the user to specifically determine the exact
edge of REFCLK on which the data is being latched, a rising
edge must be periodically applied to SYNC_I. The frequency of
the SYNC_I signal must be equal to fDAC/2N, N being an integer,
and must be no greater than DATACLK for proper
synchronization. There is no limit on how slow the SYNC_I
signal can be driven. As long as the set up and hold timing
relationship between SYNC_I and REFCLK given in Table 19 is
met, the input data is latched on the immediate next rising edge
of REFCLK. Note that a rising edge of DATACLK out occurs
concurrently with the next REFCLK rising edge, after a short
propagation delay. Although this propagation delay is not
specified, input data setup and hold timing information is given
with respect to REFCLK in and DATACLK out in Figure 92 to
Figure 95. Also, note that in 1× interpolation, because there is
no phase ambiguity, there is no need to use the SYNC_I signal.
Valid Timing Window
In addition to the timing requirements of SYNC_I with respect
to REFCLK, it is important to understand that the valid timing
window for SYNC_I is limited by the internal DAC sample rate.
This is shown in Figure 96. When the tS and tH requirements are
met, the valid timing window for SYNC_I extends only as far as
one period of the internal DAC sample rate (minus tS and tH).
Failure to meet this timing specification can potentially result in
erroneous data being latched into the AD9779 digital inputs.
As an example, if the AD9779 input data rate is 122.88 MSPS
and the REFCLK is the same, with the AD9779 in 4× interpola-
tion, the DAC sample rate is 1/491.52 MHz or about 2 ns. With
a tS of −0.2 ns and tH of 1.0 ns, this gives a valid timing window
for SYNC_I of
2 ns − 0.8 ns = 1.2 ns
The timing window of the digital input data to REFCLK can be
moved in increments of one internal REFCLK cycle by using
the REFCLK OFFSET register (Register 0x7, Bits<4:0>).
Because SYNC_I can be run at the same frequency as REFCLK
when the PLL is enabled, best practice suggests that in this con-
dition, REFCLK and SYNC_I originate from the same source.
This limits the variation in time between these two signals and
makes the overall timing budget easier to achieve. A slight delay
may be necessary on the REFCLK path in this configuration to
add more timing margin between REFCLK and SYNC_I (see
Table 1 9 for timing relationship).
0
5361-124
REFCL
K
SYNC_I
t
S
t
H
t
DAC_SAMPLE
t
DAC_SAMPLE
Figure 96. Valid Timing Relationship for SYNC_I to REFCLK
AD9776/AD9778/AD9779
Rev. A | Page 44 of 56
Using Data Delay to Meet Timing Requirements
To meet strict timing requirements at input data rates of up to
250 MSPS, the AD977x has a fine timing feature. Fine timing
adjustments are made by programming values into the data
clock delay register (Register 0x04, Bits<7:4>). This register can
be used to add delay between the REFCLK in and the
DATACLK out. Figure 97 shows the default delay present when
DATACLK delay is disabled. The disable function bit is found
in Register 0x02, Bit 4. Figure 98 shows the delay present when
DATACLK delay is enabled and set to 0000. Figure 99 indicates
the delay when DATACLK delay is enabled and set to 1111.
Note that the setup and hold times specified for data to
DATACLK are defined for DATACLK delay disabled.
CH1 1.00VΩ
TEK RUN: 5.00GS/s SAMPLE
CH2 500mVΩM2.00ns CH1 420mV
Δ: 4.48nS
@: 40.28nS
2
1
05361-089
Figure 97. Delay from REFCLK to DATACLK with DATACLK Delay Disabled
CH1 1.00V
Ω
TEK RUN: 5.00GS/s SAMPLE
CH2 500mV
Ω
M2.00ns CH1 420mV
Δ
: 4.76nS
@: 35.52nS
2
1
05361-090
Figure 98. Delay from REFCLK to DATACLK Out with DATACLK Delay = 0000
CH1 1.00V
Ω
TEK RUN: 5.00GS/s SAMPLE
CH2 500mV
Ω
M2.00ns CH1 420mV
Δ
: 7.84nS
@: 32.44nS
2
1
05361-091
Figure 99. Delay from REFCLK to DATACLK Out with DATACLK Delay = 1111
The difference between the minimum delay shown in Figure 98
and the maximum delay shown in Figure 99 is the range
programmable using the DATACLK delay register. The delay
(in absolute time) when programming DATACLK delay
between 0000 and 1111 is a linear extrapolation between these
two figures. The typical delays per increment over temperature
are shown in Table 20.
Table 20. Data Delay Line Typical Delays Over Temperature
Delays −40°C +25°C +85°C Unit
Delay Between Disabled and
Enabled
370 416 432 ps
Average Delay per Increment 171 183 197 ps
The frequency of DATACLK out depends on several program-
mable settings: interpolation, zero stuffing, and interleaved/
dual port mode, all of which have an effect on the REFCLK
frequency. The divisor function between REFCLK and
DATACLK is equal to the values shown in Table 21.
Table 21. REFCLK to DATACLK Divisor Ratio
Interpolation Zero Stuffing Input Mode Divisor
1 Disabled Dual port 1
2 Disabled Dual port 2
4 Disabled Dual port 4
8 Disabled Dual port 8
1 Disabled Interleaved Invalid
2 Disabled Interleaved 1
4 Disabled Interleaved 2
8 Disabled Interleaved 4
1 Enabled Dual port 2
2 Enabled Dual port 4
4 Enabled Dual port 8
8 Enabled Dual port 16
1 Enabled Interleaved 1
2 Enabled Interleaved 2
4 Enabled Interleaved 4
8 Enabled Interleaved 8
AD9776/AD9778/AD9779
Rev. A | Page 45 of 56
In addition to this divisor function, DATACLK can be divided
by up to an additional factor of 4, according to the state of the
DATACLK divide register (Register 0x03, Bits<5:4>). For more
details, see Table 2 2).
Table 22. Extra DATACLK Divisor Ratio
Register 0x03, Bits<5:4> Divider Ratio
00 1
01 2
10 4
11 1
The maximum divisor resulting from the combination of the
values in Table 21, and the DATACLK divide register is 32.
Manual Input Timing Correction
Correction of input timing can be achieved manually. The
correction function is controlled by Register 0x03, Bits<7:6>.
The function is programmed as shown in Table 2 3.
Table 23. Input Timing Correction Mode
Register 0x03, Bits<7:6> Function
00 Error check disabled
01 Reserved
10 Reserved
11 Reserved
Necessary corrections can be made by adjusting DATACLK
delay and the DATACLK invert bit (Register 2, Bit 2).
DATACLK delay can then be swept to find the range over which
the timing is valid. The final value for data delay should be the
value that corresponds to the middle of the valid timing range.
If a valid timing range is not found during this sweep, the user
should invert the DATACLK invert bit and repeat the process.
Multiple DAC Synchronization
The AD9779 has programmable features that allow the CMOS
digital data bus inputs and internal filters on multiple devices to
be synchronized. This means that the DATACLK output signal
on one AD9779 can be used to register the output data for a data
bus delivering data to multiple AD9779s. The details of this opera-
tion are given in the Analog Devices Application Note AN-822.
AD9776/AD9778/AD9779
Rev. A | Page 46 of 56
EVALUATION BOARD OPERATION
The AD977x evaluation board is designed to optimize the DAC
performance and the speed of the digital interface, yet remains
user friendly. To operate the board, the user needs a power
source, a clock source, and a digital data source. The user also
needs a spectrum analyzer or an oscilloscope to look at the DAC
output. The diagram in Figure 100 illustrates the test setup. A
sine or square wave clock works well as a clock source. The dc
offset on the clock is not a problem, since the clock is ac-coupled
on the evaluation board before the REFCLK inputs. All
necessary connections to the evaluation board are shown in
more detail in Figure 101.
The evaluation board comes with software that allows the user
to program the SPI port. Via the SPI port, the devices can be
programmed into any of its various operating modes. When
first operating the evaluation board, it is useful to start with a
simple configuration, that is, a configuration in which the SPI
port settings are as close as possible to the default settings. The
default software window is shown in Figure 102. The arrows
indicate which settings need to be changed for an easy first time
evaluation. Note that this implies that the PLL is not being used
and that the clock being used is at the speed of the DAC output
sample rate. For a more detailed description of how to use the
PLL, see the PLL Loop Filter Bandwidth section.
DIGITAL
PATTERN
GENERATOR
ADAPTER
CABLES
CLOCK
GENERATOR
AD9779
EVALUATION
BOARD
CLKIN SPI PORT
DATACLK OUT
C
LOCK IN
SPECTRUM
ANALYZER
1.8V POWER SUPPLY
3.3V POWER SUPPLY
05361-097
Figure 100. Typical Test Setup
SPI PORT
AD9779
J1 CLOCK IN
P4 Digital Input Connec tor
S7 DCLKOUT
AUX33 DVDD18 DVDD33 CVDD18 AVDD33 J2
5V Supply
ANALOG
DEVICES
AD9779/8/6
REV D
S5 OUTPUT 1
S6 OUTPUT 2
AD8349
LOCA L OSC
INPUT
MODULATOR
OUTPUT
+5V
GND
JP4
JP15
JP8
JP14
JP3
JP16
JP2
JP17
05361-098
Figure 101. AD977x Evaluation Board Showing All Connections
AD9776/AD9778/AD9779
Rev. A | Page 47 of 56
1. SET INTERPOL
A
TION R
A
TE
2. SET INTERPOLATION FILTER MODE
3. SET INPUT DATA FORMAT
4. SET DATACLK POLARITY TO MATCH INPUT TIMING
0
5361-099
Figure 102. SPI Port Software Window
The default settings for the evaluation board allow the user to
view the differential outputs through a transformer that
converts the DAC output signal to a single-ended signal. On the
evaluation board, these transformers are designated T1A, T2A,
T3A, and T4A. There are also four common-mode transformers
on the board that are designated T1B, T2B, T3B, and T4B. The
recommended operating setup places the transformer and
common-mode transformer in series. A pair of transformers
and common-mode transformers are installed on each DAC
output, so that the pairs can be set up in either order. As an
example, for the frequency range of dc to 30 MHz, it is
recommended that the transformer be placed right after the
DAC. Above DAC output frequencies of 30 MHz, it is
recommended that the common-mode transformer is placed
right after the DAC outputs, followed by the transformer.
AD9776/AD9778/AD9779
Rev. A | Page 48 of 56
MODIFYING THE EVALUATION BOARD TO USE
THE AD8349 ON-BOARD QUADRATURE
MODULATOR
The evaluation board contains an Analog Devices AD8349
quadrature modulator. The AD977x and AD8349 provide an
easy-to-interface DAC/modulator combination that can be
easily evaluated on the evaluation board. To route the DAC
output signal to the quadrature modulator, the following
jumper settings must be made:
Unsoldered: JP14, JP15, JP16, JP17
Soldered: JP2, JP3, JP4, JP8
The DAC output area of the evaluation board is shown in
Figure 103. The jumpers that need to be changed to use the
AD8349 are circled. Also circled are the 5 V and GND
connections for the AD8349.
05361-100
Figure 103. Photo of Evaluation Board, DAC Output Area
AD9776/AD9778/AD9779
Rev. A | Page 49 of 56
EVALUATION BOARD SCHEMATICS
C69
0.1μF
+
CVDD18
TP2
BLACK
TP17
RED
TP1
RED
L1
EXC-CL4532U1
L6
EXC-CL4532U1
C68
0.1μF
C77
22μF
16V
CVDD18_IN
C66
0.1μF
+
VDDM
DGND2
2
TP14
RED
TP15
BLACK
L12
EXC-CL4532U1
L16
EXC-CL4532U1
C67
0.1μF
C46
22μF
16V
VDDM_IN
DGND2
TP13
RED
R51
9kΩ
R52
10kΩ
R55
10kΩ
C26
0.1μF
+
AVDD33
TP8
BLACK
TP19
RED
TP5
RED
L3
EXC-CL4532U1
L13
EXC-CL4532U1
C28
0.1μF
C20
22μF
16V
AVDD33_IN
C49
0.1μF
+
DPWR33
TP10
BLACK
TP21
RED
TP7
RED
L5
EXC-CL4532U1
L15
EXC-CL4532U1
C48
0.1μF
C22
22μF
16V
DPWR33_IN
+C70
0.1μF
DVDD18
TP4
BLACK
TP18
RED
TP3
RED
L2
EXC-CL4532U1
L7
EXC-CL4532U1
C71
0.1μF
C76
22μF
16V
DVDD18_IN
C42
0.1μF
+
DVDD33
TP9
BLACK
TP20
RED
TP6
RED
L4
EXC-CL4532U1
L14
EXC-CL4532U1
C45
0.1μF
C21
22μF
16V
DVDD33_IN
3U6 4
74AC14
11 U6 10
74AC14
9U6 8
74AC14
5U6 6
74AC14
2U5
CSB
S1
SWSECMA
S3
SWSECMA
S2
SWSECMA
1
1
3
2
74AC14
SPI_CSB
SPI_CLK
SPI_SDI
SPI_SDO
4U5 3
74AC14
6U5 5
74AC14
1U6 2
74AC14
12 U5 13
74AC14
10 U5 11
74AC14
8U5 9
74AC14
13 U6 12
74AC14
P1
1
2
3
4
5
6
R53
9kΩ
R54
9kΩ
SDI
13
2
SCLK
1
3
2
S4
SWSECMA
TP16
RED
TJAK06RAP
CLASS = IO
FCI-68898
SDO
1
3
2
05361-101
Figure 104. Evaluation Board, Rev. D, Power Supply Decoupling and SPI Interface
AD9776/AD9778/AD9779
Rev. A | Page 50 of 56
6
AUX1_N
AUX1_P
AUX2_P
CLK_N
CLK_P
DCLK
I120
IOUT1_N
IOUT1_P
IOUT1_N
IOUT1_P
IOUT2_P
IOUT2_N
IOUT2_P
IOUT2_N
IPTAT
IRQ
P1D0
P1D1
P1D10
P1D11
P1D12
P1D13
P1D14
P1D15
P1D2
P1D3
P1D4
P1D5
P1D6 TP12 RED
P1D7
P1D8
P1D9
P2D0
P2D1
P2D10
P2D11
P2D12
P2D13
P2D14
P2D15
P2D2
P2D3
P2D4
P2D5
P2D6
P2D0
P2D1
P2D2
P2D3
P2D4
P2D5
P2D6P2D7
JP7
JP18
U11
U1
9779TQFP
+C4
4.7µF
C29
1nF
VOLT
DVDD33
DVDD18
P2D8
P2D9
PAD
PLL_LOCK
RESET
SPI_CLK
SPI_CSB
SPI_SDI
SPI_SDO
SPI_CLK
SPI_CSB
SPI_SDI
SPI_SDO
SYNC_1N
SYNC_1P
SYNC_ON
SYNC_OP
VDD18_43
VDDA33_76
VDDA33_78
VDDA33_80
VDDC18_1
VDDC18_10
VDDC18_2
VDDC18_9
VDDD18_23
VDDD18_33
VDDD18_53
VDDD18_60
VDDD18
VDDD33_38
VDDD33_61
VREF_74
VSSA_77
VSSA_79
VSSA_81
VSSA_82
VSSA_85
VSSA_88
VSSA_91
VSSA_94
VSSA_95
VSSC_11
VSSC_3
VSSC_4
VSSC_7
VSSC_8
VSSD_15
VSSD_22
VSSD_32
VSSD_44
VSSD_54
VSSD_64
VSS_12
VSS_72
TX
AUX2_N
AUX1_N
AUX1_P
AUX2_P
AUX2_N
VDDA33_100
VSSA_99
VDDA33_98
VSSA_97
VDDA33_96
90
89
86
87
6
5
37
75
92
93
83
84
73
71
36
35
24
21
20
19
18
17
34
31
30
29
28
27
26
25
59
58
47
46
45
42
41
40
57
56
55
52
51
50
49
48
PAD
VCC
Y
NC
A
GND 3
2
5
4
SN74LVC1G34
1
65
70
68
69
67
66
14
13
62
63
43
100
76
78
80
96
98
1
10
2
9
23
33
53
60
16
38
61
74
77
79
81
82
85
88
91
94
95
97
99
11
3
4
7
8
15
22
32
44
54
64
12
72
39
DVDD18
DVDD33
P2D15
DPWR33
DPWR33
DPWR33
TP11 RED
+
C12
0.1µF
C30
1nF
C13
0.1µF
R59
22Ω
R26
22Ω
R26
22Ω
C5
4.7µF
C58
1nF
VOLT
CVDD18
AVDD33
CLK_N
CLK_P
+
C55
0.1µF
C57
0.1µF
C56
1nF
C31
1nF
S15
1
2
C14
0.1µF
C6
4.7µF
C40
0.1µF
VOLT
+
C36
1nF
C35
1nF
C39
0.1µF
C27
1nF
C11
0.1µF
C3
4.7µF
C33
1nF
JP4
D1ND1P
JP8
VOLT
+
C37
0.1µF
C24
1nF
C9
0.1µF
C1
4.7µF
+
C62
0.1µF C34
1nF
VOLT
+
C38
0.1µF
C25
1nF
C10
0.1µF
C2
4.7µF
C59
1nF
C61
1nF
C60
0.1µF
C18
1nF
C8
10µF
6.3V
VOLT
VOLT
+
C15
1nF
C7
4.7µF
C32
0.1µF
+
C78
4.7µF
S2
S7
DATACLK
1
2
1
2
S16
1
2
U10
74LCX112 74LCX112
KCLR
PRE
J
Q_
Q5
2
15
4
3
1
6
5
3
1
4
2
R63
10Ω
R7
0Ω
R11
50Ω
R10
50Ω
R8
0Ω
R32
25Ω
R58
22Ω
7
U10
KCLR
PRE
J
Q_
Q9
12
14
10
11
13
C84
0.1µF
R56
10Ω
R64
1kΩ
CR1
VAL
JP13
JP3
D2PD2N
JP2
JP16
JP17
R64
1kΩ
DPWR33
DGND;5
CR2
VAL
3
4
1
2
SW1
4
6P
3
S
ADTL1-12
T4B
1
3
1
1
4
2
2
TC1-1T
T4A S6
6
4
6P
3
S
ADTL1-12
T3B
1
3
1
4
2
TC1-1T
T3A
6
1
3S
6
P
ADTL1-12
T1B
4
TC1-1T
T1A
1
3S
6
P
ADTL1-12
T2B
4
1
3
6
2
1
3
2
TC1-1T
T2A
4
6
4
1
2
S5
R6
0Ω
R11
50Ω
R9
50Ω
R5
0Ω
JP14
JP15
05361-102
Figure 105. Evaluation Board, Rev. D, Circuitry Local to Devices
AD9776/AD9778/AD9779
Rev. A | Page 51 of 56
G2ENBL
VPS1
G1A
G1B
LOIP
VPS2
G4A
G4B
QBBP
VOUT
G3
IBBP
IBBN QBBN
LOIN
AD8349
98
7
3
4
6
12
13
14
16
11
10
1
215
5
U9
VDDM
DGND2
VDDM
R14
1kΩ
JP1
J4
C47
100pF
C72
0.1µF
C73
0.1µF
C41
10µF
10V
22
1
DGND2
2
DGND2
2
DGND2
2
DGND2
2
DGND2
DGND2
MODULATED OUTPUT
2
J5
JP9
2
1
DGND2
LOCAL OSC OUTPUT
C74
100pF
C54
0.1µF
C79
17.2pF
C65
17.2pF
C75
100pF
C51
0.1µF
+
JP13
R60
40Ω
R2
150Ω
R3
150Ω
R25
150Ω
R61
40Ω
1
3P
5
2S
ETC1-1-13
T4
4
6
4
P
1S
ADTL1-12
T3
3
JP10
R24
20Ω
R62
147.5Ω
C82
2.1pF
L11
55nH
C43
17.2pF
C44
17.2pF
C83
2.1pF
L10
55nH
R27
300Ω
D2N
D2P
AUX2_P
AUX2_N
R23
20Ω
C53
0.1µF
C52
17.2pF
C50
17.2pF
JP13
R20
40Ω
R4
150Ω
R12
150Ω
R17
150Ω
R21
40Ω
6
4P
1
S
ADTL1-12
T5
3
R15
20Ω
R22
147.5Ω
C81
2.1pF
L11
55nH
C63
17.2pF
C64
17.2pF
C80
2.1pF
L10
55nH
R19
300Ω
D1N
D1P
AUX1_P
AUX1_N
R16
20Ω
05361-103
Figure 106. Evaluation Board, Rev. D, AD8349 Quadrature Modulator
4
5S
3
2
R13
VAL
R30
1k
Ω
R31
300
Ω
R28
25
Ω
R29
25
Ω
P
ETC1-1-13
T2
J1
CLKIN
C19
0.1
μ
FC16
DNB
CVDD18
CLK_P
CLK_N
C17
0.1
μ
F
C23
0.1
μ
F
1
05361-104
Figure 107. Evaluation Board, Rev. D, DAC Clock Interface
AD9776/AD9778/AD9779
Rev. A | Page 52 of 56
A1
P4
PKG_TYPE = MOLEX110
VAL
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
C1
P4
PKG_TYPE = MOLEX110
VAL
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
CSB
SD1
P2D0
P2D2
P2D4
P2D6
P2D8
P2D10
P2D12
P2D14
P1D0
P1D2
P1D4
P1D6
P1D8
P1D10
P1D12
P1D14
DGND
BLK
E1
P4
PKG_TYPE = MOLEX110
VAL
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
SCLK
SD0
P2D1
P2D3
P2D5
P2D7
P2D9
P2D11
P2D13
P2D15
P1D1
P1D3
P1D5
P1D7
P1D9
P1D11
P1D13
P1D15
B1
P4
PKG_TYPE = MOLEX110
VAL
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
D1
P4
PKG_TYPE = MOLEX110
VAL
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
DGND1
BLK
05361-105
Figure 108. Evaluation Board, Rev. D, Digital Input Buffers
VAL
CNTERM_2P
1
2
J
2
5V
1
2
3
4
U2
ADP3339-1-8
CVDD18_IN
JP19
C85
1μF
C86
1μF
1
P2
2
1
2
3
4
U8
ADP3339-3-3
DPWR33_IN
JP23
C97
1μF
C96
1μF
1
2
3
4
U7
ADP3339-3-3
AVDD33_IN
JP22
C94
1μF
C93
1μF
1
2
3
4
U4
ADP3339-3-3
DVDD33_IN
JP21
C91
1μF
C92
1μF
1
2
3
4
U3
ADP3339-1-8
DVDD18_IN
JP20
C88
1μF
C89
1μF
05361-106
Figure 109. Evaluation Board, On-Board Voltage Regulators
AD9776/AD9778/AD9779
Rev. A | Page 53 of 56
05361-107
Figure 110. Evaluation Board, Rev. D, Top Silk Screen
05361-108
Figure 111. Evaluation Board, Rev. D, Top Layer
AD9776/AD9778/AD9779
Rev. A | Page 54 of 56
05361-109
Figure 112. Evaluation Board, Rev. D, Layer 2
05361-110
Figure 113. Evaluation Board, Rev. D, Layer 3
AD9776/AD9778/AD9779
Rev. A | Page 55 of 56
05361-111
Figure 114. Evaluation Board, Rev. D, Bottom Layer
05361-112
Figure 115. Evaluation Board, Rev. D, Bottom Silkscreen
AD9776/AD9778/AD9779
Rev. A | Page 56 of 56
OUTLINE DIMENSIONS
NOTES
1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
2
. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION O
F
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNA
L
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIV
E
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE
DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
1
25
26 50
76100
75
51
14.00 BSC SQ
16.00 BSC SQ
0.27
0.22
0.17
0.50 BSC
1.05
1.00
0.95
0.15
0.05
0.75
0.60
0.45
SEATING
PLANE
1.20
MAX
1
25
2650
76 100
75
51
6.50
NOM
7°
3.5°
0°
COPLANARITY
0.08
0.20
0.09
TOP VIEW
(PINS DOWN)
BOTTOM VIEW
(PINS UP)
CONDUCTIVE
HEAT SINK
PIN 1
Figure 116. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-100-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9776BSVZ1−40°C to +85°C 100-lead TQFP_EP SV-100-1
AD9776BSVZRL1−40°C to +85°C 100-lead TQFP_EP SV-100-1
AD9778BSVZ1−40°C to +85°C 100-lead TQFP_EP SV-100-1
AD9778BSVZRL1−40°C to +85°C 100-lead TQFP_EP SV-100-1
AD9779BSVZ1−40°C to +85°C 100-lead TQFP_EP SV-100-1
AD9779BSVZRL1−40°C to +85°C 100-lead TQFP_EP SV-100-1
AD9776-EB Evaluation Board
AD9778-EB Evaluation Board
AD9779-EBZ1 Evaluation Board
1 Z = RoHS Compliant Part.
©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05361-0-3/07(A)
