MC33351A Advanced Information Lithium Battery Protection Circuit for Three Battery Packs The MC33351A is a monolithic lithium battery protection circuit that is designed to enhance the useful operating life of three cell rechargeable battery packs. The MC33351A is specifically designed to be placed in a lithium battery pack where the battery cells continuously power it. In order to maintain cell operation within specified limits, the protection circuit senses cell voltages, and discharge current, and correspondingly controls the state of two P-channel MOSFET switches. These switches are connected in series with the positive terminal of the third cell and the positive terminal of the battery pack. During a fault condition, the MC33351A open circuits the pack by turning off one of these MOSFET switches. http://onsemi.com MARKING DIAGRAMS 20 1 MC35 1A1 ALYW TSSOP-20 DTB SUFFIX CASE 948E Features * Selectable Charge Interrupt Voltage Sensing Mode for Precise Cell Voltage Measurements * Programmable Overvoltage Delay * Choice of Discharge Current Limit Sensing Elements consisting of * * * * * either Low-Side Resistor or High-Side MOSFET Switches Programmable Discharge Current Limit Threshold and Shutdown Delay Selectable Cell Voltage Balancing Virtually Zero Current Sleepmode State when Cells are Discharged Minimum External Components for Inclusion within the Battery Pack Available in Low Profile Surface Mount Package Typical Three Cell Smart Battery Pack VCC/ High-Side Discharge Current Limit 16 Discharge Gate Drive Output 7 Charge Gate Drive Output 9 Charge and Discharge Gate Drive Common 8 17 Cell 3 18 Balance 3 19 A WL, L YY, Y WW,W = Assembly Location = Wafer Lot = Year = Work Week PIN CONNECTIONS Charge Inhibit Input 20 Balance 1 1 Discharge Inhibit/ Test Input 2 Overvoltage Shutdown Delay 3 Discharge Current Limit Shutdown Delay 4 Low-Side Discharge Current Limit Input 5 Charge Interrupt Mode Select 6 Discharge Gate Drive Output 7 Charge and Discharge Gate Drive Common 8 Charge Gate Drive Output 9 Undervoltage Fault Output 10 19 Balance 3 18 Cell 3 17 NC VCC/High Side 16 Discharge Current Limit 15 Cell 1/VC 14 Balance 2 13 Ground 12 Cell 2 High-Side 11 Discharge Current Limit Threshold (Top View) Cell 2 12 Balance 2 14 Undervoltage Fault Output MC33351A 11 High-Side Discharge Current LimitThreshold 4 Discharge Current Limit Shutdown Delay 5 Low-Side Current Limit Input Semiconductor Components Industries, LLC, 2000 June, 2000 - Rev. 3 ORDERING INFORMATION 10 Cell 1/VC 15 Balance 1 20 Ground 13 Overvoltage Shutdown Delay Charge 3 Interrupt 6 Mode Select 1 Charge Inhibit Input Device Package Shipping MC33351ADTB-1 TSSOP-20 75 Units/Rail MC33351ADTB-1R2 TSSOP-20 2500 Tape/Reel 2 Discharge Inhibit Input 1 Publication Order Number: MC33351A/D MC33351A Smart Battery Pack with Low-Side Discharge Current Sensing, Charge Interrupt Voltage Sensing, and Cell Voltage Balancing 4.7 M Discharge Switch Q2 Charge Switch Q1 Discharge Gate Drive RG Output 7 RG VCC/ High-Side Discharge Current Limit MC33351A Charge Gate Drive Output 9 Charge and Discharge Gate Drive Common 8 CI 16 17 R1 Cell 3 Floating Over/Under Cell Voltage Detector & Reference 18 Balance 3 19 Cell Selector 12 Ck 10 k Oscillator Balance 2 Cell 2 Ck 14 Undervoltage Fault Output Cell 1/VC Over/Under Data Latch & Control Logic 15 10 k Balance 1 Cell 1 En 10 20 Ground 13 Cell Voltage Balancing Logic Overvoltage Shutdown Delay 3 VCC 6 Charge Interrupt Mode Select Discharge Current Limit Detector 11 High-Side Discharge Current Limit Threshold 4 Discharge Current Limit Shutdown Delay Charge/Discharge Gate Drivers 10 k Cdly Rlim(LS) 5 Low-Side Discharge Current Limit Input Figure 1. 2 Discharge Inhibit Input Control Logic Inputs from Microcontroller Output Ports http://onsemi.com 2 Sense Enable VC 10 k 1 Charge Inhibit Input Control Logic Output R3 10 k Cell 2 To Microcontroller Input Port Cell 3 R2 5.1 k RT + 22 mfd CT MC33351A Smart Battery Pack with High-Side Discharge Current Sensing 4.7 M Discharge Switch Q2 Charge Switch Q1 Discharge Gate Drive Output 7 RG VCC/ High-Side Discharge Current Limit MC33351A RG Charge Gate Drive Output 9 Charge and Discharge Gate Drive Common 8 CI 16 17 R1 Cell 3 Floating Over/Under Cell Voltage Detector & Reference 18 Balance 3 19 Cell Selector 12 Ck 10 k Oscillator Balance 2 Cell 2 Ck 14 Undervoltage Fault Output Cell 1/VC Over/Under Data Latch & Control Logic 15 10 k Balance 1 Cell 1 En 10 20 Ground 13 Cell Voltage Balancing Logic Overvoltage Shutdown Delay 3 VCC 6 Charge Interrupt Mode Select Discharge Current Limit Detector Charge/Discharge Gate Drivers Rth(HS) 11 High-Side Discharge Current Limit Threshold 4 Discharge Current Limit Shutdown Delay 10 k Cdly 5 Low-Side Discharge Current Limit Input Figure 2. 2 Discharge Inhibit Input Control Logic Inputs from Microcontroller Output Ports http://onsemi.com 3 Sense Enable VC 10 k 1 Charge Inhibit Input Control Logic Output R3 10 k Cell 2 To Microcontroller Input Port Cell 3 R2 5.1 k RT + 22 mfd CT MC33351A MAXIMUM RATINGS AAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAA AAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAA Ratings Symbol Input Voltage (Measured with respect to Ground, Pin 13) Cell 1/Vc (Pin 15) Cell 2 (Pin 12) Cell 3 (Pin 18) Vcc/ High Side Discharge Current Limit (Pin 16) Charge Inhibit Input (Pin 1) Discharge Inhibit Input (Pin 2) Overvoltage Shutdown Delay (Pin 3) Discharge Current Limit Shutdown Delay (Pin 4) Low-Side Discharge Current Limit Input (Pin 5) Voltage Sampling Mode Select (Pin 6) Discharge Gate Drive Output (Pin 7) Charge Gate Drive Common (Pin 8) Charge Gate Drive Output (Pin 9) Undervoltage Fault Output (Pin 10) High-Side Current Limit Threshold (Pin 11) VIR Cell Balancing Current (Note 1) Balance 3, Source Current (Pin 19) Balance 1, Balance 2 Sink Current (Pin 20, 14) Ibal Undervoltage Fault Output Sink Current (Pin 10) Iflt Value Unit V 7.5 10 18 20 7.5 7.5 7.5 20 7.5 7.5 18 20 18 20 7.5 AAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAA AAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAA AAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAA AAA AAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAA AAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAA AAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAA AAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAA AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA mA 50 50 10 mA C/W RJA Thermal Resistance, Junction-to-Air DTB Suffix, TSSOP Plastic Package, Case 948E DW Suffix, SO-20L Plastic Package, Case 751D 135 105 Operating Temperature (Note 1) Storage Temperature TJ -40 to 150 C Tstg -55 to 150 C ELECTRICAL CHARACTERISTICS (Vcell 3 (Pin 18) = 10.5V, Vcell 2 (Pin 12) = 7.0V, Vcell 1 (Pin 15) = 3.5V, Cdly (Pin 4) = 1000 pF, TA = 25C) Characteristic Symbol Min 4.207 Overvoltage Hysteresis, VCell Decreasing Vth(OV) VH Delay tdly(OV) Typ Max Unit 4.293 V VOLTAGE SENSING Cell Charging Cutoff (Pin 15 to 13, 12 to 15, 18 to 12) Overvoltage Threshold, VCell Increasing MC33351A-1 One Overvoltage Sample (Pin 3 = Gnd) 50 125 200 mV 0 - 1.2 s AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA Two Consecutive Overvoltage Samples (Pin 3 = Vc) Cell Discharging Cutoff MC33351A-1 1.0 - 2.3 s Vth(UV) 2.185 2.3 2.415 V IIB - 28 - A t(smpl) - 1.0 - s Undervoltage Threshold, VCell Decreasing Input Bias Current During Cell Voltage Sampling Cell Voltage Sampling Rate Charge Interrupt Vth(Intrrpt) V Input Voltage Range (Pin 6) Enabled - - - (Vc/2+0.2 to Vc) (0 to Vc/2-0.2) - 20 - AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA Disabled Enabled Charge Interrupt Time NOTE: tIntrrp 1 Maximum package power dissipation limits must be observed. http://onsemi.com 4 - ms MC33351A ELECTRICAL CHARACTERISTICS (Vcell 3 (Pin 18) = 10.5V, Vcell 2 (Pin 12) = 7.0V, Vcell 1 (Pin 15) = 3.5V, Cdly (Pin 4) = 1000 pF, TA = 25C) Characteristic Symbol Min Typ Max CELL VOLTAGE BALANCING Internal Balancing MOSFET On-Resistance Unit W RDS(on) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA W Balance 3, (Pin 19) - 100 - Balance 1, Balance 2 (Pin 20, 14) - 50 - 200 280 380 mV 100 170 230 mV 2.5 6.0 ms 0.0 2.5 ms 59 mV CURRENT SENSING High-Side Discharge Current Limit (Pin 16 to Pin 8) Threshold Voltage Vth(HSdschg) Rpin 11 = 1.0 M Rpin 11 = 2.0 MW Delay Overcurrent Detect (Vsense = 250 mV) tdly(HSdschg) AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA W AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA W AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA AAAAAAAAAAAAAAAAA AAAAA AAAA AAAAA AAAA AAA Short Circuit Detect (Vsense = 1.0 V) Low-Side Discharge Current Limit (Pin 13 to Pin 5) Threshold Voltage Vth(LSdschg) 48 - tdly(LSdschg) 2.5 6.0 ms 0.3 0.4 ms Delay Overcurrent Detect (Vsense = 50 mV) Short Circuit Detect (Vsense = 200 mV) LOGIC Charge and Discharge Inhibit Inputs (Pin 1, 2) Threshold Voltage Vth(inhbt) tPL/H Vc/2 100 - V - - s Low State Sink Resistance - 100 - Off State Leakage Current (Vdrain = 16V) - 100 - nA Detection Delay Time Before Discharge MOSFET Turn Off (Note 2) - 16 - s RDS(source) - 100 - RDS(sink) - 100 - Operating (VCC = 12 V) - 15 20 A Sleepmode (VCC = 6.0 V) - - 500 nA Cell 1 Voltage 1.5 1.8 - Cell 2, or Cell 3 Voltage 0.7 0.8 - Propagation Delay to Respective Gate Drive Output - Undervoltage Fault Output (Pin 10) Charge and Discharge Gate Drive Outputs (Pin 9, 7) High State Source Resistance Low State Sink Resistance TOTAL DEVICE Average Cell Current ICC Minimum Operating Cell Voltage NOTE: VCC V 2 Refer to "Voltage Sensing" text of Operating Description. Guaranteed by Design Only; NOT TESTED. http://onsemi.com 5 MC33351A 4.35 CHARGE ON THRESHOLD (VOLTS) OVER VOLTAGE THRESHOLD (VOLTS) 4.45 4.40 4.35 4.30 4.25 4.20 4.15 -40 -25 -10 5 20 35 65 50 4.30 4.25 4.20 4.15 4.10 4.05 -40 80 80 60 60 DISCHARGE CURRENT (LOW SIDE) THRESHOLD IN MILLIVOLTS UNDERVOLTAGE THRESHOLD (VOLTS) 40 TEMPERATURE (C) 2.295 2.290 2.285 2.280 2.275 2.270 -20 0 20 40 60 80 58 56 54 52 50 48 46 44 42 40 -40 -20 0 20 40 60 80 TEMPERATURE (C) TEMPERATURE (C) Figure 5. Undervoltage Threshold versus Temperature Figure 6. Discharge Current (Low Side) versus Temperature DISCHARGE CURRENT THRESHOLD (mV) 210 DISCHARGE CURRENT (HIGH SIDE) THRESHOLD (MILLIVOLTS) 20 Figure 4. Charge ON Voltage Threshold versus Temperature 2.300 205 200 195 190 185 180 -40 0 Figure 3. Over Voltage Threshold versus Temperature 2.305 2.265 -40 -20 TEMPERATURE (C) -20 0 20 40 60 80 350 330 310 290 270 250 230 210 190 170 150 0.7 0.9 1.1 1.3 1.5 1.7 1.9 TEMPERATURE (C) RESISTANCE (mW) Figure 7. Discharge Current (High Side) Threshold versus Temperature (R11 = 1.5 mOhms) Figure 8. Discharge Current (High Side) versus Resistance http://onsemi.com 6 2.1 MC33351A 4.2 5.0 4.0 4.6 I EE (nA) 3.6 4.2 3.8 3.4 3.4 3.2 3.0 9.5 10 10.5 11 11.5 3.0 7.0 12 7.5 8.0 8.5 VCC (V) (3 X Vcell) VCC (V) = (3 X Vcell) Figure 9. VCC versus IEE (No Load) Figure 10. VCC versus IEE (Sleep-Mode) 250 TIME DELAY (I sense Vth to D gate) (ms) IEE ( A) 3.8 200 150 100 50 0 0 5000 10000 15000 20000 Capacitance (pF) Figure 11. Discharge Current Limit Shutdown Delay versus Capacitance http://onsemi.com 7 9.0 MC33351A PIN FUNCTION DESCRIPTION Pin No. AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA Function Description 1 Charge Inhibit Input A logic low level at this input will disable battery pack charging. A 10 k internal pull-up resistor connects from this pin to VC. 2 Discharge Inhibit Input A logic low level at this input will disable battery pack discharging. A 10 k internal pull-up resistor connects from this pin to VC. Also, connecting this pin to 3.0V above VC the internal logic is held in reset state and both MOSFET switches are turned on. 3 Overvoltage Shutdown Delay This input controls the required number of cell overvoltage events that must be detected before charge switch Q1 is turned off. With a logic level low at this input, charge switch Q1 turns off after a single overvoltage event is detected. With a logic level high, charge switch Q1 turns off after two successive overvoltage events are detected. 4 Discharge Current Limit Shutdown Delay A capacitor connects from this pin to ground and is used to program a time delay from when the discharge current limit is exceeded to when discharge switch Q2 is turned off. 5 Low-Side Discharge Current Limit Input This pin is used to monitor the load induced voltage drop that appears across current sensing resistor Rlim(LS). This voltage drop is sensed by pins 13 and 5. 6 Charge Interrupt Mode Select The logic level that is applied to this input determines if the charge current will be interrupted during the cell voltage sampling period. The charge current is interrupted when this input is connected to VC, and not interrupted when connected to ground, pin 13. 7 Discharge Gate Drive Output This output connects to the gate of discharge switch Q2 allowing it to enable or disable battery pack discharging. 8 Charge and Discharge Gate Drive Common This pin provides a gate turn-off path for charge switch Q1. The charge switch source and the battery pack positive terminal connect to this point. 9 Charge Gate Drive Output This output connects to the gate of charge switch Q1 allowing it to enable or disable battery pack charging. 10 Undervoltage Fault Output This is an open drain output that is active low when an undervoltage fault limit has been exceeded. Discharge switch Q2 will turn off 16 seconds after the Fault goes low. 11 High-Side Discharge Current Limit Threshold A resistor connects from this pin to ground and is used to program the high-side discharge current limit threshold. The programmed threshold voltage is sensed by pins 16 and 8. 12 Cell 2 This pin connects to a high impedance node of the Cell Selector where it is used to monitor the positive terminal of Cell 2 and the negative terminal of Cell 3. 13 Ground This is the protection IC ground and all voltage ratings are with respect to this pin. 14 Balance 2 This pin is used if cell balancing is desired. It connects to the drain of an internal N-channel MOSFET and is active low during the balancing of Cell 2. 15 Cell 1/VC This is a multi-function pin that connects to a high impedance node of the Cell Selector where it is used to monitor the positive terminal of Cell 1 and the negative terminal of Cell 2. This pin also provides bias for the internal logic. 16 VCC/High-Side Discharge Current Limit This is a multi-function pin that connects to a high impedance node of the Cell Selector where it is used to monitor the positive terminal of Cell 3 and to provide positive supply voltage for the protection IC. This pin can also be used for high-side discharge current limit protection by monitoring the load induced voltage drop that appears across the on-resistance of switches Q2 and diode of Q1. This voltage drop is sensed by pins 16 and 8. 17 NC No Connection 18 Cell 3 This pin connects to a high impedance node of the Cell Selector where it is used to monitor the positive terminal of Cell 3 and VCC. 19 Balance 3 This pin is used if cell balancing is desired. It connects to the drain of an internal P-channel MOSFET and is active high during the balancing of Cell 3. 20 Balance 1 This pin is used if cell balancing is desired. It connects to the drain of an internal N-channel MOSFET and is active low during the balancing of Cell 1. http://onsemi.com 8 MC33351A AAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAA AAAA AAAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAAA AAAA PROTECTION CIRCUIT OPERATING MODE TABLE Outputs MOSFET Switches (Note 3) Input Conditions Cell Status Cell Balancing Circuit Operation Battery Pack Status Charge Q1 Discharge Q2 Balancing Outputs Both Charge MOSFET Q1 and Discharge MOSFET Q2 are on. The battery pack is available for charging or discharging. On On Active Charge Voltage Limit Fault: VCell Vth(OV) for tdly(OV) tdly(OV) = 0 to 1.2 s, Pin 3 to 13 1.0 to 2.1 s, Pin 3 to 15 Charge MOSFET Q1 is latched off and the cells are disconnected from the charging source. An internal hysteresis voltage is generated when the overvoltage cell is sensed. The shutdown delay is programmable for either one or two successive overvoltage events by the state of Pin 3. The battery pack is available for discharging. On to Off On Active Charge Voltage Limit Reset: VCell < (Vth(OV) - VH) for 1.2 s Charge MOSFET Q1 will turn on when the voltage across the overvoltage cell falls sufficiently to overcome the internal hysteresis voltage. This can be accomplished by applying a load to the battery pack. Off to On On Active Discharge Current Limit Fault: VPin 16 (VPin 8 + Vth(HS dschg) for tdly(HS dschg) or VPin 5 (VPin 13 + Vth(LS dschg) for tdly(LS dschg) Discharge MOSFET Q2 is latched off and the cells are disconnected from the load. Q2 will remain in the off state as long as VPin 16 exceeds VPin 8 by VTH(HSdschrg). A discharge current limit fault can be activated by either high-side or a low-side current sensing methods. The battery pack is available for charging. On On to Off Active Discharge Current Limit Reset: VPin 16 - VPin 8 < VTH(HSdschrg) The Sense Enable circuit will reset and turn on discharge MOSFET Q2 when VPin 16 no longer exceeds VPin 8 by 2.0 V. This can be accomplished by either disconnecting the load from the battery pack, or by connecting the battery pack to the charger. On Off to On Active Discharge Voltage Limit Fault: VCell Vth(UV) for 2.1 s Undervoltage Fault Output (Pin 10) is driven low after two successive undervoltage events are detected. After a 16 second delay, discharge MOSFET Q2 is latched off, the cells are disconnected from the load, and the protection circuit enters a low current sleepmode state. The battery pack is available for charging. On On to Off after 16 s Disabled Discharge Voltage Limit Reset: VPin 8 > (VPin 16 + 0.6 V) The Sense Enable circuit will reset and turn on discharge MOSFET Q2 when VPin 8 exceeds VPin 16 by 0.6 V. This can be accomplished by connecting the battery pack to the charger. On Off to On Active This condition can happen if there is a defective cell in the battery pack. The protection circuit will remain in the sleepmode state until the battery pack is connected to a charger. If Cell 2, or 3 is faulty and a charger is connected, the protection circuit will cycle in and out of sleepmode. If Cell 1 is faulty (<1.5 V) the protection circuit logic will not function and the battery pack cannot be charged. Cycles Cell 1 Good Cycles Cell 1 Good Cycles Cell 1 Good Disabled Cell 1 Faulty Disabled Cell 1 Faulty Disabled Cell 1 Faulty CELL CHARGING/DISCHARGING Storage or Nominal Operation: No current or voltage faults CELL CHARGING FAULT/RESET CELL DISCHARGING FAULT/RESET VPin 5 - VPin 13 < VTH(LSdschrg) FAULTY CELL Simultaneous Charge and Discharge Voltage Limit Faults NOTE: 3 Charge switch Q1 and discharge switch Q2 can be selectively turned off via the appropriate inhibit input except during the sleepmode state. http://onsemi.com 9 MC33351A OPERATING DESCRIPTION INTRODUCTION The demand for smaller lightweight portable electronic equipment has dramatically increased the requirements of battery performance. Today's most attractive chemistries include lithium-polymer, lithium-ion, and lithium-metal. Each of these chemistries require electronic protection in order to constrain cell operation to within the manufacturers limits. Rechargeable lithium-based cells require precise charge and discharge termination limits for both voltage and current in order to maximize cell capacity, cycle life, and to protect the end user from a catastrophic event. The MC33351A features internally-fixed cell voltage limits, programmable cell voltage balancing, low operating current, a virtually zero current sleepmode state, and requires few external components. 7 9 8 16 17 18 Cell 3 19 12 Cell 2 MC33351A 10 14 OPERATING DESCRIPTION 15 The MC33351A is specifically designed to be placed in the battery pack where it can be continuously powered from three lithium cells. In order to maintain cell operation within specified limits, the protection circuit senses both cell voltage and discharge current, and correspondingly controls the state of two P-channel MOSFET switches. These switches, Q1 and Q2, are placed within the series path of the positive terminal of cell 3 and the positive terminal of the battery pack. For lowside current limit sense, a resistor is placed within the series path of the negative terminal of Cell 1 and the negative terminal of the battery pack. This configuration allows the protection circuit to interrupt the appropriate charge or discharge path FET in the event that a programmed voltage or current limit for any cell has been exceeded. A functional description of the protection circuit blocks follows. Refer to the detailed block diagram shown in Figure 1. Voltage Sensing Individual cell voltage sensing is accomplished by the use of the Cell Selector in conjunction with the Floating Over/Under Voltage Detector and Reference block. The Cell Selector applies the voltage of each cell across an internal resistor divider string. The voltage at each of the tap points is sequentially polled and compared to an internal reference. If a limit has been exceeded, the result is stored in the Over/Under Data Latch and Control Logic block. The Cell Selector is gated on for a 4.0 ms period at a fixed one second repetition rate. This low duty cycle sampling technique reduces the average load current that the divider presents across each cell, thus extending the useful battery pack capacity. Cell 1 20 13 3 6 1 4 5 1 2 Figure 12. Simplified Smart Battery Pack AAAAA AAAA AAAAA AAAAA AAAAA AAAA AAAAA AAAAA AAAAA AAAA AAAAA AAAAA AAAAA AAAA AAAAA AAAAA AAAAA AAAA AAAAA AAAAA AAAAA AAAA AAAAA AAAAA AAAAA AAAA AAAAA AAAAA AAAAA AAAA AAAAA AAAAA Cell Sensing Sequence Polling Sequence 1 2 3 4 5 6 Time (ms) 0.25 0.25 0.25 0.25 0.25 0.25 Cell Sensed Cell 1 Cell 2 Cell 3 Cell 1 Cell 2 Cell 3 Tested Limit Overvoltage Overvoltage Overvoltage Undervoltage Undervoltage Undervoltage By incorporating this polling technique with a single floating comparator and voltage divider, a significant reduction of circuitry and trim elements is achieved. This results in a smaller die size, lower cost, and reduced operating current. http://onsemi.com 10 MC33351A Figure 13. Cell Voltage Limit Sampling vs. Programming From Cell Selector capacity. Figure 13 illustrates the operation of an unbalanced three cell pack. As the cells become unbalanced, the full battery pack capacity is not realized. This is due to the requirement that charging must terminate when the highest voltage cell reaches the overvoltage limit, and discharging must terminate when the lowest voltage cell reaches the undervoltage limit. By employing a method of keeping the cell voltages equal, each of the cells can be charged and discharged to their specified limits, thus attaining the maximum possible capacity. Cell Voltage Floating Over/Under Cell Voltage Detector & Reference To Cell Selector Discharge Voltage Threshold R1 Charge Voltage Threshold R2 Cell Voltage Return R3 + Cell Voltage - Figure 14. Unbalanced Battery Pack Operation The cell charge and discharge voltage limits are controlled by the values selected for the internal resistor divider string. As the battery pack reaches full charge, the Cell Voltage Detector will sense an overvoltage fault condition on the first cell that exceeds the pre-set overvoltage limit. The fault information is stored in a data latch and charge MOSFET Q1 is turned off, disconnecting the battery pack from the charging source. An internal current source pull-up is then applied to the lower tap of the divider when the overvoltage cell is again sensed. This creates an input hysteresis voltage with divider resistors R1 and R2. As a result of an overvoltage fault, the battery pack is available for discharging only. The overvoltage fault is reset by applying a load to the battery pack. As the voltage across the highest voltage cell falls below the hysteresis level, charge MOSFET Q1 will turn on and the current source pull-up will turn off. The battery pack will now be available for charging or discharging. As the load eventually depletes the battery pack charge, the Cell Voltage Detector will sense an undervoltage fault condition on the first cell that falls below the designed undervoltage limit. After an undervoltage cell is detected, undervoltage fault output goes low and discharge MOSFET Q2 is turned off, disconnecting the battery pack from the load after 16 seconds. The protection circuit will now enter a low current sleepmode state drawing less than 15.0 nA typically, thus preventing any further cell discharging. As a result of the undervoltage fault, the battery pack is available for charging only. An alternate method of turning discharge MOSFET Q2 can be employed using RT and CT as shown in Figures 1 and 2. Recommended value of RT and CT of 5.1 kW and 22 mfd respectively generates a time delay of 110 10% milliseconds. The undervoltage fault is reset by applying charge current to the battery pack. When the voltage on Pin 8 exceeds Pin 16 by 0.6 V, discharge MOSFET Q2 will be turned on. The battery pack will now be available for charging or discharging. Cell 3 Cell 3 4.2 V Overvoltage Limit Charge 2.7 V Cell 2 Cell 2 4.0 V Cell 1 Charged 2.5 V Disharge Undervoltage Limit Cell 1 Discharged The MC33351A contains a Cell Voltage Balancing Logic circuit that controls three internal MOSFETs. These MOSFETs are connected to an external transistor and resistor combination across the individual cells. The circuit samples the voltage of each cell during the polling period. If all of the cells are below the programmed overvoltage fault limit, no cell balancing takes place. If one or more cells reach the overvoltage fault limit, a specific latch is set for each cell. At the end of the polling period, charge MOSFET Q1 is turned off and the latches are interrogated. If all of the latches were set, no cell balancing takes place. If one, two, or three latches were set, the required cell balancing MOSFETs are then activated. The overvoltage cells are discharged to the pre-set level. As each cell attains this level, the balancing MOSFETs successively turn off. Upon completion of cell balancing, charge MOSFET Q1 is turned on. Cell voltage balancing can be active during charging and discharging, but is disabled during the low current sleepmode state. Test Mode A test option is provided to speed up device and battery pack testing. By connecting Pin 2 to 3.0 V above VC the internal logic is held in a reset state and both MOSFET switches are turned on. Upon release, the Control Logic becomes active and the cell are polled within 4.0 ms. Cell Voltage Balancing With series connected cells, successive charge and discharge cycles can result in a significant difference in cell voltage with a corresponding degradation of battery pack http://onsemi.com 11 MC33351A circuit will turn on discharge MOSFET Q2. Discharge current sensing can be disabled by connecting Pin 16 to Pin 8. The discharge current protection circuit contains a built in response delay of 3.0 ms. This helps to prevent fault activation when the battery pack is subjected to pulsed currents during charging or discharging. Discharge Current Sensing Discharge current limit protection can be selectively added to the battery pack with the addition of a sense resistor Rlim(dschg) on the Low-Side or by monitoring the voltage drop across the series FETs on the High-Side. Sense resistor - low-side The sense resistor Rlim(dschg) is placed in series with the negative terminal of Cell 1 and the negative terminal of the battery pack, Refer to Figure 1. As the battery pack discharges, Pins 5 and 13 sense the voltage drop across RLim(dschg). A discharge current limit fault is detected if the voltage at Pin 5 is greater than Pin 13 by 50 mV for more than 3.0 ms. The fault information is stored in a data latch and discharge MOSFET Q2 is turned off, disconnecting the battery pack from the load. As a result of the discharge current fault, the battery pack is available for charging only. The discharge current limit is given by: V I + R th(dschg) + R Lim(dschg) Lim(dschg) Battery Pack Application Each of the application figures show a capacitor labeled CI that connects directly across the battery pack terminals, and two resistors labeled Rg that are placed in series with the charge and discharge gate drive outputs. These components prevent excessive currents from flowing into the MC33351A when the battery pack terminals are shorted or arced and are mandatory. Capacitor CI is a 1.0 F 20% ceramic leaded or surface mount type. It must be placed directly across the battery pack plus and minus terminals with extremely short lead lengths (1/16") and as close to the IC as possible. The gate drive output resistors for both Q1 and Q2 are 10 k 5.o% carbon film type. In applications where inordinately low leakage MOSFETs are used, the protection circuit may take several seconds to reset from an overcurrent fault after the load is removed. If desired, this situation can be remedied by providing a small leakage path for charging CI, thus allowing Pin 8 to rapidly rise, so that it no longer exceeds Pin 16 by approximately 2.0 V. A 4.7 M resistor placed across the MOSFET switches accomplishes this task with a minimum increase in cell discharge current when the battery pack is connected to the load. 50 mV Lim(dschg) Voltage across FETs - high-side A 1M or 2M resistor connected from pin# 11 to ground is used to program the high-side discharge current limit threshold. The discharge current fault is reset by either disconnecting the load from the battery pack, or by connecting the battery pack to the charger. When the voltage on Pin 16 no longer exceeds Pin 8 by approximately 2.0 V, the Sense Enable Upon assembly of the battery pack, it is imperative that Cell 1 be connected first so that VC is properly biased. The remaining cells can then be connected in any order. This assembly method prevents forward biasing the protection IC substrate which can result in overheating and non-functionality. http://onsemi.com 12 MC33351A MC33351A - Cell Voltage versus Undervoltage Fault 4.25 V ANY CELL VOLTAGE No FAULT FAULT remains active 2.30 V High (Inactive) 1 sec + (0 - 1 sec) FAULT (pin 10) Low (Active) 16 sec (not resetable) ON DISCHARGE FET OFF Connected CHARGER Disconnected http://onsemi.com 13 MC33351A PACKAGE DIMENSIONS TSSOP-20 DTB SUFFIX PLASTIC PACKAGE CASE 948E-02 ISSUE A 20X 0.15 (0.006) T U K REF 0.10 (0.004) S M T U S V S K K1 2X L/2 20 11 J J1 B -U- L PIN 1 IDENT III III III SECTION N-N 1 10 0.25 (0.010) N 0.15 (0.006) T U S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. M A -V- N F DETAIL E -W- C D G H DETAIL E 0.100 (0.004) -T- SEATING PLANE http://onsemi.com 14 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC33351A Notes http://onsemi.com 15 MC33351A ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303-675-2167 or 800-344-3810 Toll Free USA/Canada N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (M-F 1:00pm to 5:00pm Munich Time) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (M-F 1:00pm to 5:00pm Toulouse Time) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (M-F 12:00pm to 5:00pm UK Time) Email: ONlit@hibbertco.com EUROPEAN TOLL-FREE ACCESS*: 00-800-4422-3781 *Available from Germany, France, Italy, England, Ireland CENTRAL/SOUTH AMERICA: Spanish Phone: 303-308-7143 (Mon-Fri 8:00am to 5:00pm MST) Email: ONlit-spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001-800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 16 MC33351A/D