MC33351A - ON Semiconductor - Datasheet.Directory

 Semiconductor Components Industries, LLC, 2000

June, 2000 – Rev. 3 1Publication Order Number:

MC33351A/D

MC33351A

Advanced Information

Lithium Battery Protection

Circuit for Three Battery

Packs

The MC33351A is a monolithic lithium battery protection circuit that is

designed to enhance the useful operating life of three cell rechargeable

battery packs. The MC33351A is specifically designed to be placed in a

lithium battery pack where the battery cells continuously power it. In order

to maintain cell operation within specified limits, the protection circuit

senses cell voltages, and discharge current, and correspondingly controls

the state of two P–channel MOSFET switches. These switches are

connected in series with the positive terminal of the third cell and the

positive terminal of the battery pack. During a fault condition, the

MC33351A open circuits the pack by turning off one of these MOSFET

switches.

Features

•Selectable Char ge Interrupt Voltage Sensing Mode for Precise Cell

Voltage Measurements

•Programmable Overvoltage Delay

•Choice of Discharge Current Limit Sensing Elements consisting of

either Low–Side Resistor or High–Side MOSFET Switches

•Programmable Dischar ge Current Limit Threshold and Shutdown Delay

•Selectable Cell Voltage Balancing

•Virtually Zero Current Sleepmode State when Cells are Discharged

•Minimum External Components for Inclusion within the Battery Pack

•Available in Low Profile Surface Mount Package

5

Low–Side

Current

Limit Input

4

Discharge

Current Limit

Shutdown Delay

Typical Three Cell Smart Battery Pack

Charge and

Discharge Gate

Drive Common

8

VCC/

High–Side

Discharge

Current Limit

16

MC33351A

2

Discharge

Inhibit

Input

Cell 3

Cell 2

Cell 1/VC 15

Ground 13

Overvoltage

Shutdown

Delay

3

20

10

Undervoltage

Fault Output

1

Charge

Inhibit

Input

Discharge Gate

Drive Output

7

Charge Gate

Drive Output

9

6

11

High–Side

Discharge Current

LimitThreshold

Charge

Interrupt

Mode Select

17

18

Balance 3

19

12

Balance 2

14

Balance 1

http://onsemi.com

PIN CONNECTIONS

20

1

120

17

16

15

14

13

3

4

5

6

7

8

(Top View)

Charge Inhibit Input

Overvoltage

Shutdown Delay

Charge Interrupt

Mode Select

Discharge

Gate Drive Output

Charge and Discharge

Gate Drive Common

Balance 1

Ground

Cell 1/VC

Balance 2

19

18

2

12

11

9

10

Balance 3

VCC/High Side

Discharge Current

Limit

Cell 2

High–Side

Discharge Current

Limit Threshold

Discharge Inhibit/

Test Input

Discharge Current Limit

Shutdown Delay

Low–Side Discharge

Current Limit Input

Charge

Gate Drive Output

Undervoltage

Fault Output

NC

Cell 3

TSSOP–20

DTB SUFFIX

CASE 948E

Device Package Shipping

ORDERING INFORMATION

MC33351ADTB–1 TSSOP–20 75 Units/Rail

MC33351ADTB–1R2 TSSOP–20 2500 Tape/Reel

MARKING

DIAGRAMS

MC35

1A1

ALYW

A = Assembly Location

WL, L = W afer Lot

YY, Y = Year

WW,W = Work Week

MC33351A

http://onsemi.com

2

Floating

Over/Under

Cell Voltage

Detector

&

Reference

Oscillator

Balance 3

Balance 2

Balance 1

Cell 3

Cell 2

Cell 1/VC

Ground

Over/Under

Data Latch

&

Control Logic

Cell

Selector

Cell Voltage

Balancing

Logic

R1

R2

R3

Discharge Current

Limit Detector Charge/Discharge

Gate Drivers Sense

Enable

5

Low–Side

Discharge Current

Limit Input

Discharge

Current Limit

Shutdown Delay

1

Charge

Inhibit Input

2

Discharge Inhibit Input

Rlim(LS)

Cdly

4

11

High–Side

Discharge Current

Limit Threshold

6

Charge Interrupt

Mode Select

Overvoltage

Shutdown

Delay

3

VCC

Cell 1

Control Logic Inputs from

Microcontroller Output Ports

10 k 10 k

VC

Undervoltage

Fault Output

10

Cell 2

Cell 3

13

20

15

14

12

19

18

17

16

VCC/

High–Side

Discharge

Current Limit

MC33351A

En

Ck

Charge and

Discharge Gate

Drive Common

8

Charge

Gate Drive

Output

9

Discharge

Gate Drive

Output

7

Discharge Switch Q2 Charge Switch Q1

10 k

4.7 M

Smart Battery Pack with Low–Side Discharge Current Sensing, Charge Interrupt Voltage Sensing, and Cell Voltage Balancing

CI

Contro

l

Logic

Out

p

utTo

M

icrocontro

ll

er

I

n

p

ut

P

ort

Figure 1.

RG RG

5.1 k RT

CT

+

22

m

fd

MC33351A

http://onsemi.com

3

Floating

Over/Under

Cell Voltage

Detector

&

Reference

Oscillator

Balance 3

Balance 2

Balance 1

Cell 3

Cell 2

Cell 1/VC

Ground

Over/Under

Data Latch

&

Control Logic

Cell

Selector

Cell Voltage

Balancing

Logic

R1

R2

R3

Discharge Current

Limit Detector Charge/Discharge

Gate Drivers Sense

Enable

5

Low–Side

Discharge Current

Limit Input

Discharge

Current Limit

Shutdown Delay

1

Charge

Inhibit Input

2

Discharge Inhibit Input

Cdly

4

11

High–Side

Discharge Current

Limit Threshold

6

Charge Interrupt

Mode Select

Overvoltage

Shutdown

Delay

3

VCC

Cell 1

Control Logic Inputs from

Microcontroller Output Ports

10 k 10 k

VC

Undervoltage

Fault Output

10

Cell 2

Cell 3

13

20

15

14

12

19

18

17

16

VCC/

High–Side

Discharge

Current Limit

MC33351A

En

Ck

Charge and

Discharge Gate

Drive Common

8

Charge

Gate Drive

Output

9

Discharge

Gate Drive

Output

7

Discharge Switch Q2 Charge Switch Q1

10 k

4.7 M

Smart Battery Pack with High–Side Discharge Current Sensing

CI

Contro

l

Logic

Out

p

utTo

M

icrocontro

ll

er

I

n

p

ut

P

ort

Rth(HS)

RG RG

Figure 2.

5.1 k RT

CT

+

22

m

fd

MC33351A

http://onsemi.com

4

MAXIMUM RATINGS

Ratings Symbol Value Unit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Voltage (Measured with respect to Ground, Pin 13)

ÁÁÁÁ

VIR

ÁÁÁÁÁÁ

ÁÁÁ

V

Cell 1/Vc (Pin 15) 7.5

Cell 2 (Pin 12) 10

Cell 3 (Pin 18) 18

Vcc/ High Side Discharge Current Limit (Pin 16) 20

Charge Inhibit Input (Pin 1) 7.5

Discharge Inhibit Input (Pin 2) 7.5

Overvoltage Shutdown Delay (Pin 3) 7.5

Discharge Current Limit Shutdown Delay (Pin 4) 20

Low–Side Discharge Current Limit Input (Pin 5) 7.5

Voltage Sampling Mode Select (Pin 6) 7.5

Discharge Gate Drive Output (Pin 7) 18

Charge Gate Drive Common (Pin 8) 20

Charge Gate Drive Output (Pin 9) 18

Undervoltage Fault Output (Pin 10) 20

High–Side Current Limit Threshold (Pin 11) 7.5

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Cell Balancing Current (Note 1)

ÁÁÁÁ

Ibal

ÁÁÁÁÁÁ

ÁÁÁ

mA

Balance 3, Source Current (Pin 19) 50

Balance 1, Balance 2 Sink Current (Pin 20, 14) 50

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Undervoltage Fault Output Sink Current (Pin 10)

ÁÁÁÁ

Iflt

ÁÁÁÁÁÁ

10

ÁÁÁ

mA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Thermal Resistance, Junction–to–Air

ÁÁÁÁ

RθJA

ÁÁÁÁÁÁ

ÁÁÁ

°C/W

DTB Suffix, TSSOP Plastic Package, Case 948E 135

DW Suffix, SO–20L Plastic Package, Case 751D 105

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Operating Temperature (Note 1)

ÁÁÁÁ

TJ

ÁÁÁÁÁÁ

–40 to 150

ÁÁÁ

°C

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Storage Temperature

ÁÁÁÁ

Tstg

ÁÁÁÁÁÁ

–55 to 150

ÁÁÁ

°C

ELECTRICAL CHARACTERISTICS (Vcell 3 (Pin 18) = 10.5V, Vcell 2 (Pin 12) = 7.0V, Vcell 1 (Pin 15) = 3.5V,

Cdly (Pin 4) = 1000 pF, TA = 25°C)

Characteristic Symbol Min Typ Max Unit

VOLTAGE SENSING

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Cell Charging Cutoff (Pin 15 to 13, 12 to 15, 18 to 12)

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

Overvoltage Threshold, VCell Increasing MC33351A–1 Vth(OV) 4.207 4.293 V

Overvoltage Hysteresis, VCell Decreasing VH50 125 200 mV

Delay tdly(OV)

One Overvoltage Sample (Pin 3 = Gnd) 0 – 1.2 s

Two Consecutive Overvoltage Samples (Pin 3 = Vc) 1.0 – 2.3 s

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Cell Discharging Cutoff MC33351A–1

ÁÁÁÁÁ

Vth(UV)

ÁÁÁÁ

2.185

ÁÁÁÁÁ

2.3

ÁÁÁÁ

2.415

ÁÁÁ

V

Undervoltage Threshold, VCell Decreasing

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Bias Current During Cell Voltage Sampling

ÁÁÁÁÁ

IIB

ÁÁÁÁ

–

ÁÁÁÁÁ

28

ÁÁÁÁ

–

ÁÁÁ

µA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Cell V oltage Sampling Rate

ÁÁÁÁÁ

t(smpl)

ÁÁÁÁ

–

ÁÁÁÁÁ

1.0

ÁÁÁÁ

–

ÁÁÁ

s

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Charge Interrupt

ÁÁÁÁÁ

Vth(Intrrpt)

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

V

Input Voltage Range (Pin 6)

Enabled – (Vc/2+0.2 to Vc) –

Disabled – (0 to Vc/2–0.2) –

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Enabled Charge Interrupt T ime

ÁÁÁÁÁ

tIntrrp

ÁÁÁÁ

–

ÁÁÁÁÁ

20

ÁÁÁÁ

–

ÁÁÁ

ms

NOTE: 1 Maximum package power dissipation limits must be observed.

MC33351A

http://onsemi.com

5

ELECTRICAL CHARACTERISTICS (Vcell 3 (Pin 18) = 10.5V, Vcell 2 (Pin 12) = 7.0V, Vcell 1 (Pin 15) = 3.5V,

Cdly (Pin 4) = 1000 pF, TA = 25°C)

Characteristic UnitMaxTypMinSymbol

CELL VOLTAGE BALANCING

Internal Balancing MOSFET On–Resistance RDS(on)

W

Balance 3, (Pin 19) – 100 –

Balance 1, Balance 2 (Pin 20, 14) – 50 –

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CURRENT SENSING

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

High–Side Discharge Current Limit (Pin 16 to Pin 8)

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

Threshold Voltage Vth(HSdschg)

Rpin 11 = 1.0 M

W

200 280 380 mV

Rpin 11 = 2.0 M

W

100 170 230 mV

Delay

Overcurrent Detect (Vsense = 250 mV) tdly(HSdschg) 2.5 6.0 ms

Short Circuit Detect (Vsense = 1.0 V) 0.0 2.5 ms

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Low–Side Discharge Current Limit (Pin 13 to Pin 5)

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

Threshold Voltage Vth(LSdschg) 48 – 59 mV

Delay

Overcurrent Detect (Vsense = 50 mV) tdly(LSdschg) 2.5 6.0 ms

Short Circuit Detect (Vsense = 200 mV) 0.3 0.4 ms

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

LOGIC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Charge and Discharge Inhibit Inputs (Pin 1, 2)

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

Threshold Voltage Vth(inhbt) – Vc/2 – V

Propagation Delay to Respective Gate Drive Output tPL/H – 100 – µs

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Undervoltage Fault Output (Pin 10)

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

Low State Sink Resistance – 100 –

W

Off State Leakage Current (Vdrain = 16V) – 100 – nA

Detection Delay T ime Before Discharge MOSFET Turn Off

(Note 2) – 16 – s

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Charge and Discharge Gate Drive Outputs (Pin 9, 7)

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

W

High State Source Resistance RDS(source) – 100 –

Low State Sink Resistance RDS(sink) – 100 –

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TOTAL DEVICE

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Average Cell Current

ÁÁÁÁÁ

ICC

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

Operating (VCC = 12 V) – 15 20 µA

Sleepmode (VCC = 6.0 V) – – 500 nA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Minimum Operating Cell Voltage

ÁÁÁÁÁ

VCC

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁ

V

Cell 1 Voltage 1.5 1.8 –

Cell 2, or Cell 3 Voltage 0.7 0.8 –

NOTE: 2 Refer to “V oltage Sensing” text of Operating Description. Guaranteed by Design Only; NOT TESTED.

MC33351A

http://onsemi.com

6

Figure 3. Over Voltage Threshold versus

Temperature Figure 4. Charge ON Voltage Threshold versus

Temperature

Figure 5. Undervoltage Threshold versus

Temperature Figure 6. Discharge Current (Low Side) versus

Temperature

–40

4

.

45

TEMPERATURE (°C)

4.40

4.30

4.25

4.20

4.15 –25 –10 5 20 35 50 80

OVER VOLTAGE THRESHOLD (VOLTS)

4.35

–40

2.305

TEMPERATURE (°C)

2.295

2.285

2.280

2.275

2.270

2.265 –200 20406080

UNDERVOLTA

G

E

THRESHOLD

(VOLTS)

2.290

–40

60

TEMPERATURE (°C)

52

48

46

44

42

40 –20 0 20406080

DISCHARGE CURRENT (LOW SIDE)

50

65 –40

4

.3

5

TEMPERATURE (°C)

4.30

4.20

4.15

4.10

4.05 –20 0 20 40 80

CHARGE ON THRESHOLD (VOLTS)

4.25

60

2.300

THRESHOLD IN MILLIVOLTS

58

54

56

Figure 7. Discharge Current (High Side) Threshold

versus Temperature (R11 = 1.5 mOhms) Figure 8. Discharge Current (High Side)

versus Resistance

–40

210

TEMPERATURE (°C)

205

195

190

185

180 –200 20406080

D

I

SCHAR

G

E

CURRENT

(H

IG

H

S

I

DE)

200

0.7

350

RESISTANCE (m

W

)

270

230

210

190

170

150 0.9 1.1 1.3 1.5 2.1

DISCHARGE CURRENT THRESHOLD (mV)

250

1.7 1.9

330

290

310

THRESHOLD (MILLIVOL TS)

MC33351A

http://onsemi.com

7

Figure 9. VCC versus IEE (No Load) Figure 10. VCC versus IEE (Sleep–Mode)

9.5

4.0

VCC (V) (3 X Vcell)

3.8

3.6

3.4

3.2

3.0 10 10.5 11 11.5 12

IEE

(

A)

7.0

VCC (V) = (3 X Vcell)

4.6

4.2

3.8

3.4

3.0 7.5 8.0 8.5 9.0

IEE (nA)

5

.

0

4

.

2

µ

Figure 11. Discharge Current Limit Shutdown Delay

versus Capacitance

0

Capacitance (pF)

200

150

100

50

05000 10000 15000 20000

TIME DELAY (I senseV

250

th to Dgate) (ms)

MC33351A

http://onsemi.com

8

PIN FUNCTION DESCRIPTION

No. Function Description

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

1

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Charge Inhibit Input

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

A logic low level at this input will disable battery pack charging. A 10 k internal pull–up resistor

connects from this pin to VC.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

2

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Discharge Inhibit Input

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

A logic low level at this input will disable battery pack discharging. A 10 k internal pull–up resistor

connects from this pin to VC. Also, connecting this pin to 3.0V above VC the internal logic is held in

reset state and both MOSFET switches are turned on.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

3

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Overvoltage Shutdown

Delay

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This input controls the required number of cell overvoltage events that must be detected before

charge switch Q1 is turned off. With a logic level low at this input, charge switch Q1 turns off after a

single overvoltage event is detected. With a logic level high, charge switch Q1 turns off after two

successive overvoltage events are detected.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

4

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Discharge Current

Limit Shutdown Delay

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

A capacitor connects from this pin to ground and is used to program a time delay from when the

discharge current limit is exceeded to when discharge switch Q2 is turned off.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

5

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Low–Side Discharge

Current Limit Input

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This pin is used to monitor the load induced voltage drop that appears across current sensing resistor

Rlim(LS). This voltage drop is sensed by pins 13 and 5.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

6

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Charge Interrupt Mode

Select

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

The logic level that is applied to this input determines if the charge current will be interrupted during

the cell voltage sampling period. The charge current is interrupted when this input is connected to VC,

and not interrupted when connected to ground, pin 13.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

7

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Discharge Gate Drive

Output

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This output connects to the gate of discharge switch Q2 allowing it to enable or disable battery pack

discharging.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

8

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Charge and Discharge

Gate Drive Common

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This pin provides a gate turn–off path for charge switch Q1. The charge switch source and the battery

pack positive terminal connect to this point.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

9

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Charge Gate Drive

Output

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This output connects to the gate of charge switch Q1 allowing it to enable or disable battery pack

charging.

ÁÁÁÁ

10

ÁÁÁÁÁÁ

Undervoltage Fault

Output

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This is an open drain output that is active low when an undervoltage fault limit has been exceeded.

Discharge switch Q2 will turn off 16 seconds after the Fault goes low.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

11

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

High–Side Discharge

Current Limit

Threshold

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

A resistor connects from this pin to ground and is used to program the high–side discharge current

limit threshold. The programmed threshold voltage is sensed by pins 16 and 8.

ÁÁÁÁ

12

ÁÁÁÁÁÁ

Cell 2

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This pin connects to a high impedance node of the Cell Selector where it is used to monitor the

positive terminal of Cell 2 and the negative terminal of Cell 3.

ÁÁÁÁ

13

ÁÁÁÁÁÁ

Ground

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This is the protection IC ground and all voltage ratings are with respect to this pin.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

14

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Balance 2

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This pin is used if cell balancing is desired. It connects to the drain of an internal N–channel MOSFET

and is active low during the balancing of Cell 2.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

15

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Cell 1/VC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This is a multi–function pin that connects to a high impedance node of the Cell Selector where it is

used to monitor the positive terminal of Cell 1 and the negative terminal of Cell 2. This pin also

provides bias for the internal logic.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

16

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

VCC/High–Side

Discharge Current

Limit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This is a multi–function pin that connects to a high impedance node of the Cell Selector where it is

used to monitor the positive terminal of Cell 3 and to provide positive supply voltage for the protection

IC. This pin can also be used for high–side discharge current limit protection by monitoring the load

induced voltage drop that appears across the on–resistance of switches Q2 and diode of Q1. This

voltage drop is sensed by pins 16 and 8.

ÁÁÁÁ

17

ÁÁÁÁÁÁ

NC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

No Connection

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

18

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Cell 3

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This pin connects to a high impedance node of the Cell Selector where it is used to monitor the

positive terminal of Cell 3 and VCC.

ÁÁÁÁ

19

ÁÁÁÁÁÁ

Balance 3

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This pin is used if cell balancing is desired. It connects to the drain of an internal P–channel MOSFET

and is active high during the balancing of Cell 3.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

20

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Balance 1

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This pin is used if cell balancing is desired. It connects to the drain of an internal N–channel MOSFET

and is active low during the balancing of Cell 1.

MC33351A

http://onsemi.com

9

PROTECTION CIRCUIT OPERATING MODE TABLE

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

Outputs

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

MOSFET Switches

(Note 3)

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

Cell

Balancing

ÁÁÁÁÁÁÁÁÁÁ

Input Conditions

Cell Status

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Circuit Operation

Battery Pack Status Charge

Q1

ÁÁÁÁÁ

Discharge

Q2

ÁÁÁÁ

Balancing

Outputs

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CELL CHARGING/DISCHARGING

ÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Storage or Nominal Operation:

No current or voltage faults

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Both Charge MOSFET Q1 and Discharge MOSFET

Q2 are on. The battery pack is available for charging

or discharging.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

On

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

On

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

Active

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CELL CHARGING FAULT/RESET

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Charge V oltage Limit Fault:

VCell ≥ Vth(OV) for tdly(OV)

tdly(OV) =

0 to 1.2 s, Pin 3 to 13

1.0 to 2.1 s, Pin 3 to 15

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Charge MOSFET Q1 is latched off and the cells are

disconnected from the charging source. An internal

hysteresis voltage is generated when the overvoltage

cell is sensed. The shutdown delay is programmable

for either one or two successive overvoltage events

by the state of Pin 3. The battery pack is available for

discharging.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

On to Off

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

On

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

Active

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Charge V oltage Limit Reset:

VCell < (Vth(OV) – VH) for 1.2 s

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Charge MOSFET Q1 will turn on when the voltage

across the overvoltage cell falls sufficiently to overcome

the internal hysteresis voltage. This can be

accomplished by applying a load to the battery pack.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

Off to On

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

On

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

Active

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CELL DISCHARGING FAULT/RESET

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Discharge Current Limit Fault:

VPin 16 ≥ (VPin 8 + Vth(HS dschg)

for tdly(HS dschg) or

VPin 5 ≥ (VPin 13 + Vth(LS dschg)

for tdly(LS dschg)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Discharge MOSFET Q2 is latched off and the cells

are disconnected from the load. Q2 will remain in

the off state as long as VPin 16 exceeds VPin 8 by

≈VTH(HSdschrg). A discharge current limit fault can be

activated by either high–side or a low–side current

sensing methods. The battery pack is available for

charging.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

On

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

On to Off

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

Active

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Discharge Current Limit Reset:

VPin 16 – VPin 8 < VTH(HSdschrg)

VPin 5 – VPin 13 < VTH(LSdschrg)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

The Sense Enable circuit will reset and turn on

discharge MOSFET Q2 when VPin 16 no longer

exceeds VPin 8 by 2.0 V. This can be accomplished

by either disconnecting the load from the battery

pack, or by connecting the battery pack to the

charger.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

On

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

Off to On

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

Active

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Discharge V oltage Limit Fault:

VCell ≤ Vth(UV) for 2.1 s

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Undervoltage Fault Output (Pin 10) is driven low

after two successive undervoltage events are

detected. After a 16 second delay, discharge

MOSFET Q2 is latched off, the cells are

disconnected from the load, and the protection

circuit enters a low current sleepmode state. The

battery pack is available for charging.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

On

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

On to Off

after 16 s

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

Disabled

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Discharge V oltage Limit Reset:

VPin 8 > (VPin 16 + 0.6 V)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

The Sense Enable circuit will reset and turn on

discharge MOSFET Q2 when VPin 8 exceeds VPin 16

by 0.6 V. This can be accomplished by connecting

the battery pack to the charger.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

On

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

Off to On

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

Active

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

FAULTY CELL

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Simultaneous Charge and

Discharge V oltage Limit Faults

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This condition can happen if there is a defective cell

in the battery pack. The protection circuit will remain

in the sleepmode state until the battery pack is

connected to a charger. If Cell 2, or 3 is faulty and a

charger is connected, the protection circuit will cycle

in and out of sleepmode. If Cell 1 is faulty (<1.5 V)

the protection circuit logic will not function and the

battery pack cannot be charged.

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

Cycles

Cell 1 Good

Disabled

Cell 1 Faulty

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

Cycles

Cell 1 Good

Disabled

Cell 1 Faulty

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

Cycles

Cell 1 Good

Disabled

Cell 1 Faulty

NOTE: 3 Charge switch Q1 and discharge switch Q2 can be selectively turned of f via the appropriate inhibit input except during the sleepmode state.

MC33351A

http://onsemi.com

10

OPERATING DESCRIPTION

INTRODUCTION

The demand for smaller lightweight portable electronic

equipment has dramatically increased the requirements of

battery performance. Today’s most attractive chemistries

include lithium–polymer, lithium–ion, and lithium–metal.

Each of these chemistries require electronic protection in

order to constrain cell operation to within the manufacturers

limits.

Rechargeable lithium–based cells require precise charge

and discharge termination limits for both voltage and current

in order to maximize cell capacity, cycle life, and to protect

the end user from a catastrophic event.

The MC33351A features internally–fixed cell voltage

limits, programmable cell voltage balancing, low operating

current, a virtually zero current sleepmode state, and

requires few external components.

OPERATING DESCRIPTION

The MC33351A is specifically designed to be placed in

the battery pack where it can be continuously powered from

three lithium cells. In order to maintain cell operation within

specified limits, the protection circuit senses both cell

voltage and discharge current, and correspondingly controls

the state of two P–channel MOSFET switches. These

switches, Q1 and Q2, are placed within the series path of the

positive terminal of cell 3 and the positive terminal of the

battery pack. For lowside current limit sense, a resistor is

placed within the series path of the negative terminal of Cell

1 and the negative terminal of the battery pack. This

configuration allows the protection circuit to interrupt the

appropriate charge or discharge path FET in the event that

a programmed voltage or current limit for any cell has been

exceeded.

A functional description of the protection circuit blocks

follows. Refer to the detailed block diagram shown in

Figure 1.

Voltage Sensing

Individual cell voltage sensing is accomplished by the use

of the Cell Selector in conjunction with the Floating

Over/Under Voltage Detector and Reference block. The Cell

Selector applies the voltage of each cell across an internal

resistor divider string. The voltage at each of the tap points

is sequentially polled and compared to an internal reference.

If a limit has been exceeded, the result is stored in the

Over/Under Data Latch and Control Logic block. The Cell

Selector is gated on for a 4.0 ms period at a fixed one second

repetition rate. This low duty cycle sampling technique

reduces the average load current that the divider presents

across each cell, thus extending the useful battery pack

capacity.

Figure 12. Simplified Smart Battery Pack

4512

9

16

17

10

MC33351A

Cell 3 18

19

12

14

Cell 2

Cell 1 15

20

13

3

6

1

7 8

Cell Sensing Sequence

ÁÁÁÁÁ

Polling

Sequence

ÁÁÁÁ

Time

(ms)

ÁÁÁÁÁ

Cell

Sensed

ÁÁÁÁÁ

Tested

Limit

ÁÁÁÁÁ

1

ÁÁÁÁ

0.25

ÁÁÁÁÁ

Cell 1

ÁÁÁÁÁ

Overvoltage

ÁÁÁÁÁ

2

ÁÁÁÁ

0.25

ÁÁÁÁÁ

Cell 2

ÁÁÁÁÁ

Overvoltage

ÁÁÁÁÁ

3

ÁÁÁÁ

0.25

ÁÁÁÁÁ

Cell 3

ÁÁÁÁÁ

Overvoltage

ÁÁÁÁÁ

4

ÁÁÁÁ

0.25

ÁÁÁÁÁ

Cell 1

ÁÁÁÁÁ

Undervoltage

ÁÁÁÁÁ

5

ÁÁÁÁ

0.25

ÁÁÁÁÁ

Cell 2

ÁÁÁÁÁ

Undervoltage

ÁÁÁÁÁ

6

ÁÁÁÁ

0.25

ÁÁÁÁÁ

Cell 3

ÁÁÁÁÁ

Undervoltage

By incorporating this polling technique with a single

floating comparator and voltage divider, a significant

reduction of circuitry and trim elements is achieved. This

results in a smaller die size, lower cost, and reduced

operating current.

MC33351A

http://onsemi.com

11

Figure 13. Cell Voltage Limit

Sampling

vs. Programming

From

Cell

Selector

Floating

Over/Under

Cell Voltage

Detector

&

Reference

Discharge V oltage

Threshold

Charge V oltage

Threshold

Cell Voltage

Return

Cell Voltage

+

Cell

Voltage

–

R1

R2

R3

To

Cell

Selector

The cell charge and discharge voltage limits are controlled

by the values selected for the internal resistor divider string.

As the battery pack reaches full charge, the Cell Voltage

Detector will sense an overvoltage fault condition on the

first cell that exceeds the pre–set overvoltage limit. The fault

information is stored in a data latch and charge MOSFET Q1

is turned off, disconnecting the battery pack from the

charging source. An internal current source pull–up is then

applied to the lower tap of the divider when the overvoltage

cell is again sensed. This creates an input hysteresis voltage

with divider resistors R1 and R2. As a result of an

overvoltage fault, the battery pack is available for

discharging only.

The overvoltage fault is reset by applying a load to the

battery pack. As the voltage across the highest voltage cell

falls below the hysteresis level, charge MOSFET Q1 will

turn on and the current source pull–up will turn off. The

battery pack will now be available for charging or

discharging.

As the load eventually depletes the battery pack charge,

the Cell Voltage Detector will sense an undervoltage fault

condition on the first cell that falls below the designed

undervoltage limit. After an undervoltage cell is detected,

undervoltage fault output goes low and discharge MOSFET

Q2 is turned off, disconnecting the battery pack from the

load after 16 seconds. The protection circuit will now enter

a low current sleepmode state drawing less than 15.0 nA

typically, thus preventing any further cell discharging. As a

result of the undervoltage fault, the battery pack is available

for charging only. An alternate method of turning discharge

MOSFET Q2 can be employed using RT and CT as shown

in Figures 1 and 2. Recommended value of RT and CT of

5.1 k

W

and 22

m

fd respectively generates a time delay of 110

±10% milliseconds.

The undervoltage fault is reset by applying charge current

to the battery pack. When the voltage on Pin 8 exceeds

Pin 16 by 0.6 V, discharge MOSFET Q2 will be turned on.

The battery pack will now be available for charging or

discharging.

Cell Voltage Balancing

With series connected cells, successive charge and

discharge cycles can result in a significant dif ference in cell

voltage with a corresponding degradation of battery pack

capacity. Figure 13 illustrates the operation of an

unbalanced three cell pack. As the cells become unbalanced,

the full battery pack capacity is not realized. This is due to

the requirement that charging must terminate when the

highest voltage cell reaches the overvoltage limit, and

discharging must terminate when the lowest voltage cell

reaches the undervoltage limit. By employing a method of

keeping the cell voltages equal, each of the cells can be

charged and discharged to their specified limits, thus

attaining the maximum possible capacity.

Figure 14. Unbalanced Battery Pack Operation

Disharge

4.0 V

4.2 V

Overvoltage

Limit

Charged

2.5 V

Undervoltage

Limit

2.7 V

Charge

Cell 3

Cell 1

Cell 2

Discharged

Cell 3

Cell 1

Cell 2

The MC33351A contains a Cell Voltage Balancing Logic

circuit that controls three internal MOSFETs. These

MOSFETs are connected to an external transistor and

resistor combination across the individual cells. The circuit

samples the voltage of each cell during the polling period. If

all of the cells are below the programmed overvoltage fault

limit, no cell balancing takes place. If one or more cells reach

the overvoltage fault limit, a specific latch is set for each cell.

At the end of the polling period, charge MOSFET Q1 is

turned off and the latches are interrogated. If all of the

latches were set, no cell balancing takes place. If one, two,

or three latches were set, the required cell balancing

MOSFETs are then activated. The overvoltage cells are

discharged to the pre–set level. As each cell attains this level,

the balancing MOSFETs successively turn off. Upon

completion of cell balancing, charge MOSFET Q1 is turned

on. Cell voltage balancing can be active during charging and

discharging, but is disabled during the low current

sleepmode state.

Test Mode

A test option is provided to speed up device and battery

pack testing. By connecting Pin 2 to 3.0 V above VC the

internal logic is held in a reset state and both MOSFET

switches are turned on. Upon release, the Control Logic

becomes active and the cell are polled within 4.0 ms.

MC33351A

http://onsemi.com

12

Discharge Current Sensing

Discharge current limit protection can be selectively

added to the battery pack with the addition of a sense resistor

Rlim(dschg) on the Low–Side or by monitoring the voltage

drop across the series FETs on the High–Side.

Sense resistor – low–side

The sense resistor Rlim(dschg) is placed in series with the

negative terminal of Cell 1 and the negative terminal of the

battery pack, Refer to Figure 1.

As the battery pack discharges, Pins 5 and 13 sense the

voltage drop across RLim(dschg).

A discharge current limit fault is detected if the voltage at

Pin 5 is greater than Pin 13 by 50 mV for more than 3.0 ms.

The fault information is stored in a data latch and discharge

MOSFET Q2 is turned off, disconnecting the battery pack

from the load. As a result of the discharge current fault, the

battery pack is available for charging only. The discharge

current limit is given by:

ILim(dschg)

+

Vth(dschg)

RLim(dschg)

+

50 mV

RLim(dschg)

Voltage across FETs – high–side

A 1MΩ or 2MΩ resistor connected from pin# 11 to ground

is used to program the high–side discharge current limit

threshold.

The discharge current fault is reset by either disconnecting

the load from the battery pack, or by connecting the battery

pack to the charger. When the voltage on Pin 16 no longer

exceeds Pin 8 by approximately 2.0 V, the Sense Enable

circuit will turn on discharge MOSFET Q2. Discharge

current sensing can be disabled by connecting Pin 16 to

Pin 8.

The discharge current protection circuit contains a built

in response delay of 3.0 ms. This helps to prevent fault

activation when the battery pack is subjected to pulsed

currents during charging or discharging.

Battery Pack Application

Each of the application figures show a capacitor labeled

CI that connects directly across the battery pack terminals,

and two resistors labeled Rg that are placed in series with the

charge and discharge gate drive outputs. These components

prevent excessive currents from flowing into the

MC33351A when the battery pack terminals are shorted or

arced and are mandatory. Capacitor CI is a 1.0 µF ±20%

ceramic leaded or surface mount type. It must be placed

directly across the battery pack plus and minus terminals

with extremely short lead lengths (≤1/16”) and as close to

the IC as possible. The gate drive output resistors for both Q1

and Q2 are 10 kΩ ±5.o% carbon film type.

In applications where inordinately low leakage

MOSFETs are used, the protection circuit may take several

seconds to reset from an overcurrent fault after the load is

removed. If desired, this situation can be remedied by

providing a small leakage path for charging CI, thus allowing

Pin 8 to rapidly rise, so that it no longer exceeds Pin 16 by

approximately 2.0 V. A 4.7 MΩ resistor placed across the

MOSFET switches accomplishes this task with a minimum

increase in cell discharge current when the battery pack is

connected to the load.

Upon assembly of the battery pack, it is imperative that Cell 1 be connected first so that V

C

is properly biased. The

remaining cells can then be connected in any order . This assembly method prevents forward biasing the protection IC

substrate which can result in overheating and non–functionality.

MC33351A

http://onsemi.com

13

ANY

CELL

VOLTAGE

4.25 V

2.30 V

ON

OFF

Connected

Disconnected

High

(Inactive)

Low

(Active)

16 sec (not resetable)

CHARGER

DISCHARGE

FET

FAULT

(pin 10)

FAULT remains active

No FAULT

1 sec + (0 – 1 sec)

MC33351A – Cell Voltage versus Undervoltage Fault

MC33351A

http://onsemi.com

14

PACKAGE DIMENSIONS

TSSOP–20

DTB SUFFIX

PLASTIC PACKAGE

CASE 948E–02

ISSUE A

DIM

AMIN MAX MIN MAX

INCHES

6.60 0.260

MILLIMETERS

B4.30 4.50 0.169 0.177

C1.20 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.27 0.37 0.011 0.015

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

____

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS. MOLD

FLASH OR GATE BURRS SHALL NOT EXCEED

0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL NOT

EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN

EXCESS OF THE K DIMENSION AT MAXIMUM

MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE –W–.

ÍÍÍ

110

1120

PIN 1

IDENT

A

B

–T–0.100 (0.004)

C

DGH

SECTION N–N

K

K1

JJ1

N

M

F

–W–

SEATING

PLANE

–V–

–U–

S

U

M

0.10 (0.004) V S

T

20X REFK

L

L/2

2X

S

U0.15 (0.006) T

DETAIL E

0.25 (0.010)

DETAIL E

6.40 0.252

––– –––

S

U0.15 (0.006) T

MC33351A

http://onsemi.com

15

Notes

MC33351A

http://onsemi.com

16

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular

purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,

including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “T ypicals” must be

validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or

death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold

SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable

attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim

alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Af firmative Action Employer.

PUBLICATION ORDERING INFORMATION

CENTRAL/SOUTH AMERICA:

Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)

Email: ONlit–spanish@hibbertco.com

ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support

Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)

Toll Free from Hong Kong & Singapore:

001–800–4422–3781

Email: ONlit–asia@hibbertco.com

JAPAN: ON Semiconductor , Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031

Phone: 81–3–5740–2745

Email: r14525@onsemi.com

ON Semiconductor Website : http://onsemi.com

For additional information, please contact your local

Sales Representative.

MC33351A/D

NORTH AMERICA Literature Fulfillment:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver , Colorado 80217 USA

Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada

Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada

Email: ONlit@hibbertco.com

Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada

N. American Technical Support: 800–282–9855 Toll Free USA/Canada

EUROPE: LDC for ON Semiconductor – European Support

German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich T ime)

Email: ONlit–german@hibbertco.com

French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse Time)

Email: ONlit–french@hibbertco.com

English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time)

Email: ONlit@hibbertco.com

EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781

*Available from Germany, France, Italy , England, Ireland