The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
© 1999, 2000, 2001
MOS FIELD EFFECT TRANSISTOR
µ
µµ
µ
PA1727
SWITCHING
N-CHANNEL POWER MOS FET
DATA SHEET
Document No. G14330EJ3V0DS00 (3rd edition)
Date Published March 2002 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
DESCRIPTION
The
µ
PA1727 is N-Channel MOS Field Effect Transistor
designed for high current switching applications.
FEATURES
•Single chip type
•Low on-state resistance
RDS(on)1 = 14 mΩ TYP. (VGS = 10 V, ID = 5.0 A)
RDS(on)2 = 17 mΩ TYP. (VGS = 4.5 V, ID = 5.0 A)
RDS(on)3 = 19 mΩ TYP. (VGS = 4.0 V, ID = 5.0 A)
•Low Ciss: Ciss = 2400 pF TYP.
•Built-in G-S protection diode
•Small and surface mount package (Power SOP8)
ORDERING INFORMATION
PART NUMBER PACKAGE
µ
PA1727G Power SOP8
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
Drain to Source Voltage (VGS = 0 V) VDSS 60 V
Gate to Source Voltage (VDS = 0 V) VGSS ±20 V
Drain Current (DC) ID(DC) ±10 A
Drain Current (Pulse) Note1 ID(pulse) ±40 A
Total Power Dissipation (TA = 25°C) Note2 PT2.0 W
Channel Temperature Tch 150 °C
Storage Temperature Tstg –55 to + 150 °C
Single Avalanche Current Note3 IAS 10 A
Single Avalanche Energy Note3 EAS 200 mJ
Notes 1. PW ≤ 10
µ
s, Duty Cycle ≤ 1%
2. Mounted on ceramic substrate of 1200 mm2 x 2.2 mm
3. Starting Tch = 25°C, VDD = 30 V, RG = 25 Ω, VGS = 20 → 0 V
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When
this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated
voltage may be applied to this device.
EQUIVALENT CIRCUIT
Source
Body
Diode
Gate
Protection
Diode
Gate
Drain
PACKAGE DRAWING (Unit: mm)
1.27
0.12 M
6.0 ±0.3
4.4
0.40
+0.10
–0.05
0.78 Max.
0.05 Min.
1.8 Max.
1.44
0.8
0.5 ±0.2
0.15
+0.10
–0.05
5.37 Max.
0.10
14
85 1, 2, 3
4
5, 6, 7, 8
; Source
; Gate
; Drain
★
Data Sheet G14330EJ3V0DS
2
µ
µµ
µ
PA1727
ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.)
CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Zero Gate Volt age Drai n Current IDSS VDS = 60 V, VGS = 0 V 10
µ
A
Gate Leakage Current IGSS VGS = ±20 V, VDS = 0 V ±10
µ
A
Gate Cut-off Voltage VGS(off) VDS = 10 V, ID = 1 mA 1.5 2.0 2.5 V
Forward Transfer Adm i t tance | yfs |V
DS = 10 V, ID = 5. 0 A 8.0 14 S
RDS(on)1 VGS = 10 V, ID = 5. 0 A 14 19 mΩ
RDS(on)2 VGS = 4.5 V, ID = 5.0 A 17 22 mΩ
Drain to Sourc e On-state Resist ance
RDS(on)3 VGS = 4.0 V, ID = 5.0 A 19 25 mΩ
Input Capac i t ance Ciss VDS = 10 V 2400 pF
Output Capaci tance Coss VGS = 0 V 400 pF
Reverse Transf er Capacitanc e Crss f = 1 MHz 200 pF
Turn-on Delay Time td(on) VDD = 30 V, I D = 5. 0 A 24 ns
Rise Ti me trVGS = 10 V 120 ns
Turn-off Del a y T i me td(off) RG = 10 Ω120 ns
Fall Time tf70 ns
Total Gate Charge QGVDD = 48 V 45 nC
Gate to Source Charge QGS VGS = 10 V 6 nC
Gate to Drain Charge QGD ID = 10 A 13 nC
Body Diode Forward Voltage VF(S-D) IF = 10 A, VGS = 0 V 0.8 V
Reverse Recovery T i me trr IF = 10 A, V GS = 0 V 45 ns
Reverse Recovery Charge Qrr di/dt = 100 A /
µ
s84nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
RG = 25 Ω
50 Ω
PG.
L
VDD
VGS = 20 → 0 V
BVDSS
IAS
IDVDS
Starting T
ch
VDD
D.U.T.
TEST CIRCUIT 3 GATE CHARGE
TEST CIRCUIT 2 SWITCHING TIME
PG. RG
0
VGS
D.U.T.
RL
VDD
τ = 1
s
µ
Duty Cycle ≤ 1%
VGS
Wave Form
ID
Wave Form
VGS
10% 90%
10%
0
ID
90%
90%
t
d(on)
t
r
t
d(off)
t
f
10%
τ
ID
VGS
0
t
on
t
off
PG. 50 Ω
D.U.T.
RL
VDD
IG = 2 mA
Data Sheet G14330EJ3V0DS 3
µ
µµ
µ
PA1727
TYPICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
T
C
- Case Temperature - °C
dT - Percentage of Rated Power - %
0200 40 60 80 100 120 140 160
20
40
60
80
100
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
T
C
- Case Temperature - °C
P
T
- Total Power Dissipation - W
020 40 60 80 100 120 140 160
2.8
2.4
2.0
1.6
1.2
0.8
0.4
Mounted on ceramic
substrate of
1200
mm
2
x 2.2
mm
FORWARD BIAS SAFE OPERATING AREA
1 10 100
I
D
- Drain Current - A
0.1
V
DS
- Drain to Source Voltage - V
0.1
1
10
100
0.01
100
ms
10
ms
1
ms
PW
=
100
µs
I
D(DC)
Power Dissipation
Limited
DC
R
DS(on)
Limited
(at V
GS
= 10 V)
I
D(pulse)
T
A
= 25˚C
Single Pulse
Remark
Mounted on ceramic substrate of 1200 mm2 × 2.2 mm
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
PW - Pulse Width - s
r
th(t)
- Transient Thermal Resistance -
˚
C/W
100
0.01
0.1
1
10
1000
1m 10m 100m 1 10 100 1000 10
µ
100
µ
Mounted on ceramic
substrate of
1200
mm2 x 2.2
mm
Single Pulse, TA = 25˚C
R
th(ch-A)
= 62.5˚C/W
Data Sheet G14330EJ3V0DS
4
µ
µµ
µ
PA1727
FORWARD TRANSFER CHARACTERISTICS
V
GS
- Gate to Source Voltage - V
I
D
- Drain Current - A
0.1
0.01
1
10
100
012345
T
A
= 150˚C
75˚C
25˚C
−25˚C
Pulsed
V
DS
= 10
V
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
V
DS
- Drain to Source Voltage - V
I
D
- Drain Current - A
0 0.2 0.4 0.6 0.8 1.0
40
50 Pulsed
V
GS
=
10 V
V
GS
=
4V
V
GS
=
4.5V
30
20
10
0
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
I
D
- Drain Current - A
|
y
fs
| - Forward Transfer Admittance - S
0.01 0.1 1 10 100
100
10
1
0.1
0.01
V
DS
= 10 V
Pulsed
T
A
= 150˚C
75˚C
25˚C
−25˚C
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
V
GS
- Gate to Source Voltage - V
R
DS(on)
- Drain to Source On-state Resistance - mΩ
00
20
30
10
40
15105
I
D
=
10 A
Pulsed
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
I
D
- Drain Current - A
R
DS(on)
- Drain to Source On-state Resistance - mΩ
1 10 1000.1
0
10
20
30
40
V
GS
= 10
V
V
GS
= 4.5
V
V
GS
= 4
V
Pulsed
GATE TO SOURCE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
T
ch
- Channel Temperature - ˚C
V
GS(off)
- Gate to Source Cut-off Voltage - V
V
DS
= 10 V
I
D
= 1 mA
−50 0 50 100 150
0
1.0
2.0
2.5
3.0
1.5
0.5
Data Sheet G14330EJ3V0DS 5
µ
µµ
µ
PA1727
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
T
ch
- Channel Temperature - ˚C
R
DS(on)
- Drain to Source On-state Resistance - mΩ
0−50
10
0 50 100 150
I
D
= 5 A
20
40
50
30 V
GS
= 4.0
V
V
GS
= 10
V
V
GS
= 4.5
V
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
1.0
I
SD
- Diode Forward Current - A
01.5
V
SD
- Source to Drain Voltage - V
0.5
0.01
0.1
1
10
100 Pulsed
V
GS
= 10 V
V
GS
= 0 V
CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
V
DS
- Drain to Source Voltage - V
C
iss
, C
oss
, C
rss
- Capacitance - pF
10
0.1
100
1000
10000
1 10 100
V
GS
= 0 V
f = 1
MHz
C
iss
C
oss
C
rss
SWITCHING CHARACTERISTICS
I
D
- Drain Current - A
t
d(on)
, t
r
, t
d(off)
, t
f
- Switching Time - ns
0.1
1
10
100
1000
1 10 100
V
DD
= 30
V
V
GS
= 10
V
R
G
= 10
Ω
t
d(off)
t
d(on)
t
r
t
f
REVERSE RECOVERY TIME vs.
DRAIN CURRENT
I
F
- Drain Current - A
t
rr
- Reverse Recovery Time - ns
di/dt
=
100
A
/
V
GS
=
0 V
µ
s
1
0.1
10
1 10 100
1000
100
V
GS
- Gate to Source Voltage - V
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
Q
G
- Gate Charge - nC
V
DS
- Drain to Source Voltage - V
0
010 20 30 40 50 60
10
20
30
40
50
60
2
4
6
8
10
12
0
I
D
= 10
A
V
DS
V
GS
V
DD
= 48 V
30 V
12 V
Data Sheet G14330EJ3V0DS
6
µ
µµ
µ
PA1727
SINGLE AVALANCHE CURRENT vs.
INDUCTIVE LOAD
L - Inductive Load - H
I
AS
- Single Avalanche Current - A
1
10
100
1
m10
m
R
G
= 25 Ω
V
DD
= 30 V
V
GS
= 20 → 0 V
I
AS
= 10
A
10
µ
100
µ
0.1
E
AS
=
200
mJ
SINGLE AVALANCHE ENERGY
DERATING FACTOR
Starting T
ch
- Starting Channel Temperature - ˚C
Energy Derating Factor - %
25 50 75 100
160
140
120
100
80
60
40
20
0
125 150
VDD = 30 V
RG = 25 Ω
VGS = 20 → 0 V
IAS ≤ 10 A
Data Sheet G14330EJ3V0DS 7
µ
µµ
µ
PA1727
[MEMO]
µ
µµ
µ
PA1727
M8E 00. 4
The information in this document is current as of March, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
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