! User's Guide June 2003 PMP Systems Power SLVU087 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. 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Following are URLs where you can obtain information on other Texas Instruments products & application solutions: Products Amplifiers Applications amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety measures typically found in the end product incorporating the goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may not meet the technical requirements of the directive. Should this evaluation kit not meet the specifications indicated in the EVM User's Guide, the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction of the product, it is the user's responsibility to take any and all appropriate precautions with regard to electrostatic discharge. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Please read the EVM User's Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM User's Guide prior to handling the product. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact the TI application engineer. Persons handling the product must have electronics training and observe good laboratory practice standards. No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or combination in which such TI products or services might be or are used. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of 3 V to 5 V and the output voltage range of 0.9 V to 3.3 V. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures greater than 55C. The EVM is designed to operate properly with certain components above 60C as long as the input and output ranges are maintained. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated Preface About This Manual This user's guide describes the characteristics, operation and use of the TPS54380EVM evaluation module (EVM). The user's guide includes a schematic diagram, printout-circuit board (PCB) layouts, and bill of materials. How to Use This Manual - Chapter 1--Introduction - Chapter 2--Test Setup and Results - Chapter 3--Board Layout - Chapter 4--Schematic and Bill of MAterials Information About Cautions and Warnings This book may contain cautions and warnings. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment. This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you. Related Documentation From Texas Instruments - TPS54380 data sheet (literature number SLVS454) v Information About Cautions and Warnings Trademarks SWIFT is a trademark of Texas Instruments. PowerPAD is a trademark of Texas Instruments. vi Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-2 1-3 1-4 1-5 2 Test Setup and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 Input/Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.4 Output Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.5 Load Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.6 Loop Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.7 Output Voltage Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.8 Input Voltage Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.9 Powering Up and Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 3 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 4 Schematic and Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 vii Contents Figures 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 3-1 3-2 3-3 4-1 Frequency Trimming Resistor Selection Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Measured Efficiency, TPS54380 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Measured Circuit Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Load Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Line Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Load Transient Response, TPS54380 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Measured Loop Response, TPS54380, VI = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Measured Loop Response, TPS54380, VI = 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Measured Output Voltage Ripple, TPS54380 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Input Voltage Ripple, TPS54380 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Power Up With Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Powering Down With Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Powering Up With Rationmetric Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Powering Down With Ratiometric Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Powering Up With Core Voltage Rising First . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Powering Up With Core Voltage Falling Second . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Top-Side Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Bottom-Side Layout (looking from top side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Top-Side Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 TPS54380EVM-001 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Tables 1-1 1-2 1-3 4-1 viii Input Voltage and Output Current Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TPS54380EVM-001 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TPS54380EVM-001 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1-3 1-4 4-3 Chapter 1 Introduction This chapter contains background information for the TPS54380 as well as support documentation for the TPS54380EVM-001 evaluation module (HPA001). The TPS54380EVM-001 performance specifications are given, with the schematic and bill of material for the TPS54380EVM-001. Topic Page 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1-1 Background 1.1 Background The TPS54380 tracking dc/dc converter provides accurate power sequencing in applications where two or more voltages are required for a load. These types of applications include core and I/O power supplies for microprosessors, DSPs, and FPGAs. Typically, some specific relation between the core and I/O supply voltages has to be provided during the power-up and power-down sequences. The TPS54380 tracking dc/dc converter is capable of direct tracking, ratiometric tracking, and voltage sequencing with a second power source. The TPS54380EVM-001 is a two-channel EVM demonstrating the flexibility inherent in the TPS54380 design for tracking and sequencing core and I/O voltages. The TPS54380 generates the core voltage and is nominally set at 1.8 V. The nominal 3.3-V I/O voltage is provided by a TPS2013 distribution switch. Rated input voltage and output current range is given in Table 1-1. This evaluation module demonstrates the small PCB areas that are achieved when designing with the TPS54380 regulator. The switching frequency is set at a nominal 700 kHz, allowing the use of a small footprint 1.0-H output inductor. The MOSFETs of the TPS54380 are incorporated inside the TPS54380 package. This eliminates the need for external MOSFETs and their associated drivers. The low drain-to-source on resistance of the MOSFETs gives the TPS54380 high efficiency and helps to keep the junction temperature low at high output currents. The compensation components are provided external to the IC, and allow for an adjustable output voltage and a customizable loop response. The TPS54380 device uses the TRACKIN pin to access the tracking and sequencing capabilities. An internal multiplexer circuit compares the voltage at this pin with the internal reference voltage and uses the lesser of the two as the reference for the output voltage regulation. When the output of another power supply or distribution switch is connected to the TRACKIN pin of TPS54380, the output of the TPS54380 tracks the output of this other channel during power up or down, until the voltage at TRACKIN pin becomes higher then the internal reference voltage. By applying the other power supply output to the TRACKIN pin through an appropriate resistor divider network, any required power up and power down relation between two output voltages of regulators can be set by changing the ratio of the divider network. Table 1-1. Input Voltage and Output Current Summary EVM Input Voltage Range Output Current Range TPS54380EVM-001 3.0 to 5.5 V Core, -3 A to 3 A I/O, 0-1.5 A Input voltage range is limited by the TPS2013 distribution switch. 1-2 Performance Specification Summary 1.2 Performance Specification Summary A summary of the TPS54380EVM-225 performance specifications is provided in Table 1-2. Specifications are given for an input voltage of 3.3 V and an output voltage of 1.8 V unless otherwise specified. The ambient temperature is 25C for all measurements, unless otherwise noted. The data presented in Table 1-2 compiled with no load on the I/O output. The input voltage range is limited to 5.5 V by the distribution switch. The maximum input voltage for the TPS54380 is 6 V. Table 1-2. TPS54380EVM-001 Performance Specification Summary Specification Test Conditions Min Typ Max Units Input voltage range 3.0 3.3 or 5.0 5.5 V Output voltage set point 0.9 1.8 3.3 V 3 A Output current range VI = 3 V to 5.5 V Line regulation IO = 0-3 A, VI = 3 V to 5.5 V 0.1% Load regulation VI = 3.3 V, IO = 0 to 3 A 0.2% Voltage change Load transient response Recovery time Voltage change -3 IO =0.75 A to 2.25 A IO = 2.25 A to 075 A -24 mVPK 120 s 20 mVPK 120 s Loop bandwidth VI = 3 V 50 kHz Phase margin VI = 3 V 62 Loop bandwidth VI = 5.5 V 80 Phase margin VI = 5.5 V 46 Recovery time Input ripple voltage Output ripple voltage Output rise time 50 200 mVPP 6 10 mVPP N/A Operating frequency Maximum efficiency kHz 280 VI = 5.0 V, Vo = 1.8 V, IO = 1.0 A 700 ms 700 89% Introduction kHz - 1-3 Modifications 1.3 Modifications The TPS54380EVM-001 is designed to demonstrate the small size that can be attained when designing with the TPS54380, so many of the features, which allow for extensive modifications have been omitted from this EVM. Changing the value of R2 can change the output voltage in the range of 0.9 V to 3.3 V. The value of R2 for a specific output voltage can be calculated by using Equation 1-1. Table 1-3 list the values for R2 for some common output voltages. Equation 1-1. R2 + 10 kW V 0.891 V * 0.891 V O Table 1-3. Output Voltage Programming Output Voltage (V) R2 Value (k) 0.9 1000 1.2 28.7 1.5 14.7 1.8 9.76 2.5 5.49 3.3 3.74 The minimum output voltage is limited by the minimum controllable on time of the device, 200 ns, and is dependent upon the duty cycle and operating frequency. The approximate minimum output voltage can be calculated using Equation 1-2. Equation 1-2. VOUTMIN = 200n sec x s x VINMAX The switching frequency may be trimmed to any value between 280 kHz and 700 kHz by changing the value of R4. Decreasing the switching frequency results in increased output ripple unless the value of L1 is increased. A plot of the value of RT versus the switching frequency is given in Figure 1-1. 1-4 Modifications Figure 1-1. Frequency Trimming Resistor Selection Graph 750 700 Switching Frequency - kHz 650 600 550 500 450 400 350 300 250 60 70 80 90 100 110 120 130 140 150 160 170 180 Resistance - k An onboard electrolytic input capacitor may be added at C1. 1.3.1 Power Sequencing By selecting different R6-R7 resistor divider ratios, different power sequencing scenarios can be set. The equations 1-3, 1-4 and 1-5 below show how to select the different ways of power sequencing. Equation 1-3. R6 + R1 R2 R7 Equation 1-4. R6 + R7 -core voltage tracks I/O voltage; VIO * 0.891 8.891 - ratiometric relation between core and I/O voltage; Equation 1-5. R6 t R1 -core voltage rises first at power up and falls seconde R2 R7 at power down. Introduction 1-5 1-6 Chapter 2 Test Setup and Results This chapter describes how to properly connect, set up, and use the TPS54380EVM-001 evaluation module. The chapter also includes test results typical for the TPS54380EVM-001 and covers efficiency, output voltage regulation, load transients, loop response, output ripple, input ripple, and start up. Topic Page 2.1 Input/Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.4 Output Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.5 Load Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.6 Loop Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.7 Output Voltage Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.8 Input Voltage Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.9 Powering Up and Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Test Setup and Results 2-1 Input/Output Connections 2.1 Input/Output Connections The TPS54380EVM-001 has the following three input/output connectors: VI J1, VO I/O J2 and VO Core J3. A diagram showing the connection points is shown in Figure 2-1. A power supply capable of supplying 5 A is connected to J1 through a pair of 20 AWG wires. The load is connected to J2 through a pair of 16 AWG wires. The maximum load current capability should be 3 A. Wire lengths are minimized to reduce losses in the wires. Test point TP6 provides a place to easily connect an oscilloscope voltage probe to monitor the output voltage. The TPS54380 is intended to be used as a point of load regulator. In typical applications it is usually located close to the input voltage source. When using the TPS54380EVM-001 with an external power supply as the source for VI, an additional bulk capacitor may be required, depending upon the output impedance of the source and length of the hook-up wires. The test results presented were obtained using a 470 F, 16-V additional input capacitor. Alternately, C1 may be populated with an input filter capacitor. Connection is shown for no load on the I/O voltage output. The I/O voltage may be supply up to 1.5 A into an external load. Figure 2-1. Connection Diagram Power Supply Oscilloscope Voltmeter CH1 Ch2 - 3-6V, 5 A + S1 ON 3.3 V FIRST 1.8 V FIRST OFF TP1 + 0 - 3A - TP2 Voltmeter - 2-2 J1 GND VIN Load + Capacitor Optional Input Efficiency 2.2 Efficiency The TPS54380EVM-001 efficiency peaks at load current of about 1 A to 2 A, and then decreases as the load current increases towards full load. Figure 2-2 shows the efficiency for the TPS54380 at an ambient temperature of 25C. The efficiency is lower at higher ambient temperatures, due to temperature variation in the drain-to-source resistance of the MOSFETs. The efficiency is slightly lower at 700 kHz than at lower switching frequencies, due to the gate and switching losses in the MOSFETs. Figure 2-2. Measured Efficiency, TPS54380 EFFICIENCY vs OUTPUT CURRENT 100 95 VI = 5 V 90 Efficiency - % 85 VI = 3.3 V 80 75 70 65 60 55 50 0 0.5 1 1.5 2 2.5 3 3.5 IO - Output Current - A Test Setup and Results 2-3 Power Dissipation 2.3 Power Dissipation The low junction-to-case thermal resistance of the PWP package, along with a good board layout, allows the TPS54380EVM-001 EVMs to output full rated load current while maintaining safe junction temperatures. With a 3.3-V input source and a 3-A load, the junction temperature is approximately 60C, while the case temperature is approximately 55C. The total circuit losses at 25C are shown in Figure 2-3. Power dissipation is shown for input voltages of 3.3 V and 5.0 V. For additional information on the dissipation ratings of the devices, see the individual product data sheets. Figure 2-3. Measured Circuit Losses POWER DISSIPATION vs OUTPUT CURRENT PD - Power Dissipation - W 2 1.5 VI = 3.3 V 1 VI = 5 V 0.5 0 2-4 0 0.5 1 1.5 2 2.5 3 IO - Output Current - A 3.5 4 Output Voltage Regulation 2.4 Output Voltage Regulation The output voltage load regulation of the TPS54380EVM-001 is shown in Figure 2-4, while the output voltage line regulation is shown in Figure 2-5. Measurements are given for an ambient temperature of 25C. Figure 2-4. Load Regulation OUTPUT VOLTAGE vs OUTPUT CURRENT 0.5 VO - Output Voltage Change - % 0.4 0.3 0.2 0.1 VI = 3.3 V 0 -0.1 VI = 5 V -0.2 -0.3 -0.4 -0.5 0 0.5 1 1.5 2 2.5 IO - Output Current - A 3 3.5 Figure 2-5. Line Regulation OUTPUT VOLTAGE vs INPUT VOLTAGE 0.5 VO - Output Voltage Change - % 0.4 0.3 0.2 IO = 3 A IO = 0 A 0.1 0 -0.1 IO = 1.5 A -0.2 -0.3 -0.4 -0.5 3 4 5 VI - Input Voltage - V 6 Test Setup and Results 2-5 Load Transients 2.5 Load Transients The TPS54380EVM-001 response to load transients is shown in Figure 2-6. The current step is from 25% to 75% of maximum rated load. Total peak-to-peak voltage variation is as shown, including ripple and noise on the output. Figure 2-6. Load Transient Response, TPS54380 VO (ac) 20 mV/div IO 1 A/div Time Scale 200 s/div 2-6 Loop Characteristics 2.6 Loop Characteristics The TPS54380EVM-001 loop response characteristics are shown in Figure 2-7 and Figure 2-8. Gain and phase plots are shown for each device at minimum and maximum operating voltage. Figure 2-7. Measured Loop Response, TPS54380, VI = 3 V MEASURED LOOP RESPONSE 60 180 50 150 120 40 Phase 30 90 Gain - dB 10 Gain 30 0 0 -10 -30 -20 -60 -30 -90 -40 -120 -50 -150 -60 100 1k 10 k Phase - deg 60 20 -180 1M 100 k f - Frequency - Hz Figure 2-8. Measured Loop Response, TPS54380, VI = 5.5 V MEASURED LOOP RESPONSE 60 180 50 150 120 40 Phase 30 Gain 10 30 0 0 -10 -30 -20 -60 -30 -90 -40 -120 -50 -150 -60 100 1k 10 k 100 k f - Frequency - Hz Phase - deg 60 20 Gain - dB 90 -180 1M Test Setup and Results 2-7 Output Voltage Ripple 2.7 Output Voltage Ripple The TPS54X73EVM-225 output voltage ripple is shown in Figure 2-9. The input voltage is 3.3 V for the TPS54380. Output current is the rated full load of 3 A. Voltage is measured directly across output capacitors. Figure 2-9. Measured Output Voltage Ripple, TPS54380 VO (ac) 10 mV/div Vphase 1 V/div Time Scale 1 s/div 2-8 Input Voltage Ripple 2.8 Input Voltage Ripple The TPS54X73EVM-225 output voltage ripple is shown in Figure 2-10. The input voltage is 3.3 V for the TPS54380. Output current for each device is rated full load of 3 A. Figure 2-10. Input Voltage Ripple, TPS54380 VO (ac) 20 mV/div Vphase 1 V/div Time Scale 1 s/div Test Setup and Results 2-9 Powering Up and Down 2.9 Powering Up and Down The TPS54380 regulator provides different modes for power up and power down sequencing of the core and I/O voltages. By selecting the different ratios for the resistor divider R6/R7 (Figure 4-1), the slope of core voltage during powering up and down can be set equal to, higher than, or lower than the slope of I/O voltage. If the resistors R6 = R1 and R7 = R2, then the core voltage tracks the I/O voltage. The start-up voltage waveform of the TPS54380EVM-001 for this condition is shown in Figure 2-11. The waveform shows that the core voltage regulator tracks the output of I/O regulator until the core regulator reaches its nominal 1.8-V level. After that, the core regulator starts to regulate its output at the preset 1.8-V level. The I/O regulator continues its ramp up until the voltage reaches the nominal 3.3-V level. The output voltage waveforms during powering up do not depend on load currents. The output voltage waveforms are powered up by asserting the ENABLE signal, while the input voltage is already applied. Figure 2-11. Power Up With Tracking VO I/O 500 mV/div VO CORE 500 mV/div Time Scale 500 s/div The power-down waveform is shown in Figure 2-12. During power down, the output voltage fall time is defined by the output capacitance and load resistance. In this case the I/O output load resistance has been set to 20 and the core output load resistance set to 1 . With the I/O output voltage falling with a slew rate of about 1.25 V/ms, there is essentially no difference between the core voltage and I/O voltage. 2-10 Powering Up and Down Figure 2-12. Powering Down With Tracking VO I/O 500 mV/div VO CORE 500 mV/div Time Scale 1 ms/div The TPS54380EVM-001 EVM provides the ability to change the slew rate of output voltage of core regulator by using jumper JP2 (see schematic in Figure 4-1). If jumper JP2 is set so that R8 is connected in parallel to R7, ratiometric power sequencing is implemented. For ratiometric sequencing the following condition needs to be met: if R6 = 10 k then R8 II R7 = (R7 x 0.891)/(VI/O - 0.891). In this case the I/O and core voltages reach their nominal values at the same time. The waveforms for ratiometric powering up and down are shown in Figure 2-13 and Figure 2-14. Test Setup and Results 2-11 Powering Up and Down Figure 2-13. Powering Up With Ratiometric Sequencing VO I/O 500 mV/div VO CORE 500 mV/div Time Scale 500 s/div Figure 2-14. Powering Down With Ratiometric Sequencing VO I/O 500 mV/div VO CORE 500 mV/div Time Scale 1 ms/div If jumper JP2 is set so that R8 is connected in parallel to R6, the core voltage rises first during powering up and falls second during power down. The waveforms with this type of sequencing are shown in Figure 2-15 and Figure 2-16. 2-12 Powering Up and Down Figure 2-15. Powering Up With Core Voltage Rising First VO I/O 500 mV/div VO CORE 500 mV/div Time Scale 500 s/div Figure 2-16. Powering Up With Core Voltage Falling Second VO I/O 500 mV/div VO CORE 500 mV/div Time Scale 1 ms/div Test Setup and Results 2-13 2-14 Chapter 3 Board Layout This chapter provides a description of the TPS54380EVM-001 board layout and layer illustrations. Topic 3.1 Page Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Board Layout 3-1 Layout 3.1 Layout The board layout for the TPS54380EVM-001 is shown in Figure 3-1 through Figure 3-3. The top-side layer of the TPS54380EVM-001 is laid out in a manner typical of a user application. The top and bottom layers are 1.5 oz. copper. The top layer contains the main power traces for VI, VO, and V(phase). Also on the top layer are connections for the remaining pins of the TPS54380 and a large area filled with ground. The bottom layer contains ground and VO copper areas, and some signal routing. The top and bottom ground traces are connected with multiple vias placed around the board including 10 directly under the TPS54380 device to provide a thermal path from the PowerPAD land to ground. The input decoupling capacitors (C5 and C9), bias decoupling capacitor (C4), and bootstrap capacitor (C3) are all located as close to the IC as possible. In addition, the compensation components are kept close to the IC. The compensation circuit ties to the output voltage at the point of regulation, adjacent to the high frequency bypass output capacitor. Figure 3-1. Top-Side Layout 3-2 Layout Figure 3-2. Bottom Side Layout (looking from top side) Board Layout 3-3 Layout Figure 3-3. Top Side Assembly 3-4 Chapter 4 Schematic and Bill of Materials The TPS54380EVM-001 schematic and bill of materials are presented in this chapter. Topic Page 4.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Schematic and Bill of Materials 4-1 Schematic 4.1 Schematic The schematic for the TPS54380EVM-001 is shown in Figure 4-1. Figure 4-1. TPS54380EVM-001 Schematic J1 VIN GND TP1 2 1 + TP2 C5 10 F C1 220 F C10 0.1 F 1 2 3 4 U1 TPS2013D OUT GND IN OUT IN OUT EN OUT 8 5 C8 820 pF R5 590 R1 10 k C7 82 pF R3 6.34 k C9 10 F C6 1500 pF JP1 3.3 V First 1.8 V First R8 6.04 k R6 10 k R7 9.76 k Jumper JP2 Not Used For Tracking Option 4-2 R2 9.76 k C15 1000 pF R4 71.5 k Optional Input Capacitor C4 1 F 14 VIN PWRGD 15 VIN 16 BOOT VIN 3 COMP PH 2 VSENSE PH PH 18 TRACKIN PH 20 RT PH 19 ENA 17 PGND VBIAS PGND 1 AGND PGND Pwd 21 GND TP4 R10 R9 U2 TPS54380PWP VOUT I/O C17 0.1 F C11 22 F TP3 10 k J2 1 2 7 6 0 4 5 C3 0.047 F TP6 TP5 10 9 8 7 6 13 12 11 2 1 R11 2.4 C15 3300 pF 1 2 L1 1 H C2 22 F C12 22 F C13 22 F C14 0.1 F TP7 TP8 J3 VOUT CORE GND Bill of Materials 4.2 Bill of Materials Table 4-1 contains the bill of materials for the TPS54380EVM-001. Table 4-1. TPS54380EVM-001 Bill of Materials Count RefDes Description MFR Part Number - C1 Capacitor, POSCAP, 220 F, 10 V, 40-m, 20% 4 C2, C11, C12, C13 Capacitor, ceramic, 22 F, 6.3 V, X5R, 20% 1210 Sanyo 10TPB220M Taiyo Yuden JMK325BJ226MN 1 C3 Capacitor, ceramic, 0.047 F, 25 V, X7R, 10% 603 Std Std 1 C4 2 C5, C9 Capacitor, ceramic, 1.0 F, 10 V, X5R, 20% 603 Std Std Capacitor, ceramic, 10 F, 10 V, X5R, 20% 1210 Taiyo Yuden LMK325BJ106MN 1 1 C6 Capacitor, ceramic, 1500 pF, 50 V, X7R, 10% 603 Std Std C7 Capacitor, ceramic, 82 pF, 50 V, NPO, 5% 603 Std Std 1 C8 Capacitor, ceramic, 820 pF, 50 V, X7R, 10% 603 Std Std 2 C10, C17 Capacitor, ceramic, 0.1 F, 25 V, X7R, 10% 603 Std Std 1 C14 Capacitor, ceramic, 0.1 F, 25 V, X7R, 10% 603 Std Std 1 C15 Capacitor, ceramic, 3300 pF, 50 V, X7R, 10% 603 Std Std 1 C16 Capacitor, ceramic, 1000 pF, 25 V, X7R, 10% 603 Std Std 3 J1, J2, J3 Terminal block, 2 pin, 6 A, 3,5 mm 75525 OST ED1514 1 JP1 Header, 2 pin, 100 mil spacing, (36-pin strip) 0.100 x 2" Sullins PTC36SAAN 1 JP2 Header, 3 pin, 100 mil spacing, (36-pin strip) 0.100 x 3" Sullins PTC36SAAN 1 L1 Inductor, SMT, 1.0 H, 8.5 A, 10 m 0.270 sq Vishay IHLP-2525CZ-01 1 R1 Resistor, chip, 10.0 k, 1/16 W, 1% 603 Std Std 1 R2 Resistor, chip, 9.7 k, 1/16 W, 1% 603 Std Std 1 R3 Resistor, chip, 6.34 k, 1/16 W, 1% 603 Std Std 1 R4 Resistor, chip, 71.5 k, 1/16 W, 1% 603 Std Std 1 R5 Resistor, chip, 590 , 1/16 W, 1% 603 Std Std 1 R6 Resistor, chip, 10.0 k, 1/16 W, 1% 603 Std Std 1 R7 Resistor, chip, 9.76 k, 1/16 W, 1% 603 Std Std 1 R8 Resistor, chip, 6.04 k, 1/16 W, 1% 603 Std Std 1 R9 Resistor, chip, 768 , 1/16 W, 1% 603 Std Std 1 R10 Resistor, chip, 0 , 1/16 W, 1% 603 Std Std 1 R11 Resistor, chip, 2.4 , 1/8 W, 1% 1206 Std Std 1 S1 Switch, 1P2T, slide, PC mount, 200 mA E_Switch EG1218 1 SH1 Short jumper 5 TP1, TP3, TP4, TP5, TP6 Test point, red, 1 mm 0.038", 6400" Farnell 240-345 2 TP2, TP8 Test point, black, 1 mm 0.038", 6400" Farnell 240-333 1 TP7 Adaptor, 3.5-mm probe clip (or 131-5031-00) Tektronix 131-4244-00 1 U1 IC, High-side power distribution SW with current limit SO8 TI TPS2013D 1 U2 IC, dc/dc tracking converter PWP20 TI TPS54380PWP 1 -- PCB, 3 In x 3 In x 0.062 In Any HPA001 Notes: 1) 2) 3) 4) Size D4 0.46 x 0.16 72900 These assemblies are ESD sensitive, ESD precautions must be observed. These assemblies must be clean and free from flux and all contaminants. Use of no clean flux is not acceptable. These assemblies must comply with workmanship standards IPC-A-610 Class 2. Ref designators marked with an asterisk ('**') cannot be substituted. All other components can be substituted with equivalent MFG's components. Schematic and Bill of Materials 4-3 4-4 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: TPS54380EVM-001