
ISO3086T
www.ti.com
SLLSE27C –JANUARY 2011–REVISED JULY 2011
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIT(+) Positive-going input threshold voltage IO= -8 mA –85 –10 mV
VIT(–)Negative-going input threshold voltage IO= 8 mA –200 –115 mV
Vhys Hysteresis voltage (VIT+ –VIT–) 30 mV
VCC1 = 3.3 V VCC1–0.4 3.1
VID = 200 mV, IO=–8 mA,
VOH High-level output voltage V
See Figure 8 VCC1 = 5 V 4 4.8
VCC1 = 3.3 V 0.15 0.4
VID = 200 mV, IO= 8 mA,
VOL Low-level output voltage V
See Figure 8 VCC1 = 5 V 0.15 0.4
IO(Z) High-impedance state output current VO= 0 or VCC1, RE = VCC1 –1 1 µA
VAor VB= 12 V 40 100
VAor VB= 12 V, VCC2 = 0 60 130
Other input
IA, IBBus input current µA
at 0 V
VAor VB=–7 V –100 –40
VAor VB=–7 V, VCC2 = 0 –100 –30
IIH High-level input current, RE VIH = 2. V –10 10 µA
IIL Low-level input current, RE VIL = 0.8 V –10 10
RID Differential input resistance A, B 96 kΩ
CID Differential input capacitance VI= 0.4 sin (4E6πt) + 0.5 V 7 pF
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay 103 125
tsk(p) Pulse skew (|tPHL –tPLH|) See Figure 9 3 15 ns
tr, trOutput signal rise and fall time 1
tPHZ, Propagation delay, high-level to high-impedance output See Figure 10, DE at 0 V 11 22
tPZH Propagation delay, high-impedance to high-level output ns
tPLZ, Propagation delay, low-level to high-impedance output See Figure 11, DE at 0 V 11 22
tPZL Propagation delay, high-impedance to low-level output
TRANSFORMER DRIVER CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC1 = 5V ±10%, D1 and D2 connected to 350 450 610
transformer
fOSC Oscillator frequency kHz
VCC1 = 3.3V ±10%, D1 and D2 connected to 300 400 550
transformer
RON Switch on resistance D1 and D2 connected to 50Ωpull-up resistors 1 2.5 Ω
VCC1 = 5V ±10%, see Figure 14,(1) 80
tr_D D1, D2 output rise time ns
VCC1 = 3.3V ±10%, see Figure 14,(1) 70
VCC1 = 5V ±10%, see Figure 14,(1) 55
tf_D D1, D2 output fall time ns
VCC1 = 3.3V ±10%, see Figure 14,(1) 80
fSt Startup frequency VCC1 = 2.4 V, D1 and D2 connected to transformer 350 kHz
VCC1 = 5V ±10%, see Figure 14,(1) 38
tBBM Break before make time delay ns
VCC1 = 3.3V ±10%, see Figure 14,(1) 140
(1) D1 and D2 connected to 50Ωpull-up resistors
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