Philips Semiconductors PowerMOS transistors Package outlines PACKAGE OUTLINES Package SOT23 SOT54 (TO-92) SOT54variant (TO-92variant) SOT78 (TO-220AB) SOT89 SOT96-1 (SO8) SOT137-1 (SO24) SOT186 (TO-220 exposed tabs) SOT186A (TO-220) SOT223 SOT226 (low-profile TO-220) SOT263 (5-lead TO-220) SOT263-01 (lead option TO-220) SOT323 SOT338-1 (SSOP16) SOT340-1 (SSOP24) SOT363 SOT404 SOT426 SOT428 SOT429 (TO-247) SOT457 (TSOP6) 1998 Apr 02 1869 Surface-mount yes no no no yes yes yes no no yes no no no yes yes yes yes yes yes yes no yes Page .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... Philips Semiconductors PowerMOS transistors Package outlines Plastic surface mounted package; 3 leads SOT23 D E B A X HE v M A 3 Q A A1 1 2 e1 bp c w M B Lp e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max. bp c D E e e1 HE Lp Q v w mm 1.1 0.9 0.1 0.48 0.38 0.15 0.09 3.0 2.8 1.4 1.2 1.9 0.95 2.5 2.1 0.45 0.15 0.55 0.45 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 97-02-28 SOT23 1998 Apr 02 EUROPEAN PROJECTION 1870 Philips Semiconductors PowerMOS transistors Package outlines Plastic single-ended leaded (through hole) package; 3 leads SOT54 c E d A L b 1 e1 2 D e 3 b1 L1 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A b b1 c D d E e e1 L L1(1) mm 5.2 5.0 0.48 0.40 0.66 0.56 0.45 0.40 4.8 4.4 1.7 1.4 4.2 3.6 2.54 1.27 14.5 12.7 2.5 Note 1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities. OUTLINE VERSION SOT54 1998 Apr 02 REFERENCES IEC JEDEC EIAJ TO-92 SC-43 1871 EUROPEAN PROJECTION ISSUE DATE 97-02-28 Philips Semiconductors PowerMOS transistors Package outlines Plastic single-ended leaded (through hole) package; 3 leads (on-circle) SOT54 variant c L2 E d A L b 1 e1 2 e D 3 b1 L1 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A b b1 c D d E e e1 L L1(1) max L2 max mm 5.2 5.0 0.48 0.40 0.66 0.56 0.45 0.40 4.8 4.4 1.7 1.4 4.2 3.6 2.54 1.27 14.5 12.7 2.5 2.5 Notes 1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities. OUTLINE VERSION SOT54 variant 1998 Apr 02 REFERENCES IEC JEDEC EIAJ TO-92 variant SC-43 1872 EUROPEAN PROJECTION ISSUE DATE 98-03-26 Philips Semiconductors PowerMOS transistors Package outlines Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB E SOT78 A A1 P q D1 D L1 L2(1) Q b1 L 1 2 3 b e c e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) (1) UNIT A A1 b b1 c D D1 E e L L1 L2 max. P q Q mm 4.5 4.1 1.39 1.27 0.9 0.7 1.3 1.0 0.7 0.4 15.8 15.2 6.4 5.9 10.3 9.7 2.54 15.0 13.5 3.30 2.79 3.0 3.8 3.6 3.0 2.7 2.6 2.2 Note 1. Terminals in this zone are not tinned. OUTLINE VERSION SOT78 1998 Apr 02 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-11 TO-220AB 1873 Philips Semiconductors PowerMOS transistors Package outlines padpad for good heatheat transfer; 3 leads Plastic surface mounted package; drain collector for good transfer; 3 leads SOT89 B D A b3 E HE L 1 2 3 c b2 w M b1 e1 e 0 2 4 mm scale DIMENSIONS (mm are the original dimensions) UNIT A b1 b2 b3 c D E e e1 HE L min. w mm 1.6 1.4 0.48 0.35 0.53 0.40 1.8 1.4 0.44 0.37 4.6 4.4 2.6 2.4 3.0 1.5 4.25 3.75 0.8 0.13 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ SOT89 1998 Apr 02 EUROPEAN PROJECTION ISSUE DATE 97-02-28 1874 Philips Semiconductors PowerMOS transistors Package outlines SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index Lp L 4 1 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.244 0.039 0.028 0.050 0.041 0.228 0.016 0.024 inches 0.010 0.057 0.069 0.004 0.049 0.01 0.01 0.028 0.004 0.012 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03S MS-012AA 1998 Apr 02 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-05-22 1875 o 8 0o Philips Semiconductors PowerMOS transistors Package outlines SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c HE y v M A Z 13 24 Q A2 A (A 3) A1 pin 1 index Lp L 1 12 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.61 0.60 0.30 0.29 0.050 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT137-1 075E05 MS-013AD 1998 Apr 02 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-24 97-05-22 1876 Philips Semiconductors PowerMOS transistors Package outlines Plastic single-ended package; isolated heatsink mounted; 1 mounting hole; 3 lead TO-220 exposed tabs SOT186 E E1 A P A1 m q D1 D L1 Q b1 L L2 1 2 3 b c w M e e1 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b b1 c D D1 E E1 e e1 L L1(1) L2 m P Q q w mm 4.4 4.0 2.9 2.5 0.9 0.7 1.5 1.3 0.55 0.38 17.0 16.4 7.9 7.5 10.2 9.6 5.7 5.3 2.54 5.08 14.3 13.5 4.8 4.0 10 0.9 0.5 3.2 3.0 1.4 1.2 4.4 4.0 0.4 Note 1. Terminal dimensions within this zone are uncontrolled. Terminals in this zone are not tinned. OUTLINE VERSION SOT186 1998 Apr 02 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-11 TO-220 1877 Philips Semiconductors PowerMOS transistors Package outlines Plastic single-ended package; isolated heatsink mounted; 1 mounting hole; 3 lead TO-220 E SOT186A A A1 P q D1 T D j L2 L1 K Q b1 L b2 1 2 3 b c w M e e1 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) (1) UNIT A A1 b b1 b2 c D D1 E e e1 j K mm 4.6 4.0 2.9 2.5 0.9 0.7 1.1 0.9 1.4 1.2 0.7 0.4 15.8 15.2 6.5 6.3 10.3 9.7 2.54 5.08 2.7 2.3 0.6 0.4 L L1 14.4 3.30 13.5 2.79 L2 max. P Q q 3 3.2 3.0 2.6 2.3 3.0 2.6 T (2) 2.5 w 0.4 Notes 1. Terminal dimensions within this zone are uncontrolled. Terminals in this zone are not tinned. 2. Both recesses are 2.5 x 0.8 max. depth OUTLINE VERSION SOT186A 1998 Apr 02 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-11 TO-220 1878 Philips Semiconductors PowerMOS transistors Package outlines padpad for good heatheat transfer; 4 leads Plastic surface mounted package; drain collector for good transfer; 4 leads D SOT223 E B A X c y HE v M A b1 4 Q A A1 1 2 3 Lp bp e1 w M B detail X e 0 2 4 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp b1 c D E e e1 HE Lp Q v w y mm 1.8 1.5 0.10 0.01 0.80 0.60 3.1 2.9 0.32 0.22 6.7 6.3 3.7 3.3 4.6 2.3 7.3 6.7 1.1 0.7 0.95 0.85 0.2 0.1 0.1 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 96-11-11 97-02-28 SOT223 1998 Apr 02 EUROPEAN PROJECTION 1879 Philips Semiconductors PowerMOS transistors Package outlines Plastic single-ended package; 3 lead low-profile TO-220 SOT226 A A1 E D1 mounting base D L1 L2 Q b1 L 1 2 3 b e c e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) (1) UNIT A A1 b b1 c D D1 E e L L1 L2 max Q mm 4.5 4.1 1.39 1.27 0.9 0.7 1.3 1.0 0.7 0.4 11.0 10.0 1.5 1.1 10.3 9.7 2.54 15.0 13.5 3.30 2.79 3.0 2.6 2.2 Note 1. Terminals in this zone are not tinned. OUTLINE VERSION SOT226 1998 Apr 02 REFERENCES IEC JEDEC EIAJ low-profile TO-220 EUROPEAN PROJECTION ISSUE DATE 97-06-11 1880 Philips Semiconductors PowerMOS transistors Package outlines Plastic single-ended package; heatsink mounted; 1 moumting hole; 5-lead TO-220 E SOT263 A A1 P q D1 mounting base D L1 L3 Q L2 m L 1 5 e b c w M 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c D D1 E e L mm 4.5 4.1 1.39 1.27 0.9 0.7 0.7 0.4 15.8 15.2 6.4 5.9 10.3 9.7 1.7 15.0 13.5 L1 (1) 2.4 1.6 L2 (2) 0.5 (3) L3 max. m P q Q w 3.5 0.8 0.6 3.8 3.6 3.0 2.7 2.6 2.2 0.4 Notes 1. Terminal dimensions are uncontrolled in this zone. 2. Positional accuracy of the terminals is controlled in this zone. 3. Terminals in this zone are not tinned. OUTLINE VERSION SOT263 1998 Apr 02 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-11 5-lead TO-220 1881 Philips Semiconductors PowerMOS transistors Package outlines Plastic single-ended package; heatsink mounted; 1 mounting hole; 5-lead TO-220 lead form option SOT263-01 E A A1 P q D1 mounting base D L4 L3 L1 R L L5 m 1 L2 5 e b w M R c Q Q1 Q2 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A mm 4.5 4.1 A1 b 1.39 0.90 1.27 0.75 c D D1 E e L L1 L2 0.7 0.4 15.8 15.2 6.4 5.9 10.3 9.7 1.7 9.8 9.7 5.9 5.3 5.2 5.0 L3(1) max. 3.5 L4(2) L5(3) max. m P q Q Q1 Q2 R w 2.4 1.6 0.5 0.8 0.6 3.8 3.6 3.0 2.7 2.0 4.5 8.2 0.5 0.4 Notes 1. Terminals in this zone are not tinned. 2. Positional accuracy of the terminals is controlled in this zone. 3. Terminal dimensions are uncontrolled in this zone. OUTLINE VERSION SOT263-01 1998 Apr 02 REFERENCES IEC JEDEC EIAJ 5-lead (option) TO-220 EUROPEAN PROJECTION ISSUE DATE 97-06-11 1882 Philips Semiconductors PowerMOS transistors Package outlines Plastic surface mounted package; 3 leads SOT323 D E B A X HE y v M A 3 Q A A1 c 1 2 e1 bp Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w mm 1.1 0.8 0.1 0.4 0.3 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.23 0.13 0.2 0.2 OUTLINE VERSION SOT323 1998 Apr 02 REFERENCES IEC JEDEC EIAJ SC-70 1883 EUROPEAN PROJECTION ISSUE DATE 97-02-28 Philips Semiconductors PowerMOS transistors Package outlines SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 1998 Apr 02 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 94-01-14 95-02-04 MO-150AC 1884 o Philips Semiconductors PowerMOS transistors Package outlines SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm D SOT340-1 E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.8 0.4 8 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT340-1 1998 Apr 02 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-09-08 95-02-04 MO-150AG 1885 o Philips Semiconductors PowerMOS transistors Package outlines Plastic surface mounted package; 6 leads SOT363 D E B y X A HE 6 v M A 4 5 Q pin 1 index A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION SOT363 1998 Apr 02 REFERENCES IEC JEDEC EIAJ SC-88 1886 EUROPEAN PROJECTION ISSUE DATE 97-02-28 Philips Semiconductors PowerMOS transistors Package outlines Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) SOT404 A A1 E mounting base D1 D HD 2 Lp 1 3 c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c D D1 E e Lp HD Q mm 4.5 4.1 1.40 1.27 0.85 0.60 0.64 0.46 9.65 8.65 1.6 1.2 10.3 9.7 2.54 2.9 2.1 15.4 14.8 2.60 2.20 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 98-04-07 SOT404 1998 Apr 02 EUROPEAN PROJECTION 1887 Philips Semiconductors PowerMOS transistors Package outlines Plastic single-ended surface mounted package (Philips version of D2-PAK); 5 leads (one lead cropped) SOT426 A A1 E mounting base D HE 3 1 2 4 e e L1 5 c b e e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c D max. E e L1 HE mm 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 11 10.30 9.70 1.70 2.90 2.10 15.80 14.80 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 98-04-07 SOT426 1998 Apr 02 EUROPEAN PROJECTION 1888 Philips Semiconductors PowerMOS transistors Package outlines Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads (one lead cropped) SOT428 seating plane y A E A2 A A1 b2 D1 mounting base E1 D HE L2 2 L1 L 1 3 b1 w M A b c e e1 0 10 20 mm scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 2.38 2.22 A1(1) A2 b b1 max. b2 c 0.65 0.45 0.89 0.71 0.89 0.71 1.1 0.9 5.36 5.26 0.4 0.2 D1 E D max. max. max. E1 min. 6.22 5.98 4.0 6.73 6.47 4.81 4.45 e e1 2.285 4.57 HE max. L L1 min. L2 w y max. 10.4 9.6 2.95 2.55 0.5 0.7 0.5 0.2 0.2 Note 1. Measured from heatsink back to lead. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ SOT428 1998 Apr 02 EUROPEAN PROJECTION ISSUE DATE 98-04-07 1889 Philips Semiconductors PowerMOS transistors Package outlines Plastic single-ended through-hole package; heatsink mounted; 1 mounting hole; 3-lead TO-247 SOT429 E P A A1 q S R D Y L1(1) Q b2 L 1 2 3 c w M b b1 e e 0 10 20 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b b1 b2 c D E e L mm 5.3 4.7 1.9 1.7 1.2 0.9 2.2 1.8 3.2 2.8 0.9 0.6 21 20 16 15 5.45 16 15 (1) L1 4.0 3.6 P Q q R S w Y 3.7 3.3 2.6 2.4 5.3 3.5 3.3 7.5 7.1 0.4 15.7 15.3 6 4 17 13 Note 1. Tinning of terminals are uncontrolled within zone L1. OUTLINE VERSION SOT429 1998 Apr 02 REFERENCES IEC JEDEC EIAJ TO-247 EUROPEAN PROJECTION ISSUE DATE 98-04-07 1890 Philips Semiconductors PowerMOS transistors Package outlines Plastic surface mounted package; 6 leads SOT457 D E B y A HE 6 X v M A 4 5 Q pin 1 index A A1 1 2 bp e c 3 Lp w M B detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.1 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION SOT457 1998 Apr 02 REFERENCES IEC JEDEC EIAJ SC-74 1891 EUROPEAN PROJECTION ISSUE DATE 97-02-28