FQP7N20J69Z - Fairchild Semiconductor Corporation

FEATURES

• Advanced New Des ign

• Avanced Rugged Technology

• Rug ged Gat e Oxide Tec hnolo gy

• Very Low Intrinsi c Ca pacitances

• Excellen t Switching Characteristics

• Unrivalled Ga te Charge: 8.0nC (Typ.)

• Exte nded Safe Op erating Area

•Lower R

DS(ON): 0.55Ω (Typ.)

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

mbol Characteristics Value Units

VDSS Drain-to-Source Vol tage 200 V

IDContinuous Drain Current (TC = 25°C) 6.6 A

Continuous Drain Current (TC = 100°C) 4.2

IDM Drain Cu rrent-Pulsed ①26 V

VGS Gate-to-Source Voltage ±30 J

EAS Sing le Pulsed Avalanche Energy ②73 mJ

IAR Avalanche Current ①6.6 A

EAR Re petiti v e Ava la nche Ene r g y ①6.3 mJ

dv/dt Peak Diode Recovery dv/dt ③5.5 V/ns

PDTotal Power Dissipation (TC = 25°C)

Linear Derating Factor 63

0.51 W

W/°C

TJ, TSTG Operating Junction and Storage

Temperature Range −55 to +150 °C

TLMaximum Lead Temp. for So ldering

Purposes, 1/8” from case for 5-seconds 300

Symbol Characteristics Typ. Max. Units

RθJC Junction-to-Case −1.98

°C/WRθCS Case-to-Sink 0.5 −

RθJA Junction-to-Ambient −62.5

BVDSS = 200V

RDS(ON) = 0.69Ω

ID = 6.6A

TO-220

1. Gat e 2. Drai n 3. So urc e

QFET N-CHANNEL FQP7N20

 1999 Fairchild Semiconductor Corporation

REV. B

FQP7N20 QFET N-CHANNEL

ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise specified)

SOURCE-DRAIN DIODE RATINGS AND CHARACTERIS TICS

Notes:

①Repetitive Ratin

: Pulse Width Limited by Maximum Junct ion Temperature

②L=2.5mH, IAS=6.6A, VDD=50V, RG=25Ω, Startin

TJ =25°C

③ISD ≤ 6.6A, di/dt ≤ 30 0 µs, VDD ≤ BVDSS, Startin

TJ =25°C

④Pulse Test : Pulse Width ≤ 300µs, Dut y Cycle ≤ 2%

⑤Essentially Independent of Operatin

Temperat ure

Symbo l Charac te ristics Min. Typ. Max. Units Test Con ditions

BVDSS Drain-Source Breakdown Vot lage 200 −−VV

GS=0V, ID=250µA

∆BV/∆TJBreskdown Voltage Temp. Coeff. −0.27 −V/°CI

=250µA,

Se e Fig 7

VGS(th) Gat e Threshold Voltage 3.0 −5.0 V VDS=5V, ID=250µA

IGSS Gate-So urce Leakage, Forw ard −−100 nA VGS=30V

Gat e-Source Leakage, Reverse −−−100 VGS= −30V

IDSS D rain-to-Source Leakag e Current −−1

µA

DS=200V

−−10 VDS=160V, TC=125°C

RDS(on) Static Drain-Source

On-State Resistance −0.55 0.69 ΩVGS=10V, ID=3.3A ④

gfs Forward Transco nductanc e −3.7 −SV

DS=40V, ID=3.3A ④

Ciss I nput Capac itanc e −300 400

pF VGS=0V, VDS=25V

f=1MHz

S ee Fi g 5

Coss Out put Capacitan ce −60 75

Crss R everse Transfer Capacitance −912

d(on) Tu rn-On Delay Ti m e −8.0 25

ns VDD=100V, ID=6.6A

RG=50Ω

S ee Fi g 13

④ ⑤

trRi se Time −65 140

td(off) Tu rn- Of f Delay Time −15 40

tfFa ll T ime −35 80

QgTotal Ga te Charge −8.0 10

nC VDS=160V, VGS=10V

ID=6.6A

See Fig 6 & Fig 12

④ ⑤

Qgs Gate-Source Charge −2.4 −

Qgd Gate-Drain (Miller) Charge −3.3 −

Symbo l Characteristics Min. Typ. Max. Units Test Con ditio ns

ISC ontinuous So urce Current −−6.6 AIntegral reverse pn-diode

in the MOSFE T

ISM Pulsed-Source Current ①−−26

VSD D iode Forward Voltage ④−−1.5 V TJ=25°C, IS=6.6A, VGS=0V

Qrr Reverse Resovery Time −110 −ns TJ=25°C, IF=6.6A, VDD=160V

diF/dt=100A/µs ④

R everse Resovery Charge −0.51 −µC

246810

10-1

100

101

¡Ø Note

1. VDS = 40V

2. 250¥ìs P ulse Test

-55¡É

150¡É

25¡É

ID , Drain Current [A]

VGS , Gate-Source Voltage [V]

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

10-1

100

101

25¡É

150¡É ¡Ø Note :

1. VGS = 0V

2. 250¥ìs Pulse Test

IDR , Reverse Drain Current [A]

VSD , Source-Drain Voltage [V]

0246810

VDS = 100V

VDS = 40V

VDS = 160V

¡Ø Note : I D = 6.6 A

VGS, Gate-Source Voltage [V]

QG, To ta l G a te C h a r ge [n C]

Fig 1. Output Character istics Fig 2. Tran sfer Charac terist ics

Fig 6. G ate Cha rge vs. Gate-Source VoltageFig 5. Capacitanc e vs. Drain-Source Voltage

Fig 4. Source-Drain Diode Forward VoltageFig 3. On-Res istance vs. Drai n Cur rent

10-1 100101

100

200

300

400

500

600 Ciss = Cgs + Cgd (Cds = s horted)

Coss = Cds + Cgd

Crss = Cgd

¡Ø Note ;

1 . V GS = 0 V

2 . f = 1 MHz

Crss

Coss

Ciss

Capacitances [pF]

VDS, Dra in-Source Voltage [V]

10-1 100101

10-1

100

101

VGS

Top : 15 V

10 V

8.0 V

7.0 V

6.5 V

6.0 V

B ottom : 5.5 V

¡Ø Note :

1 . 250¥ìs P ulse Test

2 . TC = 25¡É

ID , Drain C urrent [A]

VDS , Drain-Source Voltage [V ]

03691215

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

VGS = 20V

VGS = 10V

RDS(on) , [Ω]

D rain-Source On-R esistance

ID , Drain C urrent [A]

QFET N-CHANNEL FQP7N20

FQP7N20 QFET N-CHANNEL

-100 -50 0 50 100 150 200

0.8

0.9

1.0

1.1

1.2

¡Ø N ote :

1. V GS = 0 V

2. ID = 250 ¥ìA

BVDSS , (Normalized)

Drain-Source Breakdown Voltage

TJ, Junction Temperature [oC]

100101102

10-1

100

101

102

10 ms

1 ms

100 µs

O peration in This Area

is Limited by R DS(on)

¡Ø No tes :

1 . TC = 25 oC

2 . TJ = 150 oC

3. Single Pulse

ID, Drain Cur rent [A ]

VDS, Dr a i n-Source Vo lt a g e [V]

-100 -50 0 50 100 150 200

0.0

0.5

1.0

1.5

2.0

2.5

3.0

¡Ø Note :

1. VGS = 10 V

2. ID = 3.3 A

RDS(ON), (Nor malized)

Drain-Source On-Resistance

TJ, Junction Temperature [oC]

Fig 7. Breakd own Vol tag e vs. Temperature Fig 8. On-Resistan ce vs. Temperature

Fig 11. Thermal Response

Fig 10. Max. Drain Current vs. Case TemperatureFig 9. Max. Safe Operating Area

PDM

t1t2

10-5 10-4 10-3 10-2 10-1 100101

10-2

10-1

100

¡Ø Not es :

1 . Z¥èJC

(t ) = 1 .98 ¡É /W Ma x .

2. Duty Fac tor, D=t1/t2

3 . TJM - TC = PDM * Z¥èJC

(t)

single pulse

D=0.5

0.02

0.2

0.05

0.1

0.01

Z¥èJC

(t), Therm al Response

t1, Square Wave Pulse Duration [sec]

25 50 75 100 125 150

ID, Dr ain Current [A]

TC, C a se Tempe ra ture [¡ É]

[°C]

Fig 12. Gate Charge Test Circuit & Waveform

Fig 13. Resistive Switchin g Test Circu it & Wa veforms

Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms

EAS =L

L IAS2

----

1--------------------

BVDSS -- VDD

BVDSS

Vin

VDS

10%

90%

td(on) tr

t on t off

td(off) tf

Charge

VGS

10V Qg

Qgs Qgd

VDD

VDS

BVDSS

t p

VDD

IAS

VDS (t)

ID (t)

Time

VDD

(

0.5 rated VDS

)

10V

VDS RL

DUT

3mA

VGS

DUT

VDS

300nF

50K

200nF

12V

Same Typ e

as DUT

10V DUT

I D

QFET N-CHANNEL FQP7N20

FQP7N20 QFET N-CHANNEL

Fig 15. Peak Diode Rec overy dv/dt Test Cir cuit & W aveforms

DUT

VDS

Driver

RGSame T

as DUT

VGS • dv/dt controlled by RG

• IS controlled by pulse period

VDD

I S

10V

VGS

( Driver )

I S

( DUT )

VDS

( DUT )

VDD

Body Diode

Forward Volta

e D rop

IFM , Body Diod e Forward Current

Body Diode Reverse Current

IRM

Body Di ode Reco very dv/dt

di/dt

D = Gate Pulse Width

Gate Pulse Period

--------------------------

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Definition of Terms

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Advance Information

Preliminary

No Identification Needed

Obsolete

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

This datasheet contains final specifications. Fairchild

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any time without notice in order to improve design.

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Formative or

In Design

First Production

Full Production

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