April 2005
Copyright © Alliance Semiconductor. All rights reserved.
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3.3V 128K x 18 Flowthrough Synchronous SRAM with NTDTM
Features
• Organization: 131,072 words × 18 bits
•NTD
™ architecture for efficient bus operation
• Fast clock to data access: 7.5/8.0/10.0 ns
•Fast OE
access time: 3.5/4.0 ns
• Fully synchronous operation
• Flow-through mode
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic block diagram
Selection guide
-75 -80 -10 Units
Minimum cycle time 8.5 10 12 ns
Maximum clock access time 7.5 8.0 10 ns
Maximum operating current 260 230 200 mA
Maximum standby current 110 100 90 mA
Maximum CMOS standby current (DC) 30 30 30 mA
Write Buffer
Address
DQ
CLK
register
Output
buffer
DQ [a,b]
17
17
CLK
CE0
CE1
CE2
A[16:0]
OE
CEN
Control
CLK
logic
Data
DQ
CLK
input
register
18 18
OE
128K x 18
SRAM
array
R/W
DQ [a,b]
BWa
BWb
CLK
Q
D
ADV / LD
LBO
burst logic
addr. registers
Write delay
17
ZZ
CLK
18 18
18
18
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2 Mb Synchronous SRAM products list1,2
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
3 Refer corresponding product datasheets for the latest information on Clock Speed and Clock Access Time availability.
PL-SCD : Pipelined Burst Synchronous SRAM - Single Cycle Deselect
PL-DCD : Pipelined Burst Synchronous SRAM - Double Cycle Deselect
FT : Flow-through Burst Synchronous SRAM
NTD1-PL : Pipelined Burst Synchronous SRAM with NTDTM
NTD-FT : Flow-through Burst Synchronous SRAM with NTDTM
Org Part Number Mode Speed3
128KX18 AS7C33128PFS18B PL-SCD 200/166/133 MHz
64KX32
AS7C3364PFS32B PL-SCD 200/166/133 MHz
64KX36 AS7C3364PFS36B PL-SCD 200/166/133 MHz
128KX18 AS7C33128PFD18B PL-DCD 200/166/133 MHz
64KX32
AS7C3364PFD32B PL-DCD 200/166/133 MHz
64KX36 AS7C3364PFD36B PL-DCD 200/166/133 MHz
128KX18 AS7C33128FT18B FT 6.5/7.5/8.0/10 ns
64KX32
AS7C3364FT32B FT 6.5/7.5/8.0/10 ns
64KX36 AS7C3364FT36B FT 6.5/7.5/8.0/10 ns
128KX18 AS7C33128NTD18B NTD-PL 200/166/133 MHz
64KX32
AS7C3364NTD32B NTD-PL 200/166/133 MHz
64KX36 AS7C3364NTD36B NTD-PL 200/166/133 MHz
128KX18 AS7C33128NTF18B NTD-FT 7.5/8.0/10 ns
64KX32
AS7C3364NTF32B NTD-FT 7.5/8.0/10 ns
64KX36 AS7C3364NTF36B NTD-FT 7.5/8.0/10 ns
1. NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property
of their respective owners.
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100-pin TQFP - top view
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
LBO
A
A
A
A
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE0
CE1
NC
NC
BWb
BWa
CE2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
NC
A
A
TQFP 14 x 20mm
NC
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQb0
DQb1
V
SSQ
V
DDQ
DQb2
DQb3
NC
V
DD
NC
V
SS
DQb4
DQb5
V
DDQ
V
SSQ
DQb6
DQb7
DQPb
NC
V
SSQ
V
DDQ
NC
NC
NC
A
NC
NC
V
DDQ
V
SSQ
NC
DQPa
DQa7
DQa6
V
SSQ
V
DDQ
DQa5
DQa4
V
SS
ZZ
DQa3
DQa2
V
DDQ
V
SSQ
DQa1
DQa0
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
V
DD
NC
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Functional Description
The AS7C33128NTF18B family is a high performance CMOS 2 Mbit synchronous Static Random Access Memory (SRAM)
organized as 131,072 words × 18 bits and incorporates a LATE Write.
This variation of the 2Mb+ synchronous SRAM uses the No Turnaround Delay (NTD™) architecture, featuring an enhanced
write operation that improves bandwidth over flowthrough burst devices. In a normal flowthrough burst device, the write data,
command, and address are all applied to the device on the same clock edge. If a read command follows this write command,
the system must wait for one 'dead' cycle for valid data to become available. This dead cycle can significantly reduce overall
bandwidth for applications requiring random access or read-modify-write operations.
NTD™ devices use the memory bus more efficiently by introducing a write latency which matches the one-cycle flow-
through read latency. Write data is applied one cycle after the write command and address, allowing the read pipeline to clear.
With NTD™, write and read operations can be used in any order without producing dead bus cycle.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 18
bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied
to the device one clock cycle later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write
operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-selected by
any of the three chip enable inputs.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip
select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any
device operations, including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C33128NTF18B operates with a 3.3V ± 5% power supply for the device core (VDD). DQ circuits use a separate
power supply (VDDQ) that operates across 2.5V or 3.3V ranges. These devices are available in a 100-pin TQFP package.
TQFP Capacitance
*Guranteed not tested
TQFP thermal resistance
Parameter Symbol Test conditions Min Max Unit
Input capacitance CIN*Vin = 0V - 5 pF
I/O capacitance CI/O*Vin = Vout = 0V - 7 pF
Description Conditions Symbol Typical Units
Thermal resistance
(junction to ambient)1
1 This parameter is sampled
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51
1–layer θJA 40 °C/W
4–layer θJA 22 °C/W
Thermal resistance
(junction to top of case)1θJC 8°C/W
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Signal descriptions
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ
is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.
Burst order
Signal I/O Properties Description
CLK I CLOCK Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock.
CEN I SYNC Clock enable. When de-asserted high, the clock input signal is masked.
A, A0, A1 I SYNC Address. Sampled when all chip enables are active and ADV/LD is asserted.
DQ[a,b] I/O SYNC Data. Driven as output when the chip is enabled and OE is active.
CE0, CE1,
CE2 I SYNC Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.
Are ignored when ADV/LD is high.
ADV/LD I SYNC Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. When low, a new address is loaded.
R/W I SYNC A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.
BW[a,b] I SYNC Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
OE I ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive.
LBO ISTATIC
Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When
driven Low, device follows linear Burst order. This signal is internally pulled High.
ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
NC - - No connects.
Interleaved burst order LBO = 1 Linear burst order LBO = 0
A1A0 A1A0 A1A0 A1A0 A1A0 A1A0 A1A0 A1A0
Starting address 0 0 0 1 1 0 1 1 Starting Address 0 0 0 1 1 0 1 1
First increment 0 1 0 0 1 1 1 0 First increment 0 1 1 0 1 1 0 0
Second increment 1 0 1 1 0 0 0 1 Second increment 1 0 1 1 0 0 0 1
Third increment 1 1 1 0 0 1 0 0 Third increment 1 1 0 0 0 1 1 0
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Synchronous truth table[5,6,7,8,9,11]
Key: X = Don’t Care, H = HIGH, L = LOW. BWn = H means all byte write signals (BWa, BWb) are HIGH. BWn = L means one or more byte write
signals are LOW.
Notes:
1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chose in the initial
BEGIN BURST cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first.
2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a
WRITE command is given, but no operation is performed.
3 OE may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE
cycle. OE may be used when the bus turn-on and turn-off times do not meet an application’s requirements.
4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will
remain in High-Z. No WRITE operations will be performed during the INHIBIT CLOCK cycle.
5 BWa enables WRITEs to byte “a” (DQa pins); BWb enables WRITEs to byte “b” (DQb pins).
6 All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
7 Wait states are inserted by setting CEN HIGH.
8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.
10 The address counter is incremented for all CONTINUE BURST cycles.
11 ZZ pin is always Low.
CE0 CE1 CE2 ADV/LD R/W BWnOE CEN
Address
source CLK Operation DQ Notes
H X X L X X X L NA L to H DESELECT Cycle High-Z
X X H L X X X L NA L to H DESELECT Cycle High-Z
X L X L X X X L NA L to H DESELECT Cycle High-Z
X X X H X X X L NA L to H CONTINUE DESELECT Cycle High-Z 1
L H L L H X L L External L to H READ Cycle (Begin Burst) Q
X X X H X X L L Next L to H READ Cycle (Continue Burst) Q 1,10
L H L L H X H L External L to H NOP/DUMMY READ (Begin Burst) High-Z 2
X X X H X X H L Next L to H DUMMY READ (Continue Burst) High-Z 1,2,10
L H L L L L X L External L to H WRITE CYCLE (Begin Burst) D 3
X X X H X L X L Next L to H WRITE CYCLE (Continue Burst) D 1,3,10
L H L L L H X L External L to H NOP/WRITE ABORT (Begin Burst) High-Z 2,3
X X X H X H X L Next L to H WRITE ABORT (Continue Burst) High-Z 1,2,3,
10
X X X X X X X H Current L to H INHIBIT CLOCK - 4
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State diagram for NTD SRAM
Absolute maximum ratings
Note: Stresses greater than those listed in this table may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions may affect reliability.
Recommended operating conditions at 3.3V I/O
*VDDQ cannot be greater than VDD
Recommended operating conditions at 2.5V I/O
*VDDQ cannot be greater than VDD
Parameter Symbol Min Max Unit
Power supply voltage relative to GND VDD, VDDQ –0.5 +4.6 V
Input voltage relative to GND (input pins) VIN –0.5 VDD + 0.5 V
Input voltage relative to GND (I/O pins) VIN –0.5 VDDQ + 0.5 V
Power dissipation PD–1.8W
DC output current IOUT –20mA
Storage temperature (plastic) Tstg –65 +150 oC
Temperature under bias Tbias –65 +135 oC
Parameter Symbol Min Nominal Max Unit
Supply voltage for inputs VDD 3.135 3.3 3.465 V
Supply voltage for I/O VDDQ*3.135 3.3 VDD V
Ground supply Vss 0 0 0 V
Parameter Symbol Min Nominal Max Unit
Supply voltage for inputs VDD 3.135 3.3 3.465 V
Supply voltage for I/O VDDQ*2.375 2.5 VDD V
Ground supply Vss 0 0 0 V
Dsel
Dsel
Read
Read
Burst
Burst
Write
Read
Write
Burst
Read
Read
Write
Dsel
Read
Burst
Write
Dsel
Dsel
Write
Write
Burst
Dsel
Burst
Burst
Write
Read
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DC electrical characteristics for 3.3V I/O operation
DC electrical characteristics for 2.5V I/O operation
† LBO pin has an internal pull-up and input leakage = -10 µA.
*VIH max < VDD +1.5V for pulse width less than 0.2 X tCYC
**VIL min = -1.5 for pulse width less than 0.2 X tCYC
IDD operating conditions and maximum limits
Parameter Sym Conditions Min Max Unit
Input leakage current† |ILI|V
DD = Max, 0V < VIN < VDD -2 2 µA
Output leakage current |ILO|OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ -2 2 µA
Input high (logic 1) voltage VIH
Address and control pins 2* VDD+0.3
V
I/O pins 2* VDDQ+0.3
Input low (logic 0) voltage VIL
Address and control pins -0.3** 0.8
V
I/O pins -0.5** 0.8
Output high voltage VOH IOH = –4 mA, VDDQ = 3.135V 2.4 – V
Output low voltage VOL IOL = 8 mA, VDDQ = 3.465V – 0.4 V
Parameter Sym Conditions Min Max Unit
Input leakage current† |ILI|V
DD = Max, 0V < VIN < VDD -2 2 µA
Output leakage current |ILO|OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ -2 2 µA
Input high (logic 1) voltage VIH
Address and control pins 1.7* VDD+0.3 V
I/O pins 1.7* VDDQ+0.3 V
Input low (logic 0) voltage VIL
Address and control pins -0.3** 0.7 V
I/O pins -0.3** 0.7 V
Output high voltage VOH
IOH = –4 mA, VDDQ = 2.375V 1.7 –
V
IOH = –1 mA, VDDQ = 2.375V 2.0 –
Output low voltage VOL
IOL = 8 mA, VDDQ = 2.625V – 0.7
V
IOL = 1 mA, VDDQ = 2.625V – 0.4
Parameter Sym Conditions -75 -80 -10 Unit
Operating power supply current1
1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading.
ICC
CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax,
IOUT = 0 mA, ZZ < VIL
260 230 200 mA
Standby power supply current
ISB
All VIN ≤ 0.2V or >
V
DD
– 0.2V,
Deselected,
f = fMax, ZZ < VIL
110 100 90
mA
ISB1
Deselected, f = 0, ZZ < 0.2V,
all VIN ≤ 0.2V or ≥ VDD – 0.2V 30 30 30
ISB2
Deselected, f = f
Max
, ZZ
≥
V
DD
– 0.2V,
all VIN ≤ VIL or ≥ VIH
30 30 30
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Timing characteristics over operating range
Snooze Mode Electrical Characteristics
Parameter Sym
-75 -80 -10
Unit Notes1
1 See “Notes:” on page 15.
Min Max Min Max Min Max
Cycle time tCYC 8.5 –10 –12 –ns
Clock access time tCD –7.5 –8.0 –10 ns
Output enable low to data valid tOE –3.5 –4.0 –4.0 ns
Clock high to output low Z tLZC 2.5 –2.5 –2.5 –ns 2,3,4
Data Output invalid from clock high tOH 2.5 –2.5 –2.5 –ns 2
Output enable low to output low Z tLZOE 0–0–0–ns 2,3,4
Output enable high to output high Z tHZOE –3.5 –4.0 –4.0 ns 2,3,4
Clock high to output high Z tHZC –3.5 –4.0 –4.0 ns 2,3,4
Clock high pulse width tCH 3.0 –4.0 –4.0 –ns 5
Clock low pulse width tCL 3.0 –4.0 –4.0 –ns 5
Address and Control setup to clock high tAS 2.0 –2.0 –2.0 –ns 6
Data setup to clock high tDS 2.0 –2.0 –2.0 –ns 6
Write setup to clock high tWS 2.0 –2.0 –2.0 –ns 6, 7
Chip select setup to clock high tCSS 2.0 –2.0 –2.0 –ns 6, 8
Address hold from clock high tAH 0.5 –0.5 –0.5 –ns 6
Data hold from clock high tDH 0.5 –0.5 –0.5 –ns 6
Write hold from clock high tWH 0.5 –0.5 –0.5 –ns 6, 7
Chip select hold from clock high tCSH 0.5 –0.5 –0.5 –ns 6, 8
Clock enable setup to clock high tCENS 2.0 –2.0 –2.0 –ns 6
Clock enable hold from clock high tCENH 0.5 –0.5 –0.5 –ns 6
ADV setup to clock high tADVS 2.0 –2.0 –2.0 –ns 6
ADV hold from clock high tADVH 0.5 –0.5 –0.5 –ns 6
Description Conditions Symbol Min Max Units
Current during Snooze Mode ZZ > VIH ISB2 30 mA
ZZ active to input ignored tPDS 2cycle
ZZ inactive to input sampled tPUS 2cycle
ZZ active to SNOOZE current tZZI 2cycle
ZZ inactive to exit SNOOZE current tRZZI 0
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Key to switching waveforms
Timing waveform of read cycle
Undefined
Falling inputRising input don’t care
tCH tCYC
tCL
tAS
CLK
CEN
R/W
tCENH
A1 A2 A3
Address
tAH
tCENS
tWS tWH
CE0,CE2
tADVS
tCSH
Dout
CE1
tADVH
tOE
tLZOE
tHZOE
Q(A1)
Q(A2Y‘10)
Q(A3)
OE
ADV/LD
Q(A2Y‘11)
Q(A3Y‘01)
Q(A2)
Q(A2Y‘01)
tCSS
Command READ
Q(A2)
BURST
READ
Q(A2Ý01)
BURST
READ
Q(A2Ý10)
BURST
READ
Q(A2Ý11)
STALL READ
Q(A3)
BURST
READ
Q(A3Ý01)
READ
Q(A1)
DSEL
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Timing waveform of write cycle
BURST
WRITE
D(A3Ý01)
tCH tCYC
tCL
tAS
CLK
CEN
R/W
tCENH
A1 A2 A3
Address
tAH
tCENS
CE0,CE2
tADVS
tCSH
Din
CE1
tADVH
tHZOE
D(A1) D(A2) D(A3)
tDS
OE
ADV/LD
tDH
Dout
BWn
Q(n-1)
D(A2Y‘01) D(A2Y‘10) D(A2Y‘11) D(A3Y‘01)
tCSS
Command WRITE
D(A2)
BURST
WRITE
D(A2Ý01)
STALL WRITE
D(A3)
WRITE
D(A1)
DSEL BURST
WRITE
D(A2Ý10)
BURST
WRITE
D(A2Ý11)
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Timing waveform of read/write cycle
Note: Ý = XOR when LBO = high/no connect. Ý = ADD when LBO = low.
tCH tCYC
tCL
tCENS
tOH tOE
CLK
CEN
CE0, CE2
ADV/LD
R/W
ADDRESS
D/Q
OE
Command
tHZOE
BWn
A2A1 A3 A5A4
A7
A6
D(A1) D(A5) Q(A6)
D(A2)
D(A2
Ý
01)
Q(A3) Q(A4)
Q(A4
Ý
01
)
tCENH
tDS tDH tLZC
tCD
tHZC
tLZOE
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4Ý01)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DSEL
tCSS
tADVH
tWS tWH
tWS tWH
CE1
WRITE
D(A1)
WRITE
D(A2)
tADVS
tCSH
tAS tAH
D(A7)
BURST
WRITE
D(A2Ý01)
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NOP, stall and deselect cycles
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. OE is low.
CLK
CEN
CE0, CE2
ADV/LD
R/W
Address
D/Q
Command
BWn
A1 A2
Q(A1) D(A2)
Q(A1
Ý
10)
BURST
Q(A1
Ý
01
)
STALL DSEL BURST
DSEL
WRITE
D(A2)
BURST
NOP
D(A2
Ý
01
)
WRITE
NOP
D(A3)
A3
READ
Q(A1)
BURST
Q(A1
Ý
10
)
BURST
D(A2Ý10)
CE1
Q(A1
Ý
01)
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Timing waveform of snooze mode
CLK
All inputs
ZZ
tZZI
Isupply
(except ZZ)
Dout
tPUS
ZZ recovery cycle
ISB2
tRZZI
ZZ setup cycle
Deselect or Read Only Deselect or Read Only
Normal
operation
Cycle
High-Z
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AC test conditions
Notes:
1) For test conditions, see “AC test conditions”, Figures A, B, C
2) This parameter measured with output load condition in Figure C.
3) This parameter is sampled, but not 100% tested.
4) tHZOE is less than tLZOE and tHZC is less than tLZC at any given temperature and voltage.
5) tCH measured high above VIH and tCL measured as low below VIL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to R/
W
and
BW[a,b]
.
8) Chip select refers to
CE0
,
CE1
, and
CE2
.
Z
0
= 50
Ω
D
OUT
50
Ω
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+3.0V
• Output load: For tLZC, tLZOE, tHZOE, and tHZC, see Figure C. For all others, see Figure B.
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (measured at 0.3V and 2.7V): 1.0V/ns. See Figure A.
• Input and output timing reference levels: 1.5V.
V
L
= 1.5V
for 3.3V I/O;
= V
DDQ
/2
for 2.5V I/O
Thevenin equivalent:
353
Ω
/1538
Ω
5 pF*
319
Ω
/1667
Ω
D
OUT
GND
Figure C: Output load(B)
*including scope
and jig capacitance
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
®
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Package dimensions
100-pin quad flat pack (TQFP)
TQFP
Min Max
A1 0.05 0.15
A2 1.35 1.45
b0.22 0.38
c0.09 0.20
D13.90 14.10
E19.90 20.10
e0.65 nominal
Hd 15.90 16.10
He 21.90 22.10
L0.45 0.75
L1 1.00 nominal
a0° 7°
Dimensions in
millimeters
He E
Hd
D
b
e
α
A1 A2
L1
L
c
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Ordering information
Note: Add suffix ‘N’ to the above part numbers for Lead Free Parts (Ex.
AS7C33128NTF18B-75TQCN)
Part numbering guide
1. Alliance Semiconductor SRAM prefix
2. Operating voltage: 33 = 3.3V
3. Organization:
128 = 128K
4. NTF = No Turn-Around Delay. Flow-through mode
5. Organization: 18 = x18
6. Production version: B = Product revision
7. Clock access time: [-75 = 7.5 ns; -80 = 8.0 ns; -10 = 10.0]
8. Package type: TQ = TQFP
9. Operating temperature: C = commercial (
0
°
C to 70
°
C); I = industrial (
-40
°
C to 85
°
C)
10. N = Lead free part
Package Width -75 –80 –10
TQFP x18 AS7C33128NTF18B-75TQC AS7C33128NTF18B-80TQC AS7C33128NTF18B-10TQC
TQFP x18 AS7C33128NTF18B-75TQI AS7C33128NTF18B-80TQI AS7C33128NTF18B-10TQI
AS7C 33 128 NTF 18 B –XX TQ C/I X
1
23
45678
910
®
AS7C33128NTF18B
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Revision History
Rev. No. History Revised Date
v 1.0 Initial version 4/28/05
®
AS7C33128NTF18B
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Part Number: AS7C33128NTF18B
Document Version: v 1.0
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