Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPS7A7200 SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 TPS7A7200 2-A, Fast-Transient, Low-Dropout Voltage Regulator 1 Features 3 Description * * * * * * * The TPS7A7200 low-dropout (LDO) voltage regulator is designed for applications seeking very-low dropout capability (180 mV at 2 A) with an input voltage from 1.5 V to 6.5 V. The TPS7A7200 offers an innovative, user-configurable, output-voltage setting from 0.9 V to 3.5 V, thus eliminating external resistors and any associated error. * * * Low-Dropout Voltage: 180 mV at 2 A VIN Range: 1.5 V to 6.5 V Configurable Fixed VOUT Range: 0.9 V to 3.5 V Adjustable VOUT Range: 0.9 V to 5 V Very Good Load- and Line-Transient Response Stable With Ceramic Output Capacitor 1.5% Accuracy Overline, Overload, and Overtemperature Programmable Soft Start Power Good (PG) Output 3-mm x 3-mm QFN-16 and 5-mm x 5-mm VQFN-20 Packages 2 Applications * * * * * * Wireless Infrastructure: SerDes, FPGA, DSPTM RF Components: VCO, ADC, DAC, LVDS Set-Top Boxes: Amplifier, ADC, DAC, FPGA, DSP Wireless LAN, Bluetooth(R) PCs and Printers Audio and Visual The TPS7A7200 has very fast load-transient response, is stable with ceramic output capacitors, and supports a better than 2% accuracy over line, load, and temperature. A soft-start pin allows for an application to reduce inrush into the load. Additionally, an open-drain, Power Good signal allows for sequencing power rails. The TPS7A7200 is available in 3-mm x 3-mm, 16-pin QFN and 5-mm x 5-mm, 20-pin VQFN packages. Device Information(1) PART NUMBER TPS7A7200 BODY SIZE (NOM) 3.00 mm x 3.00 mm VQFN (20) 5.00 mm x 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Load Transient Response With Seven Different Outputs 1.5 V IN PACKAGE QFN (16) PG CIN 6 TPS7A7200 OUT SNS FB Optional GND CFF 1.2 V = 0.5 Vref + 100 mV COUT + 200 mV + 400 mV Output Voltage (V) CSS Output Current Slew Rate: 1A/s 5 EN SS 3 5.5V to 5.0V Output Current 4 3.3V to 3.0V 3.0V to 2.5V 2.5V to 1.8V 2 1.8V to 1.5V 3 2 1 Output Current (A) 1 1 1.5V to 1.2V 50mV 0 100mV 1.6V 200mV 400mV 800mV 1.5V to 1.0V 0 Time (100s/div) G311 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS7A7200 SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configurations................................................. Specifications......................................................... 1 1 1 2 4 5 6.1 6.2 6.3 6.4 6.5 6.6 5 5 5 6 7 8 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 12 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 12 12 13 22 8 Application and Implementation ........................ 23 8.1 Application Information............................................ 23 8.2 Typical Application .................................................. 23 9 Power Supply Recommendations...................... 27 10 Layout................................................................... 27 10.1 10.2 10.3 10.4 10.5 Layout Guidelines ................................................. Layout Example .................................................... Thermal Considerations ........................................ Power Dissipation ................................................. Estimating Junction Temperature ........................ 27 27 28 28 29 11 Device And Documentation Support................. 31 11.1 11.2 11.3 11.4 11.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 31 31 31 31 31 12 Mechanical, Packaging, And Orderable Information ........................................................... 31 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (September 2013) to Revision F Page * Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1 * Changed name of section from Enable and Shutdown the Device to Enable ..................................................................... 21 Changes from Revision C (May 2012) to Revision D Page * Added CFF capacitor to front page block diagram .................................................................................................................. 1 * Added text to FB pin description ............................................................................................................................................ 4 * Added CFF test condition and table note to Electrical Characteristics.................................................................................... 7 * Deleted maximum value for Output Current Limit parameter in Electrical Characteristics table ........................................... 7 * Added CFF capacitor to Figure 24......................................................................................................................................... 13 * Added CFF capacitor to Figure 25......................................................................................................................................... 14 * Added CFF capacitor to Figure 26......................................................................................................................................... 15 * Added CFF capacitor to Figure 27......................................................................................................................................... 16 * Added CFF capacitor to Figure 28......................................................................................................................................... 17 * Added CFF capacitor to Figure 29......................................................................................................................................... 18 * Added CFF capacitor to Figure 30......................................................................................................................................... 20 * Changed capacitor values in first sentence of Output Capacitor Requirements section ..................................................... 24 2 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 TPS7A7200 www.ti.com SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 Changes from Revision B (April 2012) to Revision C Page * Added RGT package to Figure 44 ....................................................................................................................................... 28 * Added RGT package to Figure 46 ....................................................................................................................................... 30 Changes from Revision A (March 2012) to Revision B Page * Changed Accuracy feature bullet ........................................................................................................................................... 1 * Added RGT (QFN-16) package to Features .......................................................................................................................... 1 * Added RGT package pinout drawing...................................................................................................................................... 4 * Added RGT package to Pin Descriptions table ...................................................................................................................... 4 * Added RGT (QFN-16) package to Thermal Information table................................................................................................ 6 * Added test conditions for RGT package to Output Voltage Accuracy parameter .................................................................. 7 Changes from Original (March 2012) to Revision A * Page Changed from product preview to production data ................................................................................................................ 1 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 3 TPS7A7200 SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 www.ti.com 5 Pin Configurations OUT GND IN IN 18 17 16 IN 13 19 IN 14 OUT OUT 15 RGW Package 20-Pin VQFN With Exposed Thermal Pad Top View 20 OUT 16 RGT Package 16-Pin With Exposed Thermal Pad Top View SNS 1 12 EN OUT 1 15 IN FB 2 11 SS SNS 2 14 EN PG 3 10 1.6V FB 3 13 SS 50mV 4 9 800mV PG 4 12 NC 50mV 5 11 1.6V 7 8 9 10 GND 400mV 800mV 8 400mV 200mV 7 GND 6 6 200mV Thermal Pad 100mV 5 100mV Thermal Pad Pin Functions PIN NAME RGW 50mV, 100mV, 200mV, 400mV, 800mV, 1.6V RGT I/O DESCRIPTION 5, 6, 7, 9, 10, 11 4, 5, 6, 8, 9, 10 I Output voltage setting pins. These pins must be connected to ground or left floating. Connecting these pins to ground increases the output voltage by the value of the pin name; multiple pins can be simultaneously connected to GND to select the desired output voltage. Leave these pins floating (open) when not in use. See the User-Configurable Output Voltage section for more details. EN 14 12 I Enable pin. Driving this pin to logic high enables the device; driving the pin to logic low disables the device. See the Enable section for more details. FB 3 2 I Output voltage feedback pin. Connected to the error amplifier. See the User-Configurable Output Voltage and Traditional Adjustable Configuration sections for more details. TI highly recommends connecting a 220-pF ceramic capacitor from FB pin to OUT. 8, 18 7 -- IN 15, 16, 17 13, 14 I NC 12 -- -- Not internally connected. The NC pin is not connected to any electrical node. TI strongly recommends connecting this pin and the thermal pad to a large-area ground plane. See the Power Dissipation section for more details. 1, 19, 20 15, 16 O Regulated output pin. A 4.7-F or larger capacitance is required for stability. See Output Capacitor Requirements for more details. PG 4 3 O Active-high power good pin. An open-drain output that indicates when the output voltage reaches 90% of the target. See Power Good for more details. SNS 2 1 I Output voltage sense input pin. See the User-Configurable Output Voltage and Traditional Adjustable Configuration sections for more details. SS 13 11 -- Soft-start pin. Leaving this pin open provides soft start of the default setting. Connecting an external capacitor between this pin and the ground enables the soft-start function by forming an RC-delay circuit in combination with the integrated resistance on the silicon. See the Soft-Start section for more details. -- TI strongly recommends connecting the thermal pad to a large-area ground plane. If available, connect an electrically-floating, dedicated thermal plane to the thermal pad as well. GND OUT Thermal Pad 4 Ground pin. Unregulated supply voltage pin. TI recommends connecting an input capacitor to this pin. See Input Capacitor Requirements for more details. Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 TPS7A7200 www.ti.com SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 6 Specifications 6.1 Absolute Maximum Ratings Over operating junction temperature range (unless otherwise noted). (1) IN, PG, EN Voltage (2) 7 -0.3 50 mV, 100 mV, 200 mV, 400 mV, 800 mV, 1.6 V -0.3 UNIT V VIN + 0.3 (2) V VOUT + 0.3 (2) V Internally limited PG (sink current into IC) Temperature (1) MAX SS, FB, SNS, OUT OUT Current MIN -0.3 A 5 mA Operating virtual junction, TJ -55 160 C Storage, Tstg -55 150 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. The absolute maximum rating is VIN + 0.3 V or +7 V, whichever is smaller. 6.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT 2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) V 500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating junction temperature range (unless otherwise noted) MIN VIN Supply voltage 1.425 VOUT Output voltage VEN Enable voltage VPG Pullup voltage Any-out voltage IOUT Output current COUT Output capacitance CF Feedforward capacitance TJ Junction temperature (1) 50 mV, 100 mV, 200 mV, 400 mV, 800 mV, 1.6 V NOM MAX UNIT 6.5 V 0.9 5 V 0 6.5 V 0 6.5 V 0 VOUT V 0 2 A 4.7 200 (1) F 0 100 nF -40 125 C For output capacitors larger than 47 F, a feedforward capacitor of at least 220 pF must be used. Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 5 TPS7A7200 SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 www.ti.com 6.4 Thermal Information TPS7A7200 (3) THERMAL METRIC (1) (2) RGW (VQFN) RGT (QFN) 20 PINS 16 PINS UNIT RJA Junction-to-ambient thermal resistance 35.7 44.6 C/W RJC(top) Junction-to-case (top) thermal resistance 33.6 54.3 C/W RJB Junction-to-board thermal resistance 15.2 17.2 C/W JT Junction-to-top characterization parameter 0.4 1.1 C/W JB Junction-to-board characterization parameter 15.4 17.2 C/W RJC(bot) Junction-to-case (bottom) thermal resistance 3.8 3.8 C/W (1) (2) (3) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. For thermal estimates of this device based on printed-circuit-board (PCB) copper area, see the TI PCB Thermal Calculator. Thermal data for the RGW package is derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) i. RGW: The exposed pad is connected to the PCB ground layer through a 4 x 4 thermal via array. ii. RGT: The exposed pad is connected to the PCB ground layer through a 2 x 2 thermal via array. (b) i. RGW: Both the top and bottom copper layers have a dedicated pattern for 4% copper coverage. ii .RGT: Both the top and bottom copper layers have a dedicated pattern for 5% copper coverage. (c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3-inch x 3-inch copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature sections. Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 TPS7A7200 www.ti.com SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 6.5 Electrical Characteristics Over operating temperature range (TJ = -40C to 125C), 1.425 V VIN 6.5 V, VIN VOUT(TARGET) + 0.3 V or VIN VOUT(TARGET) + 0.5 V (1) (2), OUT connected to 50 to GND (3),VEN = 1.1 V, COUT = 10 F, CSS = 10 nF, CFF = 0 pF (RGW package), CFF = 220 pF (RGT package) (4), and PG pin pulled up to VIN with 100 k, 27 k R2 33 k for adjustable configuration (5), unless otherwise noted. Typical values are at TJ = 25C. PARAMETER VIN Input voltage range V(SS) SS pin voltage TEST CONDITIONS Output voltage accuracy (6) (7) Fixed with voltage setting pins 0.9 3.5 -1.5% 1.5% RGT package only, fixed, -40C TA 85C, 25 mA IOUT 2 A -2% 2% Adjustable, 25 mA IOUT 2 A -2% 2% Fixed, 25 mA IOUT 2 A -3% IOUT = 25 mA VO(IO) Load regulation 25 mA IOUT 2 A V(DO) Dropout voltage (8) Output current limit V 3% 0.01 %/V 0.1 %/A 180 mV 3.3 V < VOUT, IOUT = 2 A, V(FB) = GND 470 mV VOUT forced at 0.9 x VOUT(TARGET), VIN = 3.3 V, VOUT(TARGET) = 0.9 V 2.4 3.1 I(EN) EN pin current VIL(EN) EN pin low-level input voltage (disable device) VIH(EN) EN pin high-level input voltage (enable device) VIT(PG) PG pin threshold For the direction PG with decreasing VOUT Vhys(PG) PG pin hysteresis For PG VOL(PG) PG pin low-level output voltage VOUT < VIT(PG), IPG = -1 mA (current into device) Ilkg(PG) PG pin leakage current VOUT > VIT(PG), V(PG) = 6.5 V I(SS) SS pin charging current V(SS) = GND, VIN = 3.3 V Vn Output noise voltage BW = 100 Hz to 100 kHz, VIN = 1.5 V, VOUT = 1.2 V, IOUT = 2 A Tsd Thermal shutdown temperature TJ Operating junction temperature A 2.6 Minimum load, VIN = 6.5 V, VOUT(TARGET) = 0.9 V, IOUT = 25 mA mA 4 mA 5 A 0.1 A 0 0.5 V 1.1 6.5 V 0.96VOUT V Shutdown, PG = (open), VIN = 6.5 V, VOUT(TARGET) = 0.9 V, V(EN) < 0.5 V (8) V VOUT 3.3 V, IOUT = 2 A, V(FB) = GND Full load, IOUT = 2 A GND pin current UNIT V 5 Line regulation (3) (4) (5) (6) (7) 6.5 0.9 VO(VI) (1) (2) MAX Adjustable with external feedback resistors RGT package only, adjustable, -40C TA 85C, 25 mA IOUT 2 A VOUT I(GND) TYP 0.5 Output voltage range I(LIM) MIN 1.425 0.1 VIN = 6.5 V, V(EN) = 0 V and 6.5 V 0.85VOUT 0.9VOUT 0.02VOUT 3.5 5.1 V 0.4 V 1 A 7.2 A VRMS 40.65 Shutdown, temperature increasing 160 Reset, temperature decreasing 140 -40 C C 125 C When VOUT 3.5 V, VIN (VOUT + 0.3 V) or 1.425 V, whichever is greater; when VOUT > 3.5 V, VIN (VOUT + 0.5 V). VOUT(TARGET) is the calculated target VOUT value from the output voltage setting pins: 50mV, 100mV, 200mV, 400mV, 800mV, and 1.6V in fixed configuration, or the expected VOUT value set by external feedback resistors in adjustable configuration. This 50- load is disconnected when the test conditions specify an IOUT value. CFF is the capacitor between FB pin and OUT R2 is the bottom-side of the feedback resistor between the FB pin and OUT. See Figure 30 for details. When the TPS7A7200 is connected to external feedback resistors at the FB pin, external resistor tolerances are not included. The TPS7A7200 is not tested at VOUT = 0.9 V, 2.7 V VIN 6.5 V, and 500 mA IOUT 2 A because the power dissipation is higher than the maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the power dissipation limit of the package. V(DO) is not defined for output voltage settings less than 1.2 V. Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 7 TPS7A7200 SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 www.ti.com 6.6 Typical Characteristics At TJ = 25C, VIN = VOUT(TARGET) + 0.3 V, IOUT = 25 mA, V(EN) = VIN, CIN = 10 F, COUT = 10 F, C(SS) = 10 nF, and the PG pin pulled up to VIN with 100-k pullup resistor, unless otherwise noted. - 40C 0C 25C 85C 105C 125C Output Voltage (V) 0.918 0.909 5.15 Y-axis scale is 1%Vout/div Y-axis scale is 1%Vout/div 5.1 Output Voltage (V) 0.927 0.9 0.891 0.882 0.873 0.5 1 Output Current (A) 1.5 5 - 40C 0C 25C 85C 105C 125C 4.95 4.9 VIN = 1.425 V R1 = 24.1 k, R2 = 30.1 k 0 5.05 4.85 2 0 0.5 G001 Figure 1. Load Regulation (0.9 V, Adjustable) 3.605 - 40C 0C 25C 85C 105C 125C Y-axis scale is 1%Vout/div 3.57 Output Voltage (V) Output Voltage (V) 0.918 0.909 0.9 0.891 0.882 0.873 0 0.5 VIN = 1.425 V VOUT(TARGET) = 0.9 V 400mV pin to GND; 50mV, 100mV 200mV, 800mV, 1.6V pins open 1 Output Current (A) 1.5 200 0 0.5 1 Output Current (A) 1.5 2 1 Output Current (A) 1.5 2 G204 - 40C 0C 25C 85C 105C 125C 250 200 150 100 50 0 IOUT = 2 A FB = GND and plot VIN - VOUT 1 2 G011 Figure 5. Dropout Voltage vs Output Current 8 3.465 300 50 0.5 VIN = 3.8 V VOUT(TARGET) = 3.5 V 200mV, 400mV, 800mV, 1.6V pins to GND; 50mV, 100mV pins open Figure 4. Load Regulation (3.5 V, Fixed By Setting Pins) VIN = 1.5 V FB = GND 100 0 G004 Y-axis scale is 1%Vout/div 150 0 2 3.5 3.395 2 Dropout Voltage (mV) Dropout Voltage (mV) 250 3.535 G201 - 40C 0C 25C 85C 105C 125C 1.5 3.43 Figure 3. Load Regulation (0.9 V, Fixed By Setting Pins) 300 1 Output Current (A) Figure 2. Load Regulation (5.0 V, Adjustable) 0.927 - 40C 0C 25C 85C 105C 125C VIN = 5.3 V R1 = 271 k, R2 = 30.1 k 3 4 Input Voltage (V) 5 5.5 G014 Figure 6. Dropout Voltage vs Temperature Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 TPS7A7200 www.ti.com SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 Typical Characteristics (continued) At TJ = 25C, VIN = VOUT(TARGET) + 0.3 V, IOUT = 25 mA, V(EN) = VIN, CIN = 10 F, COUT = 10 F, C(SS) = 10 nF, and the PG pin pulled up to VIN with 100-k pullup resistor, unless otherwise noted. 0.927 0.909 Y-axis scale is 1%Vout/div Y-axis scale is 1%Vout/div 5.1 Output Voltage (V) 0.918 Output Voltage (V) 5.15 - 40C 0C 25C 85C 105C 125C 0.9 0.891 0.882 0.873 1.5 2 2.5 3 3.5 4 4.5 Input Voltage (V) 5 5.5 6 5 - 40C 0C 25C 85C 105C 125C 4.95 4.9 IOUT = 25 mA R1 = 24.1 k, R2 = 30.1 k 1 5.05 4.85 6.5 5 5.5 6 Input Voltage (V) G006 Figure 7. Line Regulation (0.9 V, Adjustable) 3.605 - 40C 0C 25C 85C 105C 125C Y-axis scale is 1%Vout/div 3.57 Output Voltage (V) Output Voltage (V) 0.918 0.909 0.9 0.891 0.882 0.873 1 1.5 2 IOUT = 25 mA VOUT(TARGET) = 0.9 V 400mV pin to GND; 50mV, 100mV 200mV, 800mV, 1.6V pins open 2.5 3 3.5 4 4.5 Input Voltage (V) 5 5.5 6 3.535 IOUT = 25 mA VOUT(TARGET) = 3.5 V 200mV, 400mV, 800mV, 1.6V pins to GND; 50mV, 100mV pins open 3.5 3.465 Y-axis scale is 1%Vout/div 3.395 6.5 5 5.5 6 Input Voltage (V) G206 6.5 G207 Figure 10. Line Regulation (3.5 V, Fixed By Setting Pins) 3.6 Error in Actual Output Voltage (%) 1 3.2 Actual Output Voltage (V) G007 3.43 Figure 9. Line Regulation (0.9 V, Fixed By Setting Pins) 2.8 2.4 2 1.6 1.2 0.8 0.8 6.5 Figure 8. Line Regulation (5 V, Adjustable) 0.927 - 40C 0C 25C 85C 105C 125C IOUT = 25 mA R1 = 271 k, R2 = 30.1 k VIN = 4 V IOUT = 50 mA 1.2 1.6 2 2.4 VOUT(TARGET) (V) 2.8 3.2 3.6 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 VIN = 4 V IOUT = 50 mA -0.8 -1 0.8 G020 Figure 11. Measured Output Voltage vs Pin-Setting 1.2 1.6 2 2.4 VOUT(TARGET) (V) 2.8 3.2 Product Folder Links: TPS7A7200 G021 Figure 12. Accuracy vs Pin-Setting Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated 3.6 9 TPS7A7200 SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 www.ti.com Typical Characteristics (continued) At TJ = 25C, VIN = VOUT(TARGET) + 0.3 V, IOUT = 25 mA, V(EN) = VIN, CIN = 10 F, COUT = 10 F, C(SS) = 10 nF, and the PG pin pulled up to VIN with 100-k pullup resistor, unless otherwise noted. 4 Ground Current (mA) 5 - 40C 0C 25C 85C 105C 125C 3 VIN = 1.8 V VOUT(TARGET) = 1.5 V 200mV, 800mV pins to GND 50mV, 100mV, 200mV, 400mV pins open 2 1 0 - 40C 0C 25C 85C 105C 125C 4 Ground Current (mA) 5 3 2 1 0 0.5 1 Output Current (A) 1.5 0 2 1 2.5 3 3.5 4 4.5 Input Voltage (V) 5 5.5 6 0 6.5 6.5 G033 0.5 VOUT(TARGET) = 1.2 V 100mV, 200mV, 400mV pins to GND 50mV, 800mV, 1.6V pins open 50- resistor between OUT and GND 1 1.5 2 2.5 Forced Output Voltage (V) 3 3.5 G041 Figure 16. Current Limit vs Output Voltage (Foldback) VIN = 1.5 V, - 40 C VIN = 1.5 V, 25 C VIN = 1.5 V, 125 C VIN = 6.5 V, - 40 C VIN = 1.5 V, 25 C VIN = 1.5 V, 125 C 0.8 PG Pin Voltage (V) Threshould Voltage (%VOUT) 0 1 VIN=1.5V VIN=6.5V 0.6 VOUT(TARGET) = 1.2 V 100mV, 200mV, 400mV pins to GND 50mV, 800mV, 1.6V pins open 50- resistor from OUT to GND Spec limit defined at 1-mA. 0.4 0.2 -25 0 25 50 Temperature (C) 75 100 125 0 0 0.5 1 1.5 Forced PG Pin Current (mA) G050 Figure 17. Power-Good Threshold Voltage vs Temperature 10 6 VIN = 4 V VOUT(TARGET) = 3.5 V 200mV, 400mV, 800mV, 1.6V pins to GND 50mV, 100mV pins open G032 Figure 15. GND Pin Current In Shutdown vs Temperature 96 95 94 93 92 91 90 89 88 87 86 85 84 -50 5.5 2 1 2 5 3 1 1.5 3 3.5 4 4.5 Input Voltage (V) EN = GND 50- resistor between OUT and GND 2 1 2.5 Figure 14. GND Pin Current vs Input Voltage Current Limit (A) Shutdown Ground Current (A) 3 2 4 - 40C 0C 25C 85C 105C 125C 4 1.5 G030 Figure 13. Gnd Pin Current vs Output Current 5 0 IOUT = 25 mA VOUT(TARGET) = 0.9 V 400mV pin to GND; 50mV, 100mV 200mV, 800mV, 1.6V pins open 2 G051 Figure 18. Power-Good Pin Drive Capability Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 TPS7A7200 www.ti.com SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 Typical Characteristics (continued) 10 VOUT(TARGET) = 0.9 V VOUT(TARGET) = 1.2 V VOUT(TARGET) = 3.3 V 1 VIN = VOUT(TARGET) + 0.3 V IOUT = 2 A 100 Hz to 100 kHz RMS Noise 0.9 V: 37.43 VRMS 1.2 V: 40.65 VRMS 3.3 V: 82.59 VRMS 10 100 1k Frequency (Hz) 10k 1 0.01 100k Figure 19. Noise Spectral Density By Output Voltage 100 1k Frequency (Hz) 10k Figure 20. Noise Spectral Density By External Capacitors VOUT(TARGET) = 3.3 V 400mV, 800mV, 1.6V pins to GND 50mV, 100mV, 200mV pins open Output Voltage (V) 80 70 60 50 40 30 VIN=3.6V, IOUT=0.1A VIN=3.6V, IOUT=2A VIN=3.8V, IOUT=0.1A VIN=3.8V, IOUT=2A 20 10 10 100 1k 8 Output Current Slew Rate: 1A/s VOUT(TARGET)=1.2V 100mV, 200mV, 400mV pins to GND 50mV, 800mV, 1.6V pins open 1.3 1.2 6 4 Output Voltage 1.1 2 Output Current 1 10k 100k Frequency (Hz) 1M 0 10M Time (100s/div) G314 G071 Figure 21. Power-Supply Ripple Rejection vs Frequency Figure 22. Load Transient Response (VOUT = 1.2 V) 3.5 Output Voltage (V) 100k G063 1.4 90 PSRR (dB) 10 G061 100 0 CSS = 100nF, COUT = 100F CSS = 100nF, COUT = 10F CSS = 10nF, COUT = 100F CSS = 10nF, COUT = 10F CSS = 1nF, COUT = 100F CSS = 1nF, COUT = 10F 0.1 8 Output Current Slew Rate: 1A/s VOUT(TARGET)=3.3V 400mV, 800mV, 1.6V pins to GND 50mV, 100mV, 200mV pins open 3.4 3.3 6 Output Current (A) 0.01 VIN = 1.8 V, IOUT = 1 A VOUT(TARGET) = 1.5 V 200mV, 800mV pins to GND 50mV, 100mV, 400mV, 1.6V pins open Output Current (A) 0.1 10 Output Spectral Noise Density (V/ Hz) Output Spectral Noise Density (V/ Hz) At TJ = 25C, VIN = VOUT(TARGET) + 0.3 V, IOUT = 25 mA, V(EN) = VIN, CIN = 10 F, COUT = 10 F, C(SS) = 10 nF, and the PG pin pulled up to VIN with 100-k pullup resistor, unless otherwise noted. 4 Output Voltage 3.2 2 Output Current 3.1 0 Time (100s/div) G317 Figure 23. Load Transient Response (VOUT = 3.3 V) Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 11 TPS7A7200 SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 www.ti.com 7 Detailed Description 7.1 Overview The TPS7A7200 belongs to a family of new-generation LDO regulators that uses innovative circuitry to offer very low dropout voltage along with the flexibility of a programmable output voltage. The dropout voltage for this LDO regulator family is 0.18 V at 2 A. This voltage is ideal for making the TPS7A7200 into a point-of-load (POL) regulator because 0.18 V at 2 A is lower than any voltage gap among the most common voltage rails: 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3 V, and 3.3 V. This device offers a fully user-configurable output voltage setting method. The TPS7A7200 output voltage can be programmed to any target value from 0.9 V to 3.5 V in 50-mV steps. Another big advantage of using the TPS7A7200 is the wide range of available operating input voltages: from 1.5 V to 6.5 V. The TPS7A7200 also has very good line and load transient response. All these features allow the TPS7A7200 to meet most voltage-regulator needs for under 6-V applications, using only one device so less time is spent on inventory control. Texas Instruments also offers different output current ratings with other family devices: the TPS7A7100 (1 A) and TPS7A7300 (3 A). 7.2 Functional Block Diagram Current Limit IN Charge Pump SS CSS UVLO 0.5-V Reference OUT Thermal Protection PG 700-s Delay 1.2-V Reference 70 k Optional 0.45 V 50 k 50 k SNS 3.2R FB Hysteresis EN 32R GND 50mV 16R 8R 4R 2R 100mV 200mV 400mV 800mV 1R 1.6V NOTE: 32R = 1.024 M (that is, 1R = 32 k). 12 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 TPS7A7200 www.ti.com SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 7.3 Feature Description 7.3.1 User-Configurable Output Voltage IN IN GND OUT OUT Unlike traditional LDO devices, the TPS7A7200 comes with only one orderable part number. There is no adjustable or fixed output voltage option. The output voltage of the TPS7A7200 is selectable in accordance with the names given to the output voltage setting pins: 50 mV, 100 mV, 200 mV, 400 mV, 800 mV, and 1.6 V. For each pin connected to the ground, the output voltage setting increases by the value associated with that pin name, starting from the value of the reference voltage of 0.5 V. Floating the pins has no effect on the output voltage. Figure 24 through Figure 29 show examples of how to program the output voltages. OUT IN SNS EN FB SS CFF NC PG Thermal Pad 1.6V Optional 800mV 400mV GND 200mV 100mV 50mV VIN FB OUT SNS 0.5 V 3.2R CFF FB 32R 16R 8R 4R 2R 1R 50mV 100mV 200mV 400mV 800mV 1.6V VOUT = 0.9 V = 0.5 V + 400 mV 0.5 V is Vref VOUT = 0.5 V (1 + 3.2R/4R) Figure 24. 0.9-V Configuration Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 13 TPS7A7200 SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 www.ti.com IN IN GND OUT OUT Feature Description (continued) OUT IN SNS EN FB SS CFF NC PG Thermal Pad 1.6V Optional 800mV 400mV GND 200mV 100mV 50mV VIN FB OUT SNS 0.5 V 3.2R CFF FB 32R 16R 8R 4R 2R 1R 50mV 100mV 200mV 400mV 800mV 1.6V VOUT = 1.2 V = 0.5 V + 100 mV + 200 mV + 400 mV 0.5 V is Vref VOUT = 0.5 V (1 + 3.2R/2.29R) 2.29R is parallel resistance of 16R, 8R, and 4R. Figure 25. 1.2-V Configuration 14 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 TPS7A7200 www.ti.com SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 IN IN GND OUT OUT Feature Description (continued) OUT IN SNS EN FB SS CFF NC PG Thermal Pad 1.6V Optional 800mV 400mV GND 200mV 100mV 50mV VIN FB OUT SNS 0.5 V 3.2R CFF FB 32R 16R 8R 4R 2R 1R 50mV 100mV 200mV 400mV 800mV 1.6V VOUT = 1.8 V = 0.5 V + 100 mV + 400 mV + 800 mV 0.5 V is Vref VOUT = 0.5 V (1 + 3.2R/1.23R) 1.23R is parallel resistance of 16R, 4R, and 2R. Figure 26. 1.8-V Configuration Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 15 TPS7A7200 SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 www.ti.com IN IN GND OUT OUT Feature Description (continued) OUT IN SNS EN FB SS CFF NC PG Thermal Pad 1.6V Optional 800mV 400mV GND 200mV 100mV 50mV VIN FB OUT SNS 0.5 V 3.2R CFF FB 32R 16R 8R 4R 2R 1R 50mV 100mV 200mV 400mV 800mV 1.6V VOUT = 2.5 V = 0.5 V + 400 mV + 1.6 V 0.5 V is Vref VOUT = 0.5 V (1 + 3.2R/0.8R) 0.8R is parallel resistance of 4R and 1R. Figure 27. 2.5-V Configuration 16 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 TPS7A7200 www.ti.com SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 IN IN GND OUT OUT Feature Description (continued) OUT IN SNS EN FB SS CFF NC PG Thermal Pad 1.6V Optional 800mV 400mV GND 200mV 100mV 50mV VIN FB OUT SNS 0.5 V 3.2R CFF FB 32R 16R 8R 4R 2R 1R 50mV 100mV 200mV 400mV 800mV 1.6V VOUT = 3.3 V = 0.5 V + 400 mV + 800 mV + 1.6 V 0.5 V is Vref VOUT = 0.5 V (1 + 3.2R/0.571R) 0.571R is parallel resistance of 4R, 2R, and 1R. Figure 28. 3.3-V Configuration Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 17 TPS7A7200 SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 www.ti.com IN IN GND OUT OUT Feature Description (continued) OUT IN SNS EN FB SS CFF NC PG Thermal Pad 1.6V Optional 800mV 400mV GND 200mV 100mV 50mV VIN FB OUT SNS 0.5 V 3.2R CFF FB 32R 16R 8R 4R 2R 1R 50mV 100mV 200mV 400mV 800mV 1.6V VOUT = 3.5 V = 0.5 V + 200 mV + 400 mV + 800 mV + 1.6 V 0.5 V is Vref VOUT = 0.5 V (1 + 3.2R/0.533R) 0.533R is parallel resistance of 8R, 4R, 2R, and 1R. Figure 29. 3.5-V Configuration See Table 1 for a full list of target output voltages and corresponding pin settings. The voltage setting pins have a binary weight; therefore, the output voltage can be programmed to any value from 0.9 V to 3.5 V in 50-mV steps. Figure 11 and Figure 12 show this output voltage programming performance. 18 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 TPS7A7200 www.ti.com SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 Feature Description (continued) SPACE NOTE Any output voltage setting that is not listed in Table 1 is not covered in Electrical Characteristics . For output voltages greater than 3.5 V, use a traditional adjustable configuration (see the Traditional Adjustable Configuration section). Table 1. User Configurable Output Voltage Setting VOUT(TARGET) (V) 50 mV 100 mV 200 mV 400 mV 800 mV 1.6 V VOUT(TARGET) (V) 50 mV 100 mV 200 mV 400 mV 800 mV 1.6 V 0.9 open open open GND open open 2.25 GND GND open open open GND 0.95 GND open open GND open open 2.3 open open GND open open GND 1 open GND open GND open open 2.35 GND open GND open open GND 1.05 GND GND open GND open open 2.4 open GND GND open open GND 1.1 open open GND GND open open 2.45 GND GND GND open open GND 1.15 GND open GND GND open open 2.5 open open open GND open GND 1.2 open GND GND GND open open 2.55 GND open open GND open GND 1.25 GND GND GND GND open open 2.6 open GND open GND open GND 1.3 open open open open GND open 2.65 GND GND open GND open GND 1.35 GND open open open GND open 2.7 open open GND GND open GND 1.4 open GND open open GND open 2.75 GND open GND GND open GND 1.45 GND GND open open GND open 2.8 open GND GND GND open GND 1.5 open open GND open GND open 2.85 GND GND GND GND open GND 1.55 GND open GND open GND open 2.9 open open open open GND GND 1.6 open GND GND open GND open 2.95 GND open open open GND GND 1.65 GND GND GND open GND open 3 open GND open open GND GND 1.7 open open open GND GND open 3.05 GND GND open open GND GND 1.75 GND open open GND GND open 3.1 open open GND open GND GND 1.8 open GND open GND GND open 3.15 GND open GND open GND GND 1.85 GND GND open GND GND open 3.2 open GND GND open GND GND 1.9 open open GND GND GND open 3.25 GND GND GND open GND GND 1.95 GND open GND GND GND open 3.3 open open open GND GND GND 2 open GND GND GND GND open 3.35 GND open open GND GND GND 2.05 GND GND GND GND GND open 3.4 open GND open GND GND GND 2.1 open open open open open GND 3.45 GND GND open GND GND GND 2.15 GND open open open open GND 3.5 open open GND GND GND GND 2.2 open GND open open open GND Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 19 TPS7A7200 SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 www.ti.com 7.3.2 Traditional Adjustable Configuration For any output voltage target that is not supported in the User-Configurable Output Voltage section, a traditional adjustable configuration with external-feedback resistors can be used with the TPS7A7200. Figure 30 shows how to configure the TPS7A7200 as an adjustable regulator with an equation and Table 2 lists recommended pairs of feedback resistor values. IN IN OUT GND OUT NOTE The bottom side of feedback resistor R2 in Figure 30 must be in the range of 27 k to 33 k to maintain the specified regulation accuracy. CFF OUT IN R1 SNS EN R2 FB SS NC PG Thermal Pad 1.6V Optional 800mV 400mV 200mV GND 100mV 50mV VIN FB OUT SNS 0.5 V 3.2R CFF FB 32R 16R 8R 4R 2R 1R 50mV 100mV 200mV 400mV 800mV 1.6V R1 R2 VOUT = (R1 + R2 ) R2 0.500 Figure 30. Traditional Adjustable Configuration With External Resistors Table 2. Recommended Feedback-Resistor Values 20 E96 SERIES R40 SERIES VOUT(TARGET) (V) R1 (k) R2 (k) R1 (k) R2 (k) 1 30.1 30.1 30 30 1.2 39.2 28 43.7 31.5 1.5 61.9 30.9 60 30 1.8 80.6 30.9 80 30.7 1.9 86.6 30.9 87.5 31.5 2.5 115 28.7 112 28 3 147 29.4 150 30 3.3 165 29.4 175 31.5 5 280 30.9 243 27.2 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 TPS7A7200 www.ti.com SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 7.3.3 Undervoltage Lockout (UVLO) The TPS7A7200 uses an undervoltage lockout circuit to keep the output shut off until the internal circuitry is operating properly. The UVLO circuit has a deglitch feature that typically ignores undershoot of the input voltage upon the event of device start-up. Still, a poor input line impedance may cause a severe input voltage drop when the device powers on. As explained in the Input Capacitor Requirements section, the input line impedance must be well-designed. 7.3.4 Soft-Start The TPS7A7200 has an SS pin that provides a soft-start (slow start) function. By leaving the SS pin open, the TPS7A7200 performs a soft-start by its default setting. As shown in Functional Block Diagram, by connecting a capacitor between the SS pin and the ground, the CSS capacitor forms an RC pair together with the integrated 50-k resistor. The RC pair operates as an RC-delay circuit for the soft-start together with the internal 700-s delay circuit. The relationship between CSS and the soft-start time is shown in Figure 40 through Figure 42. 7.3.5 Current Limit The TPS7A7200 internal current limit circuitry protects the regulator during fault conditions. During a current limit event, the output sources a fixed amount of current that is mostly independent of the output voltage. The current limit function is provided as a fail-safe mechanism and is not intended to be used regularly. Do not design any applications to use this current limit function as a part of expected normal operation. Extended periods of current limit operation degrade device reliability. Powering on the device with the enable pin, or increasing the input voltage above the minimum operating voltage while a low-impedance short exists on the output of the device, may result in a sequence of high-current pulses from the input to the output of the device. The energy consumed by the device is minimal during these events; therefore, there is no failure risk. Additional input capacitance helps to mitigate the load transient requirement of the upstream supply during these events. 7.3.6 Enable The EN pin switches the enable and disable (shutdown) states of the TPS7A7200. A logic high input at the EN pin enables the device; a logic low input disables the device. When disabled, the device current consumption is reduced. 7.3.7 Power Good The TPS7A7200 has a power good function that works with the PG output pin. When the output voltage undershoots the threshold voltage VIT(PG) during normal operation, the PG open-drain output turns from a highimpedance state to a low-impedance state. When the output voltage exceeds the VIT(PG) threshold by an amount greater than the PG hysteresis, Vhys(PG), the PG open-drain output turns from a low-impedance state to highimpedance state. By connecting a pullup resistor (usually between OUT and PG pins), any downstream device can receive an active-high enable logic signal. When setting the output voltage to less than 1.8 V and using a pullup resistor between OUT and PG pins, depending on the downstream device specifications, the downstream device may not accept the PG output as a valid high-level logic voltage. In such cases, place a pullup resistor between IN and PG pins, not between OUT and PG pins. Figure 18 shows the open-drain output drive capability. The on-resistance of the open-drain transistor is calculated using Figure 18, and is approximately 200 . Any pullup resistor greater than 10 k works fine for this purpose. Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 21 TPS7A7200 SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 www.ti.com 7.4 Device Functional Modes 7.4.1 Normal Operation The device regulates to the nominal output voltage under the following conditions: * The input voltage is at least as high as VIN(MIN). * The input voltage is greater than the nominal output voltage added to the dropout voltage. * The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased below the enable falling threshold. * The output current is less than the current limit. * The device junction temperature is less than the maximum specified junction temperature. 7.4.2 Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode of operation, the output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is significantly degraded because the pass device (such as a bipolar junction transistor, or BJT) is in saturation and no longer controls the current through the LDO. Line or load transients in dropout can result in large output voltage deviations. 7.4.3 Disabled The device is disabled under the following conditions: * The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising threshold. * The device junction temperature is greater than the thermal shutdown temperature. Table 3 lists the conditions that lead to the different modes of operation. Table 3. Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VEN IOUT TJ Normal mode VIN > VOUT(NOM) + VDO and VIN > VIN(MIN) VEN > VIH(EN) IOUT < I(LIM) TJ < 125C Dropout mode VIN < VOUT(NOM) + VDO VEN > VIH(EN) -- TJ < 125C -- VEN < VIL(EN) -- TJ > 160C Disabled mode (any true condition disables the device) 22 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 TPS7A7200 www.ti.com SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The is a very-low dropout LDO with very fast load transient response. The provides a number of features such as a power good signal for output monitoring, a soft-start pin to reduce inrush currents during start-up, and it is suitable for applications that require up to 3 A of output current. 8.2 Typical Application 1.5 V IN PG CIN TPS7A7200 EN OUT SS CSS SNS CFF 1.2 V = 0.5 Vref + 100 mV COUT + 200 mV + 400 mV FB Optional GND 50mV 100mV 1.6V 200mV 400mV 800mV Figure 31. 1.2-V Output Using ANY-OUT Pins 8.2.1 Design Requirements Table 4 lists the design parameters for this example. Table 4. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 1.425 V to 6.5 V Output voltage 1.2 V Output current rating 3A Output capacitor range 4.7 F to 200 F feedforward capacitor range 220 pF to 100 nF Soft-Start capacitor range 0 to 1 F Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 23 TPS7A7200 SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 www.ti.com 8.2.2 Detailed Design Procedure 8.2.2.1 ANY-OUT Programmable Output Voltage For ANY-OUT operation, the TPS7A7001 does not use any external resistors to set the output voltage, but uses device pins labeled 50 mV, 100 mV, 200 mV, 400 mV, 800 mV, and 1.6 V to set the regulated output voltage. Each pin is either connected to ground (active) or is left open (floating). The ANY-OUT programming is set as the sum of the internal reference voltage (V(SS) = 0.5 V) plus the sum of the respective voltages assigned to each active pin. By leaving all ANY-OUT pins open, or floating, the output is set to the minimum possible output voltage equal to V(SS). By grounding all of the ANY-OUT pins, the output is set to 3.65 V. When using the ANY-OUT pins, the SNS pin must always be connected between the OUT and FB pins. However, the feedforward capacitor must be connected to the FB pin, not the SNS pin. 8.2.2.2 Traditional Adjustable Output Voltage For applications that need the regulated output voltage to be greater than 3.65 V (or those that require more resolution than the 50 mV that the ANY-OUT pins provide), the can also be use the traditional adjustable method of setting the regulated output. When using the traditional method of setting the output, the FB pin must be connected to the node connecting the top and bottom resistors of the resistor divider. The SNS pin must be left floating. 8.2.2.3 Input Capacitor Requirements As a result of its very fast transient response and low-dropout operation support, it is necessary to reduce the line impedance at the input pin of the TPS7A7200. The line impedance depends heavily on various factors, such as wire (PCB trace) resistance, wire inductance, and output impedance of the upstream voltage supply (power supply to the TPS7A7200). Therefore, a specific value for the input capacitance cannot be recommended until the previously listed factors are finalized. In addition, simple usage of large input capacitance can form an unwanted LC resonance in combination with input wire inductance. For example, a 5-nH inductor and a 10-F input capacitor form an LC filter that has a resonance at 712 kHz. This value of 712 kHz is well inside the bandwidth of the TPS7A7200 control loop. The best guideline is to use a capacitor of up to 1 F with well-designed wire connections (PCB layout) to the upstream supply. If it is difficult to optimize the input line, use a large tantalum capacitor in combination with a good-quality, low-ESR, 1-F ceramic capacitor. 8.2.2.4 Output Capacitor Requirements The TPS7A7200 is designed to be stable with standard ceramic capacitors with capacitance values from 4.7 F to 47 F without a feedforward capacitor. For output capacitors from 47 F to 200 F a feedforward capacitor of at least 220 pF must be used. The TPS7A7200 is evaluated using an X5R-type, 10-F ceramic capacitor. TI highly recommends the X5R- and X7R-type capacitors because they have minimal variation in value and ESR over temperature. Maximum ESR must be less than 1 . As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude, but increases duration of the transient response. 24 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 TPS7A7200 www.ti.com SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 8.2.3 Application Curves 1.2 3 2 Output Voltage 1.1 1 4 Output Current Slew Rate: 1A/s VOUT(TARGET)=3.3V 400mV, 800mV, 1.6V pins to GND 50mV, 100mV, 200mV pins open 3.4 3.3 2 Output Voltage 3.2 1 Output Current Output Current 1 0 3.1 Time (100s/div) Time (100s/div) Voltage (V) VIN 4 Voltage (V) IOUT=1A, VOUT(TARGET)=3.3V 400mV, 800mV, 1.6V pins to GND 50mV, 100mV, 200mV pins open 3.8 3.6 VOUT 3.4 3.2 Time (20 s/div) 7 6.5 6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 G301 5 4.5 VIN 4 4 VIN 3.5 Voltage (V) 3.5 Voltage (V) VOUT Figure 35. Power Up and Power Down (IN = EN) 4.5 3 2.5 VOUT 2 0.5 VIN Time (2 ms/div) 5 1 VOUT(TARGET)=3.3V 400mV, 800mV, 1.6V pins to GND 50mV, 100mV, 200mV pins open 50- resistor between OUT and GND G300 Figure 34. Line Transient Response 1.5 G316 Figure 33. Load Transient Response (VOUT = 3.3 V) 4.6 4.2 0 G313 Figure 32. Load Transient Response (VOUT = 1.2 V) 4.4 3 Output Current (A) 1.3 3.5 Output Voltage (V) 4 Output Current Slew Rate: 1A/s VOUT(TARGET)=1.2V 100mV, 200mV, 400mV pins to GND 50mV, 800mV, 1.6V pins open Output Current (A) Output Voltage (V) 1.4 IN = EN 50- resistor from OUT to GND VOUT(TARGET) = 3.3 V 400mV, 800mV, 1.6V pins to GND 50mV, 100mV, 200mV pins open IN = EN 50- resistor from OUT to GND VOUT(TARGET) = 3.3 V 400mV, 800mV, 1.6V pins to GND 50mV, 100mV, 200mV pins open 3 2.5 2 VOUT 1.5 1 0.5 0 0 Time (1 ms/div) G302 Figure 36. Turnon Response (IN = EN) Time (1 ms/div) Figure 37. Turnoff Response (IN = EN) Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 G303 25 TPS7A7200 SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 www.ti.com 5 5 4.5 4.5 VOUT VIN 4 3.5 3 Voltage (V) Voltage (V) 3.5 VEN 2.5 2 1.5 0.5 3 2 50- resistor from OUT to GND VOUT(TARGET) = 3.3 V 400mV, 800mV, 1.6V pins to GND 50mV, 100mV, 200mV pins open 1 0 Time (1 ms/div) Time (1 ms/div) G304 Figure 38. EN Pulse On Response (Over Stable VIN) G305 Figure 39. EN Pulse Off Response (Over Stable VIN) 5 5 VOUT (CSS=0F) 4.5 VIN VOUT(TARGET) = 3.3 V 50- resistor from OUT to GND 4.5 4 VIN VOUT (CSS=0F) 3.5 Voltage (V) 3.5 Voltage (V) VEN 0.5 0 3 2.5 VOUT 2.5 1.5 50- resistor from OUT to GND VOUT(TARGET) = 3.3 V 400mV, 800mV, 1.6V pins to GND 50mV, 100mV, 200mV pins open 1 4 VIN 4 VEN VOUT (CSS=10nF) 2 VOUT (CSS=100nF) 1.5 3 2.5 VOUT (CSS=10nF) VEN VOUT (CSS=100nF) 2 1.5 1 VOUT (CSS=1F) 1 VOUT (CSS=1F) 0.5 VOUT(TARGET) = 3.3 V 50- resistor from OUT to GND 0.5 0 0 Time (5 ms/div) Time (50 ms/div) G306 Figure 40. Soft-Start Delay vs CSS (Enlarged View) G307 Figure 41. Soft-Start Delay vs CSS (Reduced View) Softstart Delay (ms) 1000 0%VOUT to 90%VOUT 50- resistor from OUT to GND VOUT(TARGET) = 3.3 V 400mV, 800mV, 1.6V pins to GND 50mV, 100mV, 200mV pins open 100 10 1 0.1 1 10 100 1000 CSS (nF) G308 Figure 42. Soft-Start Delay vs CSS 26 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 TPS7A7200 www.ti.com SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 9 Power Supply Recommendations This device is designed for operation from an input voltage supply ranging from 1.425 V to 6.5 V. This input supply must be well regulated. The family of fast-transient, low-dropout linear regulators achieve stability with a minimum output capacitance of 4.7 F; however, TI recommends using 10-F ceramic capacitors for both the input and output to maximize AC performance. 10 Layout 10.1 Layout Guidelines * * * * * * * To improve AC performance such as PSRR, output noise, and transient response, TI recommends designing the board with separate ground planes for IN and OUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor must connect directly to the GND pin of the device. Equivalent series inductance (ESL) and ESR must be minimized to maximize performance and ensure stability. Every capacitor must be placed as close as possible to the device and on the same side of the PCB as the regulator itself. Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use of vias and long traces is strongly discouraged because they may impact system performance negatively and even cause instability. If possible, and to ensure the maximum performance denoted in this product data sheet, use the same layout pattern used for the evaluation board, SLAU430. 10.2 Layout Example 100 mV 200 mV GND 400 mV 800 mV Ground 1.6 V 50 mV NC PG CSS Thermal Pad EN CIN FB R1 OUT OUT OUT IN GND SNS IN SS IN R2 Input Output COUT Notes: Cin and Cout are 0805 packages CSS, R1, and R2 are 0402 packages R1 and R2 only needed for adjustable operation Denotes a via to a connection made on another layer Figure 43. Recommended Layout Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 27 TPS7A7200 SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 www.ti.com 10.3 Thermal Considerations The thermal protection feature disables the output when the junction temperature rises to approximately 160C, allowing the device to cool. When the junction temperature cools to approximately 140C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal-protection circuit may cycle on and off. This thermal limit protects the device from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature must be limited to 125C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection must trigger at least 35C above the maximum expected ambient condition of your particular application. This configuration produces a worst-case junction temperature of 125C at the highest-expected ambient temperature and worstcase load. The internal-protection circuitry of the TPS7A7200 has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS7A7200 into thermal shutdown degrades device reliability. 10.4 Power Dissipation Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad is critical to avoiding thermal shutdown and ensuring reliable operation. Power dissipation of the device depends on input voltage and load conditions and can be calculated using Equation 1: PD VIN VOUT u IOUT (1) Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation. On the VQFN (RGW or RGT) package, the primary conduction path for heat is through the exposed pad to the PCB. The pad can be connected to ground or be left floating; however, it must be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be calculated using Equation 2: RqJA = +125C - TA PD (2) Knowing the maximum RJA, the minimum amount of PCB copper area needed for appropriate heatsinking can be estimated using Figure 44. 120 JA(RGW) JA(RGT) 100 JA (C/W) 80 60 40 20 0 0 1 2 3 4 5 6 7 Board Copper Area (inch2) 8 9 10 G800 Figure 44. JA vs Board Size 28 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 TPS7A7200 www.ti.com SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 Power Dissipation (continued) shows the variation of JA as a function of ground plane copper area in the board. It is intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and must not be used to estimate actual thermal performance in real application environments. NOTE When the device is mounted on an application PCB, TI strongly recommends using JT and JB, as explained in the Estimating Junction Temperature section. 10.5 Estimating Junction Temperature Using the thermal metrics JT and JB, as shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 3). For backwards compatibility, an older JC,Top parameter is listed as well. YJT: TJ = TT + YJT * PD YJB: TJ = TB + YJB * PD Where: PD is the power dissipation shown by Equation 2. TT is the temperature at the center-top of the IC package. TB is the PCB temperature measured 1 mm away from the IC package on the PCB surface (see Figure 45). (3) NOTE Both TT and TB can be measured on actual application boards using a thermo-gun (an infrared thermometer). For more information about measuring TT and TB, see the Application Report SBVA025, Using New Thermal Metrics. TT on top of IC TB on PCB 1mm (a) Example RGW (QFN) Package Measurement Figure 45. Measuring Points For TT And TB Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 29 TPS7A7200 SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 www.ti.com Estimating Junction Temperature (continued) By looking at Figure 46, the new thermal metrics (JT and JB) have very little dependency on board size. That is, using JT or JB with Equation 3 is a good way to estimate TJ by simply measuring TT or TB, regardless of the application board size. 25 JB(RGT) JT and JB (C/W) 20 15 JB(RGW) 10 5 0 JT(RGT) 0 1 2 JT(RGW) 3 4 5 6 7 Board Copper Area (inch2) 8 9 10 G801 Figure 46. JT And JB vs Board Size For a more detailed discussion of why TI does not recommend using JC(top) to determine thermal characteristics, see Application Report SBVA025, Using New Thermal Metrics. For further information, see Application Report SPRA953, Semiconductor and IC Package Thermal Metrics. 30 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 TPS7A7200 www.ti.com SBVS136F - MARCH 2012 - REVISED NOVEMBER 2015 11 Device And Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: * Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator, SBVA042. * Using New Thermal Metrics, SBVA025. * TPS7A7x00EVM-718 Evaluation Module, SLAU430. * Semiconductor and IC Package Thermal Metrics, SPRA953. 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks DSP, E2E are trademarks of Texas Instruments. Bluetooth is a registered trademark of Bluetooth SIG, Inc. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, And Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS7A7200 31 PACKAGE OPTION ADDENDUM www.ti.com 11-Aug-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPS7A7200RGTR ACTIVE VQFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PYMQ TPS7A7200RGTT ACTIVE VQFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PYMQ TPS7A7200RGWR ACTIVE VQFN RGW 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 SAC TPS7A7200RGWT ACTIVE VQFN RGW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 SAC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Aug-2017 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS7A7200 : * Enhanced Product: TPS7A7200-EP NOTE: Qualified Version Definitions: * Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPS7A7200RGTR VQFN RGT 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS7A7200RGTT VQFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS7A7200RGWR VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2 TPS7A7200RGWT VQFN RGW 20 250 180.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS7A7200RGTR VQFN RGT 16 3000 367.0 367.0 35.0 TPS7A7200RGTT VQFN RGT 16 250 210.0 185.0 35.0 TPS7A7200RGWR VQFN RGW 20 3000 367.0 367.0 35.0 TPS7A7200RGWT VQFN RGW 20 250 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE RGT0016C VQFN - 1 mm max height SCALE 3.600 PLASTIC QUAD FLATPACK - NO LEAD 3.1 2.9 A B PIN 1 INDEX AREA 3.1 2.9 C 1 MAX SEATING PLANE 0.05 0.00 0.08 1.68 0.07 (0.2) TYP 5 12X 0.5 8 EXPOSED THERMAL PAD 4 9 4X 1.5 SYMM 1 12 16X PIN 1 ID (OPTIONAL) 13 16 0.1 0.05 SYMM 16X 0.30 0.18 C A B 0.5 0.3 4222419/B 11/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT RGT0016C VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 1.68) SYMM 13 16 16X (0.6) 1 12 16X (0.24) SYMM (0.58) TYP 12X (0.5) (2.8) 9 4 ( 0.2) TYP VIA 5 (R0.05) ALL PAD CORNERS 8 (0.58) TYP (2.8) LAND PATTERN EXAMPLE SCALE:20X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4222419/B 11/2016 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN RGT0016C VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 1.55) 16 13 16X (0.6) 1 12 16X (0.24) 17 SYMM (2.8) 12X (0.5) 9 4 METAL ALL AROUND 5 SYMM 8 (R0.05) TYP (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 17: 85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:25X 4222419/B 11/2016 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. 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