© Semiconductor Components Industries, LLC, 2017
June, 2018 − Rev. 18
1Publication Order Number:
NCS333/D
NCS333A, NCV333A,
NCS2333, NCV2333,
NCS4333, NCV4333,
NCS333
10 mV Offset, 0.07 mV/5C,
Zero-Drift Operational
Amplifier
The NCS333/2333/4333 family of zero−drift op amps feature offset
voltage as low as 10 mV over the 1.8 V to 5.5 V supply voltage range.
The zero−drift architecture reduces the offset drift to as low as
0.07 mV/°C and enables high precision measurements over both time
and temperature. This family has low power consumption over a wide
dynamic range and is available in space saving packages. These
features make it well suited for signal conditioning circuits in portable,
industrial, automotive, medical and consumer markets.
Features
•Gain−Bandwidth Product:
♦270 kHz (NCx2333)
♦350 kHz (NCx333, NCx333A, NCx4333)
•Low Supply Current: 17 mA (typ at 3.3 V)
•Low Offset Voltage:
♦10 mV max for NCS333, NCS333A
♦30 mV max for NCV333A, NCx2333 and NCx4333
•Low Offset Drift: 0.07 mV/°C max for NCS333/A
•Wide Supply Range: 1.8 V to 5.5 V
•Wide Temperature Range: −40°C to +125°C
•Rail−to−Rail Input and Output
•Available in Single, Dual and Quad Packages
•NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
Applications
•Automotive
•Battery Powered/ Portable Application
•Sensor Signal Conditioning
•Low Voltage Current Sensing
•Filter Circuits
•Bridge Circuits
•Medical Instrumentation
SOT23−5
SN SUFFIX
CASE 483
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1
5
SC70−5
SQ SUFFIX
CASE 419A
1
5
UDFN8
MU SUFFIX
CASE 517AW
MSOP−8
DM SUFFIX
CASE 846A−02
SOIC−8
D SUFFIX
CASE 751
SOIC−14
D SUFFIX
CASE 751A
See detailed ordering and shipping information on page 3 of
this data sheet.
ORDERING INFORMATION
See general marking information in the device marking
section on page 2 of this data sheet.
DEVICE MARKING INFORMATION
1
14
1
8
1
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
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2
DEVICE MARKING INFORMATION
SOIC−14
CASE 751A
Quad Channel Configuration
NCS4333, NCV4333
NCS4333G
AWLYWW
1
14
X = Specific Device Code
= E = NCS333 (SOT23−5)
= H = NCS333 (SC70−5)
= G = NCS333A (SOT23−5)
= K = NCS333A (SC70−5)
= M = NCV333A (SOT23−5)
= N = NCV333A (SC70−5)
A = Assembly Location
Y = Year
W = Work Week
M = Date Code
G or G= Pb−Free Package
UDFN8, 2x2, 0.5P
CASE 517AW
Micro8/MSOP8
CASE 846A−02
SOIC−8
CASE 751
N2333
ALYW
G
1
8
Dual Channel Configuration
NCS2333, NCV2333
TSOP−5/SOT23−5
CASE 483
SC70−5
CASE 419A
Single Channel Configuration
NCS333, NCS333A, NCV333A
33XMG
G
33XAYWG
G
(Note: Microdot may be in either location)
2333
AYWG
G
1
8
33A
YM
1
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
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3
PIN CONNECTIONS
Single Channel Configuration
NCS333, NCS333A, NCV333A
1
2
34
5
OUT
VSS
IN+ IN−
VDD 1
2
34
5
IN+
VSS
IN−OUT
VDD
SOT23−5 / TSOP−5SC70−5 / SC−88−5 / SOT−353−5
Dual Channel Configuration
NCS2333, NCV2333
Quad Channel Configuration
NCS4333, NCV4333
1
4
3
2
14
11
12
13
OUT 1
IN− 1
IN+ 1
VDD
OUT 4
IN− 4
IN+ 4
VSS
7
6
5
8
9
10
IN+ 2
IN− 2
OUT 2
IN+ 3
IN− 3
OUT 3
+
−
+
−
−
++
−
1
4
3
2
8
5
6
7
OUT 1
IN− 1
IN+ 1
VSS
VDD
OUT 2
IN− 2
IN+ 2
+
+−
−
UDFN8* / Micro8 / SOIC−8
SOIC−14
*The exposed pad of the UDFN8 package
can be floated or connected to VSS.
ORDERING INFORMATION
Configuration Automotive Device Package Shipping †
Single No NCS333SN2T1G SOT23−5 / TSOP−53000 / Tape & Reel
NCS333ASN2T1G 3000 / Tape & Reel
NCS333SQ3T2G SC70−5 / SC−88−5 / SOT−353−53000 / Tape & Reel
NCS333ASQ3T2G 3000 / Tape & Reel
Yes NCV333ASQ3T2G 3000 / Tape & Reel
NCV333ASN2T1G SOT23−5 / TSOP−53000 / Tape & Reel
Dual No NCS2333MUTBG UDFN8 3000 / Tape & Reel
NCS2333DR2G SOIC−83000 / Tape & Reel
NCS2333DMR2G MICRO−84000 / Tape & Reel
Yes NCV2333DR2G SOIC−83000 / Tape & Reel
NCV2333DMR2G MICRO−84000 / Tape & Reel
Quad No NCS4333DR2G SOIC−14 2500 / Tape & Reel
Yes NCV4333DR2G SOIC−14 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
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4
ABSOLUTE MAXIMUM RATINGS
Over operating free−air temperature, unless otherwise stated.
Parameter Rating Unit
Supply Voltage 7 V
INPUT AND OUTPUT PINS
Input Voltage (Note 1) (VSS) − 0.3 to (VDD) + 0.3 V
Input Current (Note 1) ±10 mA
Output Short Circuit Current (Note 2) Continuous
TEMPERATURE
Operating Temperature Range −40 to +125 °C
Storage Temperature Range −65 to +150 °C
Junction Temperature +150 °C
ESD RATINGS (Note 3)
Human Body Model (HBM) ±4000 V
Machine Model (MM) ±200 V
Charged Device Model (CDM) ±2000 V
OTHER RATINGS
Latch−up Current (Note 4) 100 mA
MSL Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Input terminals are diode−clamped to the power−supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should
be current limited to 10 mA or less
2. Short−circuit to ground.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JEDEC standard JS−001 (AEC−Q100−002)
ESD Machine Model tested per JEDEC standard JESD22−A115 (AEC−Q100−003)
ESD Charged Device Model tested per JEDEC standard JESD22−C101 (AEC−Q100−011)
4. Latch−up Current tested per JEDEC standard: JESD78.
THERMAL INFORMATION (Note 5)
Parameter Symbol Package Value Unit
Thermal Resistance,
Junction to Ambient
qJA SOT23−5 / TSOP5 290 °C/W
SC70−5 / SC−88−5 / SOT−353−5 425
Micro8 / MSOP8 298
SOIC−8 250
UDFN8 228
SOIC−14 216
5. As mounted on an 80x80x1.5 mm FR4 PCB with 650 mm2 and 2 oz (0.07 mm) thick copper heat spreader. Following JEDEC JESD/EIA 51.1,
51.2, 51.3 test guidelines
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Range Unit
Supply Voltage (VDD − VSS) VS1.8 to 5.5 V
Specified Operating Temperature Range NCS333 TA −40 to 105 °C
NCx333A, NCx2333, NCx4333 −40 to 125
Input Common Mode Voltage Range VICMR VSS−0.1 to VDD+0.1 V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
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5
ELECTRICAL CHARACTERISTICS: VS = 1.8 V to 5.5 V
At TA = +25°C, RL = 10 kW connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
Boldface limits apply over the specified operating temperature range, guaranteed by characterization and/or design.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS VS = +5 V NCS333, NCS333A 3.5 10 mV
NCV333A,
NCx2333, NCx4333
6.0 30
Offset Voltage Drift vs Temp DVOS/DTNCS333, NCS333A 0.03 0.07 mV/°C
NCV333A, VS = 5 V 0.03 0.14
NCx2333, VS = 5 V 0.04 0.07
NCx4333, VS = 5 V 0.095 0.19
Offset Voltage Drift vs Supply DVOS/DVSNCS333, NCS333A Full temperature range 0.32 5 mV/V
NCV333A TA = +25°C 0.40 5
Full temperature range 8
NCx2333, NCx4333 TA = +25°C 0.32 5
Full temperature range 12.6
Input Bias Current
(Note 6)
IIB TA = +25°CNCS333, NCx333A ±60 ±200 pA
NCx2333, NCx4333 ±60 ±400
Full temperature range +400
Input Offset Current
(Note 6)
IOS TA = +25°CNCS333, NCx333A ±50 ±400 pA
NCx2333, NCx4333 ±50 ±800
Common Mode Rejection Ratio
(Note 7)
CMRR VS = 1.8 V 111 dB
VS = 3.3 V 118
VS = 5.0 V NCS333, NCS333A,
NCx2333, NCx4333
106 123
NCV333A 103 123
VS = 5.5 V 127
Input Resistance RIN Differential 180 GW
Common Mode 90
Input Capacitance CIN NCS333 Differential 2.3 pF
Common Mode 4.6
NCx2333, NCx4333,
NCx333A
Differential 4.1
Common Mode 7.9
OUTPUT CHARACTERISTICS
Open Loop Voltage Gain
(Note 6)
AVOL VSS + 100 mV < VO < VDD − 100 mV 106 145 dB
Open Loop Output Impedance Zout−OL f = UGBW, IO = 0 mA 300 W
Output Voltage High,
Referenced to VDD
VOH TA = +25°C 10 50 mV
Full temperature range 70
Output Voltage Low,
Referenced to VSS
VOL TA = +25°C 10 50 mV
Full temperature range 70
6. Guaranteed by characterization and/or design
7. Specified over the full common mode range: VSS − 0.1 < VCM < VDD + 0.1
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
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6
ELECTRICAL CHARACTERISTICS: VS = 1.8 V to 5.5 V
At TA = +25°C, RL = 10 kW connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
Boldface limits apply over the specified operating temperature range, guaranteed by characterization and/or design.
Parameter UnitMaxTypMinConditionsSymbol
OUTPUT CHARACTERISTICS
Output Current Capability IOSinking Current NCS333 25 mA
NCx333A,
NCx2333, NCx4333
11
Sourcing Current 5.0
Capacitive Load Drive CLSee Figure 13
NOISE PERFORMANCE
Voltage Noise Density eNfIN = 1 kHz 62 nV / √Hz
Voltage Noise eP−PfIN = 0.1 Hz to 10 Hz 1.1 mVPP
fIN = 0.01 Hz to 1 Hz 0.5
Current Noise Density iNfIN = 10 Hz 350 fA / √Hz
Channel Separation NCx2333, NCx4333 135 dB
DYNAMIC PERFORMANCE
Gain Bandwidth Product GBWP CL = 100 pF NCS333, NCx333A,
NCx4333
350 kHz
NCx2333 270
Gain Margin AMCL = 100 pF 18 dB
Phase Margin fMCL = 100 pF 55 °
Slew Rate SR G = +1 0.15 V/ms
POWER SUPPLY
Power Supply Rejection Ratio PSRR NCS333, NCS333A Full temperature
range
106 130 dB
NCx2333, NCx4333,
NCV333A
TA = +25°C 106 130
Full temperature range 98
Turn−on Time tON VS = 5 V 100 ms
Quiescent Current
(Note 8)
IQNCS333, NCS333A,
NCx2333, NCx4333
1.8 V ≤ VS ≤ 3.3 V 17 25 mA
27
3.3 V < VS ≤ 5.5 V 21 33
35
NCV333A 1.8 V ≤ VS ≤ 3.3 V 20 30
35
3.3 V < VS ≤ 5.5 V 28 40
45
8. No load, per channel
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
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7
TYPICAL CHARACTERISTICS
Figure 1. Open Loop Gain and Phase Margin
vs. Frequency
Figure 2. CMRR vs. Frequency
FREQUENCY (Hz) FREQUENCY (Hz)
−20
0
20
60
80
120
1M100k10k1k10010
0
10
30
50
70
80
100
120
Figure 3. PSRR vs. Frequency Figure 4. Output Voltage Swing vs. Output
Current
FREQUENCY (Hz) OUTPUT CURRENT (mA)
100k10k1k10010
0
20
40
60
80
100
120
97654210
−3
−2
−1
0
1
2
3
GAIN (dB)
CMRR (dB)
PSRR (dB)
OUTPUT SWING (V)
20
40
60
90
110
TA = 25°C
TA = 25°C
+PSRR
−PSRR
3810
TA = 25°C
VS = 5.5 V, VOH
VS = 1.8 V, VOH
VS = 1.8 V, VOL
VS = 5.5 V, VOL
−40
40
100
Gain
Phase Margin
1M100k10k1k10010
CL = 100 pF
RL = 10 kW
TA = 25°C
1M
15
30
45
75
90
120
0
60
105
PHASE MARGIN (°)
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
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8
TYPICAL CHARACTERISTICS
Figure 5. Input Bias Current vs. Common
Mode Voltage
Figure 6. Input Bias Current vs. Temperature
COMMON MODE VOLTAGE (V) TEMPERATURE (°C)
1.81.41.20.80.40.2−0.2
−200
−150
−100
−50
0
50
150
200
100806040200−20−40
−200
−150
−100
−50
50
100
150
200
Figure 7. Quiescent Current vs. Temperature Figure 8. Large Signal Step Response
TEMPERATURE (°C) TIME (ms)
100806040200−20−40
0
5
10
15
20
25
30
4003002001000−100
−4
−3
−2
−1
0
2
3
4
Figure 9. Small Signal Step Response Figure 10. Positive Overvoltage Recovery
TIME (ms) TIME (50 ms/div)
3020100−10
−0.15
−0.10
−0.05
0
0.05
0.10
0.15
0.20
−3.0
−2.5
−2.0
−1.5
−1.0
−0.5
0.5
1.0
INPUT BIAS CURRENT (pA)
INPUT BIAS CURRENT (pA)
IQ (mA)
INPUT (V)
INPUT AND OUTPUT (V)
INPUT (V)
VS = 1.8 V
VS = 3.3 V
VS = 5.0 V
VS = 5.5 V
1
Input
Output
VS = 5.0 V
AV = +1
RL = 10 kW
−3
−2
−1
0
2
3
4
1
5
OUTPUT (V)
Input
Output
VS = 5.0 V
AV = −1
RL = 10 kW
0
VS = 5.0 V
AV = −10
RL = 10 kW
Input
Output
−1.0
−0.5
0
0.5
1.5
2.0
2.5
1.0
3.0
OUTPUT (V)
0 0.6 1.0 1.6 2.0
100
TA = 25°C
VS = 1.8 V
IIB+
IIB−
TA = 25°C
VS = 5 V
IIB+
IIB−
0
Per Channel
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
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9
TYPICAL CHARACTERISTICS
Figure 11. Negative Overvoltage Recovery Figure 12. Setting Time to 0.1% vs.
Closed−Loop Gain
TIME (50 ms/div) GAIN (V/V)
−1.0
−0.5
0
0.5
1.0
2.0
2.5
3.0
100101
0
100
200
300
400
500
Figure 13. Small−Signal Overshoot vs. Load
Capacitance
Figure 14. 0.1 Hz to 10 Hz Noise
LOAD CAPACITANCE (pF) TIME (s)
100010010
0
10
20
30
40
50
60
87654210
−2000
−1500
−1000
−500
0
1000
1500
2000
Figure 15. Voltage Noise Density vs.
Frequency
Figure 16. Current Noise Density vs.
Frequency
FREQUENCY (Hz) FREQUENCY (Hz)
10,0001000100101
10
100
1000
10,0001000100101
10
100
1000
INPUT (V)
SETTLING TIME (ms)
OVERSHOOT (%)
VOLTAGE (nV)
VOLTAGE NOISE DENSITY (nV/√Hz)
CURRENT NOISE DENSITY (fA/√Hz)
VS = 5.0 V
AV = −10
RL = 10 kW
Input
Output
TA = 25°C
5
15
25
35
45
55
65
3910
500
VCM = VS/2
RL = 10 kW
TA = 25°C
TA = 25°CTA = 25°C
1.5
−3.0
−2.5
−2.0
−1.5
−0.5
0
0.5
−1.0
1.0
OUTPUT (V)
TA = 25°C
RL = 10 kW
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
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10
APPLICATIONS INFORMATION
OVERVIEW
The NCS333, NCS333A, NCS2333, and NCS4333
precision op amps provide low offset voltage and zero drift
over temperature. The input common mode voltage range
extends 100 mV beyond the supply rails to allow for sensing
near ground or VDD. These features make the NCS333
series well−suited for applications where precision is
required, such as current sensing and interfacing with
sensors.
NCS333 series of precision op amps uses a
chopper−stabilized architecture, which provides the
advantage of minimizing offset voltage drift over
temperature and time. The simplified block diagram is
shown in Figure 17. Unlike the classical chopper
architecture, the chopper stabilized architecture has two
signal paths.
+
−
−
+
+
−+
−
IN+
IN−
O
RC notch filterChopper
Chopper
Main amp
Figure 17. Simplified NCS333 Block Diagram
RC notch filter
In Figure 17, the lower signal path is where the chopper
samples the input offset voltage, which is then used to
correct the offset at the output. The offset correction occurs
at a frequency of 125 kHz. The chopper−stabilized
architecture is optimized for best performance at
frequencies up to the related Nyquist frequency (1/2 of the
offset correction frequency). As the signal frequency
exceeds the Nyquist frequency, 62.5 kHz, aliasing may
occur at the output. This is an inherent limitation of all
chopper and chopper−stabilized architectures.
Nevertheless, the NCS333 op amps have minimal aliasing
up to 125 kHz and low aliasing up to 190 kHz when
compared to competitor parts from other manufacturers.
ON Semiconductor’s patented approach utilizes two
cascaded, symmetrical, RC notch filters tuned to the
chopper frequency and its fifth harmonic to reduce aliasing
effects.
The chopper−stabilized architecture also benefits from
the feed−forward path, which is shown as the upper signal
path of the block diagram in Figure 17. This is the high speed
signal path that extends the gain bandwidth up to 350 kHz.
Not only does this help retain high frequency components of
the input signal, but it also improves the loop gain at low
frequencies. This is especially useful for low−side current
sensing and sensor interface applications where the signal is
low frequency and the differential voltage is relatively
small.
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
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11
APPLICATION CIRCUITS
Low−Side Current Sensing
Low−side current sensing is used to monitor the current
through a load. This method can be used to detect
over−current conditions and is often used in feedback
control, as shown in Figure 18. A sense resistor is placed in
series with the load to ground. Typically, the value of the
sense resistor is less than 100 mW to reduce power loss
across the resistor. The op amp amplifies the voltage drop
across the sense resistor with a gain set by external resistors
R1, R2, R3, and R4 (where R1 = R2, R3 = R4). Precision
resistors are required for high accuracy, and the gain is set
to utilize the full scale of the ADC for the highest resolution.
+
−
Load
VDD
ADC
Microcontroller
control
RSENSE
R1
R2
R3
R4
VDD
VDD
VLOAD
Figure 18. Low−Side Current Sensing
Differential Amplifier for Bridged Circuits
Sensors to measure strain, pressure, and temperature are
often configured in a Wheatstone bridge circuit as shown in
Figure 19. In the measurement, the voltage change that is
produced is relatively small and needs to be amplified before
going into an ADC. Precision amplifiers are recommended
in these types of applications due to their high gain, low
noise, and low offset voltage.
Figure 19. Bridge Circuit Amplification
+
−
VDD
VDD
EMI Susceptibility and Input Filtering
Op amps have varying amounts of EMI susceptibility.
Semiconductor junctions can pick up and rectify EMI
signals, creating an EMI−induced voltage offset at the
output, adding another component to the total error. Input
pins are the most sensitive to EMI. The NCS333 op amp
family integrates low−pass filters to decrease sensitivity to
EMI.
General Layout Guidelines
To ensure optimum device performance, it is important to
follow good PCB design practices. Place 0.1 mF decoupling
capacitors as close as possible to the supply pins. Keep traces
short, utilize a ground plane, choose surface−mount
components, and place components as close as possible to
the device pins. These techniques will reduce susceptibility
to electromagnetic interference (EMI). Thermoelectric
effects can create an additional temperature dependent
offset voltage at the input pins. To reduce these effects, use
metals with low thermoelectric−coefficients and prevent
temperature gradients from heat sources or cooling fans.
NCS333A, NCV333A, NCS2333, NCV2333, NCS4333, NCV4333, NCS333
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12
UDFN8 Package Guidelines
The UDFN8 package has an exposed leadframe die pad on
the underside of the package. This pad should be soldered to
the PCB, as shown in the recommended soldering footprint
in the Package Dimensions section of this datasheet. The
center pad can be electrically connected to VSS or it may be
left floating. When connected to VSS, the center pad acts as
a heat sink, improving the thermal resistance of the part.
1
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
DIM
A
MIN MAX MIN MAX
MILLIMETERS
1.80 2.200.071 0.087
INCHES
B1.15 1.350.045 0.053
C0.80 1.100.031 0.043
D0.10 0.300.004 0.012
G0.65 BSC0.026 BSC
H--- 0.10---0.004
J0.10 0.250.004 0.010
K0.10 0.300.004 0.012
N0.20 REF0.008 REF
S2.00 2.200.079 0.087
STYLE 1:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 2:
PIN 1. ANODE
2. EMITTER
3. BASE
4. COLLECTOR
5. CATHODE
B0.2 (0.008) MM
12 3
45
A
G
S
D 5 PL
H
C
N
J
K
−B−
STYLE 3:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. CATHODE 1
STYLE 4:
PIN 1. SOURCE 1
2. DRAIN 1/2
3. SOURCE 1
4. GATE 1
5. GATE 2
STYLE 5:
PIN 1. CATHODE
2. COMMON ANODE
3. CATHODE 2
4. CATHODE 3
5. CATHODE 4
STYLE 7:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 6:
PIN 1. EMITTER 2
2. BASE 2
3. EMITTER 1
4. COLLECTOR
5. COLLECTOR 2/BASE 1
XXXMG
G
XXX = Specific Device Code
M = Date Code
G= Pb−Free Package
GENERIC MARKING
DIAGRAM*
STYLE 8:
PIN 1. CATHODE
2. COLLECTOR
3. N/C
4. BASE
5. EMITTER
STYLE 9:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. ANODE
5. ANODE
*This infomration is generic. Please refer
to device data sheet for actual part
marking.
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE L
DATE 17 JAN 2013
SCALE 2:1
(Note: Microdot may be in either location)
ǒmm
inchesǓ
SCALE 20:1
0.65
0.025
0.65
0.025
0.50
0.0197
0.40
0.0157
1.9
0.0748
SOLDER FOOTPRINT
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 − Rev. 0
Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
NEW STANDARD:
DESCRIPTION:
98ASB42984B
ON SEMICONDUCTOR STANDARD
SC−88A (SC−70−5/SOT−353)
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2
DOCUMENT NUMBER:
98ASB42984B
PAGE 2 OF 2
ISSUE REVISION DATE
CCONVERTED FROM PAPER DOCUMENT TO ELECTRONIC. REQ. BY N LAFEB-
RE.
20 JUN 1998
DCONVERTED FROM MOTOROLA TO ON SEMICONDUCTOR. ADDED STYLE 5.
REQ. BY E. KIM.
24 JUL 2000
EADDED STYLES 6 & 7. REQ. BY S. BACHMAN. 03 AUG 2000
FDELETED DIMENSION V, WAS 0.3−0.44MM/0.012−0.016IN. REQ. BY G. KWONG. 14 JUN 2001
GADDED STYLE 8, REQ. BY S. CHANG; ADDED STYLE 9, REQ. BY S. BACHMAN;
ADDED NOTE 4, REQ. BY S. RIGGS
25 JUN 2003
HCHANGED STYLE 6. REQ. BY C. LIM 28 APR 2005
JCHANGED TITLE DESCRIPTION. REQ. BY B. LOFTS. 31 AUG 2005
KCORRECTED TITLE AND DESCRIPTION TO SC−88A (SC−70−5/SOT−353). COR-
RECTED MARKING DIAGRAM. REQ. BY D. TRUHITTE.
13 JUL 2010
LADDED SOLDER FOOTPRINT. REQ. BY I. MARIANO. 17 JAN 2013
© Semiconductor Components Industries, LLC, 2013
January, 2013 − Rev. L
Case Outline Number:
419A
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
TSOP−5
CASE 483
ISSUE M DATE 17 MAY 2016
SCALE 2:1
1
5
XX MG
G
GENERIC
MARKING DIAGRAM*
1
5
0.7
0.028
1.0
0.039
ǒmm
inchesǓ
SCALE 10:1
0.95
0.037
2.4
0.094
1.9
0.074
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
XXX = Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
G= Pb−Free Package
1
5
XXXAYWG
G
Discrete/Logic
Analog
(Note: Microdot may be in either location)
XX = Specific Device Code
M = Date Code
G= Pb−Free Package
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
DIM MIN MAX
MILLIMETERS
A
B
C0.90 1.10
D0.25 0.50
G0.95 BSC
H0.01 0.10
J0.10 0.26
K0.20 0.60
M0 10
S2.50 3.00
123
54 S
AG
B
D
H
CJ
__
0.20
5X
CAB
T0.10
2X
2X T0.20
NOTE 5
CSEATING
PLANE
0.05
K
M
DETAIL Z
DETAIL Z
TOP VIEW
SIDE VIEW
A
B
END VIEW
1.35 1.65
2.85 3.15
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 − Rev. 0 Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
NEW STANDARD:
DESCRIPTION:
98ARB18753C
ON SEMICONDUCTOR STANDARD
TSOP−5
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2
DOCUMENT NUMBER:
98ARB18753C
PAGE 2 OF 2
ISSUE REVISION DATE
OINITIATED NEW MECHANICAL OUTLINE #483. REQ BY WL CHIN/L. RENNICK. 28 OCT 1998
AUPDATE OUTLINE DRAWING TO CORRECT DIN “C” (SHOULD BE FROM TIP OF
LID TO TOP OF PKG). DIM IN TABLE INCORRECTLY LISTED TO G, F TO H,
H TO J, N TO L & R TO M. REQ BY F. PADILLA
13 NOV 1998
BCHANGE OF LEGAL ONWERSHIP FROM MOTOROLA TO ON SEMICONDUC-
TOR. REQ BY A. GARLINGTON 20 APR 2001
CADDED NOTE “4”. REQ BY S. RIGGS 27 JUN 2003
DADDED FOOTPRINT INFORMATION. UPDATED MARKING. REQ. BY D. JOERSZ 07 APR 2005
ECHANGED DEVICE MARKING FROM AWW TO AYW. REQ. BY J. MANES. 14 SEP 2005
FUPDATED DRAWINGS TO LATEST JEDEC STANDARDS. ADDED NOTE 5. REQ.
BY T. GURNETT. 07 JUN 2006
GADDED MARKING DIAGRAM FOR IC OPTION. REQ. BY J. MILLER. 21 FEB 2007
HCORRECTED MARKING DIAGRAM ERROR BY REVERSING ANALOG AND
DISCRETE LABELS. REQ. BY GK SUA. 18 MAY 2007
JCHANGED NOTE 4. REQ. BY A. GARLINGTON. 13 MAR 2013
KREMOVED DIMENSION L AND ADDED DATUMS A AND B TO TOP VIEW. REQ.
BY A. GARLINGTON. 19 APR 2013
LREMOVED −02 FROM CASE CODE VARIANT. REQ. BY N. CALZADA. 23 SEP 2015
MCHANGED DIMENSIONS A & B FROM BASIC TO MIN AND MAX VALUES. REQ.
BY A. GARLINGTON. 17 MAY 2016
© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. M Case Outline Number
:
48
3
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, af filiates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
UDFN8, 2x2
CASE 517AW
ISSUE A DATE 13 NOV 201
5
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMI-
NALS AND IS MEASURED BETWEEN 0.15
AND 0.30 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. FOR DEVICE OPN CONTAINING W OPTION,
DETAIL B ALTERNATE CONSTRUCTION IS
NOT APPLICABLE.
ÇÇ
ÇÇ
A
D
E
B
C0.10
PIN ONE
2X
REFERENCE
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
L
D2
E2
C
C0.10
C0.10
C0.08 A1 SEATING
PLANE
8X
NOTE 3
b
8X
0.10 C
0.05 C
ABB
DIM MIN MAX
MILLIMETERS
A0.45 0.55
A1 0.00 0.05
b0.18 0.30
D2.00 BSC
D2 1.50 1.70
E2.00 BSC
E2 0.80 1.00
e0.50 BSC
L0.20 0.45
14
8
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.50
PITCH
1.00 2.30
1
DIMENSIONS: MILLIMETERS
0.50
8X
1
NOTE 4
0.30
8X
DET AIL A
A3 0.13 REF
A3
A
DETAIL B
A1 A3
ÇÇ
ÇÇ
ÉÉ
DETAIL B
MOLD CMPD
EXPOSED Cu
L1 −−− 0.15
OUTLINE
PACKAGE
e
RECOMMENDED
5
1.73
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
XX = Specific Device Code
M = Date Code
G= Pb−Free Package
XX MG
G
1
(Note: Microdot may be in either location)
ALTERNATE
CONSTRUCTION
L1
DETAIL A
L
ALTERNATE
CONSTRUCTIONS
L
e/2
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 − Rev. 0 Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
REFERENCE:
DESCRIPTION:
98AON34462E
ON SEMICONDUCTOR STANDARD
UDFN8, 2X2
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2
DOCUMENT NUMBER:
98AON34462E
PAGE 2 OF 2
ISSUE REVISION DATE
ORELEASED FOR PRODUCTION FROM POD #UDFN8−033−01 TO ON SEMICON-
DUCTOR. REQ. BY B. BERGMAN. 19 DEC 2008
AREDREW TO JEDEC STANDARDS. REQ. BY I. HYLAND. 13 NOV 2015
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. A Case Outline Number
:
517AW
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, af filiates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
SCALE 1:1
STYLES ON PAGE 2
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
XXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
GENERIC
MARKING DIAGRAM*
1
8
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
XXXXX
ALYWX
1
8
IC Discrete
XXXXXX
AYWW
G
1
8
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
Discrete
XXXXXX
AYWW
1
8
(Pb−Free)
XXXXX
ALYWX
G
1
8
IC
(Pb−Free)
XXXXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G= Pb−Free Package
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 − Rev. 0
Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
NEW STANDARD:
DESCRIPTION:
98ASB42564B
ON SEMICONDUCTOR STANDARD
SOIC−8, NB
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 3
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
http://onsemi.com
2
© Semiconductor Components Industries, LLC, 2002
October, 2002 − Rev. 0
Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
NEW STANDARD:
DESCRIPTION:
98ASB42564B
ON SEMICONDUCTOR STANDARD
SOIC−8, NB
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 2 OF 3
DOCUMENT NUMBER:
98ASB42564B
PAGE 3 OF 3
ISSUE REVISION DATE
AB ADDED STYLE 25. REQ. BY S. CHANG. 15 MAR 2004
AC ADDED CORRECTED MARKING DIAGRAMS. REQ. BY S. FARRETTA. 13 AUG 2004
AD CORRECTED MARKING DIAGRAM FOR DISCRETE. REQ. BY S. FARRETTA. 18 NOV 2004
AE UPDATED SCALE ON FOOTPRINT. REQ. BY S. WEST. 31 JAN 2005
AF UPDATED MARKING DIAGRAMS. REQ. BY S. WEST. ADDED STYLE 26. REQ. BY
S. CHANG.
14 APR 2005
AG ADDED STYLE 27. REQ. BY S. CHANG. 30 JUN 2005
AH ADDED STYLE 28. REQ. BY S. CHANG. 09 MAR 2006
AJ ADDED STYLE 29. REQ. BY D. HELZER. 19 SEP 2007
AK ADDED STYLE 30. REQ. BY I. CAMBALIZA. 16 FEB 2011
© Semiconductor Components Industries, LLC, 2011
February, 2011 − Rev. 07AK
Case Outline Number:
751
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
SOIC−14 NB
CASE 751A−03
ISSUE L DATE 03 FEB 201
6
SCALE 1:1
1
14
GENERIC
MARKING DIAGRAM*
XXXXXXXXXG
AWLYWW
1
14
XXXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
*This information is generic. Please refer t
o
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
STYLES ON PAGE 2
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
H
14 8
71
M
0.25 B M
C
h
X 45
SEATING
PLANE
A1
A
M
_
S
A
M
0.25 B S
C
b
13X
B
A
E
D
e
DET AIL A
L
A3
DET AIL A
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
D8.55 8.75 0.337 0.344
E3.80 4.00 0.150 0.157
A1.35 1.75 0.054 0.068
b0.35 0.49 0.014 0.019
L0.40 1.25 0.016 0.049
e1.27 BSC 0.050 BSC
A3 0.19 0.25 0.008 0.010
A1 0.10 0.25 0.004 0.010
M0 7 0 7
H5.80 6.20 0.228 0.244
h0.25 0.50 0.010 0.019
__ __
6.50
14X
0.58
14X
1.18
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
0.10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 − Rev. 0 Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
NEW STANDARD:
DESCRIPTION:
98ASB42565B
ON SEMICONDUCTOR STANDARD
SOIC−14 NB
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 3
SOIC−14
CASE 751A−03
ISSUE L DATE 03 FEB 2016
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
STYLE 2:
CANCELLED
http://onsemi.com
2
© Semiconductor Components Industries, LLC, 2002
October, 2002 − Rev. 0 Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
NEW STANDARD:
DESCRIPTION:
98ASB42565B
ON SEMICONDUCTOR STANDARD
SOIC−14 NB
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 2 OF 3
DOCUMENT NUMBER:
98ASB42565B
PAGE 3 OF 3
ISSUE REVISION DATE
GADDED MARKING DIAGRAM. REQ. BY S. FARRETTA 30 APR 2004
HADDED SOLDERING FOOTPRINT. REQ. BY S. RIGGS. 04 OCT 2006
JCORRECTED MARKING DIAGRAM. MOVED PB−FREE INDICATOR “G” TO TOP
LINE. REQ. BY C. BIAS. 13 FEB 2008
KUPDATED DRAWING TO JEDEC STANDARDS. REQ. BY I. CAMBALIZA. 31 MAY 2011
LADDED COPLANARITY TOLERANCE BOX TO SIDE VIEW. REQ. BY F. ESTRADA. 03 FEB 2016
© Semiconductor Components Industries, LLC, 2016
February, 2016 − Rev. L Case Outline Number
:
751A
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, af filiates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
Micro8t
CASE 846A−02
ISSUE J
DATE 02 JUL 2013
SCALE 2:1
S
B
M
0.08 (0.003) A S
T
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.
b
e
PIN 1 ID
8 PL
0.038 (0.0015)
−T−
SEATING
PLANE
A
A1 cL
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 2:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 3:
PIN 1. N-SOURCE
2. N-GATE
3. P-SOURCE
4. P-GATE
5. P-DRAIN
6. P-DRAIN
7. N-DRAIN
8. N-DRAIN
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
G= Pb−Free Package
(Note: Microdot may be in either location)
XXXX
AYWG
G
1
8
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
DIM
A
MIN NOM MAX MIN
MILLIMETERS
−− −− 1.10 −−
INCHES
A1 0.05 0.08 0.15 0.002
b0.25 0.33 0.40 0.010
c0.13 0.18 0.23 0.005
D2.90 3.00 3.10 0.114
E2.90 3.00 3.10 0.114
e0.65 BSC
L0.40 0.55 0.70 0.016
−− 0.043
0.003 0.006
0.013 0.016
0.007 0.009
0.118 0.122
0.118 0.122
0.026 BSC
0.021 0.028
NOM MAX
4.75 4.90 5.05 0.187 0.193 0.199
HE
*This information is generic. Please refer to device data
sheet for actual part marking. Pb−Free indicator, “G”
or microdot “ G”, may or may not be present.
HE
DD
E
8X 0.48
0.65
PITCH
5.25
8X
0.80
DIMENSION: MILLIMETERS
RECOMMENDED
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 Rev. 0
Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
NEW STANDARD:
DESCRIPTION:
98ASB14087C
ON SEMICONDUCTOR STANDARD
MICRO8
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2
DOCUMENT NUMBER:
98ASB14087C
PAGE 2 OF 2
ISSUE REVISION DATE
GADDED NOMINAL VALUES AND UPDATED GENERIC MARKING DIAGRAM. REQ.
BY HONG XIAO
18 JUL 2005
HCORRECTED GENERIC MARKING INFORMATION. REQ. BY T. GURNETT. 12 NOV 2007
JCORRECTED SOLDERING FOOTPRINT. REQ. BY J. LIU. 02 JUL 2013
© Semiconductor Components Industries, LLC, 2013
July, 2013 − Rev. J
Case Outline Number:
846A
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
Micro8 is a trademark of International Rectifier.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor ’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer ’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body . Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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